Ultra-thin sandwich parts
Ultra-thin sandwich components are formed by creating vias and conductive paths on a substrate, plated and sandwiched with another substrate, achieving reduced height and improved RF performance for high frequency wireless communication.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-09
- Publication Date
- 2026-03-11
AI Technical Summary
The challenge of miniaturizing passive components for high frequency wireless communication, particularly at 5G frequencies, is exacerbated by the difficulty in surface mounting small components without compromising performance, as traditional methods struggle to reduce component height effectively.
A method involving the formation of vias and conductive paths on a first substrate, followed by plating and sandwiching with a second substrate, and subsequent thickness reduction of both substrates to create ultra-thin components with conductive contact pads, allowing for secure mounting and reduced height.
The solution enables components with a thickness of less than 40 mils, enhancing RF performance and enabling higher frequency operation while maintaining electrical connectivity, thus addressing the miniaturization challenge.
Smart Images
Figure 2026508479000001_ABST
Abstract
Description
[Technical Field]
[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 490,781, filed March 17, 2023, which is incorporated herein by reference. The present invention relates to ultra-thin sandwich components. [Background technology]
[0002] There is an increasing demand for high frequency wireless signal communication. For example, the demand for increased data transmission speeds for wireless smartphone connections is driving the demand for high frequency components, including those configured to operate at 5G spectrum frequencies. The trend toward miniaturization is also driving the need for small passive components to process these high frequency signals. However, miniaturization makes it difficult to surface mount small passive components suitable for operation at the 5G frequency spectrum. Components that can reduce their height without negatively impacting their performance would be welcome in the art. Summary of the Invention [Means for solving the problem]
[0003] According to one embodiment of the present invention, a method of forming a part includes: providing a first substrate having a first surface, a second surface opposite the first surface along a height direction, and an initial thickness along the height direction from the first surface to the second surface; forming one or more vias in the first substrate, each via of the one or more vias extending from the first surface of the first substrate to the second surface of the first substrate; depositing one or more conductive paths on the first surface of the first substrate; plating the one or more vias; disposing a second substrate on the first surface of the first substrate to form a sandwich component; treating a second surface of the first substrate to reduce a thickness of the sandwich, thereby defining a treated second surface of the first substrate; and forming one or more contact pads on the treated second surface of the first substrate; Includes.
[0004] According to another embodiment of the present invention, a method of forming a part includes: providing a first substrate having a first surface, a second surface opposite the first surface along a height direction, and an initial thickness along the height direction from the first surface to the second surface; depositing one or more conductive paths on the first surface of the first substrate, such that at least one of the one or more conductive paths extends through the first substrate from the first surface to the second surface; disposing a second substrate on the first substrate, the second substrate having a first surface, a second surface opposite the first surface along a height direction, and an initial thickness from the first surface to the second surface along the height direction, the second surface of the second substrate being disposed opposite the first surface of the first substrate; and treating the second surface of the first substrate to reduce the initial thickness of the first substrate to a treatment thickness; Includes.
[0005] According to yet another embodiment of the present invention, the component comprises: a first substrate having a first surface and a second surface opposite the first surface; one or more vias defined in the first substrate, each via of the one or more vias extending from the first surface of the first substrate to the second surface of the first substrate, the one or more vias including a first via and a second via, the one or more vias comprising a conductive material; one or more conductive paths on the first surface of the first substrate, the one or more conductive paths including a first conductive path extending from the first via to the second via; one or more contact pads formed on the second surface of the first substrate, each contact pad surrounding a respective one of the one or more vias in the second surface and each contact pad being in electrical contact with a respective one of the vias; and a second substrate having a first surface and a second surface opposite the first surface, the second substrate being disposed on the first substrate such that the second surface of the second substrate contacts the first surface of the first substrate; The part has a thickness of less than about 40 mils.
[0006] According to yet another embodiment of the present invention, a method of assembling a component on an electronic device includes providing a component, the component comprising: a first substrate having a first surface and a second surface opposite the first surface; one or more vias defined in the first substrate, each via of the one or more vias extending from the first surface of the first substrate to the second surface of the first substrate, the one or more vias including a first via and a second via; the one or more vias being plated with a conductive material; one or more conductive paths on the first surface of the first substrate, the one or more conductive paths including a first conductive path extending from the first via to the second via; one or more contact pads formed on the second surface of the first substrate, each contact pad surrounding a respective one of the one or more vias in the second surface and each contact pad being in electrical contact with a respective one of the vias; and a second substrate having a first surface and a second surface opposite the first surface, the second substrate being disposed on the first substrate such that the second surface is disposed in contact with the first surface of the first substrate; The component has a thickness of less than about 40 mils. The method also includes securing the component to the electronic device and treating the second substrate to reduce the thickness of the second substrate. [Brief explanation of the drawings]
[0007] [Figure 1] FIG. 1 is a perspective view of a component assembled on an electronic device to reduce its height according to aspects of the present disclosure. [Figure 2] 1 is a flowchart illustrating a method of forming a part according to aspects of the present disclosure. [Figure 3] FIG. 2 is a perspective view of a first substrate of a component according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a perspective view of the first substrate of FIG. 3 having a plurality of vias formed therein according to an embodiment of the present disclosure. [Figure 5] 5 is a perspective view of the first substrate of FIG. 4 having two conductive paths formed on the first surface according to an embodiment of the present disclosure. [Figure 6] 6 is a perspective view of the first substrate of FIG. 5 having conductive paths extending through a plurality of vias according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a perspective view of a second substrate placed over the first substrate of FIG. 6 to form a sandwich component according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a perspective view of a second surface of the sandwich component of FIG. 7 according to an embodiment of the present disclosure. [Figure 9] FIG. 8 is a perspective view of a treated second surface of the sandwich component of FIG. 7 according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a perspective view of a treatment surface of the sandwich component of FIG. 9 having a plurality of contact pads formed thereon in accordance with an embodiment of the present disclosure. [Figure 11] 1 is a flowchart illustrating a method for assembling components on an electronic device according to an aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0008] A full and enabling disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in the remainder of the specification, including reference to the accompanying drawings, in which:
[0009] Repeat use of reference characters in the present specification and drawings is intended to represent the same or similar features or elements of the invention.
[0010] Those skilled in the art will appreciate that the description herein is merely a description of exemplary embodiments and is not intended to limit the broader scope of the invention as embodied in the exemplary configurations.
[0011] Generally speaking, the present invention relates to components with reduced height. For example, one or more conductive paths can be sandwiched between two substrates, a first of which can be thinned or reduced in height, and then one or more conductive regions can be provided on an outer surface of the sandwich component to electrically connect the one or more conductive paths to an electronic device (such as a printed circuit board). A second of the two substrates can be thinned or reduced in height to further reduce the height of the sandwich component.
[0012] For example, the sandwich component may be mounted to a mounting surface of an electronic device before the second substrate is processed to reduce the height of the sandwich component, or the second substrate may be processed to reduce the height of the sandwich component before the sandwich component is processed and mounted to a mounting surface, embedded in an electronic device, or otherwise secured to an electronic device.
[0013] By processing one side of the sandwich component and then processing the other side of the sandwich component, e.g., before or after mounting or fastening the sandwich component to an electronic device, it is possible to thin at least one side of the sandwich component to a thickness greater than previously permitted, e.g., to a relatively extreme level. Furthermore, the other side of the sandwich component can also be thinned to further reduce the height or thickness of the component, e.g., to allow the component to be mounted in an area or with other components not possible with known or existing components of greater height or thickness. As an example, after processing a first surface of the sandwich component, the sandwich component can be singulated to create a chip. Once the chip is mounted to a circuit, the second surface opposite the first surface can be thinned to a desired height. As another example, the second surface can be thinned before fastening the chip, allowing the chip to be embedded in a circuit board or the like.
[0014] Furthermore, varying the thickness of the initial substrate can be used to change the RF performance of a component, such as the RE performance of one or more transmission lines disposed between the initial substrate or the first and second substrates of a sandwich component. For example, the useful frequency range of a circuit including the thin components described herein may be expanded; for example, the components described herein may be capable of being used at higher frequencies than known components. Furthermore, the conductive paths or transmission lines may be thinner than other components, and reducing the width of the transmission lines may improve RF performance, e.g., reducing the transmission line width in response to a reduction in component or chip size. For example, thinner transmission lines may allow for the use of higher frequency filters in smaller packages, thereby improving passband loss, or / and improving rejection by using more poles within the same package. Furthermore, thinner transmission lines may result in less change in the impedance of the transmission lines over a certain frequency range, e.g., compared to thicker transmission lines, and thinner transmission lines also allow for smaller chip sizes.
[0015] In some embodiments, a "pre-thinned" component is provided, in which a first substrate is provided at a particular thickness, for example, by using techniques described herein. Because the thickness of the first substrate is not subsequently changed, performance values, such as frequency range, are known. A second substrate, or cover substrate, can be disposed on the first substrate as described herein.
[0016] Referring to the drawings, FIG. 1 shows a component 100 mounted to a mounting surface 20 of a device 10, such as a printed circuit board (PCB). In at least some embodiments, the component 100 may be referred to as an ultra-thin sandwich component. FIGS. 3-10 illustrate the formation of the component 100, for example, according to the manufacturing flow (method) 200 described with respect to FIG. 2. FIG. 11 illustrates an assembly flow (method) 1100 for assembling the component 100 onto an electronic device, such as the device 10 shown in FIG. 1.
[0017] As shown in FIG. 1 , component 100 includes a first substrate 102 having a first surface 104 ( FIG. 3 ) and a treated second surface 106′ opposite first surface 104. Treatment of first substrate 102 to form treated second surface 106′ is described in more detail herein, for example, with reference to FIGS. 8 and 9 . Furthermore, while FIG. 1 depicts component 100 mounted to mounting surface 20 of device 10, it will be understood that in other embodiments, component 100 may be embedded within device 10 such that component 100 is secured to device 10 in a manner other than by being mounted to mounting surface 20. Device 10 may be an electronic device, such as a printed circuit board (PCB).
[0018] 1 also includes four vias 108 defined in the first substrate 102: a first via 108a, a second via 108b, a third via 108c, and a fourth via 108d. Each via 108 extends from the first surface 104 of the first substrate 102 to the processed second surface 106′ of the first substrate 102.
[0019] As shown in FIG. 1 , conductive paths 110 formed on the first surface 104 of the first substrate 102 connect the vias 108. More specifically, the first conductive path 110a extends from the first via 108a to the second via 108b, and the second conductive path 110b extends from the third via 108c to the fourth via 108d. The conductive paths 110 may be formed from any conductive material suitable for electrical conduction, such that the first conductive path 110a electrically connects the first via 108a and the second via 108b, and the second conductive path 110b electrically connects the third via 108c and the fourth via 108d. For example, the conductive paths 110 may be formed from a metallic material such as copper, nickel, gold, silver, or other metals or alloys, or any other suitable conductive material.
[0020] As an example, each conductive path 110 can include one or more conductive layers formed on the first substrate 102, which can be formed from a non-conductive material such as a dielectric material. The conductive layers can include a variety of conductive materials. For example, the conductive layers can include copper, nickel, gold, silver, or other metals or alloys. The conductive layers can be formed using a variety of suitable techniques. A planar, semi-additive, or full-additive process can be used to electroplate a panel or pattern of conductive material, followed by a printing and etching step to define the patterned conductive layer. Photolithography, plating (such as electroplating), sputtering, vacuum deposition, printing, or other techniques can be used to form the conductive layer. For example, a thin layer of conductive material (e.g., a foil) can be adhered (e.g., laminated) to the surface of the dielectric layer. The thin layer of conductive material can be selectively etched using a mask and photolithography to create a desired pattern of conductive material on the surface of the dielectric material.
[0021] Furthermore, in the illustrated embodiment, the conductive material forming the conductive pathway 110 extends into each via 108, such that the conductive pathway 110 extends between the first surface 104 and the processed second surface 106′ of the first substrate 102. For example, each via 108 may be plated with a conductive material such that the conductive material extends into each via 108. One or more contact pads 126 may be disposed on the processed second surface 106′ of the first substrate 102 to enable connection of the conductive pathway 110 to the device 10. For example, each contact pad 126 may surround a respective one of the vias 108 in the processed second surface 106′ of the first substrate 102.
[0022] As further shown in FIG. 1 , the second substrate 112 is disposed on the first substrate 102. The second substrate 112 has a first surface 114 and a second surface 116 opposite the first surface 114. The second substrate 112 is disposed on the first substrate 102 such that the second surface 116 of the second substrate 112 contacts the first surface 104 of the first substrate 102. The second substrate 112 may be, for example, a top cover or cover substrate that sandwiches a conductive path 110 between the first substrate 102, or bottom substrate, and the second substrate 112, or top substrate. The second substrate 112 is shown as transparent in FIG. 1 (and throughout the figures) for purposes of illustration, e.g., to facilitate visualization of the conductive path 110 sandwiched between the first substrate 102 and the second substrate 112, and to facilitate the description herein.
[0023] The thickness t of the component is less than about 40 mils (0.004 inches). The second substrate 112 may be configured to be processed to further reduce the thickness t of the component 100. After processing, the first substrate 102 and the second substrate 112 may each have a thickness ranging from about 2 mils to about 30 mils. In some embodiments, the first substrate 102 and the second substrate 112 may have the same thickness. In other embodiments, one of the first substrate 102 or the second substrate 112 may be thicker than the other of the first substrate 102 or the second substrate 112, such that the total thickness t of the component 100 is less than about 40 mils. For example, in one embodiment, the thickness of the first substrate 102 is about 3 mils and the thickness of the second substrate 112 is about 3 mils, resulting in a thickness t of the component 100 of about 6 mils. As another example, the thickness of the first substrate 102 is about 3 mils and the thickness of the second substrate 112 is about 5 mils, resulting in a thickness t of the component 100 of about 8 mils. As yet another example, the thickness of the first substrate 102 is approximately 4 mils and the thickness of the second substrate 112 is approximately 3 mils, resulting in a thickness t of the component 100 of approximately 7 mils. The thickness of the first substrate 102 is approximately 5 mils and the thickness of the second substrate 112 is approximately 5 mils, resulting in a thickness t of the component 100 of approximately 10 mils. The thickness of the first substrate 102 is approximately 10 mils and the thickness of the second substrate 112 is approximately 10 mils, resulting in a thickness t of the component 100 of approximately 20 mils. Other substrate thicknesses may also be used.
[0024] In embodiments in which second substrate 112 is processed to further reduce the thickness of component 100 after being placed on first substrate 102, second substrate 112 may have a thickness in the range of about 5 mils to about 50 mils before processing second substrate 112 to reduce the thickness of component 100. Similarly, first substrate 102 may have a thickness in the range of about 5 mils to about 50 mils before processing described herein.
[0025] The component 100 may include one or more dielectric materials; for example, at least one of the first substrate 102 or the second substrate 112 may include a dielectric material. In some embodiments, the one or more dielectric materials may have a low dielectric constant. The dielectric constant may be less than about 100, in some embodiments, less than about 75, in some embodiments, less than about 50, in some embodiments, less than about 25, in some embodiments, less than about 15, or in some embodiments, less than about 5. For example, the dielectric constant may be in the range of about 1.5 to about 100, in some embodiments, from about 1.5 to about 75, and in some embodiments, from about 2 to about 8. The dielectric constant may be measured in accordance with IPC TM-650 2.5.5.3 at an operating temperature of 25°C and a frequency of 1 MHz. The dissipation factor may be in the range of about 0.001 to about 0.04, and in some embodiments, from about 0.0015 to about 0.0025.
[0026] In some embodiments, one or more of the dielectric materials may include organic dielectric materials. Examples of organic dielectrics include polyphenyl ether (PPE)-based materials such as Polyclad's LD621 and Park / Nelco Corporation's N6000 series, liquid crystal polymers (LCPs) such as Rogers Corporation's or W.L. Gore & Associates' LCPs, hydrocarbon composites such as Rogers Corporation's 4000 series, and epoxy-based laminates such as Park / Nelco Corp.'s N4000 series. Examples include epoxy-based N4000-13, bromine-free materials laminated to LCPs, organic layers containing high-K materials, unfilled high-K organic layers, Roger 4350, Rogers 4003, and other thermoplastic materials such as polyphenylene sulfide resins, polyethylene terephthalate resins, polybutylene terephthalate resins, polyethylene sulfide resins, polyether ketone resins, polytetrafluoroethylene resins, graft resins, or similar low-dielectric-constant, low-loss organic materials.
[0027] In some embodiments, the one or more dielectric materials may include a ceramic-filled epoxy. For example, the one or more dielectric materials may include an organic compound, such as a polymer (e.g., an epoxy), and may include particles of a ceramic dielectric material, such as barium titanate, calcium titanate, zinc oxide, alumina, including low-fire glass, or other suitable ceramic or glass-bonded material.
[0028] However, other materials can also be used, including N6000, epoxy-based N4000-13, bromine-free materials laminated to LCP, organic layers containing high-K materials, unfilled high-K organic layers, Rogers 4350, Rogers 4003 (Rogers Corporation), and other thermoplastic materials such as (hydrocarbon, Teflon, FR4, epoxy, polyamide, polyimide, acrylate, etc.), polyphenylene sulfide resin, polyethylene terephthalate resin, polybutylene terephthalate resin, polyethylene sulfide resin, polyether ketone resin, polytetrafluoroethylene resin, BT resin composites (e.g., Speedboard C), thermoset resins (e.g., Hitachi MCL-LX-67F), and graft resins, or similar low dielectric constant, low loss organic materials. Dielectric materials such as diamond and cubic boron arsenide can also be used.
[0029] Additionally, non-organic dielectric materials, including ceramics, semiconductors, and insulating materials, can also be used. Non-organic dielectric materials include, but are not limited to, barium titanate, calcium titanate, zinc oxide, alumina, including low-fire glass, or other suitable ceramic or glass-bonded materials. The dielectric material may also be an organic compound, such as epoxy (with or without ceramic fillings, with or without glass fiber), a well-known circuit board material, or other plastics commonly used as dielectrics. In these cases, the conductor may be copper foil that is chemically etched to form a pattern. In still other embodiments, the dielectric material may be a material with a relatively high dielectric constant (K), such as any one of NPO (COG), X7R, X5R, X7S, Z5U, Y5V, and strontium titanate. In such examples, the dielectric material may have a dielectric constant greater than 100, for example, in the range of about 100 to about 4000, and in some embodiments, about 1000 to about 3000.
[0030] 2-11, the formation of component 100 will be described in more detail. As indicated by reference numeral 202 in FIG. 2, a manufacturing flow (method) 200 for forming component 100 can include providing a first substrate 102. As shown in FIG. 3, first substrate 102 includes a first surface 104 and a second surface 106 located opposite first surface 104 along height direction Z. First substrate 102 has an initial thickness t from first surface 104 to second surface 106 along height direction Z. i may have
[0031] As shown at 204 in FIG. 2 , the manufacturing flow 200 may further include forming one or more vias 108 in the first substrate 102. With reference to FIG. 4 , each via 108 of the one or more vias 108 may extend from the first surface 104 of the first substrate 102 to the second surface 106 of the first substrate 102. For example, a first end 118 of each via 108 may be defined in the first surface 104 of the first substrate, and a second end 120 of each via 108 may be defined in the second surface 106 of the first substrate 102. Each via 108 may extend from the first end 118 to the second end 120. The one or more vias 108 may be formed by cutting or another suitable process.
[0032] 4, the vias 108 are formed along the side surface 122 of the first substrate 102, while in other embodiments, one or more vias 108 are defined at other locations on the first substrate 102. For example, one or more vias 108 may be spaced apart from the side surface 122 of the first substrate 102, with a portion of the first substrate 102 extending between each via 108 and the side surface 122 of the first substrate 102.
[0033] Referring to numeral 206 in FIG. 2 , the manufacturing flow 200 may include depositing one or more conductive paths 110 on the first surface 104 of the first substrate 102. As shown in FIG. 5 , each conductive path 110 may extend between two or more vias 108. For example, as described with respect to FIG. 1 , the first conductive path 110a may extend from the first via 108a to the second via 108b, and the second conductive path 110b may extend from the third via 108c to the fourth via 108d. Along the first surface 104, the one or more conductive paths 108 may extend from the first end 118 of a respective via 108 to the first end 118 of another via 108. The conductive paths 110 may be formed from any suitable conductive material, as described elsewhere herein.
[0034] 1, the conductive paths 110 can also extend into one or more vias 108. For example, as shown at 208 in FIG. 2, the manufacturing flow 200 can include plating one or more vias 108 such that each conductive path 110 extends to the second end 120 of each plated via 108, as shown in FIG. 6. That is, each conductive path 110 can extend within a via 108 (e.g., by plating the via 108), such that electrical conduction through the conductive paths 110 extends to the second surface 106 of the first substrate 102 (also shown in FIG. 8, which is a perspective view of the sandwich component 124 from the second surface 106).
[0035] Referring to 210 in Figure 2, the method may also include disposing a second substrate 112 on the first surface 104 of the first substrate 102 to form a sandwich component 124. As shown in Figure 7, the second substrate 112 is shown transparent to facilitate illustrating the relative positions of the various portions of the component 100, and has a first surface 114 and a second surface 116 located opposite the first surface 114 along the height direction Z. The second substrate 112 extends from the first surface 114 to the second surface 116 along the height direction Z with an initial thickness t i2 The second substrate 112 is positioned relative to the first substrate 102 such that the second surface 116 of the second substrate 112 covers the first surface 104 of the first substrate 102.
[0036] 2, the method may further include treating the second surface 106 of the first substrate 102 to reduce the thickness of the sandwich component 124 and define a treated second surface 106' of the first substrate 102. With reference to FIGS. 8 and 9, prior to treating the second surface 106 of the first substrate 102, the sandwich component 124 is reduced in thickness to a first thickness t cs1 and the first substrate 102 has an initial thickness t i After processing the first substrate 102, the sandwich component 124 has a second thickness t cs2 and the first substrate 102 has a processed thickness t pThe treatment for reducing the thickness of the first substrate 102 may include grinding the first substrate 102 or other treatment for reducing the thickness of the first substrate 102. After treating the first substrate 102, the conductive material in the one or more vias 108 having conductive material extends to the processed second surface 106′ of the first substrate 102, thereby exposing conductive paths 110 extending to and along the processed second surface 106′ of the first substrate 102, for example, the conductive paths 110 extending to the processed second ends 120′ of each via 108.
[0037] Because the second substrate 112 can reinforce the first substrate 102, the first substrate 102 can be processed or thinned to relatively extreme levels, or "ultra-thinned," without warping or cracking the first substrate 102 and / or sandwich component 124. For example, the first substrate 102 may be processed to about half (about 50%) or less of its initial thickness t i , e.g., the initial thickness t i It may be processed to about one-third (about 33%), about one-quarter (about 25%), about one-fifth (about 20%), about one-sixth (about 17%), or about one-eighth (about 12.5%) or less of its original volume.
[0038] 2, the manufacturing flow 200 may also include forming one or more contact pads 126 on the processed second surface 106′ of the first substrate 102. As shown in FIG. 10, in at least some embodiments, each contact pad 126 of the one or more contact pads 126 surrounds a respective via 108 on the processed second surface 106′ of the first substrate 102, such that each contact pad 126 is in electrical contact with a respective via 108 and, thereby, a respective conductive path 110. For example, as described herein, each via 108 may be plated or otherwise lined or filled with a conductive material to electrically connect each conductive path 110 to each contact pad 126. 10 , the one or more contact pads 126 include a first contact pad 126 surrounding and electrically contacting the first via 108 a, a second contact pad 126 surrounding and electrically contacting the second via 108 b, a third contact pad 126 surrounding and electrically contacting the third via 108 c, and a fourth contact pad 126 surrounding and electrically contacting the fourth via 108 d. It will be appreciated that the contact pads 126 can increase the contact area of the conductive pathway 110 on the processed second surface 106′ of the first substrate 102, for example, increasing the contact between the conductive pathway 110 and the device 10 to which the component 110 is secured.
[0039] 1 , the component 100 may be secured to the device 10, for example, by mounting the component 100 to a mounting surface 20 defined by the device 10, by embedding the component 100 within the device 10, or by other methods of securing the component 100 to the device 10. Before or after securing the component 100 to the device 10, the second substrate 112 may be thinned to further reduce the thickness of the component 100. For example, as shown at 216 in FIG. 2 , the manufacturing flow 200 may optionally include treating the first surface 114 of the second substrate 112 to reduce the thickness of the sandwich component 124.
[0040] In other embodiments, the second substrate 112 may be processed after the component 100 is secured to the device 10. For example, referring to FIG. 11 , a manufacturing flow (method) 1100 for assembling a component on an electronic device may include providing a component, such as the component 100 described herein, as shown at 1102. At 1104, the manufacturing flow 1100 may further include securing the component to an electronic device, which may be a device, such as the device 10 described herein. As described above, securing the component to the electronic device may include mounting the component to the mounting surface 20 of the device 10, partially or fully embedding the component in the device 10, or otherwise securing the component to the electronic device. For example, partially embedding the component 100 within the device 10 may result in a portion of the component 100 being disposed within the device 10 and a remainder of the component 100 protruding from or external to the device 10. Fully embedding the component 100 within the device 10 may result in the entire component 100 being disposed within the device 10. (For example, at most one or more surfaces of component 100 are flush with one or more surfaces of device 10, with the remainder of component 100 being surrounded by device 10.) Securing the component to the electronic device may include, for example, soldering the component to the electronic device and / or using other mechanical or chemical attachment mechanisms.
[0041] As shown at 1106 in FIG. 11 , the manufacturing flow 1100 may also include processing the second substrate 112 after securing the component to the electronic device to reduce its thickness, thereby reducing the thickness of the component. For example, after securing the component 110 to the mounting surface 20 of the device 10, the first surface 114 of the second substrate 112 may be processed, such as by grinding, to change the height or thickness of the component 100. Thus, the height or thickness of the component 100 may be varied within the circuit to achieve a desired or required dimension. The final thickness of the component 100 may be in the range of about 2 mils to about 40 mils, such as in the range of about 3 mils to about 20 mils, or in the range of about 4 mils to about 12 mils.
[0042] (application) Various embodiments of components with reduced height as disclosed herein may have a variety of applications. For example, a sandwich component with reduced height as described herein may be a filter for high frequency applications, such as filtering high frequency signals in high frequency wireless signal communications, for example, to improve data transmission rates for wireless connections within the 5G spectrum or at higher frequencies. Of course, components with reduced height as described herein may be types of components other than filters and may be used for applications other than those described herein.
[0043] These and other modifications and variations of the present invention may be implemented by those skilled in the art without departing from the scope of the present invention. Furthermore, it should be understood that the various embodiments may be interchanged in whole or in part. Furthermore, those skilled in the art will appreciate that the foregoing description is for illustrative purposes only and is not intended to limit the present invention as further described in the appended claims.
Claims
1. providing a first substrate having a first surface, a second surface opposite the first surface along a height direction, and an initial thickness from the first surface to the second surface along the height direction; forming one or more vias in the first substrate, each via of the one or more vias extending from the first surface of the first substrate to the second surface of the first substrate; depositing one or more conductive paths on the first surface of the first substrate; plating the one or more vias; disposing a second substrate on the first surface of the first substrate to form a sandwich component; treating the second surface of the first substrate to reduce a thickness of the sandwich component and define a treated second surface of the first substrate; and forming one or more contact pads on the treated second surface of the first substrate; A method of forming a part, comprising:
2. the thickness of the sandwich component is less than about 40 mils; A method for forming the component of claim 1.
3. the sandwich component has a thickness of less than about 20 mils; A method for forming the component of claim 2.
4. forming one or more vias in the first substrate includes drilling each via of the one or more vias; A method for forming the component of claim 1.
5. treating the second surface of the first substrate comprises grinding the second surface of the first substrate. A method for forming the component of claim 1.
6. forming one or more vias includes forming a first via extending from a first end of the first surface of the first substrate to a second end of the second surface of the first substrate, and a second via extending from the first end of the first surface of the first substrate to a second end of the second surface of the first substrate; A method for forming the component of claim 1.
7. depositing one or more conductive paths includes depositing a first conductive path extending from the first end of the first via to the first end of the second via; A method for forming the component of claim 6.
8. each via of the one or more vias and the plating of each via of the one or more vias are exposed along the treated second surface; forming the one or more contact pads includes forming a first contact pad in electrical contact with the first via and a second contact pad in electrical contact with the second via; A method for forming the component of claim 7.
9. forming one or more vias includes forming a third via extending from a first end of the first surface of the first substrate to a second end of the second surface of the first substrate, and a fourth via extending from the first end of the first surface of the first substrate to a second end of the second surface of the first substrate; depositing one or more conductive paths includes depositing a second conductive path extending from the first end of the third via to the first end of the fourth via; forming one or more compact pads includes forming a third contact pad in electrical contact with the third via and a fourth contact pad in electrical contact with the fourth via; A method for forming the component of claim 8.
10. The component is configured to be placed on a mounting surface of an electronic device. A method for forming the component of claim 1.
11. The component is configured to be embedded within an electronic device. A method for forming the component of claim 1.
12. the second substrate is configured to be treated to further reduce the thickness of the sandwich component. A method for forming the component of claim 1.
13. the second substrate is configured to be polished to further reduce the thickness of the sandwich component. A method for forming the component of claim 1.
14. providing a first substrate having a first surface, a second surface opposite the first surface along a height direction, and an initial thickness from the first surface to the second surface along the height direction; depositing one or more conductive paths on the first surface of the first substrate, at least one of the one or more conductive paths extending through the first substrate from the first surface to the second surface; a second substrate is disposed on the first substrate, the second substrate having a first surface, a second surface opposite the first surface along a height direction, and an initial thickness from the first surface to the second surface along the height direction, the second surface of the second substrate being disposed opposite the first surface of the first substrate; treating the second surface of the first substrate to reduce the initial thickness of the first substrate to a treatment thickness; A method of forming a part, comprising:
15. forming one or more vias in the first substrate prior to depositing one or more conductive paths, each via passing through the first substrate from the first surface of the first substrate to the second surface of the first substrate; The method of forming a part of claim 14 further comprising:
16. depositing the one or more conductive paths comprises plating at least one of the one or more vias.
16. A method of forming the component of claim 15.
17. forming one or more contact pads on the second surface of the first substrate after processing the second surface of the first substrate, each contact pad contacting at least one conductive path on the second surface of the first substrate; The method of forming a part of claim 14 further comprising:
18. Treating the second surface of the first substrate includes grinding the second surface of the first substrate to define a treated second surface. A method of forming the component of claim 14.
19. A part, a first substrate having a first surface and a second surface opposite the first surface; one or more vias defined in the first substrate, each via of the one or more vias extending from the first surface of the first substrate to the second surface of the first substrate, the one or more vias including a first via and a second via, the one or more vias comprising a conductive material; one or more conductive paths on the first surface of the first substrate, the one or more conductive paths including a first conductive path extending from the first via to the second via; one or more contact pads formed on the second surface of the first substrate, each contact pad surrounding a respective one of the one or more vias on the second surface such that each contact pad of the one or more contact pads is in electrical contact with a respective one of the vias; a second substrate having a first surface and a second surface opposite the first surface, the second substrate being disposed on the first substrate such that the second surface of the second substrate is disposed in contact with the first surface of the first substrate; Equipped with The part has a thickness of less than about 40 mils.
20. the part has a thickness of less than about 20 mils; 20. The component of claim 19.
21. each via of the one or more vias being plated with a conductive material to electrically connect the one or more conductive paths with the one or more contact pads; 20. The component of claim 19.
22. the one or more contact pads include a first contact pad surrounding the first via and in electrical contact with the first via, and a second contact pad surrounding the second via and in electrical contact with the second via; 20. The component of claim 19.
23. the one or more vias include a third via and a fourth via; the one or more conductive paths include a second conductive path extending from the third via to the fourth via; 20. The component of claim 19.
24. the one or more contact pads include a third contact pad surrounding the third via and in electrical contact with the third via, and a fourth contact pad surrounding the fourth via and in electrical contact with the fourth via; 24. The component of claim 23.
25. the second substrate is configured to be processed to reduce the thickness of the component; 20. The component of claim 19.
26. the thickness of the first substrate is in the range of about 2 mils to about 20 mils; the second substrate has a thickness in the range of about 5 mils to about 40 mils before processing the second substrate to reduce the thickness of the component; 26. The component of claim 25.
27. the second substrate is configured to be polished to reduce the thickness of the component; 26. The component of claim 25.
28. 1. A method of assembling components on an electronic device, comprising: Providing parts, Equipped with The part is a first substrate having a first surface and a second surface opposite the first surface; one or more vias defined in the first substrate, each via of the one or more vias extending from the first surface of the first substrate to the second surface of the first substrate, the one or more vias including a first via and a second via, the one or more vias being plated with a conductive material; one or more conductive paths on the first surface of the first substrate, the one or more conductive paths including a first conductive path extending from the first via to the second via; one or more contact pads formed on the second surface of the first substrate, each contact pad surrounding a respective one of the one or more vias on the second surface and each contact pad being in electrical contact with a respective one of the vias; a second substrate having a first surface and a second surface opposite the first surface, the second substrate being disposed on the first substrate such that the second surface of the second substrate is disposed in contact with the first surface of the first substrate; Equipped with the part has a thickness of less than about 40 mils; fastening the component to the electronic device; and treating the second substrate to reduce a thickness of the second substrate; 1. A method for assembling components on an electronic device, comprising: