A package comprising an integrated device and a metallization portion having a variable-thickness metallization interconnect on the same metal layer.

Abstract

A package comprising an integrated device and a metallization portion. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprises a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect has a first thickness. The second metallization interconnect has a second thickness different from the first thickness. The package may include a substrate and / or a bridge. The substrate may include an interposer.

Description

Technical Field

[0001] (Cross - reference to Related Applications) This application claims the priority and benefit of U.S. Provisional Application No. 63 / 491,985, filed with the United States Patent and Trademark Office on March 24, 2023, and U.S. Non - Provisional Application No. 18 / 460,471, filed with the United States Patent and Trademark Office on September 1, 2023, and the entire contents of both applications are incorporated herein by reference as if they were fully described herein in their entirety and for all applicable purposes.

[0002] Various features relate to packages that include an integrated device and a metallization portion.

Background Art

[0003] The package can include a package substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. How the integrated device and the package substrate are coupled together affects how the package functions as a whole. There is a continuing need to provide better - performing packages.

Summary of the Invention

[0004] Various features relate to packages that include an integrated device and a package substrate.

[0005] One embodiment provides a package that includes an integrated device, a substrate coupled to the integrated device via at least a first plurality of solder interconnects, and a metallization portion coupled to the substrate via at least a second plurality of solder interconnects. The metallization portion includes at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects includes a first metallization interconnect located on a first metal layer and having a first thickness, and a second metallization interconnect located on the first metal layer and having a second thickness different from the first thickness.

[0006] Another example provides a package comprising a first integrated device, a second integrated device, a bridge coupled to the first and second integrated devices, and a metallization portion coupled to the first and second integrated devices. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects include a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect has a first thickness. The second metallization interconnect has a second thickness different from the first thickness.

[0007] By reading the "Modes for Carrying Out the Invention" described below in conjunction with the drawings, various features, essences, and advantages can be revealed. In the drawings, the same reference numerals throughout indicate corresponding elements. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view of an exemplary package comprising an integrated device and a metallization portion. [Figure 2] This is a cross-sectional view of an exemplary package comprising an integrated device and a metallization portion. [Figure 3] This is a cross-sectional view of an exemplary package comprising an integrated device and a metallization portion. [Figure 4] This is a cross-sectional view of an exemplary package comprising a first integrated device, a second integrated device, and a metallization portion. [Figure 5A] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5B] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5C] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5D] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5E] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5F] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5G] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 5H] This figure shows an exemplary sequence for fabricating a package comprising an integrated device and a metallization portion. [Figure 6] This is an illustrative flowchart of a method for fabricating a package comprising an integrated device and a metallization portion. [Figure 7] This is a cross-sectional view of an exemplary package comprising an integrated device, an interposer, and a metallization portion. [Figure 8] This is a cross-sectional view of an exemplary package comprising a first integrated device, a second integrated device, a bridge, and a metallization portion. [Figure 9A] This figure shows an exemplary sequence for fabricating a package comprising integrated devices, bridges, and metallization components. [Figure 9B] This figure shows an exemplary sequence for fabricating a package comprising integrated devices, bridges, and metallization components. [Figure 9C] This figure shows an exemplary sequence for fabricating a package comprising integrated devices, bridges, and metallization components. [Figure 10]This is an illustrative flowchart of a method for fabricating a package comprising integrated devices, bridges, and metallization components. [Figure 11] This figure shows various electronic devices that can integrate dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages as described herein. [Modes for carrying out the invention]

[0009] The following description includes specific details to provide a complete understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of this disclosure.

[0010] This disclosure describes a package comprising an integrated device, a substrate coupled to the integrated device via at least a plurality of first solder interconnects, and a metallization portion coupled to the substrate via at least a plurality of second solder interconnects. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects include a first metallization interconnect located on a first metal layer and having a first thickness, and a second metallization interconnect located on the first metal layer and having a second thickness different from the first thickness.

[0011] In some implementations, a package includes a first integrated device, a second integrated device, a bridge coupled to the first integrated device and the second integrated device, and a metallization portion coupled to the first integrated device and the second integrated device. The metallization portion includes at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects includes a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect has a first thickness. The second metallization interconnect has a second thickness different from the first thickness.

[0012] As further described below, using metallization interconnects having different thicknesses in the metallization portion provides several technical advantages, including the ability to customize and optimize the metallization interconnects for the type of signal and / or power that will travel through the metallization interconnects, which can help provide improved performance in the package.

[0013] Exemplary package comprising an integrated device and a metallization portion FIG. 1 shows a cross-sectional view of a package 100 that includes a metallization portion having metallization interconnects with different thicknesses. The package 100 is coupled to a board 108 via a plurality of solder interconnects 110. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB).

[0014] Package 100 includes a metallization portion 102, an integrated device 103, and a sealing layer 106. The integrated device 103 is coupled to a first surface of the metallization portion 102. The integrated device 103 can be a first integrated device. The integrated device 103 can include a bare die (e.g., a semiconductor bare die). The integrated device 103 is coupled to the metallization portion 102. A front surface of the integrated device 103 can face the metallization portion 102. The sealing layer 106 can seal the integrated device 103. The sealing layer 106 can be coupled to the first surface of the metallization portion 102. The sealing layer (e.g., 106) can include a molding, a resin, and / or an epoxy. The sealing layer can be a means for sealing. The sealing layer can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0015] The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The plurality of metallization interconnects 122 can include a first plurality of metallization interconnects 122a and a second plurality of metallization interconnects 122b. The first plurality of metallization interconnects 122a includes metallization interconnect 122aa, metallization interconnect 122ab, metallization interconnect 122ac, metallization interconnect 122ad, metallization interconnect 122ae, metallization interconnect 122af, metallization interconnect 122ag, and metallization interconnect 122ah. The second plurality of metallization interconnects 122b includes metallization interconnect 122ba, metallization interconnect 122bb, metallization interconnect 122bc, metallization interconnect 122bd, metallization interconnect 122be, metallization interconnect 122bf, metallization interconnect 122bg, and metallization interconnect 122bh.

[0016] The metallization interconnect 122aa is coupled to the metallization interconnect 122ab. The metallization interconnect 122ab is coupled to the metallization interconnect 122ac. The metallization interconnect 122ac is coupled to the metallization interconnect 122ad. The metallization interconnect 122ad is coupled to the metallization interconnect 122ae. The metallization interconnect 122ae is coupled to the metallization interconnect 122af. The metallization interconnect 122af is coupled to the metallization interconnect 122ag. The metallization interconnect 122ag is coupled to the metallization interconnect 122ah. The metallization interconnects 122aa, 122ac, 122ae, and 122ag may include metallization vias (e.g., via interconnects, metallization via interconnects). The metallization interconnects 122ab, 122ad, 122af, and 122ah may include metallization pads and / or metallization traces.

[0017] The metallization interconnect 122ba is connected to the metallization interconnect 122bb. The metallization interconnect 122bb is connected to the metallization interconnect 122bc. The metallization interconnect 122bc is connected to the metallization interconnect 122bd. The metallization interconnect 122bd is connected to the metallization interconnect 122be. The metallization interconnect 122be is connected to the metallization interconnect 122bf. The metallization interconnect 122bf is connected to the metallization interconnect 122bg. The metallization interconnect 122bg is connected to the metallization interconnect 122bh. The metallization interconnects 122ba, 122bc, 122be, and / or 122bg may include metallization vias (e.g., via interconnects, metallization via interconnects). The metallization interconnects 122bb, 122bd, 122bf, and / or 122bh may include metallization pads and / or metallization traces.

[0018] Figure 1 shows that several metallization interconnects on the same metal layer (e.g., M1, M2, M3, M4) may have different thicknesses, and / or metallization interconnects between the same metal layers may have different heights, widths, and / or diameters. Metallization interconnect 122aa may have a height HA1. Metallization interconnect 122ab may have a thickness TA1. Metallization interconnect 122ac may have a height HA2. Metallization interconnect 122ad may have a thickness TA2. Metallization interconnect 122ae may have a height HA3. Metallization interconnect 122af may have a thickness TA3. Metallization interconnect 122ag may have a height HA4. Metallization interconnect 122ah may have a thickness TA4.

[0019] The metallization interconnect 122ba may have a height HB1. The metallization interconnect 122bb may have a thickness TB1. The metallization interconnect 122bc may have a height HB2. The metallization interconnect 122bd may have a thickness TB2. The metallization interconnect 122be may have a height HB3. The metallization interconnect 122bf may have a thickness TB3. The metallization interconnect 122bg may have a height HB4. The metallization interconnect 122bh may have a thickness TB4.

[0020] Metallization interconnects 122ab and 122bb are located on the same metal layer (e.g., M1). The thickness of metallization interconnect 122ab (TA1) is smaller than the thickness of metallization interconnect 122bb (TB1). Metallization interconnects 122ad and 122bd are located on the same metal layer (e.g., M2). The thickness of metallization interconnect 122ad (TA2) is smaller than the thickness of metallization interconnect 122bd (TB2). Metallization interconnects 122af and 122bf are located on the same metal layer (e.g., M3). The thickness of metallization interconnect 122af (TA3) is smaller than the thickness of metallization interconnect 122bb (TB3). The metallization interconnect 122ah and the metallization interconnect 122bh are located on the same metal layer (e.g., M4). The thickness of the metallization interconnect 122ah (TA4) is approximately the same as the thickness of the metallization interconnect 122bh (TB4).

[0021] The metallization interconnect 122aa may have a height HA1 that is approximately the same as the height HB1 of the metallization interconnect 122ba. The metallization interconnect 122aa may have a width and / or diameter that is approximately the same as the width and / or diameter of the metallization interconnect 122ba. The metallization interconnect 122ac and the metallization interconnect 122bc may be located between the same metal layers (e.g., between M1 and M2). The metallization interconnect 122ac may have a height HA2 that is greater than the height HB2 of the metallization interconnect 122bc. The metallization interconnect 122ac may have a width and / or diameter that is smaller than the width and / or diameter of the metallization interconnect 122bc. The metallization interconnect 122ae and the metallization interconnect 122be may be located between the same metal layers (e.g., between M2 and M3). The metallization interconnect 122ae may have a height HA3 greater than the height HB3 of the metallization interconnect 122be. The metallization interconnect 122ae may have a width and / or diameter smaller than the width and / or diameter of the metallization interconnect 122be. The metallization interconnect 122ag and the metallization interconnect 122bg may be located between the same metal layers (e.g., between M3 and M4). The metallization interconnect 122ag may have a height HA4 greater than the height HB4 of the metallization interconnect 122bg. The metallization interconnect 122ag may have a width and / or diameter smaller than the width and / or diameter of the metallization interconnect 122bg.

[0022] For example, in some implementations, the minimum thickness (e.g., TA1, TA2, TA3, TA4) of one or more interconnects (e.g., 122ab, 122ad, 122af) may be in the range of approximately 5 to 10 micrometers. In some implementations, the minimum height (e.g., HA2, HA3, HA4) of one or more via interconnects (e.g., 122ac, 122ae, 122ag) may be in the range of approximately 7 to 20 micrometers. In some implementations, the minimum thickness (e.g., TB1, TB2, TB3, TB4) of one or more interconnects (e.g., 122bb, 122bd, 122bf) may be in the range of approximately 7 to 20 micrometers. In some implementations, the minimum height (e.g., HB2, HB3, HB4) of one or more via interconnects (e.g., 122bc, 122be, 122bg) may be in the range of approximately 5 to 15 micrometers. In some implementations, one or more interconnects (e.g., trace interconnects) may have a minimum width of approximately 2 micrometers.

[0023] It should be noted that the minimum thickness, minimum height, minimum width, and / or minimum diameter described above are illustrative. Different mounting configurations may have metallization interconnects with different thicknesses, heights, widths, and / or diameters (e.g., different minimum thicknesses, minimum heights, minimum widths, and / or minimum diameters). Furthermore, different mounting configurations may have metallization interconnects with different relative thicknesses, relative heights, relative widths, and / or relative diameters. In some mounting configurations, metallization interconnects on the same metal layer may have one metallization interconnect having a thickness of at least 1.2 times that of another metallization interconnect on the same layer. For example, metallization interconnect 122bb may have a thickness TB1 of at least 1.5 times that of metallization interconnect 122ab's thickness TA1.

[0024] In some implementations, it may be optimal, preferred, and / or more ideal to have thicker metallization interconnects to allow more current to flow with less resistance. For example, if a metallization interconnect is configured as an electrical path for power, it may be desirable to have a thicker metallization interconnect to reduce resistance in the electrical path, which may allow more power to move to the integrated device. In contrast, a metallization interconnect configured to provide an electrical path for signals (e.g., input / output (I / O) signals) may not need to be as large and / or thick, since the input / output signals operate at lower voltages, and therefore its dimensions (e.g., line width, line thickness) do not need to be as large as those of a metallization interconnect configured to provide an electrical path for power.

[0025] Therefore, the thickness and / or height of various metallization interconnects can be configured to be optimized for the type of current that will travel through the metallization interconnects within the metallization portion. In one example, a metallization interconnect configured to provide an electrical path for power may have a greater thickness and / or greater width and / or diameter than an interconnect configured to provide an electrical path for signals. In another example, a metallization interconnect configured to provide an electrical path for input / output signals may have the minimum possible thickness, width and / or diameter, and / or a smaller thickness, width and / or diameter than an interconnect configured to provide an electrical path for power and / or ground.

[0026] The integrated device 103 includes die interconnects 130a and 130b. The die interconnects 130a and / or 130b may be die pads for the integrated device 103. The die interconnect 130a is coupled to and in contact with the metallization interconnect 122aa of the metallization portion 102. The die interconnect 130b is coupled to and in contact with the metallization interconnect 122ba of the metallization portion 102.

[0027] The metallization interconnect 122ah may be coupled to and in contact with solder interconnects from multiple solder interconnects 110. The metallization interconnect 122bh may be coupled to and in contact with other solder interconnects from multiple solder interconnects 110.

[0028] In some implementation configurations, the electrical path between the board 108 and the integrated device 103 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 122a, and die interconnects 130a.

[0029] In some implementation configurations, the electrical path for input / output signals between the board 108 and the integrated device 103 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 122a, and die interconnects 130a.

[0030] In some implementation configurations, the electrical path for power or grounding between the board 108 and the integrated device 103 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 122b, and die interconnects 130a.

[0031] Figure 2 shows a cross-sectional view of package 200, which includes a metallization portion having metallization interconnects of different thicknesses. Package 200 is similar to package 100 and contains the same components as package 100. However, package 200 includes metallization interconnects having different combinations of thicknesses.

[0032] The package 200 includes a metallization portion 202, an integrated device 103, and a sealing layer 106. The integrated device 103 is bonded to a first surface of the metallization portion 202. The integrated device 103 may be a first integrated device. The integrated device 103 is bonded to the metallization portion 202. The front surface of the integrated device 103 may face the metallization portion 202. The sealing layer 106 may seal the integrated device 103. The sealing layer 106 may be bonded to a first surface of the metallization portion 202.

[0033] The metallization portion 202 includes at least one dielectric layer 220 and a plurality of metallization interconnects 222. The plurality of metallization interconnects 222 may include a first plurality of metallization interconnects 222a and a second plurality of metallization interconnects 222b. The first plurality of metallization interconnects 222a includes metallization interconnects 222aa, metallization interconnects 222ab, metallization interconnects 222ac, metallization interconnects 222ad, metallization interconnects 222ae, metallization interconnects 222af, metallization interconnects 222ag, and metallization interconnects 222ah. The second plurality of metallization interconnects 222b include metallization interconnects 222ba, 222bb, 222bc, 222bd, 222be, 222bf, 222bg, and 222bh.

[0034] Metallization interconnect 222aa is coupled to metallization interconnect 222ab. Metallization interconnect 222ab is coupled to metallization interconnect 222ac. Metallization interconnect 222ac is coupled to metallization interconnect 222ad. Metallization interconnect 222ad is coupled to metallization interconnect 222ae. Metallization interconnect 222ae is coupled to metallization interconnect 222af. Metallization interconnect 222af is coupled to metallization interconnect 222ag. Metallization interconnect 222ag is coupled to metallization interconnect 222ah. Metallization interconnect 222aa, metallization interconnect 222ac, metallization interconnect 222ae, and / or metallization interconnect 222ag may include metallization vias. The metallization interconnects 222ab, 222ad, 222af, and / or 222ah may include metallization pads and / or metallization traces.

[0035] Metallization interconnect 222ba is coupled to metallization interconnect 222bb. Metallization interconnect 222bb is coupled to metallization interconnect 222bc. Metallization interconnect 222bc is coupled to metallization interconnect 222bd. Metallization interconnect 222bd is coupled to metallization interconnect 222be. Metallization interconnect 222be is coupled to metallization interconnect 222bf. Metallization interconnect 222bf is coupled to metallization interconnect 222bg. Metallization interconnect 222bg is coupled to metallization interconnect 222bh. Metallization interconnect 222ba, metallization interconnect 222bc, metallization interconnect 222be, and / or metallization interconnect 222bg may include metallization vias. The metallization interconnects 222bb, 222bd, 222bf, and / or 222bh may include metallization pads and / or metallization traces.

[0036] Figure 2 shows that several metallization interconnects on the same metal layer (e.g., M1, M2, M3, M4) may have different thicknesses, and / or metallization interconnects between the same metal layers may have different heights, widths, and / or diameters. Metallization interconnect 222aa may have a height HA1. Metallization interconnect 222ab may have a thickness TA1. Metallization interconnect 222ac may have a height HA2. Metallization interconnect 222ad may have a thickness TA2. Metallization interconnect 222ae may have a height HA3. Metallization interconnect 222af may have a thickness TA3. Metallization interconnect 222ag may have a height HA4. Metallization interconnect 222ah may have a thickness TA4.

[0037] The metallization interconnect 222ba may have a height HB1. The metallization interconnect 222bb may have a thickness TB1. The metallization interconnect 222bc may have a height HB2. The metallization interconnect 222bd may have a thickness TB2. The metallization interconnect 222be may have a height HB3. The metallization interconnect 222bf may have a thickness TB3. The metallization interconnect 222bg may have a height HB4. The metallization interconnect 222bh may have a thickness TB4.

[0038] Metallization interconnects 222ab and 222bb are located on the same metal layer (e.g., M1). The thickness of metallization interconnect 222ab (TA1) is smaller than the thickness of metallization interconnect 222bb (TB1). Metallization interconnects 222ad and 222bd are located on the same metal layer (e.g., M2). The thickness of metallization interconnect 222ad (TA2) is smaller than the thickness of metallization interconnect 222bd (TB2). Metallization interconnects 222af and 222bf are located on the same metal layer (e.g., M3). The thickness of metallization interconnect 222af (TA3) is smaller than the thickness of metallization interconnect 222bb (TB3). The metallization interconnect 222ah and the metallization interconnect 222bh are located on the same metal layer (e.g., M4). The thickness of the metallization interconnect 222ah (TA4) is approximately the same as the thickness of the metallization interconnect 222bh (TB4).

[0039] The metallization interconnect 222aa may have a height HA1 that is approximately the same as the height HB1 of the metallization interconnect 222ba. The metallization interconnect 222aa may have a width and / or diameter that is approximately the same as the width and / or diameter of the metallization interconnect 222ba. The metallization interconnect 222ac and the metallization interconnect 222bc may be located between the same metal layers (e.g., between M1 and M2). The metallization interconnect 222ac may have a height HA2 that is greater than the height HB2 of the metallization interconnect 222bc. The metallization interconnect 222ac may have a width and / or diameter that is smaller than the width and / or diameter of the metallization interconnect 222bc. The metallization interconnect 222ae and the metallization interconnect 222be may be located between the same metal layers (e.g., between M2 and M3). The metallization interconnect 222ae may have a height HA3 greater than the height HB3 of the metallization interconnect 222be. The metallization interconnect 222ae may have a width and / or diameter smaller than the width and / or diameter of the metallization interconnect 222be. The metallization interconnect 222ag and the metallization interconnect 222bg may be located between the same metal layers (e.g., between M3 and M4). The metallization interconnect 222ag may have a height HA4 greater than the height HB4 of the metallization interconnect 222bg. The metallization interconnect 222ag may have a width and / or diameter smaller than the width and / or diameter of the metallization interconnect 222bg. For example, the first via metallization interconnect (e.g., 222ac) may include a first minimum diameter, and the second via metallization interconnect (e.g., 222bc) may include a second minimum diameter that is larger than the first minimum diameter.

[0040] Figure 2 shows that the relative thickness of a metallization interconnect to another metallization interconnect on the same metal layer may differ for different metal layers. For example, for a first metal layer (e.g., M1) of the metallization portion 202, the metallization interconnect 222bb may have a thickness TB1 that is at least 1.2 times the thickness TA1 of the metallization interconnect 222ab. In another example, for a second metal layer (e.g., M2) of the metallization portion 202, the metallization interconnect 222bd may have a thickness TB2 that is at least 1.5 times the thickness TA2 of the metallization interconnect 222ad. In yet another example, for a third metal layer (e.g., M3) of the metallization portion 202, the metallization interconnect 222bf may have a thickness TB3 that is at least 2 times the thickness TA3 of the metallization interconnect 222af. In another example, with respect to the fourth metal layer (e.g., M4) of the metallization portion 202, the metallization interconnect 222bh may have a thickness TB4 that is approximately the same as the thickness TA4 of the metallization interconnect 222ah. However, it should be noted that the above thickness, height, width, and / or diameter are illustrative. Different mounting configurations may have metallization interconnects with different thicknesses, different heights, different widths, and / or different diameters. Furthermore, different mounting configurations may have metallization interconnects with different relative thicknesses, relative heights, relative widths, and / or relative diameters.

[0041] Figure 3 shows an exemplary electrical path for package 200. For example, Figure 3 shows electrical paths 302 between the integrated device 103 and the board 108, electrical paths 304 between the integrated device 103 and the board 108, and electrical paths 306 between the integrated device 103 and the board 108. Electrical path 302 between the integrated device 103 and the board 108 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 222a, and die interconnects 130a. Electrical path 302 may be configured to provide electrical paths for input / output signals.

[0042] The electrical path 304 between the integrated device 103 and the board 108 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallization interconnects 222b, and a die interconnect 130b. The electrical path 304 may be configured to provide an electrical path for power or grounding.

[0043] The electrical path 306 between the integrated device 103 and the board 108 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a third plurality of metallization interconnects 222c, and a die interconnect 130c. The electrical path 306 may be configured to provide an electrical path for power or grounding. The third plurality of metallization interconnects 222c may be similar to the second plurality of metallization interconnects 222b in that they have metallization interconnects of different thicknesses on the same metal layer.

[0044] Figure 4 shows a package including a metallization portion having metallization interconnects of different thicknesses. Package 400 includes a metallization portion 402, an integrated device 403, an integrated device 405, and a sealing layer 106. Integrated device 403 is bonded to a first surface of the metallization portion 402. Integrated device 405 is bonded to a first surface of the metallization portion 402. Integrated device 403 may include a bare die (e.g., a semiconductor bare die). Integrated device 405 may include a bare die (e.g., a semiconductor bare die). Integrated device 403 may be a first integrated device (e.g., a first chiplet), and integrated device 405 may be a second integrated device (e.g., a second chiplet). Integrated devices 403 and 405 are bonded to and in contact with the metallization portion 402. The front surface of integrated device 403 may face the metallization portion 402. The front surface of the integrated device 405 may face the metallization portion 402. The sealing layer 106 may seal the integrated device 403 and the integrated device 405. The sealing layer 106 may be bonded to the first surface of the metallization portion 402. The integrated device 403 may be configured to perform a first set of functions and / or operations. The integrated device 405 may be configured to perform a second set of functions and / or operations. The second set of functions and / or operations includes at least one function and / or operation that is different from the first set of functions and / or operations.

[0045] The metallization portion 402 includes at least one dielectric layer 420 and a plurality of metallization interconnects 422. The plurality of metallization interconnects 422 may include a first plurality of metallization interconnects 422a, a second plurality of metallization interconnects 422b, a third plurality of metallization interconnects 422c, and a fourth plurality of metallization interconnects 422d.

[0046] The first plurality of metallization interconnects 422a may be the same as the first plurality of metallization interconnects 122a and / or the first plurality of metallization interconnects 222a. The third plurality of metallization interconnects 422c may be the same as the first plurality of metallization interconnects 122a and / or the first plurality of metallization interconnects 222a. The second plurality of metallization interconnects 422b may be the same as the second plurality of metallization interconnects 122b and / or the second plurality of metallization interconnects 222b. The fourth plurality of metallization interconnects 422d may be the same as the second plurality of metallization interconnects 122b and / or the second plurality of metallization interconnects 222b.

[0047] Figure 4 shows exemplary electrical paths for the package, including electrical paths 401, 404, 412, and 414. The electrical path between the integrated device 403 and the board 108 may include electrical path 401. Electrical path 401 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 422a, and a first die interconnect from the integrated device 403. Electrical path 401 may be configured to provide electrical paths for input / output signals.

[0048] The electrical path between the integrated device 403 and the board 108 may include an electrical path 404. The electrical path 404 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallization interconnects 422b, and a second die interconnect from the integrated device 403. The electrical path 404 may be configured to provide an electrical path for power or grounding.

[0049] The electrical path between the integrated device 405 and the board 108 may include an electrical path 412. The electrical path 412 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a third plurality of metallization interconnects 422c, and a first die interconnect from the integrated device 405. The electrical path 412 may be configured to provide an electrical path for input / output signals.

[0050] The electrical path between the integrated device 405 and the board 108 may include an electrical path 414. The electrical path 414 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a fourth plurality of metallization interconnects 422d, and a second die interconnect from the integrated device 405. The electrical path 414 may be configured to provide an electrical path for power or grounding.

[0051] The electrical path 416 between the integrated device 405 and the integrated device 403 may include a die interconnect from the integrated device 405, at least one metallization interconnect from a plurality of metallization interconnects 422, and a die interconnect from the integrated device 403.

[0052] The metallization portion may include a redistribution portion, which includes a redistribution interconnect (e.g., a redistribution layer (RDL) interconnect). The redistribution interconnect may include a portion having a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or redistribution interconnect. A U-shaped interconnect (e.g., an interconnect of a U-shaped side profile) and a V-shaped interconnect (e.g., an interconnect of a V-shaped side profile) may have an upper portion and a lower portion. The lower portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the upper portion of another U-shaped interconnect (or V-shaped interconnect).

[0053] Integrated devices (e.g., 103, 403, 405) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors, and / or combinations thereof. An integrated device (e.g., 103, 403, 405) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include a transistor. An integrated device can be an example of an electrical component and / or electrical device. In some implementations, an integrated device can be a chiplet. Chiplets can be manufactured using processes that yield better results compared to other processes used to manufacture other types of integrated devices, thereby reducing the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect density (e.g., interconnects with different widths and / or spacing). In some implementations, several chiplets can be used to perform the functions of one or more chips (e.g., one or more integrated devices).As described above, using several chiplets that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some implementations, one or more of the chiplets described herein and / or one or more of the integrated devices (e.g., 103, 403, 405) may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 403) may be fabricated using a first technology node, and a chiplet (e.g., 405) may be fabricated using a second technology node that is less advanced than the first technology node. In such an example, an integrated device (e.g., 403) may include components (e.g., interconnects, transistors) having a first minimum size, and a chiplet (e.g., 405) may include components (e.g., interconnects, transistors) having a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, the integrated device 403 and integrated device 405 of the package may be fabricated using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet of the package may be fabricated using the same technology node or different technology nodes.

[0054] A technology node can refer to a specific fabrication process and / or technology used to manufacture an integrated device and / or chiplet. A technology node can specify the smallest possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. A technology node that produces highly detailed components (e.g., traces, transistors) may be more expensive and have a higher yield loss than a technology node that produces less detailed components (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and have a higher yield loss than less advanced technology nodes. If all the functionality of a package is implemented within a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some of the functionality of the integrated device does not need to be manufactured using that particular technology node. Thus, the integrated device is locked to one technology node. To optimize the cost of the package, some of the functionality may be implemented within different integrated devices and / or chiplets that can be manufactured using different technology nodes to reduce the overall cost. For example, functions requiring the use of a state-of-the-art technology node may be implemented within an integrated device, while functions that can be implemented using less advanced technology nodes may be implemented within a separate integrated device and / or one or more chiplets. One example is an integrated device fabricated using a first technology node (e.g., a state-of-the-art technology node) configured to provide a computing application, and at least one chiplet fabricated using a second technology node configured to provide other functionality, wherein the second technology node is less expensive than the first technology node, and the second technology node fabricates components whose minimum size is larger than the minimum size of components fabricated using the first technology node.Examples of computing applications may include high-performance computing and / or high-performance processing, which can be achieved by fabricating and packing as many transistors as possible in an integrated device, because other chiplets may not require as many transistors as those fabricated in the chiplet, and therefore, while integrated devices configured for computing applications can be fabricated using the most advanced technology nodes available, these chiplets can be fabricated using less advanced technology nodes. Thus, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0055] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each integrated device and / or chiplet individually. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and / or differently configured first integrated device. This saves costs by eliminating the need to redesign the first chiplet when creating a package with an improved integrated device.

[0056] Exemplary sequence for fabricating a package comprising an integrated device and a metallization portion Figures 5A to 5H show exemplary sequences for providing or fabricating a package that includes an integrated device and a metallization portion having metallization interconnects of different thicknesses. In some implementations, the sequences in Figures 5A to 5H may be used to provide or fabricate package 200 of Figure 2, or any of the packages described herein.

[0057] It should be noted that the sequences in Figures 5A to 5H may be a combination of one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. The sequences in Figures 5A to 5H may be used to manufacture one package, or several packages simultaneously, (as part of a wafer).

[0058] Stage 1 shows the state after the carrier 500 and adhesive coat 501 have been provided, as shown in Figure 5A. The adhesive coat 501 may be an adhesive layer located on the surface of the carrier 500.

[0059] Stage 2 shows the state after the integrated device 103 has been placed on the carrier 500 and adhesive coat 501. A pick-and-place process may be used to place the integrated device. The front surface of the integrated device 103 may be placed on the carrier 500 and adhesive coat 501. In some implementation configurations, two or more integrated devices (e.g., 403, 405) may be placed on the carrier 500 and adhesive coat 501.

[0060] Stage 3 shows the state after the carrier 500, adhesive coat 501, and sealing layer 106 have been formed on the integrated device 103. The sealing layer 106 can seal the integrated device 103. The sealing layer 106 may include molded articles, resins, and / or epoxy. The sealing layer 106 may be a means for sealing. The sealing layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, once the sealing layer 106 has been provided, a portion of the sealing layer 106 may be removed. For example, a grinding process may be used to remove the top of the sealing layer 106 and / or the back surface of the integrated device 103.

[0061] Stage 4 shows the state after the carrier 500 and adhesive coating 501 have been separated from the integrated device 103 and the encapsulation layer 106. The carrier 500 and adhesive coating 501 can be removed from the integrated device 103 and the encapsulation layer 106.

[0062] Step 5 shows the integrated device 103 and encapsulation layer 106 placed on the carrier 502, as shown in Figure 5B. The back surface of the integrated device 103 may be placed on the carrier 502 and bonded. An adhesive coat similar to the adhesive coat 501 may be present on the carrier 502. A pick-and-place process may be used to place the integrated device 103 and encapsulation layer 106 on the carrier 502.

[0063] Stage 6 shows the state after the dielectric layer 510 has been formed on the integrated device 103 and the sealing layer 106. A deposition and / or lamination process may be used to form the dielectric layer 510. The dielectric layer 510 may be formed on the front surface of the integrated device 103.

[0064] Step 7 shows the state after multiple cavities 511 have been formed in the dielectric layer 510. The multiple cavities 511 may be formed using an etching process (e.g., a photoetching process). Masking, exposure, and / or development processes may be used to form the multiple cavities 511. The multiple cavities 511 may be formed on the multiple die interconnects 130 of the integrated device 103 such that multiple die interconnects 130 are exposed (or at least a portion of multiple die interconnects 130 are exposed).

[0065] Step 8 shows the state after metallization interconnects have been formed in and on the dielectric layer 510 and on its surface, and within the plurality of cavities 511. A plurality of metallization interconnects 512 may be formed on (e.g., above) the first surface of the dielectric layer 510 and the plurality of cavities 511. Masking, plating, exposure, development, and / or etching processes may be used to form the plurality of metallization interconnects 512.

[0066] Step 9 shows the state after the photoresist layer 513 has been formed on the dielectric layer 510, as shown in Figure 5C. A deposition process and / or a lamination process may be used to form the photoresist layer 513. The photoresist layer 513 may include openings on some of the metallization interconnects from the multiple metallization interconnects 512.

[0067] Step 10 shows the state after some of the metallization interconnects from the multiple metallization interconnects 512 have been thickened to form multiple metallization interconnects 514. Masking, plating, exposure, development, and / or etching processes may be used to form the multiple metallization interconnects 514. As a result, several metallization interconnects on the same metal layer may have different thicknesses.

[0068] Step 11 shows the state after the photoresist layer 513 has been removed. An etching process may be used to remove the photoresist layer 513.

[0069] Step 12 shows the state after the dielectric layer 520 has been formed on the dielectric layer 510, the plurality of metallization interconnects 512, and the plurality of metallization interconnects 514. A deposition and / or lamination process may be used to form the dielectric layer 520. The dielectric layer 520 may be similar to the dielectric layer 510.

[0070] Step 13 shows the state after multiple cavities 521 have been formed in the dielectric layer 520. The multiple cavities 521 may be formed using an etching process (e.g., a photoetching process). Masking, exposure, and / or development processes may be used to form the multiple cavities 521.

[0071] Step 14 shows the state after metallization interconnects have been formed in and on the dielectric layer 520 and within the plurality of cavities 521. A plurality of metallization interconnects 522 may be formed on (e.g., above) the first surface of the dielectric layer 520 and the plurality of cavities 521. Masking, plating, exposure, development, and / or etching processes may be used to form the plurality of metallization interconnects 522.

[0072] Step 15 shows the state after the photoresist layer 523 has been formed on the dielectric layer 520. A deposition process and / or a lamination process may be used to form the photoresist layer 523. The photoresist layer 523 may include openings on some of the metallization interconnects from the multiple metallization interconnects 522.

[0073] Step 16 shows the state after some of the metallization interconnects from the multiple metallization interconnects 522 have been thickened to form multiple metallization interconnects 524. Masking, plating, exposure, development, and / or etching processes may be used to form the multiple metallization interconnects 524. As a result, several metallization interconnects on the same metal layer may have different thicknesses.

[0074] Step 17 shows the state after the photoresist layer 523 has been removed, as shown in Figure 5E. An etching process may be used to remove the photoresist layer 523.

[0075] Step 18 shows the state after the dielectric layer 530 has been formed on the dielectric layer 520, the multiple metallization interconnects 522, and the multiple metallization interconnects 524. A deposition and / or lamination process may be used to form the dielectric layer 530. The dielectric layer 530 may be similar to the dielectric layer 520.

[0076] Step 19 shows the state after multiple cavities 531 have been formed in the dielectric layer 530. The multiple cavities 531 may be formed using an etching process (e.g., a photoetching process). Masking, exposure, and / or development processes may be used to form the multiple cavities 531.

[0077] Step 20 shows the state after metallization interconnects have been formed in and on the dielectric layer 530 and within the multiple cavities 531, as shown in Figure 5F. Multiple metallization interconnects 532 may be formed on (e.g., above) the first surface of the dielectric layer 530 and the multiple cavities 531. Masking, plating, exposure, development, and / or etching processes may be used to form the multiple metallization interconnects 532.

[0078] Step 21 shows the state after the photoresist layer 533 has been formed on the dielectric layer 530. A deposition process and / or a lamination process may be used to form the photoresist layer 533. The photoresist layer 533 may include openings on some of the metallization interconnects from a plurality of metallization interconnects 532.

[0079] Step 22 shows the state after some of the metallization interconnects from the multiple metallization interconnects 532 have been thickened to form multiple metallization interconnects 534. Masking, plating, exposure, development, and / or etching processes may be used to form the multiple metallization interconnects 534. As a result, several metallization interconnects on the same metal layer may have different thicknesses.

[0080] Step 23 shows the state after the photoresist layer 533 has been removed, as shown in Figure 5G. An etching process may be used to remove the photoresist layer 533.

[0081] Step 24 shows the state after the dielectric layer 540 has been formed on the dielectric layer 530, the multiple metallization interconnects 532, and the multiple metallization interconnects 534. A deposition and / or lamination process may be used to form the dielectric layer 540. The dielectric layer 540 may be similar to the dielectric layer 530.

[0082] Step 25 shows the state after multiple cavities 541 have been formed in the dielectric layer 540. The multiple cavities 541 may be formed using an etching process (e.g., a photoetching process). Masking, exposure, and / or development processes may be used to form the multiple cavities 541.

[0083] Step 26 shows the state after metallization interconnects have been formed in and on the dielectric layer 540 and within the multiple cavities 541, as shown in Figure 5H. Multiple metallization interconnects 542 may be formed on (e.g., above) the first surface of the dielectric layer 540 and the multiple cavities 541. Masking, plating, exposure, development, and / or etching processes may be used to form the multiple metallization interconnects 542.

[0084] Step 27 shows the state after the carrier 502 has been separated from the integrated device 103 and the encapsulation layer 106. The carrier 502 can be removed from the integrated device 103 and the encapsulation layer 106. At least one dielectric layer 220 may represent dielectric layer 510, dielectric layer 520, dielectric layer 530, and / or dielectric layer 540. Multiple metallization interconnects 222 may represent multiple metallization interconnects 512, multiple metallization interconnects 514, multiple metallization interconnects 522, multiple metallization interconnects 524, multiple metallization interconnects 532, multiple metallization interconnects 534, multiple metallization interconnects 542, and / or multiple metallization interconnects 544. The multiple metallization interconnects 222 may include a first plurality of metallization interconnects 222a and a second plurality of metallization interconnects 222b, as described in at least Figures 2 and 3 of this disclosure.

[0085] Step 28 shows the state after the multiple solder interconnects 110 have been joined to the metallization portion 202. A solder reflow process may be used to join the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0086] Illustrative flowchart of a method for fabricating a package comprising an integrated device and a metallization portion. In some implementations, creating a package involves several processes. Figure 6 shows an illustrative flowchart of a method 600 for providing or creating a package. In some implementations, the method 600 of Figure 6 may be used to provide or create any of the packages of this disclosure. For example, the method 600 of Figure 6 may be used to create package 200.

[0087] It should be noted that Method 600 in Figure 13 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. Method 600 in Figure 6 may be used to manufacture one package or several packages at once (as part of a wafer).

[0088] The method involves providing a carrier (in 605). In some implementations, the carrier may be provided with an adhesive. Step 1 in Figure 5A illustrates and describes an example of providing a carrier 500 and an adhesive coat 501. The adhesive coat 501 may be an adhesive layer located on the surface of the carrier 500.

[0089] The method involves placing the front of the integrated device on the carrier (in 610). In some implementations, the front of the integrated device is placed on a carrier containing adhesive. In some implementations, two or more integrated devices may be placed on the carrier. Step 2 in Figure 5A illustrates an example of an integrated device 103 placed on the carrier 500 and adhesive coat 501. A pick-and-place process may be used to place the integrated devices. The front of the integrated device 103 may be placed on the carrier 500 and adhesive coat 501. In some implementations, two or more integrated devices (e.g., 403, 405) may be placed on the carrier 500 and adhesive coat 501.

[0090] The method involves forming a sealing layer that seals the integrated device (in 615). The sealing layer may be bonded to the integrated device and the carrier. Step 3 in Figure 5A illustrates an example of a sealing layer 106 formed on the carrier 500, the adhesive coat 501, and the integrated device 103. The sealing layer 106 may seal the integrated device 103. The sealing layer 106 may include molded articles, resins, and / or epoxy. The sealing layer 106 may be a means for sealing. The sealing layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, once the sealing layer 106 is provided, a portion of the sealing layer 106 may be removed. For example, a grinding process may be used to remove the top of the sealing layer 106 and / or the back surface of the integrated device 103.

[0091] The method involves separating the carrier (at 620) from the encapsulation layer and the integrated device. Step 4 in Figure 5A illustrates an example of the carrier 500 and adhesive coating 501 separated from the integrated device 103 and the encapsulation layer 106. The carrier 500 and adhesive coating 501 can be removed from the integrated device 103 and the encapsulation layer 106.

[0092] The method involves (in 625) placing the back surface of the integrated device and the encapsulation layer on another carrier (e.g., a second carrier). The carrier may contain an adhesive. Step 5 in Figure 5B illustrates an example of an integrated device 103 and encapsulation layer 106 placed on a carrier 502. The back surface of the integrated device 103 may be placed on and bonded to the carrier 502. An adhesive coat similar to the adhesive coat 501 may be present on the carrier 502. A pick-and-place process may be used to place the integrated device 103 and encapsulation layer 106 on the carrier 502.

[0093] The method (in 630) forms a metallization portion to be coupled to the front surface and sealing layer of the integrated device. The metallization portion may include at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects may include a first metallization interconnect on a first metal layer and a second metallization interconnect on the first metal layer, the second interconnect having a second thickness different from the first thickness of the first metallization interconnect. Forming the metallization portion may include forming at least one dielectric layer and forming the first metallization interconnect on the first metal layer and the second metallization interconnect on the first metal layer. The second interconnect may have a second thickness different from the first thickness of the first metallization interconnect. Steps 6 in Figure 5B to 26 in Figure 5H show an example of forming a metallization portion to be coupled to at least one integrated device. Different mounting configurations may have different numbers of metal layers. (At 630) Once the metallization portion is formed, the method can separate the second carrier from the integrated device and the encapsulation layer. Step 27 in Figure 5H shows an example of separating the second carrier.

[0094] The method involves connecting multiple solder interconnects (in 635) to the metallization interconnects of the metallization portion. Step 28 in Figure 5H illustrates an example of multiple solder interconnects 110 connected to the metallization portion 202. A solder reflow process may be used to connect the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0095] Exemplary package comprising integrated devices, metallization portion, bridge, and / or interposer Figure 7 shows a package including an interposer and a metallization portion having metallization interconnects of different thicknesses. Package 700 includes a metallization portion 402, an interposer 702, an integrated device 403, and an integrated device 405. Integrated device 403 is bonded to a first surface of the interposer 702 via a plurality of solder interconnects 730. Integrated device 405 is bonded to a first surface of the interposer 702 via a plurality of solder interconnects 750. The interposer 702 may be a type of substrate. The interposer 702 includes at least one dielectric layer 720 (e.g., a substrate dielectric layer, an interposer dielectric layer) and a plurality of interposer interconnects 722 (e.g., substrate interconnects). The interposer 702 may include silicon. For example, at least one dielectric layer 720 may include silicon. Integrated device 403 may include a bare die (e.g., a semiconductor bare die). The integrated device 405 may include a bare die (e.g., a semiconductor bare die). The integrated device 403 may be a first integrated device (e.g., a first chiplet), and the integrated device 405 may be a second integrated device (e.g., a second chiplet). Note that instead of the interposer 702, a multilayer substrate may be used, such as an embedded trace substrate including at least one dielectric layer and a plurality of substrate interconnects.

[0096] The integrated device 403 may be configured to perform a first set of functions and / or operations. The integrated device 405 may be configured to perform a second set of functions and / or operations. The second set of functions and / or operations includes at least one function and / or operation that is different from the first set of functions and / or operations.

[0097] The metallization portion 402 is bonded to the second surface of the interposer 702 via a plurality of solder interconnects 740. The metallization portion 402 includes at least one dielectric layer 420 and a plurality of metallization interconnects 422. The plurality of metallization interconnects 422 may include a first plurality of metallization interconnects 422a, a second plurality of metallization interconnects 422b, a third plurality of metallization interconnects 422c, and a fourth plurality of metallization interconnects 422d.

[0098] The first plurality of metallization interconnects 422a may be the same as the first plurality of metallization interconnects 122a and / or the first plurality of metallization interconnects 222a. The third plurality of metallization interconnects 422c may be the same as the first plurality of metallization interconnects 122a and / or the first plurality of metallization interconnects 222a. The second plurality of metallization interconnects 422b may be the same as the second plurality of metallization interconnects 122b and / or the second plurality of metallization interconnects 222b. The fourth plurality of metallization interconnects 422d may be the same as the second plurality of metallization interconnects 122b and / or the second plurality of metallization interconnects 222b.

[0099] Figure 7 shows exemplary electrical paths for the package, including electrical paths 701, 704, 712, and 714. The electrical path between the integrated device 403 and the board 108 may include electrical path 701. Electrical path 701 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 422a, solder interconnects from a plurality of solder interconnects 740, interposer interconnects from a plurality of interposer interconnects 722 (e.g., board interconnects from a plurality of board interconnects), solder interconnects from a plurality of solder interconnects 730, and a first die interconnect from the integrated device 403. Electrical path 701 may be configured to provide electrical paths for input / output signals.

[0100] The electrical path between the integrated device 403 and the board 108 may include an electrical path 704. The electrical path 704 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallization interconnects 422b, solder interconnects from a plurality of solder interconnects 740, interposer interconnects from a plurality of interposer interconnects 722 (e.g., board interconnects from a plurality of board interconnects), solder interconnects from a plurality of solder interconnects 730, and a second die interconnect from the integrated device 403. The electrical path 704 may be configured to provide an electrical path for power or grounding.

[0101] The electrical path between the integrated device 405 and the board 108 may include an electrical path 712. The electrical path 712 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a third plurality of metallization interconnects 422c, solder interconnects from a plurality of solder interconnects 740, interposer interconnects from a plurality of interposer interconnects 722 (e.g., board interconnects from a plurality of board interconnects), solder interconnects from a plurality of solder interconnects 750, and a first die interconnect from the integrated device 405. The electrical path 712 may be configured to provide electrical paths for input / output signals.

[0102] The electrical path between the integrated device 405 and the board 108 may include an electrical path 714. The electrical path 714 may include a further board interconnect from a plurality of board interconnects 182, a further solder interconnect from a plurality of solder interconnects 110, a fourth plurality of metallization interconnects 422d, a solder interconnect from a plurality of solder interconnects 740, an interposer interconnect from a plurality of interposer interconnects 722 (e.g., a board interconnect from a plurality of board interconnects), a solder interconnect from a plurality of solder interconnects 750, and a second die interconnect from the integrated device 405. The electrical path 714 may be configured to provide an electrical path for power or grounding.

[0103] The electrical path between the integrated device 405 and the integrated device 403 may include a die interconnect from the integrated device 405, at least one interposer interconnect from the plurality of interposer interconnects 722, and a die interconnect from the integrated device 403.

[0104] In some implementations, the package 700 may be fabricated by coupling the integrated devices 403 and 405 to an interposer 702 via a plurality of solder interconnects (e.g., 730, 750). The method may then couple the interposer 702 to a metallization portion 402 via a plurality of solder interconnects 740. The method may then couple the metallization portion 402 to a board 108 via a plurality of solder interconnects 110. However, different implementations may use different sequences to fabricate the package 700. The interposer 702 may be used when there is a significant difference between the size and / or pitch of the pad interconnects of the integrated devices (e.g., 403, 405) and the size and / or pitch of the interconnects of the metallization portion 402.

[0105] Figure 8 shows a package including a metallization portion having a bridge and a metallization interconnect having metallization interconnects of different thicknesses. Package 800 includes the metallization portion 402, the integrated device 403, the integrated device 405, and the bridge 808. The bridge 808 may include a silicon-based bridge. Package 800 is similar to package 400 in Figure 4.

[0106] Integrated device 403 is bonded to the first surface of the metallization portion 402. Integrated device 405 is bonded to the first surface of the metallization portion 402. Integrated device 403 may include a bare die (e.g., a semiconductor bare die). Integrated device 405 may include a bare die (e.g., a semiconductor bare die). Integrated device 403 may be a first integrated device (e.g., a first chiplet), and integrated device 405 may be a second integrated device (e.g., a second chiplet). Integrated devices 403 and 405 are bonded to and in contact with the metallization portion 402. The front surface of integrated device 403 may face the metallization portion 402. The front surface of integrated device 405 may face the metallization portion 402. The sealing layer 106 can seal integrated devices 403 and 405. The sealing layer 106 may be bonded to the first surface of the metallization portion 402. The integrated device 403 may be configured to perform a first set of functions and / or operations. The integrated device 405 may be configured to perform a second set of functions and / or operations. The second set of functions and / or operations includes at least one function and / or operation that is different from the first set of functions and / or operations.

[0107] The bridge 808 is located at least partially within the metallization portion 402. The bridge 808 is coupled to the integrated device 403 and the integrated device 405. The bridge 808 may be coupled to the integrated device 403 and / or the integrated device 405 via hybrid junctions (e.g., copper-to-copper junctions, interconnect-to-interconnection junctions). In some implementations, the bridge 808 may be coupled to the integrated device 403 and / or the integrated device 405 via at least a plurality of solder interconnects (not shown). The front surfaces of the integrated device 403 and the integrated device 405 may face the bridge 808. The bridge 808 may include a bridge substrate 880 and a plurality of bridge interconnects 882. The bridge 808 may include at least one dielectric layer 884. In some implementations, the bridge 808 may be a silicon-based bridge. The bridge substrate 880 may contain silicon. Multiple bridge interconnects 882 can be coupled to the die pads of the integrated device 403 (e.g., 430) and the die pads of the integrated device 405 (e.g., 450). Figure 8 shows an electrical path 816 between the integrated device 403 and the integrated device 405. The electrical path 816 may be configured to provide at least one electrical path for input / output signals between the integrated device 403 and the integrated device 405.

[0108] The electrical path 816 includes a die interconnect from the integrated device 403, at least one bridge interconnect from a plurality of bridge interconnects 882 of the bridge 808, and a die interconnect from the integrated device 405.

[0109] The metallization portion 402 includes at least one dielectric layer 420 and a plurality of metallization interconnects 422. The bridge 808 may be located at least partially within the metallization portion 402. The plurality of metallization interconnects 422 may include a first plurality of metallization interconnects 422a, a second plurality of metallization interconnects 422b, a third plurality of metallization interconnects 422c, and a fourth plurality of metallization interconnects 422d.

[0110] The first plurality of metallization interconnects 422a may be the same as the first plurality of metallization interconnects 122a and / or the first plurality of metallization interconnects 222a. The third plurality of metallization interconnects 422c may be the same as the first plurality of metallization interconnects 122a and / or the first plurality of metallization interconnects 222a. The second plurality of metallization interconnects 422b may be the same as the second plurality of metallization interconnects 122b and / or the second plurality of metallization interconnects 222b. The fourth plurality of metallization interconnects 422d may be the same as the second plurality of metallization interconnects 122b and / or the second plurality of metallization interconnects 222b.

[0111] Figure 8 shows exemplary electrical paths for the package, including electrical paths 401, 404, 412, and 414. The electrical path between the integrated device 403 and the board 108 may include electrical path 401. Electrical path 401 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallization interconnects 422a, and a first die interconnect from the integrated device 403. Electrical path 401 may be configured to provide electrical paths for input / output signals.

[0112] The electrical path between the integrated device 403 and the board 108 may include an electrical path 404. The electrical path 404 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallization interconnects 422b, and a second die interconnect from the integrated device 403. The electrical path 404 may be configured to provide an electrical path for power or grounding.

[0113] The electrical path between the integrated device 405 and the board 108 may include an electrical path 412. The electrical path 412 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a third plurality of metallization interconnects 422c, and a first die interconnect from the integrated device 405. The electrical path 412 may be configured to provide an electrical path for input / output signals.

[0114] The electrical path between the integrated device 405 and the board 108 may include an electrical path 414. The electrical path 414 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a fourth plurality of metallization interconnects 422d, and a second die interconnect from the integrated device 405. The electrical path 414 may be configured to provide an electrical path for power or grounding.

[0115] In some implementations, the electrical path between the integrated device 405 and the integrated device 403 may include a die interconnect from the integrated device 405, at least one metallization interconnect from a plurality of metallization interconnects 422, and a die interconnect from the integrated device 403.

[0116] Note that different parts of the metallized portion of a package may have different minimum interconnect thicknesses, minimum line and space dimensions, and minimum pitches. In one example, a metallized portion may have the same global set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches. In another example, a metallized portion includes (i) a first set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches, and (ii) a second set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches. For example, the second set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches may be located in a region of the metallized portion that overlaps perpendicularly with one or more integrated devices. Some of the minimum dimensions may be local minimum dimensions of the metallized portion. Some of these minimum dimensions may be global dimensions of the metallized portion. Thus, different parts of the metallized portion may have different minimum interconnect thicknesses, different minimum line and space dimensions, and / or different minimum pitches.

[0117] Exemplary sequence for fabricating a package comprising an integrated device and a metallization portion Figures 9A to 9C show exemplary sequences for providing or fabricating a package that includes an integrated device and a metallization portion having metallization interconnects of different thicknesses. In some implementations, the sequences in Figures 9A to 9C may be used to provide or fabricate the package 800 of Figure 8, or any of the packages described herein.

[0118] It should be noted that the sequences in Figures 9A to 9C may be a combination of one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. The sequences in Figures 9A to 9C may be used to manufacture one package, or several packages at once, (as part of a wafer).

[0119] Stage 1 shows the state after the carrier 500 and adhesive coat 501 have been provided, as shown in Figure 9A. The adhesive coat 501 may be an adhesive layer located on the surface of the carrier 500.

[0120] Stage 2 shows the state after the integrated devices 403 and 405 have been placed on the carrier 500 and adhesive coat 501. A pick-and-place process may be used to place the integrated devices. The front surfaces of integrated device 403 and integrated device 405 may be placed on the carrier 500 and adhesive coat 501.

[0121] Stage 3 shows the state after the sealing layer 106 has been formed on the carrier 500, adhesive coat 501, integrated device 403, and integrated device 405. The sealing layer 106 can seal the integrated device 103. The sealing layer 106 may include molded articles, resins, and / or epoxy. The sealing layer 106 may be a means for sealing. The sealing layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, once the sealing layer 106 is provided, a portion of the sealing layer 106 may be removed. For example, a grinding process may be used to remove the top of the sealing layer 106, the back surface of the integrated device 403, and / or the back surface of the integrated device 405.

[0122] Stage 4 shows the state after the carrier 500 and adhesive coat 501 have been separated from the integrated device 403, integrated device 405, and sealing layer 106. The carrier 500 and adhesive coat 501 can be removed from the integrated device 403, integrated device 405, and sealing layer 106.

[0123] Step 5 shows that the integrated device 403, integrated device 405, and encapsulation layer 106 are positioned on the carrier 502, as shown in Figure 5B. The back surfaces of integrated device 403 and integrated device 405 can be positioned and bonded to the carrier 502. An adhesive coat similar to the adhesive coat 501 may be present on the carrier 502. A pick-and-place process may be used to position the integrated device 403, integrated device 405, and encapsulation layer 106 on the carrier 502.

[0124] Step 6 shows the state after the bridge 808 is coupled to the integrated device 403 and the integrated device 405. The bridge 808 may be coupled to the integrated device 403 and / or the integrated device 405 via hybrid junctions (e.g., copper-to-copper junctions, interconnect-to-interconnection junctions, metal-to-metal junctions). In some implementations, the bridge 808 may be coupled to the integrated device 403 and / or the integrated device 405 via at least a number of solder interconnects (not shown). The front surfaces of the integrated device 403 and the integrated device 405 may face the bridge 808. The bridge 808 may include a bridge substrate 880 and a number of bridge interconnects 882. The bridge 808 may include at least one dielectric layer 884. In some implementations, the bridge 808 may be a silicon bridge. The bridge substrate 880 may contain silicon. Multiple bridge interconnects 882 can be coupled to the die pads (e.g., 430) of integrated device 403 and the die pads (e.g., 450) of integrated device 405.

[0125] Step 7 shows the state after the metallization portion 402 has been formed on the integrated device 403, integrated device 405, bridge 808, and sealing layer 106. The metallization portion 402 may include at least one dielectric layer 420 and a plurality of metallization interconnects 422. The bridge 808 may be at least partially located within the metallization portion 402 and / or at least partially surrounded by at least one dielectric layer 420 of the metallization portion 402. Steps 6 in Figure 5B to 26 in Figure 5H illustrate and explain an example of the sequence for forming the metallization portion.

[0126] Stage 8 shows the state after the carrier 502 has been separated from the integrated device 403, the integrated device 405, and the encapsulation layer 106. The carrier 502 can be removed from the integrated device 403, the integrated device 405, and the encapsulation layer 106.

[0127] Stage 9 shows the state after the multiple solder interconnects 110 have been joined to the metallization portion 402. A solder reflow process may be used to join the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0128] Illustrative flowchart of a method for fabricating a package comprising an integrated device and a metallization portion. In some implementations, creating a package involves several processes. Figure 10 shows an illustrative flowchart of a method 1000 for providing or creating a package. In some implementations, the method 1000 of Figure 10 may be used to provide or create any of the packages of this disclosure. For example, the method 1000 of Figure 10 may be used to create package 800.

[0129] It should be noted that Method 1000 in Figure 10 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. Method 1000 in Figure 10 may be used to manufacture one package or several packages at once (as part of a wafer and / or panel).

[0130] The method provides a carrier (in 1005). In some implementations, the carrier may be provided with an adhesive. Step 1 in Figure 9A illustrates and describes an example of providing a carrier 500 and an adhesive coat 501. The adhesive coat 501 may be an adhesive layer located on the surface of the carrier 500.

[0131] The method involves placing the front surfaces of the first and second integrated devices (in 1010) on the carrier. In some implementations, the front surfaces of one or more integrated devices are placed on the carrier containing adhesive. In some implementations, two or more integrated devices may be placed on the carrier. Step 2 of Figure 9A illustrates and describes an example of integrated devices 403 and 405 placed on the carrier 500 and adhesive coat 501. A pick-and-place process may be used to place the integrated devices. The front surfaces of integrated devices 403 and 405 may be placed on the carrier 500 and adhesive coat 501.

[0132] The method involves forming a sealing layer that seals the integrated device (in 1015). The sealing layer may be bonded to the integrated device and the carrier. Step 3 in Figure 9A illustrates an example of a sealing layer 106 formed on the carrier 500, the adhesive coat 501, the integrated device 403, and the integrated device 405. The sealing layer 106 may seal the integrated device 403 and the integrated device 405. The sealing layer 106 may include a molded product, a resin, and / or epoxy. The sealing layer 106 may be a means for sealing. The sealing layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, once the sealing layer 106 is provided, a portion of the sealing layer 106 may be removed. For example, a grinding process may be used to remove the top of the sealing layer 106, the back surface of the integrated device 403, and / or the back surface of the integrated device 405.

[0133] The method involves separating the carrier from the encapsulation layer and the integrated device (at 1020). Step 4 in Figure 9A illustrates an example of the carrier 500 and adhesive coating 501 separated from the integrated device 403, the integrated device 405, and the encapsulation layer 106. The carrier 500 and adhesive coating 501 can be removed from the integrated device 403, the integrated device 405, and the encapsulation layer 106.

[0134] The method involves placing the back surface of the integrated device and the encapsulation layer (in 1025) on another carrier (e.g., a second carrier). The carrier may contain an adhesive. Step 5 in Figure 9B illustrates an example of an integrated device 403, an integrated device 405, and a encapsulation layer 106 placed on a carrier 502. The back surfaces of the integrated device 403 and the back surface of the integrated device 405 can be placed and bonded on the carrier 502. An adhesive coat similar to the adhesive coat 501 may be present on the carrier 502. A pick-and-place process may be used to place the integrated device 403, the integrated device 405, and the encapsulation layer 106 on the carrier 502.

[0135] The method involves coupling the bridge to the integrated device (in 1030). For example, bridge 808 is coupled to integrated device 403 and integrated device 405. Bridge 808 may be coupled to integrated device 403 and / or integrated device 405 via hybrid junctions (e.g., copper-to-copper junctions, interconnect-to-interconnection junctions, metal-to-metal junctions). In some implementations, bridge 808 may be coupled to integrated device 403 and / or integrated device 405 via at least a number of solder interconnects. The front surfaces of integrated device 403 and integrated device 405 may face bridge 808. Bridge 808 may include a bridge substrate 880 and a number of bridge interconnects 882. Bridge 808 may include at least one dielectric layer 884. In some implementations, bridge 808 may be a silicon bridge. Bridge substrate 880 may contain silicon. Multiple bridge interconnects 882 can be coupled to the die pads of the integrated device 403 (e.g., 430) and the die pads of the integrated device 405 (e.g., 450). Step 6 in Figure 9B illustrates and explains an example of coupling the bridge to the integrated device.

[0136] The method (in 1035) forms a metallization portion that is coupled to the front surface and sealing layer of the integrated device. The metallization portion may at least partially surround and / or seal a bridge. The metallization portion may include at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects may include a first metallization interconnect on a first metal layer and a second metallization interconnect on the first metal layer, the second interconnect having a second thickness different from the first thickness of the first metallization interconnect. Forming the metallization portion may include forming at least one dielectric layer and forming the first metallization interconnect on the first metal layer and the second metallization interconnect on the first metal layer. The second interconnect may have a second thickness different from the first thickness of the first metallization interconnect. Step 7 in Figure 9C illustrates and describes an example sequence for forming a metallization portion on an integrated device and bridge (e.g., 808). Steps 6 in Figure 5B through 26 in Figure 5H show an example of forming a metallization portion coupled to at least one integrated device. Different implementation configurations may have different numbers of metal layers. Once the metallization portion is formed (in 1035), the method can separate the second carrier from the integrated device and encapsulation layer.

[0137] The method involves connecting multiple solder interconnects (at 1040) to the metallization interconnects of the metallization portion. Step 9 in Figure 9C illustrates an example of multiple solder interconnects 110 connected to the metallization portion 202. A solder reflow process may be used to connect the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0138] Exemplary electronic devices Figure 11 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a fixed-location terminal device 1106, a wearable device 1108, or a motor vehicle 1110 may include a device 1100 as described herein. Device 1100 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1102, 1104, 1106, and 1108 and the vehicle 1110 shown in Figure 11 are merely examples. Device 1100 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) compatible devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other devices that store or read data or computer instructions, or any combination thereof.

[0139] One or more of the components, processes, features, and / or functions shown in Figures 1-4, 5A-5H, 6-8, 9A-9C, and / or Figures 10-11 may be reconfigured into a single component, process, feature, or function, and / or combined, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1-4, 5A-5H, 6-8, 9A-9C, and / or Figures 10-11, and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-4, 5A-5H, 6-8, 9A-9C, and / or Figures 10-11, and their corresponding descriptions may be used to manufacture, build, provide, and / or produce devices and / or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0140] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be illustrative. In some implementations, various components and / or parts in the figures may be optional.

[0141] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” No implementation or aspect described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other aspect of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation described herein. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can be transmitted between them. Two electrically coupled objects may or may not transmit an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or above fourth) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The term “encapsulating” means that one object can partially or completely encapsulate another object. A first component “located” within a second component may mean that the first component is “partially located” within the second component or “completely located” within the second component.A first component “embedded” within a second component may mean that the first component is “partially embedded” within the second component or “fully embedded” within the second component. The terms “top” and “bottom” are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located “over” a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being located on another component, the term “on” as used in this application can be used to mean a component that is on and / or inside another component (e.g., on the surface of the component or embedded within the component). Thus, for example, a first component on a second component may mean (1) the first component is on the second component but not in direct contact with the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A first component located “in” a second component may be partially located within the second component or completely located within the second component.As used in this disclosure, the terms “about ‘value X’” or “approximately value X” mean a range of 10 percent of “value X.” For example, a value of “about 1” or “approximately 1” means a value in the range of 0.9 to 1.1.

[0142] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes can be used to form interconnects.

[0143] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0144] Further examples are described below to facilitate understanding of the present invention.

[0145] Embodiment 1: A package comprising an integrated device, a substrate coupled to the integrated device via at least a plurality of first solder interconnects, and a metallization portion coupled to the substrate via at least a plurality of second solder interconnects. The metallization portion comprises a plurality of metallization interconnects, including at least one dielectric layer and a first metal layer, a first metallization interconnect having a first thickness, and a second metallization interconnect having a second thickness different from the first thickness, both located on the first metal layer.

[0146] Embodiment 2: The package according to Embodiment 1, wherein the second thickness is greater than the first thickness.

[0147] Embodiment 3: The package according to Embodiment 2, wherein the second thickness is at least 1.2 times greater than the first thickness.

[0148] Embodiment 4: The package according to Embodiments 1 to 3, wherein the plurality of metallization interconnects include a third metallization interconnect located on a second metal layer, a fourth metallization interconnect located on a second metal layer, a first via metallization interconnect coupled to the first and third metallization interconnects and having a first via height, and a second via metallization interconnect coupled to the second and fourth metallization interconnects and having a second via height different from the first via height.

[0149] Embodiment 5: The package according to Embodiment 4, wherein the second thickness is greater than the first thickness and the first via height is greater than the second via height.

[0150] Embodiment 6: The package according to Embodiments 4-5, wherein the second metal layer is adjacent to the first metal layer.

[0151] Embodiment 7: The package according to Embodiments 4 to 6, wherein the first via metallization interconnect has a first minimum diameter, and the second via metallization interconnect has a second minimum diameter that is larger than the first minimum diameter.

[0152] Embodiment 8: The package according to Embodiments 4 to 7, wherein the third metallization interconnect has a third thickness, and the fourth metallization interconnect has a fourth thickness greater than the third thickness.

[0153] Embodiment 9: The package according to Embodiments 4 to 8, comprising: a plurality of metallization interconnects, a fifth metallization interconnect having a fifth thickness located on a third metal layer; a sixth metallization interconnect having a sixth thickness greater than the fifth thickness located on a third metal layer; a third via metallization interconnect having a third via height coupled to the fifth metallization interconnect and the third metallization interconnect; and a fourth via metallization interconnect having a fourth via height different from the third via height coupled to the sixth metallization interconnect and the fourth metallization interconnect.

[0154] Embodiment 10: The package according to Embodiments 4 to 9, wherein a first metallization interconnect, a first via metallization interconnect, and a third metallization interconnect are part of an electrical path for input / output signals to and / or from an integrated device, and a second metallization interconnect, a second via metallization interconnect, and a fourth metallization interconnect are part of an electrical path for power to an integrated device.

[0155] Embodiment 11: The package according to Embodiments 1 to 10, wherein the substrate includes an interposer having a plurality of interposer interconnection sections.

[0156] Embodiment 12: The package according to Embodiments 1 to 11, further comprising a second integrated device coupled to a substrate via at least a third plurality of solder interconnects, wherein the integrated device is a first chiplet and the second integrated device is a second chiplet.

[0157] Embodiment 13: The package according to Embodiment 12, comprising: a first plurality of metallization interconnects having a first minimum thickness, a first minimum spacing, a first minimum pitch, and / or a first minimum width, and including interconnects that overlap perpendicularly with a first integrated device and / or a second integrated device; and a second plurality of metallization interconnects having a second minimum thickness, a second minimum spacing, a second minimum pitch, and / or a second minimum width, wherein the metallization portion includes a rewiring portion, the first metallization interconnect includes a first rewiring interconnect, and the second metallization interconnect includes a second rewiring interconnect.

[0158] Embodiment 14: A package comprising a first integrated device, a second integrated device, a bridge coupled to the first integrated device and the second integrated device, and a metallization portion coupled to the first integrated device and / or the second integrated device. The metallization portion comprises a plurality of metallization interconnects, including at least one dielectric layer and a first metal layer, a first metallization interconnect having a first thickness, and a second metallization interconnect having a second thickness different from the first thickness, both located on the first metal layer.

[0159] Embodiment 15: The package according to Embodiment 14, wherein the second thickness is greater than the first thickness.

[0160] Embodiment 16: The package according to Embodiment 15, wherein the second thickness is at least 1.2 times greater than the first thickness.

[0161] Embodiment 17: The package according to embodiments 14 to 16, wherein the plurality of metallization interconnects include a third metallization interconnect located on a second metal layer, a fourth metallization interconnect located on a second metal layer, a first via metallization interconnect coupled to the first and third metallization interconnects and having a first via height, and a second via metallization interconnect coupled to the second and fourth metallization interconnects and having a second via height different from the first via height.

[0162] Embodiment 18: The package according to Embodiment 17, wherein the second thickness is greater than the first thickness and the first via height is greater than the second via height.

[0163] Embodiment 19: The package according to Embodiments 17-18, wherein the first via metallization interconnect has a first maximum diameter, and the second via metallization interconnect has a second maximum diameter smaller than the first maximum diameter.

[0164] Embodiment 20: The package according to Embodiments 14-19, wherein the bridge is located in the metallization portion.

[0165] Embodiment 21: The package according to Embodiment 20, wherein the bridge includes a silicon-based bridge.

[0166] Embodiment 22: The package according to embodiments 20-21, wherein the first integrated device and the second integrated device are configured to be electrically coupled to each other via an electrical path including a bridge.

[0167] Embodiment 23: The package according to Embodiments 20 to 22, wherein the bridge includes a silicon-based bridge, the first integrated device includes a first technology node, and the second integrated device includes a second technology node.

[0168] Embodiment 24: The package according to Embodiments 14 to 23, wherein the plurality of metallization interconnects include a first plurality of metallization interconnects having a first minimum thickness, a first minimum spacing, a first minimum pitch, and / or a first minimum width, and a second plurality of metallization interconnects having a second minimum thickness, a second minimum spacing, a second minimum pitch, and / or a second minimum width.

[0169] Embodiment 25: The package according to Embodiment 24, wherein the first plurality of metallization interconnects include interconnects that overlap vertically with the first and second integrated devices.

[0170] Embodiment 26: The package according to Embodiments 14 to 25, wherein the package is implemented in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automobile vehicles.

[0171] Various features of the Disclosure described herein can be implemented in various systems without departing from the Disclosure. It should be noted that the above-described aspects of the Disclosure are merely examples and should not be construed as limiting the Disclosure. The descriptions of the aspects of the Disclosure are intended to be illustrative and not to limit the claims. Therefore, the teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art.

Claims

1. It is a package, Integrated devices and A substrate coupled to the integrated device via at least a plurality of first solder interconnections, The metallization portion comprises a metallization portion bonded to the substrate via at least a second plurality of solder interconnections, wherein the metallization portion At least one dielectric layer, and Multiple metallization interconnection parts, A first metallization interconnection portion located on a first metal layer and having a first thickness, A package comprising a plurality of metallization interconnects, each including a second metallization interconnect having a second thickness different from the first thickness, which is located on the first metal layer.

2. The package according to claim 1, wherein the second thickness is greater than the first thickness.

3. The package according to claim 2, wherein the second thickness is at least 1.2 times greater than the first thickness.

4. The plurality of metallization interconnection units A third metallization interconnection located on the second metal layer, A fourth metallization interconnection located on the second metal layer, A first via metallization interconnect is coupled to the first metallization interconnect and the third metallization interconnect, and has a first via height, The package according to claim 1, comprising: a second via metallization interconnect, coupled to the second metallization interconnect and the fourth metallization interconnect, having a second via height different from the first via height.

5. The second thickness is greater than the first thickness. The package according to claim 4, wherein the first via height is greater than the second via height.

6. The package according to claim 4, wherein the second metal layer is adjacent to the first metal layer.

7. The first via metallization interconnect has a first minimum diameter, The package according to claim 4, wherein the second via metallization interconnect has a second minimum diameter that is larger than the first minimum diameter.

8. The third metallization interconnect has a third thickness, The package according to claim 4, wherein the fourth metallization interconnect has a fourth thickness greater than the third thickness.

9. The plurality of metallization interconnection units A fifth metallization interconnect, located on a third metal layer and having a fifth thickness, A sixth metallization interconnect is located on the third metal layer and has a sixth thickness greater than the fifth thickness, A third via metallization interconnect is coupled to the fifth metallization interconnect and the third metallization interconnect, and has a third via height, The package according to claim 4, comprising: a sixth metallization interconnect and a fourth via metallization interconnect, coupled to the fourth metallization interconnect and having a fourth via height different from the third via height.

10. The first metallization interconnect, the first via metallization interconnect, and the third metallization interconnect are part of an electrical path for input / output signals to and / or from the integrated device. The package according to claim 4, wherein the second metallization interconnect, the second via metallization interconnect, and the fourth metallization interconnect are part of an electrical path for power to the integrated device.

11. The package according to claim 1, wherein the substrate includes an interposer having a plurality of interposer interconnection sections.

12. The present invention further comprises a second integrated device coupled to the substrate via at least a third plurality of solder interconnections, The aforementioned integrated device is a first chiplet, The package according to claim 1, wherein the second integrated device is a second chiplet.

13. The plurality of metallization interconnection units A first plurality of metallization interconnects having a first minimum thickness, a first minimum spacing, a first minimum pitch, and / or a first minimum width, and including interconnects that overlap perpendicularly with the first integrated device and / or the second integrated device, It includes a second plurality of metallization interconnects having a second minimum thickness, a second minimum spacing, a second minimum pitch, and / or a second minimum width, The metallization portion includes the rewiring portion, The first metallization interconnection includes a first rewiring interconnection, The package according to claim 12, wherein the second metallization interconnect includes a second rewiring interconnect.

14. It is a package, The first integrated device and The second integrated device, A bridge coupled to the first integrated device and the second integrated device, The device comprises the first integrated device and a metallization portion coupled to the second integrated device, wherein the metallization portion is At least one dielectric layer, and Multiple metallization interconnection parts, A first metallization interconnection portion located on a first metal layer and having a first thickness, A package comprising a plurality of metallization interconnects, each including a second metallization interconnect having a second thickness different from the first thickness, which is located on the first metal layer.

15. The package according to claim 14, wherein the second thickness is greater than the first thickness.

16. The package according to claim 15, wherein the second thickness is at least 1.2 times greater than the first thickness.

17. The plurality of metallization interconnection units A third metallization interconnection located on the second metal layer, A fourth metallization interconnection located on the second metal layer, A first via metallization interconnect is coupled to the first metallization interconnect and the third metallization interconnect, and has a first via height, The package according to claim 14, comprising: a second via metallization interconnect, coupled to the second metallization interconnect and the fourth metallization interconnect, having a second via height different from the first via height.

18. The second thickness is greater than the first thickness. The package according to claim 17, wherein the first via height is greater than the second via height.

19. The first via metallization interconnect has a first maximum diameter, The package according to claim 17, wherein the second via metallization interconnect has a second maximum diameter smaller than the first maximum diameter.

20. The package according to claim 14, wherein the bridge is located in the metallization portion.

21. The package according to claim 20, wherein the bridge includes a silicon-based bridge.

22. The package according to claim 20, wherein the first integrated device and the second integrated device are configured to be electrically coupled to each other via an electrical path including the bridge.

23. The bridge includes a silicon-based bridge, The first integrated device includes a first technology node, The package according to claim 20, wherein the second integrated device includes a second technology node.

24. The plurality of metallization interconnection units A first plurality of metallization interconnects having a first minimum thickness, a first minimum spacing, a first minimum pitch, and / or a first minimum width, The package according to claim 14, comprising a second plurality of metallization interconnects having a second minimum thickness, a second minimum spacing, a second minimum pitch, and / or a second minimum width.

25. The package according to claim 24, wherein the first plurality of metallization interconnects include interconnects that overlap perpendicularly with the first integrated device and the second integrated device.

26. The package according to claim 14, wherein the package is implemented in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automobile vehicles.

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