Memory bit cell with three-dimensional cross field-effect transistor

Abstract

Apparatus and methods for efficiently generating memory bit cell layouts are described. In various embodiments, the memory bit cell uses a pair of transistors that are vertically stacked gate all-around (GAA) transistors, having gate terminals that form a T-shape with respect to each other and a single gate contact that overlaps with only one of the two active layers of the transistor pair. Such a pair of field-effect transistors (FETs) is referred to as a TFET. With respect to each other, the active layers of the TFETs use opposite doping polarities and conduct current in an orthogonal direction. The non-overlapping distance between the upper and lower active layers of the TFET pair is at least the width of the drain / source contact. The orthogonal current flow of the upper and lower active layers simplifies local connections that reduce the resistance and capacitance of the signal path.

Description

Background Art

[0001] (Description of Related Art) As semiconductor manufacturing processes have advanced and the on-die geometric dimensions have decreased, semiconductor chips have been providing more functions and performance while consuming less space. Although many advancements have been made, modern technologies in processing and integrated circuit design that limit potential benefits still have design problems. For example, capacitive coupling, electromigration, short-channel effects such as at least leakage current, and process yield are some of the problems that affect the placement of devices and the routing of signals across the die of a semiconductor chip. These problems can delay the completion of the design and affect the time to market.

[0002] To shorten the design cycle of semiconductor chips, manual full-custom design is replaced by automation if possible. In some cases, standard cell layouts are generated manually. In other cases, the rules used by placement and routing tools are adjusted to automate cell generation. However, automated processes sometimes do not meet each of the rules for both local and external signal routing, including performance, power consumption, signal integrity, process yield, internal cross-coupling connections, pin access, etc. Therefore, designers either manually generate these cells to achieve better results for multiple characteristics or rewrite the rules of the placement and routing tools. However, in many cases, layout tools and rules are set up for planar devices rather than for relatively recent non-planar devices. An example of these cells is the memory bit cell of a random access memory.

[0003] Generally speaking, various semiconductor chips include at least one processing unit coupled to memory. The processing unit sends memory access requests to memory to fetch instructions, fetch data, and store the results of calculations. Static Random Access Memory (SRAM) is commonly used as memory. SRAM consists of an array of many memory bit cells and peripheral circuits used to access the values ​​stored in the array. In addition to the processing unit and memory, the die or package may contain other units or components. The dimensions of individual components impose limitations on placing all components on the same die or package. Some types of memory, such as SRAM, are large enough to interfere with the placement of other components. As a result, the chip becomes inoperable or requires a larger and more expensive package unless it is significantly redesigned.

[0004] In light of the above, there is a need for a method and system for efficiently generating memory bit cell layouts. [Brief explanation of the drawing]

[0005] [Figure 1] This is a generalized diagram of a cross-sectional view of a semiconductor device layout. [Figure 2] This is a generalized block diagram of a top view of a standard cell layout. [Figure 3] This is a generalized block diagram of a top view of a standard cell layout. [Figure 4] This is a generalized diagram of a data storage circuit for a memory bit cell. [Figure 5] This is a generalized block diagram of a top view of a standard cell layout. [Figure 6] This is a generalized block diagram of a top view of a standard cell layout. [Figure 7] This is a generalized block diagram of a top view of a standard cell layout. [Figure 8]This is a generalized block diagram of a top view of a standard cell layout. [Figure 9] This is a generalized block diagram of a top view of a standard cell layout. [Figure 10] This is a generalized block diagram of a top view of a standard cell layout. [Figure 11] This is a generalized block diagram of a top view of a standard cell layout. [Figure 12] This is a generalized block diagram of a top view of a standard cell layout. [Figure 13] This is a generalized diagram of a memory bank. [Figure 14] This is a generalized block diagram of a top view of a standard cell layout. [Figure 15] This is a generalized block diagram of a top view of a standard cell layout. [Figure 16] This is a generalized block diagram of a top view of a standard cell layout. [Figure 17] This is a generalized block diagram of a top view of a standard cell layout. [Figure 18] This is a generalized block diagram of a top view of a standard cell layout. [Figure 19] This is a generalized block diagram of a top view of a standard cell layout. [Figure 20] This is a generalized block diagram of a top view of a standard cell layout. [Figure 21] This is a generalized block diagram of a top view of a standard cell layout. [Figure 22] This is a generalized block diagram of a top view of a standard cell layout. [Figure 23] This is a generalized block diagram of a top view of a standard cell layout. [Figure 24] This is a generalized diagram illustrating an efficient method for generating layouts for memory bit cells using TFETs. [Figure 25] This is a generalized diagram of a computing system having an integrated circuit that uses an array of memory bit cells utilizing TFETs. [Modes for carrying out the invention]

[0006] While the present invention is open to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed, but rather, the invention encompasses all modifications, equivalents, and alternatives that fall within the scope of the invention as defined by the appended claims.

[0007] The following specification includes numerous specific details to provide a full understanding of the invention. However, those skilled in the art should recognize that the invention can be carried out without these specific details. In some examples, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the invention. Furthermore, for the sake of simplicity and clarity of explanation, please understand that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are exaggerated relative to others.

[0008] A system and method for efficiently generating memory bit cell layouts are contemplated. In various embodiments, one or more standard cells include a pair of transistors having gate terminals that form a T-shape with respect to each other. As used herein, “transistor” is also referred to as “field-effect transistor (FET),” “semiconductor device,” or “device.” In some embodiments, the pair of transistors is a vertically stacked gate all-around (GAA) transistor, for example, an upper vertical GAA transistor (or GAA transistor) formed vertically on top of a lower GAA transistor, with at least an isolation oxide layer between the two GAA transistors.

[0009] In addition, the upper GAA transistor of a transistor pair has one or more conduction channels positioned orthogonally to one or more conduction channels (or channels) of the lower GAA transistor. Thus, the direction of current flow in the upper GAA transistor through one or more upper channels is orthogonal to the direction of current flow in one or more lower channels of the lower GAA transistor. In some embodiments, the channels include conducting lateral nanowires. In other embodiments, the channels include conducting nanosheets. In such embodiments, the current of a particular transistor flows through one or more channels, or in other words, the current of a particular transistor flows through one or more nanosheets.

[0010] Furthermore, the upper and lower GAA transistor pair (two vertically stacked transistors) includes a single gate contact, which is used to connect the same input signal to the two gate terminals of the vertically stacked transistor pair. This single gate contact overlaps with only one of the two active layers (i.e., only one, and not both) used to form the vertically stacked transistor pair. For example, this single gate contact overlaps vertically stacked with only one of the active layers: the n-type active layer of an n-type transistor and the p-type active layer of a p-type transistor formed either above or below the n-type transistor. As used herein, “active layer” refers to the region of the semiconductor wafer on which doped silicon is formed. In the case of a planar transistor (device), the active layer defines the region on the silicon substrate that is doped with either p-type atoms (dopants) or n-type atoms (dopants). In the case of non-planar transistors (devices), the active layer defines a region of the three-dimensional structure above the silicon substrate containing doped silicon, such as where the channel is formed. A pair of vertically stacked transistors having gate terminals that form a T-shape with each other and a single gate contact that overlaps with only one of the two active layers used to form the pair of vertically stacked transistors is called a "TFET".

[0011] The top GAA transistor of the TFET has a doping polarity of the top active layer that is opposite to the doping polarity of the bottom active layer of the bottom GAA transistor. In one embodiment, the top GAA transistor includes a p-type active layer and the bottom GAA transistor includes an n-type active layer. In another embodiment, the p-type and n-type polarities are reversed between the active layer of the top GAA transistor and the bottom GAA transistor. In the orthogonal orientation between the top GAA transistor and the bottom GAA transistor, both the top and bottom GAA transistors have the maximum drive current of their respective carriers based on their orientations. It should be understood that silicon wafers, integrated circuits, and semiconductor packages using a silicon substrate layer can be rotated and inverted. Thus, the materials and layers described can be rotated and inverted, and the orientations and directions will have different meanings. Therefore, the terms "top", "bottom", "horizontal", "vertical", "above", and "below" can change as the layout is rotated or inverted.

[0012] In various embodiments, the top active layer of the top GAA transistor of the two vertically stacked transistors does not overlap with the bottom active layer of the bottom GAA transistor of the two vertically stacked transistors. The non-overlapping distance between the first (top) active layer and the second (bottom) active layer includes at least the width of the source or drain contact. The single gate contact used to connect the same input signal to the gate terminals of both the top and bottom GAA transistors overlaps with only one of the top active layer and the bottom active layer. In one embodiment, the single gate contact overlaps with at least a portion of the bottom active layer. With respect to the position of the single gate contact, the gate terminals of the top and bottom GAA transistors form a T shape. The arrangement in which the single gate contact overlaps with only one of the top and bottom active layers simplifies semiconductor manufacturing and improves manufacturing yield as compared to arranging the single gate contact to overlap both the top and bottom active layers.

[0013] The memory array (or array) utilizes memory bit cells arranged as a plurality of rows and a plurality of columns. These memory bit cells use TFETs. In various embodiments, the orthogonal current flows of the upper and lower active layers simplify the local connections for cross-coupled inverters that reduce the resistance and capacitance of the signal paths, resulting in enhanced performance. The first memory bit cell includes a drain contact that contacts an area of the local interconnect layer of the p-type pull-up transistor between the drain node of the p-type pull-up transistor and the drain node of the n-type pull-down transistor. This area of the local interconnect layer is not physically adjacent to the p-type active layer of the p-type pull-up transistor. Details of the array using TFETs are provided in the following descriptions of FIGS. 1-25.

[0014] Referring next to FIG. 1, a generalized block diagram of a cross-sectional view of a semiconductor device layout 100 using TFETs is shown. The semiconductor material of the cross-field effect transistor (FET) 102 is shown within the left figure or frame. The cross FET is also referred to as an "XFET". Thus, the cross FET 102 is also referred to as the XFET 102. The semiconductor material of the TFET 104 is shown within the right figure or frame. Three-dimensional (3-D) views of the p-type and n-type cross FETs 102 and TFET 104 are shown. Each of the XFET 102 and TFET 104 includes a p-type device vertically stacked on an n-type device. The n-type device includes at least one n-type gate 116 formed around the entire circumference of the n-type channel 110. Similarly, a p-type gate 136 is formed around the entire circumference of the p-type channel 130. Thus, the p-type channel 130 has a doping polarity that is the opposite polarity of the n-type channel 110 of the lower n-type device.

[0015] For the cross-FET 102, a single n-type channel 110 and a single p-type channel 130 are shown, but in other embodiments, the semiconductor device includes a different number of conduction channels. For example, the TFET 104 includes an n-type channel 110 and an n-type channel 111. In some embodiments, the channel includes one or more conduction lateral nanowires. In other embodiments, the channel includes one or more conduction nanosheets. Nanosheets are doped silicon sheets, not doped silicon wires. In other words, nanosheets are conduction wires that are wider than lateral nanowires. Nanosheets can also be thought of as fins that are rotated so that they do not have physical contact with the silicon substrate and are positioned on their sides perpendicular to the silicon substrate. More precisely, a metallic gate is formed between the nanosheet and the silicon substrate. However, this embodiment does not describe the actual manufacturing steps for forming the nanosheets.

[0016] Compared to FinFETs, the use of gate-all-around (GAA) nanowires or nanosheets results in lower threshold voltages, faster switching times, lower leakage currents, and further reductions in short-channel effects. Examples of short-channel effects other than leakage current include latch-up effects, drain-induced barrier lowering (DIBL), punch-through, temperature dependence of performance, collisional ionization, and parasitic capacitance to the silicon substrate. As mentioned above, the “active layer” refers to the region of the semiconductor wafer on which the doped silicon is formed. In the case of planar transistors (devices), the active layer defines the region where the silicon substrate is doped with either p-type atoms (dopants) or n-type atoms (dopants). In the case of non-planar transistors (devices), the active layer defines the region of the three-dimensional structure above the silicon substrate containing the doped silicon, such as where the channel is formed.

[0017] In the illustrated embodiment, XFET 102 has an n-type active layer (unlabeled) containing a single n-type channel 110. In other embodiments, the n-type active layer of the n-type device contains multiple n-type channels instead of a single n-type channel 110. XFET 102 has a p-type active layer (unlabeled) containing a single p-type channel 130. In other embodiments, the p-type active layer of the p-type device contains multiple p-type channels instead of a single p-type channel 130. In the illustrated embodiment, TFET 104 has an n-type active layer 180 containing n-type channels 110 and n-type channels 111. In other embodiments, the n-type active layer 180 of the n-type device contains a different number of n-type channels. TFET 104 has a p-type active layer 182 containing a single p-type channel 130. In other embodiments, the p-type active layer 182 of the p-type device contains multiple p-type channels instead of a single p-type channel 130.

[0018] For one or more channels, the p-type active layer 182 of the p-type device includes a three-dimensional area with dimensions such as length, width, and height. These dimensions correspond to the dimensions of one or more p-type channels (or p-type nanosheets). For example, the p-type active layer length 126 is the same as the length of one or more p-type channels, such as p-type channel 130. Similarly, the n-type active layer length 124 is the same as the length of one or more n-type channels, such as the length of n-type channel 110, or the same as the length of n-type channel 111. The height 125 of the n-type active layer 180 is the same as the total height of n-type channels 110 and n-type channel 111, or the total height of one or more n-type channels. The width (unlabeled) of the p-type active layer is the same as the width of one or more p-type channels. Similarly, the width (unlabeled) of the n-type active layer 180 is the same as the width of n-type channel 110, or the same as the width of n-type channel 111.

[0019] The n-type channel 110 and n-type gate 116 are oriented orthogonal to the p-type channel 130 and p-type gate 136. In other words, the n-type channel 110 and n-type gate 116 are oriented at a 90-degree angle from the direction of the p-type channel 130 and p-type gate 136. Therefore, the direction of current flow through the n-type channel 110 of the lower n-type device is orthogonal to the direction of current flow through the p-type channel 130 of the upper p-type device. With the orthogonal orientation between the upper p-type device and the lower n-type device, both devices have their respective maximum carrier mobility based on their orientation. In addition, the orthogonal orientation of the upper p-type device and the lower n-type device allows the connection between vertically stacked devices to use a single via layer.

[0020] A complementary FET (CFET) (not shown) includes an upper GAA transistor stacked vertically on top of a lower GAA transistor, with at least an oxide layer for isolation between them. Thus, CFETs, XFETs, and TFETs use vertically stacked GAA transistors. Vertically stacking the upper GAA transistor on top of the lower GAA transistor further increases performance, reduces power consumption, and reduces the on-die area consumed by the GAA transistors. However, a CFET uses an upper GAA transistor having one or more channels aligned in the same direction as one or more channels of the lower GAA transistor. In a CFET, the upper and lower GAA transistors are not rotated relative to each other. However, as shown here, XFET102 and TFET104 have orthogonal orientation between one or more channels of the upper GAA transistor and one or more channels of the lower GAA transistor.

[0021] Compared to complementary FETs, XFET102 and TFET104 have better drive current for each of the upper and lower GAA transistors, resulting in higher performance. Typically, complementary FETs use at least two metal layers and three via layers to create the connection between the upper and lower GAA transistors. In contrast, XFET102 and TFET104 utilize a single metal layer and a single via layer for the connection between the upper and lower GAA transistors.

[0022] An insulating layer lies between the upper p-type device and the lower n-type device, and when the gate terminals of the device pair (p-type device and n-type device) receive the same input signal, a gate contact 122 is formed between the devices in the insulating layer. The gate contact 122 between the vertically stacked devices connects directly to the p-type metal gate 136 and the n-type metal gate 116 without crossing any metal layers. One advantage of the orthogonal orientation of the XFET 102 and TFET 104 is that only one via layer is used, which will be shown later in the memory bit cell layout. The use of this single via layer reduces the resistance and capacitance of the corresponding circuit.

[0023] As illustrated, the gate contact 122 of XFET 102 overlaps with the n-type active layer and the p-type active layer of the two vertically stacked transistors. Since the illustrated embodiment of XFET 102 includes a single channel for each of the p-type and n-type devices, the active layers in the illustrated embodiment include single channels 110 and 130. The gate contact 122 overlaps with each of the n-type channel 110 and the p-type channel 130. On the other hand, the gate contact 122 of TFET 104 overlaps with only one of the active layers, either the p-type active layer 182 of the p-type device or the n-type active layer 180 of the n-type device, and the p-type and n-type devices form two vertically stacked devices. In the illustrated embodiment, the gate contact 122 of TFET 104 overlaps only with the n-type active layer 180, which includes the n-type channels 110 and 111. Therefore, the gate contact 122 of TFET 104 overlaps only with the n-type active layer 180. The gate contact 122 of TFET 104 does not overlap with the p-type active layer 182.

[0024] In the case of TFET 104, in various embodiments, the p-type active layer 182 does not overlap with the n-type active layer 180. The distance between the p-type active layer 182 and the n-type active layer 180 is indicated as width (or offset) 106. Width 106 includes at least the width of the source contact or drain contact. In some embodiments, width 106 includes another minimum distance between the p-type channel 130 and the source or drain contact, which is determined by the design rules and checks of the specific semiconductor manufacturing process used to manufacture TFET 104. In one embodiment, this minimum distance is 3 nanometers (nm), and the width of the source or drain contact is 18 nm. In such embodiments, the minimum width of width 106 is 21 nm (3 nm + 18 nm = 21 nm).

[0025] The top view of TFET104 illustrates how the gate terminals (gates 116 and 136) of the upper and lower GAA transistors form a T-shape. Arranging a single gate contact 122 to overlap only one of the n-type active layer 180 and p-type active layer 182 (e.g., only the n-type active layer 180) simplifies the manufacturing of semiconductor elements and improves manufacturing yield compared to arranging a single gate contact 122 to overlap both the n-type and p-type active layers, as shown in XFET102.

[0026] Referring to Figure 2, a generalized block diagram of a top view of a semiconductor device layout 200 using TFETs is shown. The contacts (or vias), semiconductor materials, and structures described earlier are denoted by the same reference numerals. Standard cell layout 200 is for an inverter using TFET 104. Three-dimensional (3-D) diagrams of p-type and n-type TFETs are shown with layout 200. A top view of semiconductor device layout 200 (or layout 200) is shown on the right, and a cross-sectional view of TFET 104 is shown on the left. In this inverter, the p-type devices are stacked vertically on the n-type devices. However, in other embodiments, it is possible and intended to stack the n-type devices vertically on the p-type devices. Each device in the inverter uses a gate-all-around (GAA) metal that encloses one or more nanosheets in the gate region in a 360-degree manner. The lower n-type device is fabricated on a first wafer. The upper p-type device is fabricated on a separate second wafer, and then the oxides are bonded together to the first wafer. As shown in the figure, the gate contact 122 overlaps with only one of the active layers, either the n-type or p-type active layer. In addition to the direction of the current flow (Iflow) of the two devices, the length dimensions 124 and 126 are shown. The width 106 includes at least the width of the source or drain contact 120. Here, the inverter uses contact 120 as the drain contact.

[0027] The inverter uses a frontside power metal zero (or metal 0 or M0 or metal 0) layer 150 to provide a power reference level indicated as "VDD". Contact 140 connects the front M0 layer 150 to the p-type local interconnect 134 to route VDD to the source area of ​​the p-type device. The front M0 layer 150 is also used to route the input signal "IN" and the output signal "OUT". For the input signal "IN", contact 142 connects the front M0 layer 150 to the p-type gate 136. For the input signal "IN", contact 122 connects the p-type gate 136 to the n-type gate 116. The drain area of ​​the n-type device uses the n-type local interconnect 114. The drain area of ​​the p-type device uses the p-type local interconnect 134. Contact 120 connects these two drain areas to each other.

[0028] Contact 120 is located between the drain node of the p-type transistor and the drain node of the n-type transistor and contacts an area of ​​the p-type local interconnect 134 of the p-type transistor. This area of ​​the local interconnect layer 134 is not physically adjacent to the p-type active layer of the p-type transistor. By having contact 120 in this configuration, contact 120 provides low-resistance contact between the p-type local interconnect 134 and the n-type local interconnect 114. Furthermore, this configuration of contact 120 provides higher reliability (reduced process variability) and higher manufacturing yield than if contact 120 were located along an area of ​​the p-type local interconnect 134 that is physically adjacent to the p-type active layer. The technique shown in layout 200 is again used in the following layouts 500-1200 and 1100-2300, which provide a standard cell layout for memory bit cells, including the effect of TFET 104.

[0029] For the output signal "OUT", contact 140 overlaps with the area of ​​contact 120 and connects the p-type local interconnect 134 to the front M0 layer 150. The inverter uses a backside power metal zero (or metal 0 or M0 or Metal0) layer located beneath the silicon substrate layer and an oxide layer (not shown) used for insulating purposes. Micro through silicon vias (TSVs) traverse the silicon substrate layer so as to be located between the backside power M0 rail and the source region of the n-type device.

[0030] Referring to Figure 3, a generalized block diagram of a cross-sectional view of a standard cell layout 300 that utilizes power connections routed in the front and back metal layers is shown. The contacts (or vias), semiconductor materials, and structures described earlier are denoted by the same reference numerals. The standard cell layout 300 is for any of the various types of Boolean gates and composite gates, including transistors arranged in a particular manner to provide data processing functions or data storage. The standard cell layout 300 (or layout 300) uses TFETs. The HFETs include n-type device 340 and p-type device 342. The cross-sectional view shows each of the two transistors (devices) 340 and 342 with their metal gates oriented in the same direction, although the actual arrangement of these transistors in the semiconductor layout includes orthogonal arrangements relative to each other. Power signals are routed using both the front and back metal layers.

[0031] Here, a first transistor of a TFET, such as an n-type device 340, has an n-type active layer 380 that provides a current flow oriented in a first direction perpendicular to a second direction of current flow in a p-type active layer 382. In one embodiment, the n-type active layer 380 includes multiple n-type nanosheets. In the key or legend, the label "n-type nanosheet 110" is used. However, it should be understood that an n-type active layer, such as the n-type active layer 380 (and the n-type active layer 180 in Figure 1), can include multiple n-type nanosheets, as shown in the cross-sectional view provided in layout 300. The following layouts 500-1200 (in Figures 5-12) and 1400-2300 (in Figures 14-23) provide top views rather than cross-sectional views and therefore only show a single n-type nanosheet. However, it should be understood that one or more additional n-type nanosheets may be formed beneath the topmost n-type nanosheet, as shown in layout 300 and layout 100 (in Figure 1). This also applies to p-type nanosheet 130.

[0032] In various embodiments, each n-type nanosheet 110 of the n-type active layer 380 is composed of a silicon semiconductor epitaxial growth layer doped with n-type atoms. Similarly, each p-type nanosheet 130 is composed of a silicon semiconductor epitaxial growth layer doped with p-type atoms. Each of the n-type nanosheets 110 and p-type nanosheets 130 terminates within the edges of their respective drain and source regions. The drain and source regions of the n-type device 340 use the previously described n-type local interconnect 114. The drain and source regions of the p-type device 342 use the previously described p-type local interconnect 134. Unlike complementary FETs, the n-type nanosheet 110 does not traverse the entire drain and source region. Rather, the n-type nanosheet 110 utilizes metal sidewall contacts at the edges of the nanosheet within the source and drain regions, thereby allowing more nanosheets to be generated in the n-type active layer. The p-type nanosheets 130 of the p-type active layer 382 are formed in a similar manner, and in this case as well, metal sidewall contacts are also utilized at the edges of the nanosheets in the respective source and drain regions.

[0033] As described above, the n-type active layer 380 refers to the region of the semiconductor wafer on which the doped silicon is formed. The n-type active layer 380 of the n-type device 340 is a three-dimensional region whose length is equal to the distance between the metal sidewall contacts at the edges of the nanosheets in the source and drain regions. This n-type active layer 380 has a height equal to the distance from the bottom of the lower n-type nanosheet 110 to the top of the upper n-type nanosheet 110. Furthermore, this n-type active layer 380 has a width equal to the distance that the n-type nanosheet 110 traverses along the direction in which it enters (or leaves) the page. The p-type active layer 382 of the p-type device 342 has similarly defined dimensions.

[0034] The n-type device 340 is connected to a first voltage level reference provided by a back metal layer. This back power metal zero (or metal 0 or M0 or Metal0) layer 302 is located below the silicon substrate layer and any oxide layers (not shown) used for insulating purposes. A micro-through-silicon via (TSV) 304 traverses the silicon substrate layer so as to be located between the back power M0 layer 302 and the source region of the n-type device 340. Alternatively, a second transistor such as a p-type device 342 is used, which has a second channel oriented in a second direction orthogonal to the first direction and connected to a second voltage level reference provided by a front metal layer. This front power metal zero (or metal 0 or M0 or Metal0) layer 320 is located above the silicon substrate layer and any oxide layers (not shown) used for insulating purposes. The drain and source regions of the p-type device 342 use the previously described p-type local interconnect 134. In other embodiments, the n-type transistor 340 and the p-type transistor 342 are switched along with this type of voltage reference level connected to the rear power M0 layer 302 and the front power M0 layer 320.

[0035] A "micro-TSV" 304 is a through-silicon via that traverses the silicon substrate layers from the back power M0 layer 302 to the source region 306 and terminates at physical contact with the source region 306 in each of the back power M0 rails 302. The distance from the back power M0 layer 302 to the n-type local interconnect 114 used as the source region defines the height or length of the micro-TSV 304, which traverses only the silicon substrate layers and any oxide layers above the back power M0 layer 302. The micro-TSV 304 does not physically extend within the multiple insulating layers of the semiconductor die used to route multiple front metal layers. Similarly, the micro-TSV 304 does not physically extend within the multiple insulating layers of the semiconductor die used to route multiple back metal layers.

[0036] The orientation of the standard cell layout 300 (or layout 300) is shown such that the rear power M0 layer 302 and the front power M0 rail 320 are routed horizontally, but other orientations are also assumed and intended. It should be understood that silicon wafers, integrated circuits, and semiconductor packages using silicon substrate layers can be rotated and inverted. Therefore, the materials and layers described will be rotated and inverted, and the orientation and direction will have different meanings. Accordingly, the terms “top,” “bottom,” “horizontal,” “vertical,” “upward,” and “downward” may change when layout 100 is rotated or inverted, and the use of these terms in the following description corresponds to the orientation shown in layout 300.

[0037] As used herein, the “terminals” of a transistor are also referred to as the “regions” of a transistor. For example, the source region is also referred to as the source terminal, the drain region as the drain terminal, and the gate region as the gate terminal. The source and drain regions are typically formed in the same orientation (horizontal or vertical) as the corresponding gate metal of the same device. An example of a source and drain region is a trench silicide contact. In some embodiments, the source and drain regions contain cobalt silicide (CoSi2). In other embodiments, the source and drain regions contain titanium silicide (TiSi2) or ruthenium (Ru).

[0038] To supply current from the off-chip power supply to the p-type device 342, the current flows from the off-chip power supply to multiple front metal layers, the front power M0 layer 320, and the p-type source contact 308 of the p-type device 342. To supply current from the off-chip ground reference to the n-type device 340, the current flows from the off-chip ground reference to one or more back metal layers, the back power M0 layer 302, and the n-type local interconnect 114, which is used as the source region of the n-type device 340. In some embodiments, a single thick back metal layer, rather than multiple thin back metal layers, is used to supply the ground reference in order to reduce semiconductor manufacturing costs. The power connections shown in layout 300 reduce on-die area, reduce semiconductor manufacturing complexity, which improves wafer yield and further improves performance by reducing voltage droop.

[0039] Returning to Figure 4, a generalized block diagram of one embodiment of data storage in the memory bit cell 400 is shown. In the illustrated embodiment, data storage by latch elements is provided by devices P1 402, N1 406, P2 412, and N2 416. These devices provide data storage using a back-to-back configuration of two inverters. A back-to-back configuration of two inverters is also referred to as a cross-coupled inverter. As used herein, a Boolean logic high level is also referred to as a logic high level. Similarly, a Boolean logic low level is also referred to as a logic low level. In various embodiments, the logic high level is equal to the power reference level, and the logic low level is equal to the ground reference level. As used herein, a circuit node or line is “asserted” if it stores a voltage level that enables a transistor receiving a voltage level, or if that voltage level indicates that operation is enabled. For example, an n-type transistor is enabled if it receives a positive non-zero voltage level on its gate terminal that is at least a threshold voltage above the voltage level on its source terminal.

[0040] As used herein, a circuit node or line is "negated" if it stores a voltage level that disables a transistor receiving that voltage level. An n-type transistor is disabled if it receives a voltage level at its gate terminal that is at least a threshold voltage below the voltage level at its source terminal. Similarly, a p-type transistor is enabled if it receives a voltage level at its gate terminal that is at least a threshold voltage below the voltage level at its source terminal. A p-type transistor is negated if it receives a voltage level at its gate terminal that is at least a threshold voltage above the voltage level at its source terminal. Furthermore, operation is enabled and disabled based on the assertion or negation of the corresponding control signal.

[0041] When a write operation is being performed, an external circuit (not shown) asserts the write word line WL430 at a high logic level. Thus, each of the n-type transistors N3 421 and N4 422 is enabled. The enabled transistor N3 421, which is a pass gate, electrically connects the bit line BLT (Bit Line True) 440 to node B 414. The enabled transistor N4 422, which is a pass gate, electrically connects the bit line BLC (Bit Line Complement) 442 to node BB 404. In various embodiments, during a write operation, the external circuit ensures that BLC 442 has the opposite (complement) Boolean value compared to the Boolean value of BLT 440. Thus, the bit line BLT 440 drives the voltage level to be stored in node B 414. Either transistor P2 412 or N2 416 is enabled based on the voltage level of node B 414. Similarly, either transistor P1 402 or N1 406 is enabled based on node BB 404, which is the output node between the two transistors P2 412 and N2 416.

[0042] If no write operation is performed, an external circuit (not shown) negates the write word line WL430 at a logical low level. Thus, each of the n-type transistors N3 421 and N4 422 is disabled. The data storage of the memory bit cell 400 is one embodiment of static RAM (static RAM, SRAM). In other embodiments, a different RAM cell from various types of RAM cells is used. This “memory bit cell” may be referred to as a “memory bit cell,” an “SRAM bit cell,” or a “bit cell.” In various embodiments, the memory bit cell 400 is copied multiple times and arranged in rows and columns of a memory array, as will be shown later in the memory bank 1300 (Figure 13). In various embodiments, the memory bit cell 400 includes a TFET and layout techniques for cell layouts 500-1200 (Figures 5-12) and cell layouts 1400-2300 (Figures 14-23) in the following description. These layout techniques are used to form 6-transistor (6T) random-access data storage for memory bit cells.

[0043] Referring next to Figure 5, a generalized block diagram of the top view of the standard cell layout 500 is shown. The contacts (or vias), semiconductor materials, and structures described earlier are denoted by the same reference numerals. The standard cell layout 500 (or layout 500) is for a memory bit cell using the TFET 104 (in Figure 1). Layout 500 includes a symmetric layout 502 (or layout 504) and an asymmetric layout 504 (or layout 504). Each of layouts 502 and 504 is for a corresponding memory bit cell using the TFET. Layout 502 uses a symmetric arrangement of materials, electrical nodes, and signals, thereby resulting in a higher semiconductor manufacturing yield. Layout 504 uses an asymmetric arrangement of materials, electrical nodes, and signals, thereby resulting in a smaller standard cell. Therefore, the trade-off between using layout 502 and layout 504 is the choice between a higher yield or a smaller memory bit cell. Similarly, layouts 602-1202 (in Figures 6-12) use a symmetrical arrangement of materials, electrical nodes, and signals, resulting in a higher semiconductor manufacturing yield. Layouts 604-1204 (in Figures 6-12) use an asymmetrical arrangement of materials, electrical nodes, and signals, resulting in a smaller standard cell.

[0044] Here, in both layouts 502 and 504, the n-type nanosheets 110 are generated from a stack of alternating layers, such as silicon-germanium semiconductor epitaxial growth layers alternating with silicon semiconductor epitaxial growth layers. As mentioned above, the following layouts 500-1200 (Figures 5-12) and 1400-2300 (Figures 14-23) provide top views rather than cross-sectional views, and therefore only a single n-type nanosheet is shown. However, it should be understood that one or more additional n-type nanosheets are formed beneath the topmost n-type nanosheet, as shown in layout 300 (Figure 3) and layout 100 (Figure 1). The same applies to the p-type nanosheets 130 shown in layouts 800-1200 (Figures 8-12) and 1700-2300 (Figures 17-23).

[0045] In the case of n-type nanosheets 110, the alternating layer stack is etched to the size of the n-type nanosheet 110 using one of the following methods: sidewall image transfer (SIT) process, extreme ultraviolet (EUV) lithography, directed self-assembly (DSA) patterning by chemical epitaxy, or self-aligned customization. In other embodiments, the alternating layers are grown on a silicon-on-insulator (SOI) oxide layer, followed by an etching step. A predetermined conductive layer consisting of alternating silicon-germanium semiconductor epitaxial growth layers and silicon semiconductor epitaxial growth layers is selected to remain to form a gate region. Subsequently, any semiconductor layers other than the selected layer are removed. The n-type TSV local interconnect 112 is formed where the connection to the micro-TSV will be located later.

[0046] Next, referring to Figures 6-12, generalized block diagrams of top views of standard cell layouts 600-1200 (or layouts 600-1200) are shown. The contacts (or vias), materials, and structures described earlier are denoted by the same reference numerals. In layout 600, n-type source and drain regions are formed. In one embodiment, the n-type source and drain regions are phosphorus-doped epitaxially grown silicon. Subsequently, n-type local interconnects 114 are formed. In some embodiments, the n-type local interconnects 114 include tungsten, cobalt, ruthenium, or molybdenum.

[0047] A gate metal material 116 is deposited, followed by polishing the n-type gate metal 116 in a chemical mechanical planarization (CMP) step. In various embodiments, titanium nitride (TiN) is used for the gate metal 116. The gate metal 116 is provided in a 360-degree manner around the entire circumference of the n-type nanosheet 110. An interlayer dielectric (ILD) oxide layer is deposited around the gate region. The label "BLT" corresponds to the BLT440 signal of the memory bit cell 400 (in Figure 4). Similarly, the label "BLC" corresponds to the BLC442 signal of the memory bit cell 400 (in Figure 4). In addition, layout 604 includes n-type TSV local interconnects 112 along the entire length of the sides of layout 602, while layout 602 includes n-type TSV local interconnects 112 at the corners of layout 604. Although not shown in the diagram, the n-type local interconnect 114 covers the n-type TSV local interconnect 112.

[0048] Layout 700 has contacts 120 (connections from n-type local interconnects to p-type local interconnects) and formed gate contacts 122. However, only two of the gate contacts 122 will be connected to p-type gates 136, such as n-type gates for pull-down devices (transistors). Layout 800 has p-type channels 130 (or p-type nanosheets 130) and subsequently formed p-type local interconnects 134. These p-type local interconnect layers 134 are formed by etching of oxide layers and deposition of corresponding materials. Layout 900 has p-type gates 136 formed. For example, p-type gate metal material 136 is deposited, and then the p-type gate metal 136 is polished in a chemical mechanical planarization (CMP) step. In various embodiments, titanium nitride (TiN) is used for the p-type gate metal 136. Layout 900 also has formed contacts 140. The label "PD" indicates pull-down n-type devices such as the N1 406 device and N2 416 device of memory bit cell 400 (in Figure 4). The label "PU" indicates pull-up p-type devices such as the P1 402 device and P2 412 device of memory bit cell 400 (in Figure 4).

[0049] Layout 1000 has a formed contact 142. In the case of a symmetrical layout 1002, the non-overlapping distance between the p-type active layer and the n-type active layer is shown as a width (or offset) 106. This width 106 lies between the p-type active layer of the p-type pull-up device and the n-type active layer of the n-type pass-gate device. Examples of these devices are the p-type device P2 412 and the n-type device N4 422 of the memory bit cell 400 (Figure 4). Note that the n-type nanosheet (n-type active layer) of the n-type pull-down device located to the left of the p-type pull-up device also shares this drain node (this n-type local interconnect 114). An example of this n-type pull-down device is the n-type device N2 416 of the memory bit cell 400 (Figure 4). The non-overlapping distance between the p-type active layer of the p-type pull-up device and the n-type active layer of the n-type pull-down device can also be a width (or offset) 106.

[0050] The width 106 includes at least the width of a source contact or drain contact, such as contact 120 used as a drain contact between the p-type pull-up device and the n-type pass-gate device. This node may also be the source region of the n-type pass-gate device if the node has a logic low and the signal BLC has a logic high. In some embodiments, the width 106 includes another minimum distance between the p-type nanosheet 130 and the drain contact 120, determined by the design rules and checks of the specific semiconductor manufacturing process used to manufacture the TFET 104. Between the drain node of the p-type pull-up device and the n-type pass-gate device, there is a drain contact 120 that contacts an area of ​​the p-type local interconnect 134 of the p-type pull-up device. This area of ​​the p-type local interconnect layer 134 is not physically adjacent to the p-type nanosheet 130 (p-type active layer) of the p-type pull-up device. The drain contact 120 having such an arrangement provides low-resistance contact between the p-type local interconnect 134 and the n-type local interconnect 114.

[0051] In the asymmetric layout 1004, the p-type pull-up device is positioned to the right of the n-type pull-down device. The n-type pass-gate device is located at the left end of layout 1004. Unlike the symmetric layout 1002, in the asymmetric layout 1004, the p-type pull-up device is not adjacent to the n-type pass-gate device. Similar to the symmetric layout 1002, the drain contact 120 in the asymmetric layout 1004 contacts an area of ​​the p-type local interconnect 134, which is not physically adjacent to the p-type nanosheet 130 (p-type active layer) of the p-type pull-up device. Due to this arrangement of the drain contact 120, the drain contact 120 provides low-resistance contact between the p-type local interconnect 134 and the n-type local interconnect 114.

[0052] Unlike the symmetrical layout 1002, the non-overlapping distance between the p-type nanosheet 130 of the p-type pull-up device and the adjacent (but vertically downward) n-type nanosheet 110 of the n-type pull-down device is shorter than the width (or offset) 106. The p-type local interconnect 134 providing the drain node of the p-type pull-up device extends to the left beyond the n-type nanosheet 110 of the n-type pull-down device to provide a location for the drain contact 120. Unlike the symmetrical layout 1002, this drain contact 120 in the asymmetrical layout 1004 is not physically located between the p-type nanosheet 130 of the p-type pull-up device and the n-type nanosheet of the n-type pull-down device. Similar to the symmetrical layout 1002, the gate contact 122 used by the p-type gate 136 of the p-type pull-up device and the n-type gate 116 of the n-type pull-down device partially overlaps with the n-type nanosheet 110 of the n-type pull-down device but does not overlap with the p-type nanosheet 130 of the p-type pull-up device.

[0053] In layout 1100, a front M0 layer 150 is formed to complete the generation of signal connections for the 6T random access data storage of the memory bit cells. The label "WL" corresponds to the WL430 signal of the memory bit cell 400 (in Figure 4). Continuing with respect to signal connections, layout 1200 has vias 160 formed to connect the front M0 layer 150 to a metal 1 layer (or metal1 or metal 1 or M1) 170. The M1 layer 170 is deposited later to form further connections for the bit cells.

[0054] Referring now to Figure 13, a generalized block diagram of one embodiment of memory bank 1300 is shown. In various embodiments, the memory is organized into multiple memory banks, and the memory macroblock includes both the left and right banks. In some embodiments, bank 1300 is either the left or right bank of the memory macroblock. While “left” and “right” are used to describe the memory banks, other notations such as “upper bank” and “lower bank” may be used. As illustrated, memory bank 1300 includes arrays 1312A to 1312B, row decoders 1320A to 1320B, sense amplifiers 1330A to 1330B between arrays 1312A to 1312B, read and write timing control logic 1340A to 1340B, and read and write latches in block 1350. Note that in some embodiments, multiple banks are accessed simultaneously in the same clock cycle or the same pipeline stage. Access includes either read access or write access. In such an embodiment, the bank address decoder selects the corresponding bank to access.

[0055] In various embodiments, each of the blocks 1312A-1312B, 1320A-1320B, 1330A-1330B, 1340A-1340B, and 1350 within the memory bank 1300 is communicatively coupled to another block. For example, direct connections are used where routing is performed via another block. Alternatively, signal staging is performed in an intermediate block. In various embodiments, each of the arrays 1312A-1312B includes a plurality of memory bit cells 1360 (or bit cells 1360) arranged in a tile format. Here, rows are aligned with tracks used for routing word lines of the array, and in the illustrated embodiment, vertically, etc. Columns are aligned with tracks used for routing bit lines of the array, and in the illustrated embodiment, horizontally, etc. In other embodiments, the rows and columns are rotated and have different orientations.

[0056] The row decoders and word line drivers in blocks 1320A to 1320B receive address information corresponding to an access request. For example, each of blocks 1320A to 1320B receives information provided by the access request address 1370. Each of blocks 1320A to 1320B selects a specific row or entry from among multiple rows in the relevant array from arrays 1312A to 1312B. In some embodiments, blocks 1320A to 1320B use the index portion of address 1370 to select a given row or entry in the relevant array from arrays 1312A to 1312B. Each row or entry stores one or more memory lines.

[0057] In the illustrated embodiment, rows or entries in arrays 1312A-1312B are arranged vertically. However, in other embodiments, horizontal orientation is used for memory line storage. For a write access request, a write latch is located in block 1350. The write data is placed in arrays 1312A-1312B. Timing control logic 1340A-1340B updates the write latch with the new data and sets up the write word line driver logic in block 1350. The write data is written to a row of bit cells selected by the relevant block from blocks 1320A-1320B. In some embodiments, a precharge circuit is included in block 1350.

[0058] For a read access request, block 1350 is used to precharge the read bit lines routed to arrays 1312A-1312B. Timing circuits in blocks 1340A-1340B are used to precharge and set up the sense amplifiers in blocks 1330A-1330B. Timing circuits 1340A-1340B set up the read word line driver logic. One of the row decoders 1320A-1320B selects the row from which to read data, and this data is provided on the read bit lines sensed by the sense amplifiers. A read latch captures the read data.

[0059] In various embodiments, the memory bit cell 1360 (or bit cell 1360) utilizes 6-transistor (6T) random access data storage. For example, data storage uses a back-to-back configuration of two inverters (cross-coupled inverters). In various embodiments, the memory bit cell 1360 (or bit cell 1360) utilizes the data storage circuit configuration of bit cell 400 (Figure 4) and the layout techniques of standard cell layouts 600-1200 (Figures 6-12) and standard cell layouts 1100-2300 (Figures 14-23).

[0060] Next, referring to Figures 14-23, generalized block diagrams of the top views of standard cell layouts 1100-2300 (or layouts 1100-2300) are shown. The contacts (or vias), materials, and structures described earlier are denoted by the same symbols. Furthermore, the labels mentioned above use the same names. In layout 1400, an n-type nanosheet 110 is generated, an n-type TSV local interconnect 112 is formed where the connection to the micro TSV will be located later, and then an n-type local interconnect 114 is formed. Although not shown, the n-type local interconnect 114 covers the n-type TSV local interconnect 112. In layout 1500, an n-type gate 116 is deposited, and a gate contact 120 is formed.

[0061] Layout 1600 has formed gate contacts 122. However, only two of the gate contacts 122 will be connected to p-type gates 136, such as n-type gates for pull-down devices (transistors). Layout 1700 has formed p-type channels 130 (or p-type nanosheets 130). Subsequently, p-type local interconnects 134 are formed within layout 1800. Layout 1800 also has formed p-type gates 136.

[0062] Layout 1900 has formed contacts 140. Layout 2000 has formed contacts 142. In layout 2100, a front M0 layer 150 is formed to complete the generation of signal connections for the 6T random access data storage of memory bit cells. With regard to signal connections, layout 2200 has vias 160 formed to connect the front M0 layer 150 to a metal 1 layer (or metal1 or metal 1 or M1) 170. In layout 2300, the M1 170 layer is deposited later to generate further connections for the bit cells. The M1 170 layer provides connections for word line (WL) signals and power reference levels (VDD and VSS). Unlike symmetric layouts 1202 and asymmetric layouts 1204, layout 2300 does not use the M1 170 layer for bit lines (BLT and BLC). As a result, the on-die area dimensions of layout 2300 are different from both layouts 1202 and 1204. For example, the first height of layout 1202 that contributes to the on-die area of ​​this memory bit cell layout 1202 is lower than the second height of layout 2300 that contributes to the on-die area of ​​this memory bit cell layout 2300. The first width of layout 1202 that contributes to the on-die area of ​​this memory bit cell layout 1202 is greater than the second width of layout 2300 that contributes to the on-die area of ​​this memory bit cell layout 2300. A similar height-width relationship exists between layout 1204 and layout 2300.

[0063] Layouts 500-1200 and 1400-2300 provide standard cell layouts that include the advantages of TFET 104. For example, the n-type channel 110 (n-type nanosheet) and the p-type channel 130 (p-type nanosheet) are offset from each other. Semiconductor manufacturing is simplified and yield is improved. A less complex selective etching bias process can be used, and less material is used compared to complementary FETs and XFETs 102. The width 106 shows this shift. The gate terminals of the p-type and n-type devices of the TFET form a T-shape rather than an X-shape. The p-type local interconnect 134 extends beyond the p-type channel 130 (p-type active layer) to obtain a contact 120 positioned to connect to the n-type local interconnect 114. The arrangement of the contact 120 on the p-type local interconnect 134 in layout 200 (Figure 2) illustrates an example of such arrangement with respect to the drain contact. The contacts used to connect the p-type local interconnect 134 to the n-type gate 116 are removed and replaced by contact 120 when both p-type gates 136 overlap the n-type gate 116. Compared to complementary FETs and XFET 102, the TFET 104 has lower resistance and capacitance. Also, the shift of the n-type channel 110 and p-type channel 130, which generates width 106, increases thermal diffusion.

[0064] Referring now to Figure 24, a generalized block diagram of method 2400 for efficiently generating a layout for memory bit cells is shown. For illustrative purposes, the steps in this embodiment are shown in order. However, in other embodiments, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with others, and some steps are absent.

[0065] The semiconductor manufacturing processor (or process) forms transistors in a manner in which they are stacked vertically in orthogonal directions (block 2402). The process forms cross-coupled transistors within a bit cell having a single gate contact that overlaps with only one of the two active layers of the cross-coupled inverter (block 2404). The arrangement of contact 122 in layout 200 (in Figure 2) illustrates an example of such arrangement with respect to the gate contact. The process forms a drain contact between the drain nodes of two transistors that contacts an area of ​​the local interconnect layer of a particular transistor among the two transistors. This area of ​​the local interconnect layer is not physically adjacent to the active layer of a particular transistor (block 2406). The arrangement of contact 120 on the p-type local interconnect 134 in layout 200 (in Figure 2) illustrates an example of such arrangement with respect to the drain contact. The process forms a memory bit cell using the cross-coupled inverter (block 2408).

[0066] These memory bit cells are arranged in multiple rows and columns to store data (block 2410). In various embodiments, the value of the stored data is maintained by a data storage loop within the memory bit cell. Furthermore, the value of the stored data is updated by write operations. If the array does not receive a read operation (conditional block 2412: "no"), each bit cell maintains its stored binary value (block 2414). For example, each bit cell includes a latch element for storing the binary value until the binary value is modified by a write access operation. If the array receives a read operation (conditional block 2412: "yes"), the bit cells in the row targeted by the read operation carry the data stored in the bit cell to the corresponding read bit line (2416).

[0067] Referring to Figure 25, a generalized block diagram of the computing system 2500 is shown. The computing system 2500 includes a processor 2510 and memory 2530. Interfaces such as the memory controller, bus or communication fabric, one or more phased locked loops (PLLs) and other clock generation circuits, and power management units are not shown for the sake of clarity. In other embodiments, it should be understood that the computing system 2500 includes one or more other processors of the same or different type as the processor 2510, one or more peripheral devices, network interfaces, one or more other memory devices, etc. In some embodiments, the functions of the computing system 2500 are integrated on a system on a chip (SoC). In other embodiments, the functions of the computing system 2500 are integrated on a peripheral card inserted into a motherboard. The computing system 2500 is used in any of a variety of computing devices, such as desktop computers, tablet computers, laptops, smartphones, smartwatches, game consoles, and personal assistant devices.

[0068] The processor 2510 includes hardware such as circuit elements. For example, the processor 2510 includes at least one integrated circuit 2520 that utilizes TFETs to implement memory bit cells 2522 instantiated in one or more memory arrays. In some embodiments, these bit cells 2522 use the circuit of bit cell 400 (Figure 4) and one or more layouts from layouts 500-1200 (Figures 5-12) and layouts 1400-2300 (Figures 14-23). ​​In various embodiments, the processor 2510 includes one or more processing units. In some embodiments, each processing unit includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such embodiments, the processor 2510 is a central processing unit (CPU). In another embodiment, the processing cores are compute units, and each compute unit has a highly parallel data microarchitecture having multiple parallel execution lanes and associated data storage buffers. In this embodiment, the processor 2510 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0069] In some embodiments, memory 2530 includes one or more of the following: a hard disk drive, a solid-state disk, other types of flash memory, a portable solid-state drive, and a tape drive. Memory 2530 stores an operating system (OS) 2532, one or more applications represented by code 2534, and at least source data 2536. Memory 2530 can also store intermediate and final result data generated by the processor 2510 when executing a particular application of code 2534. While a single operating system 2532, and a single instance of code 2534 and source data 2536 are shown, in other embodiments, a different number of these software components are stored in memory 2530. The operating system 2532 includes instructions for starting the boot-up of the processor 2510, assigning tasks to hardware circuits, managing resources of the computing system 2500, and hosting one or more virtual environments.

[0070] Each of the processor 2510 and memory 2530 includes an interface unit for communicating with each other and with any other hardware components included in the computing system 2500. The interface unit includes a queue for handling memory requests and memory responses, and control circuit elements for communicating with each other based on a specific communication protocol. The communication protocol determines various parameters such as power performance status which determines the supply voltage level, operating supply voltage and operating clock frequency, data rate, and one or more burst modes.

[0071] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions for implementing the method and / or mechanism are transported or stored on a computer-readable medium. Numerous types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (ROM, PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, computer-accessible storage media include any storage media that is accessible by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-Ray® discs. Examples of storage media include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (static RAM, SRAM), etc.), ROM, and flash memory, as well as non-volatile memory (e.g., flash memory) accessible via peripheral interfaces such as the Universal Serial Bus (USB) interface. Other examples of storage media include microelectromechanical systems (MEMS) and storage media accessible via communication media such as networks and / or wireless links.

[0072] Additionally, in various embodiments, program instructions include operational-level or register-transfer-level (RTL) descriptions of hardware functions in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII Stream Format (GDSII). In some cases, the descriptions are read by a synthesis tool that synthesizes the descriptions to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware, including the system. The netlist can then be arranged and routed to generate a dataset describing the geometric shapes applied to a mask. The mask can then be used in various semiconductor manufacturing processes to generate semiconductor circuits or circuits corresponding to the system. Alternatively, instructions on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, as needed. Additionally, instructions are used for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0073] Although the embodiments described above are explained in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. It is an integrated circuit, It comprises a first array of memory bit cells arranged as multiple rows and multiple columns, The first memory bit cell of the first array includes a gate contact between the first gate of the first transistor and the second gate of the second transistor that overlaps with only the active layer of either the first active layer of the first transistor or the second active layer of the second transistor. Integrated circuit.

2. Each of the first and second transistors is a vertical gate all-around (GAA) device that utilizes multiple nanosheets as channels. The first array is configured to transmit data stored in the first memory bit cell in response to receiving an indicator for a first read operation targeting any of the plurality of rows, which include the first memory bit cell. The integrated circuit according to claim 1.

3. The second active layer includes channels configured to conduct current in a direction perpendicular to the direction of current flow in the channels of the first active layer, The first active layer and the second active layer do not overlap with each other. The distance between the first active layer and the second active layer is at least the width of the source or drain contact. The integrated circuit according to claim 2.

4. The first memory bit cell includes a drain contact that contacts the area of ​​the local interconnection layer of the second transistor between the drain nodes of the first transistor and the second transistor, The area of ​​the local interconnection layer is not physically adjacent to the second active layer of the second transistor. The integrated circuit according to claim 3.

5. The first memory bit cell includes an asymmetrical layout with respect to the arrangement of transistors and signal nodes within the first memory bit cell. The integrated circuit according to claim 3.

6. A second array of memory bit cells comprising multiple rows and multiple columns, The top metal layer used for signal routing within the second memory bit cell of the second array is the metal zero layer. The integrated circuit according to claim 3.

7. The height of the first memory bit cell is lower than the height of the second memory bit cell. The width of the first memory bit cell is wider than the width of the second memory bit cell. The integrated circuit according to claim 6.

8. It is a method, The first memory bit cell of a first array of memory bit cells is formed, wherein the first memory bit cell includes a gate contact between the first gate of a first transistor and the second gate of a second transistor that overlaps with only the active layer of either the first active layer of the first transistor or the second active layer of the second transistor. This includes arranging a first array of the memory bit cells, which are arranged as multiple rows and multiple columns, within an integrated circuit, method.

9. Each of the first and second transistors is a vertical gate all-around (GAA) device that utilizes multiple nanosheets as channels. The first array of memory bit cells is formed such that it transmits data stored in the first memory bit cell in response to receiving an indicator for a first read operation targeting any of the plurality of rows including the first memory bit cell. The method of claim 8.

10. The second active layer includes channels configured to conduct current in a direction perpendicular to the direction of current flow in the channels of the first active layer, The first active layer and the second active layer do not overlap with each other. The first memory bit cell is formed such that the distance between the first active layer and the second active layer is at least the width of the source or drain contact. The method of claim 9.

11. The first memory bit cell includes a drain contact that contacts the area of ​​the local interconnection layer of the second transistor between the drain nodes of the first transistor and the second transistor, The area of ​​the local interconnection layer is formed such that it is not physically adjacent to the second active layer of the second transistor, including the formation of the first memory bit cell. The method of claim 10.

12. The first memory bit cell is formed such that it includes an asymmetric layout with respect to the arrangement of transistors and signals within the first memory bit cell. The method of claim 10.

13. This includes forming a second array of memory bit cells that include multiple rows and multiple columns, The top metal layer used for signal routing within the second memory bit cell of the second array is the metal zero layer. The integrated circuit according to claim 10.

14. The height of the first memory bit cell is lower than the height of the second memory bit cell. The second memory bit cell is formed such that the width of the first memory bit cell is wider than the width of the second memory bit cell. The method of claim 13.

15. A computing system, An integrated circuit configured to execute instructions using source data, The aforementioned integrated circuit is It comprises a first array of memory bit cells arranged as multiple rows and multiple columns, The first memory bit cell of the first array includes a gate contact between the first gate of the first transistor and the second gate of the second transistor that overlaps with only the active layer of either the first active layer of the first transistor or the second active layer of the second transistor. Computing system.

16. Each of the first and second transistors is a vertical gate all-around (GAA) device that utilizes multiple nanosheets as channels. The first array is configured to transmit data stored in the first memory bit cell in response to receiving an indicator for a first read operation targeting any of the plurality of rows, which include the first memory bit cell. The computing system according to claim 15.

17. The second active layer includes channels configured to conduct current in a direction perpendicular to the direction of current flow in the channels of the first active layer, The first active layer and the second active layer do not overlap with each other. The distance between the first active layer and the second active layer is at least the width of the source or drain contact. The computing system according to claim 16.

18. The first memory bit cell includes a drain contact that contacts the area of ​​the local interconnection layer of the second transistor between the drain nodes of the first transistor and the second transistor, The area of ​​the local interconnection layer is not physically adjacent to the second active layer of the second transistor. The computing system according to claim 17.

19. The first memory bit cell includes an asymmetrical layout with respect to the arrangement of transistors and signals within the first memory bit cell. The computing system according to claim 17.

20. A second array of memory bit cells comprising multiple rows and multiple columns, The top metal layer used for signal routing within the second memory bit cell of the second array is the metal zero layer. The computing system according to claim 17.

Images