Low-temperature parallel-flow epitaxial deposition process

Abstract

A method for selectively depositing epitaxial layers is provided. In some embodiments, the selective epitaxial deposition process includes providing parallel flow of a chlorosilane precursor with at least one of an antimony-containing precursor and a phosphorus-containing precursor. By utilizing the parallel flow of multiple chlorosilane precursors, this method allows for the combination of silicon with at least one of phosphorus and antimony in the same matrix using a low-temperature selective process. Epitaxial layers deposited using the described epitaxial deposition techniques not only contain phosphorus and / or antimony, but also have high concentrations of activated phosphorus and / or antimony.

Description

Technical Field

[0001]

[0001] Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the present disclosure relates to the selective deposition of epitaxial silicon films.

Background Art

[0002]

[0002] Typical selective epitaxy processes involve deposition and etching reactions. The deposition reaction forms an epitaxial layer on the single crystal surface of the substrate, a polycrystalline layer and / or an amorphous layer on the non-single crystal surface, and for example, a patterned dielectric layer deposited on the substrate. The etching reaction removes the epitaxial layer and the polycrystalline layer and / or the amorphous layer at different rates, resulting in a net selective process, so that epitaxial material is deposited and the deposition of polycrystalline material may be limited or not deposited at all.

[0003]

[0003] As the critical dimensions of devices continue to shrink, selective epitaxial deposition methods such as the exemplary method described above require lower processing temperatures (e.g., about 600 °C or less). Unfortunately, typical etching gases cannot provide an appropriate selectivity window between the epitaxial layer and the polycrystalline layer and / or the amorphous layer at such temperatures. Furthermore, current periodic deposition / etching processes are complex processes, difficult to maintain, and have low throughput.

[0004]

[0004] For the above reasons, there is a need for a selective epitaxial process that can be carried out at lower temperatures.

Summary of the Invention

[0005]

[0005] Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the present disclosure relates to the selective deposition of epitaxial silicon films.

[0006]

[0006] In at least one aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate positioned within a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of amorphous second layers arranged in an alternating pattern. The method further includes selectively forming source and drain regions in the crystalline first layer of the substrate. The formed source and drain regions include an n-type dopant precursor concentration of greater than about 1×10 21 atoms / cm 3 . Forming the source and drain regions includes flowing a first chlorosilane precursor gas selected from dichlorosilane and trichlorosilane; flowing a higher-order chlorosilane precursor gas having the formula Cl y Si x H (2X+2-y) [where y is 3 or more and x is 1 or more, and the higher-order chlorosilane precursor gas is different from the first chlorosilane precursor gas] in parallel; flowing an n-type dopant precursor gas in parallel with the first chlorosilane precursor gas and the higher-order chlorosilane precursor gas; and heating the substrate to a temperature of about 550° C. or less.

[0007]

[0007] The implementation may include one or more of the following: The higher-order chlorosilane precursor gas includes trichlorosilane (Cl3SiH), hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or a combination thereof. The flow rate of the higher-order chlorosilane precursor gas to the flow rate of the first chlorosilane precursor gas is 3:1 or more. The flow rate of the higher-order chlorosilane precursor gas to the flow rate of the first chlorosilane precursor gas is 10:1 or more. Forming the source and drain regions further includes maintaining the temperature in the processing region in the range of about 450°C to about 500°C and maintaining the pressure in the processing region in the range of about 10 Torr to about 600 Torr. The n-type dopant precursor is a phosphorus-containing precursor, an antimony precursor, or a combination thereof. The n-type dopant precursor is an antimony-containing precursor, and the concentration of the n-type dopant precursor is the antimony concentration in the source and drain regions, which is 2 × 10⁻⁶. 21 atoms / cm 3 The antimony-containing precursor is one or a combination of stivin, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenyl antimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. The growth rate of the source and drain regions of the crystalline first layer is more than 50 times that of the growth rate of the amorphous second layer. The amorphous second layer further includes dielectric spacers arranged in its outer portion. Multiple gaps are formed adjacent to the amorphous second layer while selectively forming the source and drain regions. This method further includes flowing a first chlorosilane precursor at a flow rate in the range of approximately 100 to approximately 1,000 sccm, flowing a higher-order chlorosilane at a flow rate in the range of approximately 1,000 to approximately 10,000 sccm, and flowing an n-type dopant precursor at a flow rate in the range of approximately 300 to approximately 1,000 sccm. This method further includes flowing hydrogen gas at a flow rate in the range of approximately 1 to approximately 40 SLM.

[0008]

[0008] In another aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate positioned within a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of amorphous second layers arranged in an alternating pattern. The method further includes selectively forming source and drain regions in the crystalline first layer of the substrate. The formed source and drain regions include an n-type dopant precursor concentration greater than about 2×10 21 atoms / cm 3 sup. Forming the source and drain regions includes flowing dichlorosilane; flowing trichlorosilane in parallel; flowing a phosphorus-containing precursor gas in parallel with the dichlorosilane and trichlorosilane; and heating the substrate to a temperature of about 550° C. or less, wherein the ratio of the flow rate of TCS to DCS is in the range of about 3:1 to about 7:1.

[0009]

[0009] The implementation may include one or more of the following. The phosphorus-containing precursor is selected from phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tert-butylphosphine or combinations thereof. The method further includes flowing dichlorosilane at a flow rate in the range of about 700 sccm to about 1000 sccm; flowing trichlorosilane at a flow rate in the range of about 2000 sccm to about 7000 sccm; and flowing phosphine at a flow rate in the range of about 0.1 sccm to 300 sccm. The method further includes flowing an antimony-containing precursor gas at a flow rate in the range of about 10 sccm to about 100 sccm.

[0010]

[0010] In yet another embodiment, a method for forming a semiconductor device is provided. This method includes forming a multi-material layer on a substrate positioned within a processing area. The multi-material layer includes a plurality of crystalline first layers and a plurality of amorphous second layers arranged in an alternating pattern. This method further includes selectively forming a source region and a drain region on the crystalline first layer of the substrate. The formed source region and drain region are approximately 1 × 10 21 atoms / cm 3 The solution contains ultra-high concentrations of n-type dopant precursors. Forming source and drain regions further comprises flowing pentachlorodisilane; flowing trichlorosilane in parallel; flowing an antimony-containing precursor gas in parallel with pentachlorodisilane and trichlorosilane; and heating the substrate to a temperature of about 550°C or less, wherein the flow rate ratio of trichlorosilane to pentachlorodisilane is in the range of about 9:1 to about 16:1.

[0011]

[0011] The implementation may include one or more of the following: The antimony-containing precursor gas is selected from stivin, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony. The method further includes flowing pentachlorodisilane at a flow rate in the range of about 100 sccm to about 1000 sccm; flowing trichlorosilane at a flow rate in the range of about 7000 sccm to about 10000 sccm; and flowing the antimony-containing precursor at a flow rate in the range of about 0.1 sccm and 100 sccm.

[0012]

[0012] In another embodiment, a non-temporary computer-readable medium stores instructions which, when executed by a processor, cause the processor to perform the processing of the above-described apparatus and / or method.

[0013]

[0013] To enable a detailed understanding of the features of the present disclosure described above, a more specific description of the embodiments briefly summarized above can be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of this disclosure, as the present disclosure may also allow for other equally valid embodiments, and therefore should not be considered to limit the scope of the invention. [Brief explanation of the drawing]

[0014] [Figure 1]

[0014] This is a flowchart illustrating a method for forming an epitaxial layer according to one or more aspects of the present disclosure. [Figure 2]

[0015] A schematic isometric view of a horizontal gate-all-around structure according to one or more aspects of the present disclosure is shown. [Figure 3A-3C]

[0016] Figure 2 shows a schematic cross-sectional view of the hGAA structure according to one or more aspects of the present disclosure. [Figure 4]

[0017] This flowchart illustrates another method for forming an epitaxial layer according to one or more aspects of the present disclosure. [Modes for carrying out the invention]

[0015]

[0018] For ease of understanding, the same reference numerals have been used to indicate identical elements common to multiple figures, where possible. It is assumed that elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0016]

[0019] The aspects of this disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More specifically, this disclosure relates to the selective deposition of epitaxial silicon films. A method is provided for epitaxial deposition of n-channel metal oxide semiconductor (NMOS) source / drain regions formed within a device, for example, within a horizontal gate-all-around (hGAA) device structure. This method is carried out at a temperature of 550°C or less. This method includes the use of chlorosilane precursors, higher-order chlorosilane precursors, and n-type dopant precursors selected from antimony-containing precursors, phosphorus-containing precursors, arsenic-containing precursors, or combinations thereof.

[0017]

[0020] Current epitaxial deposition processes struggle to achieve selective Si:P or Si:Sb epitaxial deposition at low temperatures (e.g., below 550°C) with parallel flow because HCl is inactive at these temperatures. As a result, current epitaxial deposition processes employ complex and time-consuming periodic deposition / etching processes, leading to throughput problems. Aspects of this disclosure provide a selective epitaxial deposition process in which a chlorosilane precursor is flowed in parallel with at least one of an antimony-containing precursor and a phosphorus-containing precursor. By utilizing the parallel flow of multiple chlorosilane precursors, aspects of this disclosure enable the combination of silicon with at least one of phosphorus and antimony in the same matrix using a low-temperature selective process. Epitaxial layers deposited using the described epitaxial deposition technique not only contain phosphorus and / or antimony but also have high concentrations of activated phosphorus and / or antimony.

[0018]

[0021] The chlorosilane precursor combinations of this disclosure are used to continuously etch the epitaxial layer during its formation, thereby improving the selectivity of the epitaxial layer when it is deposited on a device such as a superlattice structure. The epitaxial layer forms only on the crystalline portion of the superlattice structure and not on oxide or amorphous surfaces. The antimony-containing precursor lowers the temperature at which the epitaxial layer is deposited and increases the growth rate of the epitaxial layer on the crystalline portion of the superlattice structure. The phosphorus-containing precursor dops the epitaxial layer with phosphorus, enabling better adhesion to the crystalline portion of the superlattice structure.

[0019]

[0022] Furthermore, it has been shown that the growth rate of epitaxial layers on the exposed crystal surface of a superlattice structure can be altered by adding different concentrations of antimony to the epitaxial layer. In some embodiments described, the antimony concentration in the epitaxial layer is approximately 1.0 × 10⁻⁶ 21 atoms / cm 3 It is super, and growth is mainly <110> It is done in a specific direction. The antimony concentration is, <110> It has been shown that this direction primarily induces crystal growth. <110> Crystal growth in a particular direction reduces the facet properties of the epitaxial layer on the superlattice structure.

[0020]

[0023] Figure 1 is a flowchart illustrating a method 100 for forming an epitaxial layer according to one or more embodiments of the present disclosure. In step 110, a substrate, for example, substrate 202, is positioned in a processing chamber. The processing chamber may be a CENTURA® RP Epi chamber, available from Applied Materials, Inc., Santa Clara, California. Other processing chambers, including processing chambers available from other manufacturers, may be used to carry out embodiments of the present disclosure.

[0021]

[0024] The term “substrate” is intended to broadly cover any article or material having a surface on which material layers can be deposited. A substrate may consist of a bulk material such as silicon (e.g., single-crystal silicon that may contain dopants) or one or more layers on top of the bulk material. A substrate may be a planar substrate or a patterned substrate. A patterned substrate is a substrate that may contain electronic features formed in or on the processed surface of the substrate. A substrate may consist of a single-crystal surface and / or a non-single-crystal secondary surface such as a polycrystalline surface or an amorphous surface. A single-crystal surface may consist of a bare crystalline substrate or a deposited single-crystal layer made of materials such as silicon, germanium, silicon-germanium, or silicon-carbon. A polycrystalline or amorphous surface may consist of dielectric materials such as oxides or nitrides, specifically silicon oxide or silicon nitride, as well as amorphous silicon surfaces. The substrate may have various dimensions (e.g., 200mm, 300mm, 450mm, or other diameters) and may be rectangular or square panels. Unless otherwise specified, the embodiments described are performed on substrates with a diameter of 200mm, 300mm, or 450mm.

[0022]

[0025] In at least one embodiment, the substrate includes a first surface and a second surface distinct from the first surface. At least one of the first and second surfaces is single-crystalline, and the other surface is non-single-crystalline. Positioning the substrate within the processing chamber may involve adjusting one or more reactor conditions, such as temperature, pressure, and / or carrier gas flow rate (e.g., Ar, N2, H2, or He), to conditions suitable for epitaxial film formation.

[0023]

[0026] In step 120, the substrate is heated to a temperature of 550°C or less. In at least one embodiment, the temperature in the processing chamber may be adjusted so that the reaction region formed on or near the exposed surface of the substrate, or the surface of the substrate itself, is about 550°C or less, or 500°C or less, or 450°C or less. In one example, the substrate is heated to a temperature in the range of about 400°C to about 550°C, or about 450°C to about 550°C, or about 450°C to about 500°C, or about 400°C to about 500°C. Although not bound by theory, in some embodiments in which Si:P is formed, Si:P deposition at temperatures below 450°C results in a very slow growth rate, and deposition at temperatures above 550°C may affect the heat balance of other materials formed on the substrate. By thermally decomposing the processing reagent and heating the substrate to the lowest temperature sufficient to epitaxially deposit the layer on the substrate, it is possible to minimize the heat balance of the final device. The pressure in the processing chamber can be adjusted so that the reaction region pressure is in the range of about 1 to about 760 Torr, or about 1 Torr to about 600 Torr, or about 100 Torr to about 300 Torr, or about 200 Torr to about 300 Torr. In some embodiments, a carrier gas (e.g., nitrogen) can be flowed into the processing chamber at a flow rate of about 1 to 40 SLM (standard liters / min). Nitrogen remains inert during the low-temperature deposition process. Therefore, nitrogen is not incorporated into the layer being deposited during the low-temperature process. Also, the nitrogen carrier gas does not form a hydrogen-terminated surface like a hydrogen carrier gas. However, it will be understood that in some embodiments, different carrier / diluent gases may be used, for example, inert carrier gases such as argon or helium may be used, different flow rates may be used, or such gases may be omitted.

[0024]

[0027] In step 130, a first chlorosilane precursor gas is introduced into the processing chamber. The first chlorosilane precursor gas contains a precursor comprising both silicon and chlorine. In at least one embodiment, the first chlorosilane gas comprises dichlorosilane (SiCl2H2) (DCS), trichlorosilane (SiCl3H) (TCS), or a combination thereof. In one example, when dichlorosilane is used, it is flowed into the processing chamber at a flow rate in the range of about 100 sccm to about 1000 sccm, or about 700 sccm to about 1000 sccm, or about 800 sccm to about 950 sccm, or about 850 sccm to about 900 sccm. In another example, when trichlorosilane is used, the trichlorosilane is flowed into the processing chamber at a flow rate in the range of approximately 1000 sccm to approximately 10000 sccm, or approximately 7000 sccm to approximately 10000 sccm, or approximately 7500 sccm to approximately 9000 sccm, or approximately 8000 sccm to approximately 8500 sccm.

[0025]

[0028] In step 140, a second chlorosilane precursor gas is introduced into the processing chamber. The second chlorosilane precursor gas is different from the first chlorosilane precursor gas. In at least one embodiment, the second chlorosilane precursor gas is a higher-order chlorosilane gas. The higher-order chlorosilane gas has the formula Cl y Si x H (2x+2-y)The formula has the following properties, where y is 3 or greater, or 5 or greater, and x is 1 or greater, or 2 or greater, or 3 or greater. In one example, y is from 5 to 8 and x is from 2 to 3. In at least one embodiment, the second chlorosilane precursor gas includes, consists of, or is essentially composed of, trichlorosilane, hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or a combination thereof. In another embodiment, the second chlorosilane gas consists of, consists of, or is essentially composed of, pentachlorodisilane (Cl5Si2H), hexachlorodisilane (Si2Cl6), octachlorotrisilane (Cl8Si3), or a combination thereof. In one example, when pentachlorodisilane (PCDS) is used, it is flowed into the treatment chamber at a flow rate in the range of approximately 100 sccm to 1000 sccm, or approximately 300 sccm to 600 sccm, or approximately 400 sccm to 550 sccm, or approximately 450 sccm to 500 sccm. In another example, when trichlorosilane is used, it is flowed into the treatment chamber at a flow rate in the range of approximately 1000 sccm to 10000 sccm, or approximately 7000 sccm to 10000 sccm, or approximately 7500 sccm to 9000 sccm, or approximately 8000 sccm to 8500 sccm.

[0026]

[0029] In step 150, an n-type dopant precursor is introduced into the processing chamber. In at least one embodiment, the n-type dopant precursor includes, consists of, or is essentially composed of, a phosphorus-containing precursor, an antimony precursor, an arsenic-containing precursor, or a combination thereof. In at least one embodiment, the antimony-containing precursor includes one or a combination of stivin, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenyl antimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. In at least one particular embodiment, triethyl antimony is used. The antimony-containing precursor may have a flow rate in the range of about 0.1 sccm to 300 sccm, or in the range of about 10 sccm to about 100 sccm. In at least one embodiment, the phosphorus-containing precursor includes one or a combination of phosphine and alkylphosphine. Suitable alkylphosphines include trimethylphosphine ((CH3)3P), dimethylphosphine ((CH3)2PH), triethylphosphine ((CH3CH2)3P), tert-butylphosphine, and diethylphosphine ((CH3CH2)2PH). In at least one specific embodiment, phosphine is used. Phosphorus-containing precursors may include flow rates in the range of about 0.1 sccm and 1,000 sccm, 0.1 sccm and 300 sccm, or from about 100 sccm to about 300 sccm, or from about 300 to about 1,000 sccm. In at least one embodiment, arsenic-containing precursors include arsine (AsH3), arsenic halogenated compounds, trimethylarsenic, and silylarsine [(H3Si)] 3-x AsR x ](In the equation, x = 0, 1, 2, R x The arsenic-containing precursor may have flow rates in the range of about 0.1 sccm to 1,000 sccm, 0.1 sccm to 300 sccm, or from about 100 sccm to about 300 sccm, or from about 300 to about 1,000 sccm.

[0027]

[0030] Steps 130, 140, and 150 are intended to occur simultaneously, substantially simultaneously, or in any desired order. In at least one embodiment, the first chlorosilane precursor gas, the second chlorosilane precursor gas, the antimony-containing precursor, and the phosphorus-containing precursor are each flowed simultaneously and in parallel into the processing chamber. While not bound by theory, it is believed that flowing the first chlorosilane precursor gas, the second chlorosilane precursor gas, the antimony-containing precursor, and the phosphorus-containing precursor in parallel improves the conductivity of the antimony-doped source / drain region, making it possible to achieve a deposition temperature below 550°C. In one embodiment, at least two precursor gases are mixed before being delivered to the processing region. In another embodiment, at least two precursor gases are delivered separately to the processing region and mixed within the processing region.

[0028]

[0031] In at least one embodiment, the flow rate of the second chlorosilane precursor gas to the flow rate of the first chlorosilane precursor gas is 3:1 or greater, for example, in the range of about 3:1 to about 7:1. In one example, the flow rate of the second chlorosilane precursor gas to the flow rate of the first chlorosilane precursor gas is 10:1 or greater. In another embodiment, the flow rate of the first chlorosilane precursor gas to the flow rate of the second chlorosilane precursor gas is 7:1 or greater, for example, in the range of about 7:1 to about 20:1, or in the range of about 9:1 to about 16:1. In one example, the flow rate of the first chlorosilane precursor gas to the flow rate of the second chlorosilane precursor gas is 10:1 or greater.

[0029]

[0032] In one embodiment, the first chlorosilane precursor gas is dichlorosilane, the second chlorosilane precursor gas is trichlorosilane, and the n-type dopant gas is phosphine. Mixtures of DCS and TCS include mixtures of TCS and DCS in a flow ratio of 2:1 or greater, for example, in the range of about 3:1 to about 7:1. In some embodiments, it has been shown that TCS grows a phosphorus-doped epitaxial layer only in the presence of DCS, and that if DCS is not flowed in parallel, a phosphorus-doped epitaxial layer is not formed, or the rate of formation of the phosphorus-doped epitaxial layer is drastically reduced. DCS has been shown to increase the growth rate of the phosphorus-doped source / drain region. The chlorosilane precursor enables the growth of the phosphorus-doped epitaxial layer. No etch-back treatment is performed when the phosphorus-doped epitaxial layer is growing. Chlorine in the chlorosilane precursor gas has been shown to improve the crystal growth of the epitaxial layer without an additional etch-back process. In one example, dichlorosilane is introduced into the treatment chamber at a flow rate within the range of approximately 700 sccm to 1000 sccm, or approximately 800 sccm to 950 sccm, or approximately 850 sccm to 900 sccm. Trichlorosilane is introduced into the treatment chamber at a flow rate within the range of approximately 1000 sccm to 10000 sccm, or approximately 2000 sccm to 7000 sccm, or approximately 3000 sccm to 6000 sccm, or approximately 3000 sccm to 4000 sccm. Phosphine is introduced into the treatment chamber at a flow rate within the range of approximately 0.1 sccm to 300 sccm, or approximately 100 sccm to 300 sccm.

[0030]

[0033] In another embodiment, the first chlorosilane precursor gas is trichlorosilane (TCS), the second chlorosilane precursor gas is pentachlorodisilane (PCDS), and the n-type dopant gas comprises triethylantimony and optionally phosphine. Mixtures of TCS and PCDS include mixtures of TCS and PCDS in a ratio of about 7:1 to about 20:1, or in the range of about 9:1 to about 16:1. In some embodiments, it has been shown that TCS grows an antimony-doped epitaxial layer only in the presence of PCDS, and that if PCDS is not flowed in parallel, an antimony-doped epitaxial layer is not formed, or the rate of formation of an antimony-doped epitaxial layer is drastically reduced. PCDS has been shown to increase the growth rate of the antimony-doped source / drain region. The chlorosilane precursor gas enables the growth of the antimony-doped epitaxial layer. When an antimony-doped epitaxial layer is grown, no etch-back treatment is performed. Chlorine in the chlorinated silicon precursor has been shown to improve the crystal growth of the epitaxial layer without an additional etch-back process. In one example, PCDS is flowed into the processing chamber at a flow rate in the range of approximately 100 sccm to approximately 1000 sccm, or approximately 300 sccm to approximately 600 sccm, or approximately 400 sccm to approximately 550 sccm, or approximately 450 sccm to approximately 500 sccm. Trichlorosilane is introduced into the processing chamber at a flow rate in the range of approximately 1000 sccm to approximately 10000 sccm, or approximately 7000 sccm to approximately 10000 sccm, or approximately 7500 sccm to approximately 9000 sccm, or approximately 8000 sccm to approximately 8500 sccm. Triethylantimony is introduced into the processing chamber at a flow rate within the range of approximately 0.1 sccm to 100 sccm, or within the range of approximately 100 sccm to 300 sccm. Phosphine is introduced into the processing chamber at a flow rate within the range of approximately 0.1 sccm to 300 sccm, or within the range of approximately 100 sccm to 300 sccm.

[0031]

[0034] In step 160, an n-type doped silicon layer is selectively formed on the first surface. A mixture of a first chlorosilane precursor gas, a second chlorosilane precursor gas, and one or more n-type dopants undergoes a thermal reaction to selectively form an n-type doped silicon layer on the first surface. In one embodiment, the n-type doped silicon layer is 2 × 10⁻¹⁶ 21 atoms / cm 3 For example, 3.5 × 10 21 atoms / cm 3 , 3.9×10 21 atoms / cm 3 , or 4×10 21 atoms / cm 3 This is a phosphorus-doped silicon layer having the above phosphorus concentration. In another embodiment, the n-type doped silicon layer is 1 × 10⁻⁶ 21 atoms / cm 3 For example, 1.5 × 10 21 atoms / cm 3 , 2×10 21 atoms / cm 3 , or 3 × 10 21 atoms / cm 3 This is an antimony-doped silicon layer having the above antimony concentration. In some embodiments, the n-type doped silicon layer is then subjected to a heat treatment process, such as a spike annealing process. The spike annealing process may be carried out at a temperature of about 900°C to about 1200°C for about 1 second to about 30 seconds.

[0032]

[0035] A schematic isometric view of a horizontal gate-all-around (hGAA) structure 200 according to one or more aspects of the present disclosure is shown. A portion of the hGAA structure 200 may be formed according to Method 100. The hGAA structure 200 includes a multi-material layer 205 having alternating first layers 206 and second layers 208 in which spacers 210 are formed. The hGAA structure 200 utilizes the multi-material layer 205 as nanowires (e.g., channels) between the source region 214a and drain region 214b and the gate structure 212. The composition and formation of the source / drain regions 214a, 214b on the hGAA structure 200 will be described. As shown in the cross-sectional view of the multi-material layer 205 in Figure 2, the nanowire spacers 210 formed at the bottom (e.g., or end) of each of the second layer 208 help manage the interface between the second layer 208 and the source / drain 214a, 214b in order to reduce parasitic capacitance and maintain minimal device leakage.

[0033]

[0036] The hGAA structure 200 includes a multi-material layer 205 disposed on the uppermost surface 203 of the substrate 202, such as the top of any material layer 204 disposed on the substrate 202. In embodiments where no material layer 204 is present, the multi-material layer 205 is formed directly on the substrate 202.

[0034]

[0037] In one example, the optional material layer 204 is an insulating material. Preferred examples of insulating materials may include silicon oxide materials, silicon nitride materials, silicon oxynitride materials, or any suitable insulating material. Alternatively, the optional material layer 204 may be any suitable material, including conductive or nonconductive materials as needed. The multi-material layer 205 includes at least one pair of layers, each pair including a first layer 206 and a second layer 208. In the example shown in Figure 2, four pairs and a cap of the first layer 206 are shown, each pair including a first layer 206 and a second layer 208 (alternating pairs, each pair including a first layer 206 and a second layer 208). An additional first layer 206 is placed on top of the multi-material layer 205. The number of pairs may be changed based on the needs of different processes, depending on whether extra first layers 206 or second layers 208 are required. In at least one example, the thickness of each first layer 206 may be in the range of about 20 Å to about 200 Å, for example, about 50 Å, and the thickness of each second layer 208 may be in the range of about 20 Å and about 200 Å, for example, about 50 Å. The multi-material layer 205 may have a total thickness in the range of about 10 Å to about 5000 Å, or in the range of about 40 Å and about 4000 Å.

[0035]

[0038] In at least one embodiment, the first layer 206 is a crystalline material layer, such as a single crystalline silicon layer, a polycrystalline silicon layer, or a monocrystalline silicon layer. The first layer 206 is formed using an epitaxial deposition process. Alternatively, the first layer 206 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. Suitable p-type dopants include B dopant, Al dopant, Ga dopant, In dopant, etc. Suitable n-type dopants include N dopant, P dopant, As dopant, Sb dopant, etc. In yet another example, the first layer 206 is a Group III-V material such as a GaAs layer.

[0036]

[0039] The second layer 208 is an amorphous material layer. In at least one embodiment, the second layer 208 is a Ge-containing layer such as a SiGe layer, a Ge layer, or another suitable layer. Alternatively, the second layer 208 is a doped silicon layer including a p-type doped silicon layer or an n-type doped layer. In yet another example, the second layer 208 is a III-V material such as a GaAs layer. In yet another example, the first layer 206 may be a silicon layer, and the second layer 208 is a metallic material having a coating of a high dielectric constant material on its outer surface. Suitable examples of high dielectric constant materials include, among others, hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate oxide (HfSiO4), hafnium aluminum oxide (HfAlO), zirconium silicate oxide (ZrSiO4), tantalum dioxide (TaO2), aluminum oxide, aluminum-doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT). In one particular example, the coating layer is a hafnium dioxide (HfO2) layer. In at least one embodiment, the second layer 208 is made of a material similar to the gate structure 212 and forms a wrap-around gate around the first layer 206.

[0037]

[0040] Spacer 210 is formed adjacent to the edge of the second layer 208 and may be considered part of the second layer 208. Spacer 210 is a dielectric spacer or void. Spacer 210 may be formed by etching off each portion of the second layer 208 using an etching precursor to form a recess at each edge of the second layer 208. Spacer 210 is formed in the recess adjacent to each of the second layer 208. A liner layer (not shown) may be further deposited in the recess before the deposition of spacer 210. Spacer 210 is formed from a dielectric material and separates each of the nanowires or nanosheets formed as the first layer 206. In at least one embodiment, spacer 210 is selected to be a silicon-containing material, such as a low dielectric constant material, which can reduce parasitic capacitance between the gate structure and the source / drain structure in the hGAA nanowire structure. Silicon-containing materials or low dielectric constant materials may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbide nitride, doped silicon layers, or other suitable materials such as Black Diamond® material available from Applied Materials.

[0038]

[0041] In at least one example, the spacer 210 is a low dielectric constant material (e.g., dielectric constant less than 4) or a silicon oxide / silicon nitride / silicon carbide-containing material. In another example, the spacer 210 is a void.

[0039]

[0042] The gate structure 212 is positioned on and around the multi-material layer. According to one embodiment, the gate structure 212 includes a gate electrode layer and may further include a gate dielectric layer, a gate spacer, and a mask layer. The gate electrode layer of the gate structure 212 includes a polysilicon layer or a metal layer capped with a polysilicon layer. The gate electrode layer is made of a metal nitride (titanium nitride (TiN), tantalum nitride (TaN), or molybdenum nitride (MoN)). x ) etc.), metal carbides (tantalum carbide (TaC) or hafnium carbide (HfC), etc.), metal nitrides-carbides (TaCN, etc.), metal oxides (molybdenum oxide (MoOx ) etc.), metal oxynitrides (molybdenum oxynitride (MoO x N y ) may include metal silicides (such as nickel silicide), or combinations thereof.

[0042] The gate electrode layer is positioned on top of and around the multi-material layer 205.

[0040]

[0043] The gate dielectric layer may optionally be placed below the gate electrode layer and below the multi-material layer 205. The optional gate dielectric layer may be silicon dioxide (SiO₂). x This may include ) which may be formed by thermal oxidation of one or more of the first layer 206 and / or the second layer 208, or by any suitable deposition process. Suitable materials for forming the gate dielectric layer include silicon oxide, silicon nitride, oxynitride, metal oxides (hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2)). x ), hafnium silicon oxide (HfSiO x ), hafnium titanium oxide (HfTiO x ), hafnium aluminum oxide (HfAlO x This includes (etc.), as well as combinations thereof and multi-material layers. Gate spacers are formed on the sidewalls of the gate electrode layer. Each gate spacer includes a nitride portion and / or an oxide portion. A mask layer is formed on top of the gate electrode layer, and the mask layer may contain silicon nitride.

[0041]

[0044] The hGAA structure 200 is formed using the method 400 shown in Figure 4. The described hGAA structure 200 is an n-channel metal oxide semiconductor (NMOS) device. Therefore, the dopants in the hGAA structure 200 are n-type dopants such as phosphorus, antimony, or a combination thereof. In at least one embodiment, the n-type dopant includes phosphorus (P). In at least another embodiment, the n-type dopant includes antimony (Sb). In yet another embodiment, the n-type dopant includes both phosphorus (P) and antimony (Sb).

[0042]

[0045] The multi-material layer 205 and gate structure 212 described with respect to Figure 2 are formed on the substrate 202 and an optional material layer 204 during step 410. After step 410, the hGAA structure 200 is similar to the structure shown in Figure 2A. The combination of the multi-material layer 205 and the gate structure 212 may be described as a film laminate. During step 410, the multi-material layer 205 is formed by using multiple deposition processes to form multiple alternating layers of a first layer 206 and a second layer 208. A portion of the second layer 208 is etched back to form a spacer 210.

[0043]

[0046] The gate structure 212 is formed around the multi-material layer 205. In at least one embodiment, the gate electrode layer of the gate structure 212 is made of a material similar to the material of each of the second layers 208 within the multi-material layer 205. The gate structure 212 and the second layers 208 form a wrap-around gate around each of the first layers 206. The first layers 206 act as nanowires or nanosheets placed within the wrap-around gate. After the formation of the source / drain regions, the first layers 206 function as channels between the source / drain regions.

[0044]

[0047] After the formation of the film laminate in step 410, n-type doped source / drain regions 214a and 214b are formed in step 420, as shown in Figure 2B. The n-type doped source / drain regions 214a and 214b formed in step 420 may be formed according to method 100. During step 420, a deposition gas mixture is introduced into the processing chamber to deposit the n-type doped source / drain regions 214a and 214b. As shown in Figure 2B, the n-type doped source / drain regions 214a and 214b are deposited on the substrate 202 and on the first layer 206 within the multi-material layer 205, respectively. In at least one embodiment, the n-type doped source / drain regions 214a and 214b have a thickness ranging from about 1 nm to about 10 nm. The n-type doped source / drain regions 214a, 214b are deposited by an epitaxial deposition process, such as a selective epitaxial deposition process as described in Method 100. In at least one embodiment, the n-type doped source / drain regions 214a, 214b are selectively deposited on the first layer 206 and exposed portions of the substrate 202, which are made from a crystalline material such as Si, and the n-type doped source / drain regions 214a, 214b are not deposited on the gate structure 212 or spacer 210, which are made from a dielectric material.

[0045]

[0048] In at least one embodiment, the deposition gas mixture comprises a first chlorosilane precursor, a second chlorosilane precursor, and an n-type dopant, as described.

[0046]

[0049] The amount of excess point defects in the n-type doped source / drain regions 214a and 214b can be controlled by changing processing conditions such as the partial pressure of the precursor, the ratio of the precursors, the processing temperature, and / or the layer thickness. The amount of excess point defects in the n-type doped source / drain regions 214a and 214b can control the diffusion of antimony atoms into the first layer 206 of the multimaterial layer 205. During the deposition of the n-type doped source / drain regions 214a and 214b, Sb atoms can diffuse into the first layer 206 of the multimaterial layer 205. The P dopant is added to the n-type doped source / drain regions 214a and 214b using a P-containing precursor. The P-containing precursor is flowed simultaneously through both the chlorosilane-containing precursor and the antimony-containing precursor.

[0047]

[0050] The first chlorosilane-containing precursor gas, the second chlorosilane-containing precursor gas, and the n-type dopant precursor gas are each flowed into the processing chamber simultaneously and in parallel. By flowing the first chlorosilane-containing precursor gas, the second chlorosilane-containing precursor gas, and the n-type dopant precursor gas in parallel, the conductivity of the antimony and / or phosphorus-doped source / drain regions 214a, 214b is improved, and the deposition temperature can be reduced to below 550°C. In some embodiments, the phosphorus-containing precursor is a common n-type dopant precursor. In one example described, the ratio of the first chlorosilane-containing precursor gas, the second chlorosilane-containing precursor gas, and the n-type dopant precursor gas (e.g., phosphorus) flowing into the processing chamber is approximately 3:1:0.1 to approximately 7:1:0.3 for TCS / DCS / PH3. In another example described, the ratio of the first chlorosilane precursor gas, the second chlorosilane precursor gas, and the n-type dopant precursor gas (e.g., antimony) flowing into the processing chamber is approximately 7:1:0.1 to approximately 20:1:1, or approximately 9:1:0.1 to approximately 16:1:0.1 in the case of TCS / PCDS / TeSb. In yet another example described, the ratio of the first chlorosilane precursor gas, the second chlorosilane precursor gas, and the n-type dopant precursor gas (e.g., antimony) flowing into the processing chamber is approximately 3:1:0.1:0.1 to approximately 7:1:0.3:0.3 in the case of TCS / PCDS / TeSb / PH3.

[0048]

[0051] In one example, the n-type doped source / drain regions 214a and 214b are 2.0 × 10⁻⁶. 21 atoms / cm 3 For example, 3.5 × 10 21 atoms / cm 3 , 3.9×10 21 atoms / cm 3 , or 4.0 × 10 21 atoms / cm 3 It has the above phosphorus concentration. In another example, the n-type doped source / drain regions 214a, 214b have a phosphorus concentration of 1.0 × 10⁻⁶. 21 atoms / cm 3 For example, 1.5 × 10 21 atoms / cm 3, 2.0×10 21 atoms / cm 3 , or 3.0 × 10 21 atoms / cm 3 It has the above antimony concentration. In another example, the n-type doped source / drain regions 214a, 214b have a concentration of 1.0 × 10⁻⁶. 21 atoms / cm 3 For example, 1.5 × 10 21 atoms / cm 3 , 2.0×10 21 atoms / cm 3 , or 3.0 × 10 21 atoms / cm 3 The antimony concentration is as described above. The phosphorus dopant concentration in the deposited n-type doped source / drain regions 214a and 214b is approximately 2.0 × 10⁻⁶. 21 atoms / cm 3 From approximately 4.0 x 10 21 atoms / cm 3 Therefore, low-temperature deposition of n-type doped source / drain regions 214a and 214b further reduces antimony migration to the multi-material 205 and other parts of the substrate, as antimony diffusion can cause degradation of device performance.

[0049]

[0052] The concentration of antimond dopant in the n-type doped source / drain regions 214a and 214b alters the growth rate of the n-type doped source / drain regions 214a and 214b. In embodiments where the antimond dopant concentration is low, or where the antimond dopant is not flowed in parallel, the deposition rate of the n-type doped source / drain regions 214a and 214b is found to be significantly reduced at temperatures below 550°C. In some embodiments, the antimony concentration in the n-type doped source / drain regions 214a and 214b has been found to more than double the deposition rate compared to processes without antimony-containing precursors. In some embodiments, the growth rate of the n-type doped source / drain regions 214a and 214b is close to zero at temperatures below 550°C in both crystalline and amorphous locations on the substrate, without simultaneously flowing both the antimony-containing precursor and the chlorosilane precursor in parallel. The antimony in the antimony-containing precursor acts to lower the surface activation energy of the first layer 206, causing the formation of n-type doped source / drain regions 214a and 214b. The growth rate of the n-type doped source / drain regions 214a and 214b is highly selective to the crystal structure, such that the growth rate of the n-type doped source / drain regions 214a and 214b on the first layer 206 is more than 100 times, for example more than 150 times, the growth rate of the n-type doped source / drain regions 214a and 214b on the spacer 210 and gate structure 212. In some embodiments, the growth rate of the n-type doped source / drain regions 214a and 214b is about 10 angstroms / min to about 20 angstroms / min.

[0050]

[0053] In some embodiments, the deposition of n-type doped source / drain regions 214a, 214b with antimony is carried out in a first processing chamber, and the doping of n-type doped source / drain regions 214a, 214b with phosphorus is carried out in a second processing chamber. In yet another embodiment, the formation of n-type doped source / drain regions 214a, 214b with antimony and the doping of n-type doped source / drain regions 214a, 214b with phosphorus are carried out in a single chamber.

[0051]

[0054] Following step 420, step 430 is performed to heat-treat the hGAA structure 200. In at least one embodiment, the heat treatment of the hGAA structure is a spike annealing process. The spike annealing process is performed at a temperature of about 900°C to about 1200°C for about 1 to 30 seconds. Due to the large size of the Sb atoms, they do not diffuse at the same rate as the P dopant. Therefore, short-duration spike annealing suppresses the diffusion of Sb atoms, while allowing some of the P dopant to diffuse into the first layer 206, as shown in Figure 3C, to form a doped region 320 of the first layer 206 of the multimaterial layer 205.

[0052]

[0055] Maintaining the temperature in steps 420 and 430 below approximately 550°C reduces dopant diffusion and warping of the multi-material layer 205.

[0053]

[0056] After the formation of the n-type doped source / drain regions 214a and 214b, a capping layer (not shown) may optionally be deposited on the hGAA structure 200. The capping layer is a silicon-containing layer and is deposited on top of the n-type doped source / drain regions 214a and 214b and the spacer 210, so that the capping layer fills the gap 211.

[0054]

[0057] Examples

[0058] The following non-limiting embodiments are provided to further illustrate the embodiments described. However, these embodiments are not intended to be comprehensive or to limit the scope of the embodiments described.

[0055]

[0059] The examples were carried out on an exposed crystalline silicon wafer having a patterned silicon nitride layer deposited on an exposed crystalline silicon layer. The patterned silicon nitride layer exposes trenches formed within the crystalline silicon.

[0056]

[0060] Examples of Si:P: TIFF2026510515000002.tif36170Table I

[0057]

[0061] Examples of Si:Sb:P: TIFF2026510515000003.tif26170 Table II

[0058]

[0062] Examples of Si:Sb: TIFF2026510515000004.tif36170 Table III

[0059]

[0063] The summary of the invention, the modes for carrying out the invention, the claims, and the accompanying drawings refer to specific features of the disclosure (including method processes). It should be understood that the disclosure herein includes all possible combinations of such specific features. For example, if a particular feature is disclosed in the context of a particular aspect, embodiment, or example of the disclosure, or in the context of a particular claim, that feature may, to the extent possible, be used in combination with other particular aspects and embodiments of the disclosure and / or in the context of the disclosure as a whole.

[0060]

[0064] The term “comprises” and its grammatical equivalents are used to mean that other components, ingredients, processes, etc., may optionally be present. For example, an article “comprising” (or “which comprises”) components A, B, and C may consist only of components A, B, and C (i.e., contain only components A, B, and C), or it may contain not only components A, B, and C but also one or more other components. In addition, whenever a transitional phrase or its grammatical equivalent “comprising” precedes a composition, element, or group of elements, it is understood that such a list of compositions or elements may be preceded by a group of compositions or elements having the transitional phrases “consisting essentially of,” “consisting of,” “selected from the group of consisting of,” or “is,” and vice versa.

[0061]

[0065] When referring to a method that includes two or more prescribed processes, the prescribed processes can be performed in any order or simultaneously (unless the context excludes such possibility), and the method may include one or more other processes that are performed before any prescribed process, between two of the prescribed processes, or after all of the prescribed processes (unless the context excludes such possibility).

[0062]

[0066] When describing elements of this disclosure, or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to indicate that there is one or more elements.

[0063]

[0067] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for forming a semiconductor device, Forming a multi-material layer on a substrate positioned within a processing area, wherein the multi-material layer includes a plurality of crystalline first layers and a plurality of amorphous second layers arranged in an alternating pattern; The method involves selectively forming a source region and a drain region on the crystalline first layer of the substrate, wherein the formed source region and drain region are approximately 1 × 10 ２１ atoms / cm ３ It contains an ultra-high concentration of n-type dopant precursors and forms the source region and the drain region: A first chlorosilane precursor gas selected from dichlorosilane and trichlorosilane is passed through the system; A higher chlorosilane precursor gas, which has the formula Cl ｙ Si ｘ H （２Ｘ＋２－ｙ） A higher chlorosilane precursor gas having [wherein y is 3 or more, x is 1 or more, and the higher chlorosilane precursor gas is different from the first chlorosilane precursor gas] is flowed in parallel; The n-type dopant precursor gas is flowed in parallel with the first chlorosilane precursor gas and the higher-order chlorosilane precursor gas; The substrate is heated to a temperature of approximately 550°C or lower. Furthermore, selectively forming source and drain regions, including; Methods that include...

2. The method according to claim 1, wherein the higher-order chlorosilane precursor gas includes trichlorosilane (Cl3SiH), hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or a combination thereof.

3. The method according to claim 1, wherein the flow rate of the higher-order chlorosilane precursor gas to the flow rate of the first chlorosilane precursor gas is 3:1 or greater.

4. The method according to claim 3, wherein the flow rate of the higher-order chlorosilane precursor gas to the flow rate of the first chlorosilane precursor gas is 10:1 or more.

5. The method according to claim 3, further comprising forming the source region and the drain region by maintaining the temperature in the processing region in the range of about 450°C to about 500°C and maintaining the pressure in the processing region in the range of about 10 Torr to about 600 Torr.

6. The method according to claim 1, wherein the n-type dopant precursor is a phosphorus-containing precursor, an antimony precursor, or a combination thereof.

7. The n-type dopant precursor is an antimony-containing precursor, and the concentration of the n-type dopant precursor is approximately 2 × 10 in the source region and the drain region. ２１ atoms / cm ３ The method according to claim 1, wherein the antimony concentration is above the limit.

8. The method according to claim 7, wherein the antimony-containing precursor is one or a combination of stivin, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony.

9. The method according to claim 1, wherein the growth rate of the source region and the drain region of the crystalline first layer is more than 50 times the growth rate of the amorphous second layer.

10. The method according to claim 9, wherein the amorphous second layer further comprises a dielectric spacer disposed on its outer portion.

11. The method according to claim 10, wherein a plurality of gaps are formed adjacent to the amorphous second layer during the selective formation of the source region and the drain region.

12. The first chlorosilane precursor is flowed at a flow rate in the range of approximately 100 to approximately 1,000 sccm; The aforementioned higher chlorosilane is flowed at a flow rate in the range of approximately 1,000 to approximately 10,000 sccm; The n-type dopant precursor is flowed at a flow rate in the range of approximately 300 to approximately 1,000 sccm. The method according to claim 3, further comprising:

13. The method according to claim 12, further comprising flowing hydrogen gas at a flow rate in the range of about 1 to about 40 SLMs.

14. A method for forming a semiconductor device, Forming a multi-material layer on a substrate positioned within a processing area, wherein the multi-material layer includes a plurality of crystalline first layers and a plurality of amorphous second layers arranged in an alternating pattern; Selectively forming source and drain regions on the crystalline first layer of the substrate, wherein the formed source and drain regions contain an n-type dopant precursor concentration of greater than about 2×10 ２１ atoms / cm ３ superscript, and forming the source and drain regions comprises: Discharging dichlorosilane; Streaming trichlorosilane in parallel; The phosphorus-containing precursor gas is flowed in parallel with the dichlorosilane and the trichlorosilane; Heating the substrate to a temperature of approximately 550°C or lower, wherein the ratio of the flow rate of TCS to DCS is in the range of approximately 3:1 to approximately 7:1; Furthermore, selectively forming source and drain regions, including; Methods that include...

15. The method according to claim 14, wherein the phosphorus-containing precursor is selected from phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tert-butylphosphine, or a combination thereof.

16. The aforementioned dichlorosilane is flowed at a flow rate in the range of approximately 700 sccm to approximately 1000 sccm; The trichlorosilane is flowed at a flow rate in the range of approximately 2000 sccm to approximately 7000 sccm; The phosphine is flowed at a flow rate in the range of approximately 0.1 sccm and 300 sccm. The method according to claim 14, further comprising:

17. The method according to claim 16, further comprising flowing an antimony-containing precursor gas at a flow rate in the range of about 10 sccm to about 100 sccm.

18. A method for forming a semiconductor device, Forming a multi-material layer on a substrate positioned within a processing area, wherein the multi-material layer includes a plurality of crystalline first layers and a plurality of amorphous second layers arranged in an alternating pattern; The method involves selectively forming a source region and a drain region on the crystalline first layer of the substrate, wherein the formed source region and drain region are approximately 1 × 10 ２１ atoms / cm ３ It contains an ultra-high concentration of n-type dopant precursors and forms the source region and the drain region: Discharging pentachlorodisilane; Streaming trichlorosilane in parallel; The antimony-containing precursor gas is flowed in parallel with the pentachlorodisilane and the trichlorosilane; Heating the substrate to a temperature of approximately 550°C or lower, wherein the ratio of the flow rate of trichlorosilane to pentachlorodisilane is in the range of approximately 9:1 to approximately 16:1; Furthermore, selectively forming source and drain regions, including; Methods that include...

19. The method according to claim 18, wherein the antimony-containing precursor gas is selected from stivyn, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony.

20. The aforementioned pentachlorodisilane is flowed at a flow rate in the range of approximately 100 sccm to approximately 1000 sccm; The trichlorosilane is flowed at a flow rate in the range of approximately 7,000 sccm to approximately 10,000 sccm; The antimony-containing precursor is flowed at a flow rate in the range of approximately 0.1 sccm and 100 sccm. The method according to claim 18, further comprising:

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