Techniques for efficient multiplication of complex vectors

Abstract

A processing circuit is provided for performing vector operations, and an instruction decoder circuit is used to decode instructions from a set of instructions in order to control the processing circuit for performing the vector operations specified by the instructions. Array storage is used, having storage elements for storing data blocks, and when performing vector operations, it stores at least one two-dimensional array of data blocks accessible to the processing circuit. The set of instructions includes a complex-valued cross product instruction specifying a first source operand, a second source operand, and a destination operand, each of which the first and second source operands are vector operands containing multiple source data elements, each source data element being a complex number formed from a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks in the array storage. The processing circuit, in response to a complex-valued cross product instruction, performs a cross product operation using the source data elements of the first source operand and the source data elements of the second source operand to generate multiple result data elements. Each result data element is a complex number formed from a real part and an imaginary part, and each real part and imaginary part of each result data element is associated with one of the data blocks in a given two-dimensional array of data blocks and used to update the value of that associated data block.

Description

Technical Field

[0001] This technology relates to the field of data processing, and more specifically, to a technology for efficiently performing multiplication of complex numbers.

Background Art

[0002] For example, in order to improve performance by enabling parallel processing of a plurality of complex numbers, a plurality of complex numbers can be provided within a vector so that vector calculations can be performed. However, in relation to performing calculations on complex numbers, there can still be a significant impact on performance, and in many cases, the execution of multiple vector instructions is required to perform the necessary calculations.

[0003] For example, in digital signal processing (DSP) algorithms, communication infrastructure 5G applications, high performance computing (HPC) applications, etc., there are many computational tasks that require complex number arithmetic. In many cases, multiplication of complex numbers is required, and considering the requirements for computational resources usually needed to perform such complex number multiplication operations, it is desirable to provide a technology for accelerating such multiplication operations and thereby improving performance / throughput.

Summary of the Invention

[0004] In one exemplary configuration, a device is provided which comprises a processing circuit for performing vector operations, an instruction decoder circuit for decoding instructions from a set of instructions to control the processing circuit for performing the vector operations specified by the instructions, and an array storage having storage elements for storing data blocks, the array storage being configured to store at least one two-dimensional array of data blocks accessible to the processing circuit when performing vector operations, wherein the set of instructions includes a complex-valued cross product instruction specifying a first source operand, a second source operand, and a destination operand, each of the first and second source operands being a plurality of The source operand is a vector operand containing data elements, where each source data element is a complex number formed from a real part and an imaginary part. The destination operand identifies a given two-dimensional array of data blocks in array storage. The processing circuit, in response to a complex-valued cross product instruction, performs a cross product operation using the source data elements of the first source operand and the source data elements of the second source operand to generate multiple result data elements, where each result data element is a complex number formed from a real part and an imaginary part. Each real part and each imaginary part of each result data element is associated with one of the data blocks in the given two-dimensional array of data blocks and used to update the value of that associated data block.

[0005] Another exemplary configuration provides a method which includes: performing a vector operation using a processing circuit; decoding instructions from a set of instructions to control the processing circuit for performing the vector operation specified by the instructions; and using array storage having storage elements for storing data blocks, configured to store at least one two-dimensional array of data blocks accessible to the processing circuit when performing a vector operation, wherein the set of instructions includes a complex-valued cross product instruction specifying a first source operand, a second source operand, and a destination operand, each of the first and second source operands being a plurality of source data The method is a vector operand containing elements, where each source data element is a complex number formed from a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks in array storage. The method includes using a processing circuit to perform an cross product operation using the source data elements of a first source operand and the source data elements of a second source operand to generate a plurality of result data elements in response to a complex-valued cross product instruction, where each result data element is a complex number formed from a real part and an imaginary part, and each real part and each imaginary part of each result data element is associated with one of the data blocks in a given two-dimensional array of data blocks and used to update the value of the associated data block.

[0006] In a further exemplary configuration, a computer program is provided for controlling a host data processing device to provide an instruction execution environment, the computer program including: a processing program logic for performing vector operations; an instruction decoding program logic for decoding instructions from a set of instructions to control the processing program logic for performing the vector operations specified by the instructions; and an array storage emulate program logic for emulating array storage, which has storage elements for storing data blocks and is configured to store at least one two-dimensional array of data blocks accessible to the processing program logic when performing vector operations, wherein the set of instructions includes a first source operand, a second source operand, and a destination operand. The program includes a specified complex-valued cross product instruction, where each of the first and second source operands is a vector operand containing multiple source data elements, each source data element being a complex number formed from a real part and an imaginary part; the destination operand identifies a given two-dimensional array of data blocks in array storage; and the processing program logic, in response to the complex-valued cross product instruction, performs a cross product operation using the source data elements of the first and second source operands to generate multiple result data elements, each result data element being a complex number formed from a real part and an imaginary part; each real part and each imaginary part of each result data element is associated with one of the data blocks in a given two-dimensional array of data blocks and used to update the value of the associated data block. Such a computer program can be placed on any known temporary computer-readable medium (such as wired or wireless transmission of code over a network) or on a non-temporary computer-readable medium such as a semiconductor, magnetic disk, or optical disk. [Brief explanation of the drawing]

[0007] This technology will be further described with reference only to the embodiments of this technology shown in the attached drawings. [Figure 1] This is a block diagram of a data processing unit. [Figure 2] One embodiment of an architectural register that may be provided in a device including a vector register for storing vector operands and an array register for storing a 2D array of data elements is shown, and one embodiment of a physical implementation of the array register is shown. [Figure 3A] This outlines how access to a square 2D array within array storage can be performed. [Figure 3B] This outlines how access to a square 2D array within array storage can be performed. [Figure 4A] This demonstrates the cross product operation. [Figure 4B] This demonstrates matrix multiplication. [Figure 5] This is a block diagram of a device according to an exemplary implementation, showing how a processing circuit can be used to perform an cross product operation on a vector of complex numbers. [Figure 6] This flowchart illustrates the steps performed according to an exemplary embodiment to carry out an cross product operation on a vector of complex numbers. [Figure 7] This shows a dot product circuit that can be used to perform a dot product operation on real numbers. [Figure 8] Figure 7 shows how two instances of the dot product circuit can be used to multiply two complex numbers as part of a complex-valued cross product and cumulative operation performed on two vectors of complex numbers. [Figure 9] This demonstrates the execution of the cross product operation on two vectors of complex numbers using multiple instances of the dot product circuit. [Figure 10] To coordinate how the real and imaginary parts of at least one source data element are supplied to the associated dot product circuit, an exemplary implementation shows how an input operation circuit may be provided in relation to the dot product circuit. [Figure 11]This figure shows in more detail an input operation circuit used according to one exemplary embodiment. [Figure 12A] To enable the execution of various other variants of the complex-valued cross product operation, we will show how data manipulation circuits can be used in relation to pairs of dot product circuits, as shown in Figure 8. [Figure 12B] To enable the execution of various other variants of the complex-valued cross product operation, we will show how data manipulation circuits can be used in relation to pairs of dot product circuits, as shown in Figure 8. [Figure 12C] To enable the execution of various other variants of the complex-valued cross product operation, we will show how data manipulation circuits can be used in relation to pairs of dot product circuits, as shown in Figure 8. [Figure 13] This paper demonstrates how arrays of multiplier-based circuits can be used to support performing cross product operations on vectors of real numbers, and how pairs of those circuits can be combined to support dot product calculations used when performing cross product operations on vectors of complex numbers, according to one exemplary embodiment. [Figure 14] A schematic diagram of an eight-way dot product circuit, which can be used to perform a dot product operation on two vectors of eight real numbers, is shown. [Figure 15] According to one exemplary embodiment, we demonstrate how multiple instances of such an 8-input dot product circuit can be used when performing an exterior sum product operation on a vector of complex numbers. [Figure 16] This demonstrates the execution of the cross product sum operation on two vectors of complex numbers using multiple instances of the dot product circuit. [Figure 17] According to an exemplary embodiment, the real and imaginary parts of a complex number in one of the vectors may be manipulated before being fed into the pair of dot product circuits when performing an exterior sum product operation. [Figure 18] This shows the possible implementation forms of the simulator that can be used. [Modes for carrying out the invention]

[0008] A device is provided having a processing circuit for performing vector operations and an instruction decoder circuit for decoding instructions from a set of instructions in order to control the processing circuit for performing vector operations specified by the instructions. For example, the instruction decoder circuit may respond to instructions in the set of instructions to generate a control signal, and the control signal may control the processing circuit for performing vector operations.

[0009] A vector operation is an operation performed on a vector operand, for example, an operand containing multiple data elements. A vector operation can include any operation with at least one vector operand, such as a load or store operation to load / store a vector from / to a storage location (e.g., memory or cache), or an arithmetic operation (e.g., addition, multiplication) performed on a vector operand. In this technology, the processing circuit can perform a vector operation that includes at least an cross product. Vector operands can be stored in vector registers (though not necessarily), a single vector register can store an entire vector operand, or a single vector operand can be distributed among multiple vector registers (thus, a single vector register can store elements from multiple vector operands).

[0010] Array storage is also provided according to the technology described herein, which comprises storage elements for storing data blocks and is configured to store at least one two-dimensional array of data blocks accessible to processing circuits when performing vector operations.

[0011] Furthermore, in accordance with the techniques described herein, the instruction set includes a complex-valued outer product instruction that specifies a first source operand, a second source operand, and a destination operand. Each of the first source operand and the second source operand is a vector operand that includes a plurality of source data elements, and each source data element is a complex number formed from a real part and an imaginary part. The destination operand is configured to identify a given two-dimensional array of data blocks within an array storage. Note that the terms "first" and "second" are merely labels, and the first and second source operands are not necessarily the first and second operands specified by the complex-valued outer product instruction. Conversely, the first and second operands can be identified in either order by the complex-valued outer product instruction.

[0012] In response to the complex-valued outer product instruction, the processing circuit performs an outer product operation using the source data elements of the first source operand and the source data elements of the second source operand to generate a plurality of result data elements. Each result data element is a complex number formed from a real part and an imaginary part, and each real part and each imaginary part of each result data element are associated with one of the data blocks within a given two-dimensional array of data blocks and are used to update the value of the associated data block.

[0013] In some cases, there may be a one-to-one correspondence between the real part of the result data element and the associated data block in the 2D array, and similarly between the imaginary part of the result data element and the associated data block in the 2D array. Therefore, the value in any given data block may be updated according to one of the associated real or imaginary parts of the result data elements. However, in some other examples, such as when performing an outer product sum operation of complex numbers (to be described in more detail later), the real parts of multiple result data elements may be associated with one corresponding data block in the 2D array, and similarly, the imaginary parts of multiple result data elements may be associated with one corresponding data block in the 2D array. In that case, the value in any given data block is updated according to multiple associated real parts or multiple associated imaginary parts.

[0014] By defining an instruction (a complex number value outer product instruction) that enables performing an outer product operation on a vector of complex numbers in response to a single instance of an instruction, significant performance and throughput advantages can be realized when performing tasks that require intensive use of multiplication operations with respect to complex numbers. In particular, such an approach allows performing the multiplication of a vector of complex numbers using the execution of a single instruction, whereas previously it was necessary to execute multiple instructions to perform the calculations required to generate the multiplication result. Furthermore, by configuring to perform the desired multiplication via an outer product operation and using the result to update a two-dimensional array of data blocks provided in array storage, efficient use of processing resources can be achieved. This enables, for example, easily incorporating an accumulation (or subtraction) operation when performing calculations and can provide some additional benefits. For example, by using the same destination operand (i.e., the same two-dimensional array of data blocks) for multiple instances of the complex number value outer product instruction, this can provide a particularly efficient mechanism for performing a matrix multiplication operation on a vector of complex numbers.

[0015] In one exemplary implementation, both the first and second source operands are configured to interleave the real and imaginary parts of multiple source data elements. This allows for particularly efficient implementation when performing cross product operations, by logically grouping the data elements required by various computational blocks within the processing circuit to provide those computational blocks with those elements. In particular, in one exemplary implementation, separate computational blocks can be used to generate each part (real or imaginary part) of each resulting data element, and each computational block needs to be supplied with the real and imaginary parts of at least two data elements (at least one from each source operand) as input. Thus, interleaving the real and imaginary parts of multiple source data elements within each source operand reduces the complexity of the routing circuitry used to supply the necessary inputs to each computational block.

[0016] Furthermore, in one exemplary implementation, within at least one dimension of a given two-dimensional array of data blocks, the real and imaginary parts of multiple result data elements are associated with the data block such that the real parts of the multiple result data elements are interleaved with the imaginary parts of the multiple result data elements. Again, this enables a particularly efficient implementation and reduces the complexity of routing between the compute blocks in the two-dimensional array and the associated data blocks.

[0017] The processing circuit can be configured in various ways to enable the execution of the cross product operation. However, in one exemplary implementation, the processing circuit comprises a dot product circuit associated with each data block in a given two-dimensional array of data blocks. The dot product circuit associated with a given data block may be configured to perform a dot product operation using at least one source data element of a first source operand and the real and imaginary parts of at least one source data element of a second source operand to generate the required portion (which may be either the real or imaginary part, depending on the dot product circuit under consideration) of at least one resulting data element used to update the value of the given data block. By using multiple instances of the dot product circuit, it is possible to implement the circuit required within the processing circuit for performing the cross product operation on a vector of complex numbers particularly efficiently. In fact, in some implementations, such dot product circuits may already exist in the device for other purposes, or can be easily instantiated by combining a group of components already provided for other purposes.

[0018] In one exemplary implementation, the device further comprises an input manipulation circuit associated with each data block in a given two-dimensional array of data blocks, which, in response to a complex-valued cross product instruction, performs an input manipulation operation to adjust how the real and imaginary parts of at least one source data element are supplied to the dot product circuit associated with the given data block, so as to ensure that the execution of a dot product operation produces the required portion of at least one resulting data element used to update the value of the given data block. In particular, for the dot product circuit to produce the required output, it may be necessary to invert one of the at least one input parts of the source data element, for example, the real or imaginary part, and / or rearrange the real and imaginary parts of at least one source data element, and such functions can be easily performed by the input manipulation circuit. Furthermore, by providing such input manipulation circuits, additional flexibility can be offered, for example, by adjusting how different parts of the source data elements are manipulated before being fed into the dot product circuit, depending on a particular variant of the complex-valued cross product instruction, thereby allowing the same dot product circuit to be used when implementing various different variants of the complex-valued cross product instruction.

[0019] In some implementations, the input manipulation circuit may be configured to perform operations on data elements of either the first or second source operand. However, in one particular implementation, the input manipulation circuit is configured in relation to only one of the two source operands, manipulating the data elements of that source operand as needed, thereby eliminating the need to manipulate the data elements of the other source operand. Such an approach can lead to particularly efficient and low-cost designs, for example, by reducing hardware complexity and power consumption.

[0020] The input operation circuit can take various forms, but in one exemplary implementation, it includes an inverter circuit for inverting the value of at least one part of at least one source data element, and / or a reordering circuit for swapping the order of the real and imaginary parts of at least one source data element.

[0021] In one exemplary implementation, multiple variants of the complex-valued cross product instruction are supported by the device, and the input operation performed by the input operation circuit associated with a given data block depends on the variant of the complex-valued cross product instruction being executed, thereby ensuring that the dot product operation performed by the dot product circuit associated with a given data block produces the necessary portion of at least one result data element used to update the value of the given data block. Thus, with a proper design of the input operation circuit, it is possible to accommodate the use of multiple variants of the complex-valued cross product instruction while using the same underlying computing hardware.

[0022] The input manipulation circuit can be configured in various ways, but in one exemplary implementation, the input manipulation circuit associated with each given data block is configured to generate multiple candidate variants of the real and imaginary parts of at least one source data element, and further comprises a multiplexer circuit controlled to select which of the candidate variants to supply to the dot product circuit associated with the given data block, depending on the variant of the complex-valued cross product instruction being executed. This can provide a particularly efficient implementation.

[0023] In one exemplary implementation, several variants of the complex-valued cross product instruction include a non-conjugate variant in which complex numbers are used to form the source data elements of both the first and second source operands when performing the cross product operation, and at least one conjugate variant in which the conjugate of the complex numbers is used to form the source data elements of at least one of the first and second source operands when performing the cross product operation. As will be understood by those skilled in the art, when forming the conjugate of a complex number, the sign of the imaginary part of the complex number is reversed. The use of the conjugate version of the complex number can be useful in various applications, such as data processing in communication systems, and therefore it is useful to support such variants of the complex-valued cross product instruction. By appropriately configuring the input operation circuit, such conjugate variants of the complex-valued cross product instruction can be easily accommodated, and the same underlying computing hardware can be reused.

[0024] In one exemplary implementation, one such conjugate variant may use the conjugate of the complex numbers that form the source data elements of both source operands, whereas in another exemplary implementation, one such conjugate variant may use the conjugate of the complex numbers that form the source data elements of one source operand, while the complex numbers that form the source data elements of the other source operand may be used in their original forms.

[0025] As another example of different variants of the complex-valued cross product instruction that may be supported, such variants may include an accumulation variant in which each real and imaginary part of each generated result data element is added to the current value of the associated data block to form an updated value of the associated data block, and a subtraction variant in which each real and imaginary part of each generated result data element is subtracted from the current value of the associated data block to form an updated value of the associated data block. Again, it is possible to support both of these variants using the same underlying computing hardware by appropriately configuring the input operation circuit.

[0026] As described above, in one exemplary implementation, the input operation circuit associated with a given data block may be configured to perform operations on at least one source data element of only one of the first and second source operands used by the dot product circuit associated with the given data block. This allows for support of several different variants of the complex-valued cross product instruction, while providing a particularly efficient and low-cost solution.

[0027] In one exemplary implementation, the techniques described herein may also be used to support the execution of cross product operations on complex numbers (where the number of bits forming each source data element is less than the number of bits forming each result data element). In particular, a complex-valued cross product instruction (or at least one variant thereof) may take the form of a complex-valued cross product instruction. When such an instruction is executed, the real parts of multiple result data elements have the same associated data blocks in a two-dimensional array of data blocks, and the processing circuit is configured to combine their real parts to update the values ​​of the same associated data blocks. Similarly, the imaginary parts of multiple result data elements have further identical associated data blocks in a two-dimensional array of data blocks, and the processing circuit is configured to combine their imaginary parts to update the values ​​of the further identical associated data blocks.

[0028] In some exemplary implementations, the hardware already provided for handling cross product operations on real vectors can be reused to support cross product operations on complex vectors. For example, the processing circuit may be configured to provide multiple multiplier-based circuits used to perform a real cross product operation using the real numbers of the first and second vectors in response to a real cross product instruction specifying a first real vector and a second real vector, so that each multiplier-based circuit generates one real result data element in a matrix of real result data elements produced when performing a real cross product operation. The aforementioned dot product circuits, i.e., the dot product circuits used when performing a complex cross product instruction, associated with each data block in a given two-dimensional array of data blocks, may be configured to reuse multiple multiplier-based circuits, along with a combinational circuit for combining the outputs from those multiple multiplier-based circuits, to generate the required portion of at least one result data element used to update the value of that data block. In a particular exemplary implementation, such a circuit may be reconfigured on the fly to handle either real or complex cross product operations as needed. Therefore, using the same underlying hardware, cross product operations can be performed on both real and complex numbers, with the results stored in a two-dimensional array of data blocks in each case, resulting in a particularly efficient and flexible implementation.

[0029] The form of multiplier-based circuits reused to perform the functions required when executing a complex-valued cross product instruction can take various forms. For example, a multiplier-based circuit may take the form of a multiplier-adder circuit used when performing a real-valued cross product operation, and pairs of these multiplier-adder circuits can be used in combination to form a dot product circuit used when performing a complex-valued cross product operation. Similarly, a dot product-accumulator circuit may be used when performing a real-valued cross product-sum operation, and pairs of these dot product-accumulator circuits can be used in combination to form the dot product circuit required when performing a complex-valued cross product-sum operation.

[0030] If necessary, a predicate can be used with respect to one or more source operands according to one exemplary embodiment. In particular, a complex-valued cross product instruction may include at least one predicate operand to enable one or more source data elements to be identified as being excluded from the cross product operation. In some implementations, it may be possible to provide a predicate operand to only one of the source operands, whereas in one exemplary implementation, a separate predicate operand is provided for each source operand, thereby enabling the exclusion of one or more source data elements in either or both source operands from the cross product operation.

[0031] Each predicate operand can take various forms, and in one exemplary implementation, it may contain multiple bits, each bit associated with one of the source data elements in the corresponding source operand, used to identify whether that data element is subject to the cross product operation. There are various ways in which any data element to be excluded can be handled. For example, the operation containing that data element can be prohibited, or the operation can be performed, but the result generated based on that data element cannot be used to update the corresponding data block in the two-dimensional array.

[0032] Next, we will refer to the diagram to describe a specific example implementation.

[0033] Figure 1 schematically shows a data processing system 10 comprising a processor 20 coupled to a memory 30 that stores data values ​​32 and program instructions 34. The processor 20 includes an instruction fetch unit 40 for fetching program instructions 34 from the memory 30 and supplying the fetched program instructions to an instruction decoder circuit 50. The decoder circuit 50 decodes the fetched program instructions and generates control signals to control a processing circuit 60 to perform processing operations on data values ​​held in the storage elements of register storage 65 as specified by the decoded vector instructions. As shown in Figure 1, the register storage 65 may be formed from a plurality of different blocks. For example, a scalar register file 70 containing a plurality of scalar registers that can be specified by instructions may be provided, and similarly, a vector register file 80 containing a plurality of vector registers that can be specified by instructions may be provided.

[0034] Furthermore, as shown in Figure 1, the processor 20 can access the array storage 90. In the embodiment shown in Figure 1, the array storage 90 is provided as part of the processor 20, but this is not a requirement. In various embodiments, the array storage may be implemented as one or more of the following: architecturally addressable registers, architecturally unaddressable registers, scratchpad memory, and cache.

[0035] In one exemplary implementation, the processing circuit 60 may include both a vector processing circuit and a scalar processing circuit. The general distinction between scalar and vector processing is as follows: Vector processing may involve applying a single vector processing instruction to data elements of a data vector, each having multiple data elements at different positions within the data vector. The processing circuit may also perform vector processing to perform operations on multiple vectors in a two-dimensional array (sometimes called a subarray) of data elements stored in the array storage 90. Scalar processing effectively performs operations on a single data element rather than a data vector. Vector processing may be useful when processing operations are performed on many different instances of the data being processed. In a vector processing arrangement, a single instruction can be applied simultaneously to multiple data elements (of the data vector). This can improve the efficiency and throughput of data processing compared to scalar processing.

[0036] The processor 20 may be configured to process a two-dimensional array of data elements stored in the array storage 90. In at least some embodiments, the two-dimensional array may be accessed as a one-dimensional vector of data elements in multiple directions. In one exemplary implementation, the array storage 90 may be configured to store one or more two-dimensional arrays of data elements, where each two-dimensional array of data elements may form a square array portion of a larger or even higher-dimensional array of data elements in memory.

[0037] The register storage 65 also includes a predicate register file 75, which stores predicate information (e.g., masks) for use in data processing operations (e.g., masking out specific data elements of a vector so that they are excluded from certain processing operations).

[0038] Figure 2 shows one embodiment of the architecture registers 65 of a processor 20 that may be provided in an exemplary implementation. The architecture registers (as defined in the Instruction Set Architecture (ISA)) may include a set of scalar registers 95 (labeled X0 to X30 in this embodiment) that act as general-purpose registers for processing operations performed by scalar processing circuits within the processing circuit 60. There is also a set of predicate registers 100 for storing predicate information, for example, 16 registers P0 to P15 in this example.

[0039] Furthermore, the architecture registers available for selection by program instructions within the ISA supported by the decoder 50 may include a certain number of vector registers 105 (labeled Z0 to Z31 in this embodiment). Naturally, it is not mandatory to provide the number of scalar, predicate, and / or vector registers shown in Figure 2, and other embodiments may provide a different number of registers that can be specified by program instructions. Each vector register may store a vector operand containing a variable number of data elements, each of which may represent an independent data value. In response to a vector processing (SIMD) instruction, the processing circuit may perform vector processing on the vector operands stored in the registers to produce a result. For example, the vector processing may include lane-by-lane operations, where a corresponding operation is performed on each lane of elements in one or more operand vectors to produce the corresponding results of elements in the result vector. When performing vector or SIMD processing, each vector register may have a vector length VL, where the vector length refers to the number of bits in a given vector register. The vector length VL used in vector processing modes may be fixed or variable for a given hardware implementation. The ISA supported by processor 20 may support variable vector lengths so that different processor implementations may choose to implement vector registers of different sizes, but the ISA may not depend on vector length so that instructions are designed so that the code can function correctly regardless of the specific vector length implemented on a given CPU on which the program is executed.

[0040] Vector registers Z0 to Z31 can also function as operand registers for storing vector operands that provide input to processing and cumulative operations performed by the processing circuit 60 on a two-dimensional array of data elements stored in the array storage 90.

[0041] As shown in Figure 2, the architecture registers also include array registers 110, ZA0 to ZA(NA-1), of a specific number NA, which form the aforementioned array storage 90. Each array register can be considered a set of register storage for storing a single 2D array of data elements, e.g., the results of processing and accumulating operations. However, processing and accumulating operations may not be the only operations for which array registers can be used. Array registers can also be used to store square arrays when performing row / column transposition of array structures in memory. When a program instruction refers to one of the array registers 110, it is referred to as a single entity using the array identifier ZAi, although some types of instructions (e.g., data transfer instructions) can also select a sub-part of the array by defining an index value that selects a part of the array (e.g., a horizontal / vertical group of one element).

[0042] In practice, the physical implementation of the register storage corresponding to the array register may include a specific number of array vector registers ZAR0 to ZAR(NR-1), as shown in Figure 2. The array vector registers ZAR forming the array register storage 110 may be a separate set of registers from the vector registers Z0 to Z31 used for vector input to SIMD processing and array processing. Each of the array vector registers ZAR may have a vector length VL, and therefore each array vector register ZAR may store a 1D vector of length VL that can be logically divided into a variable number of data elements. For example, if VL is 512 bits, this could be, for example, a set of 64 8-bit elements, 32 16-bit elements, 16 32-bit elements, 8 64-bit elements, or 4 128-bit elements. It will be understood that not all of these options need to be supported in a given implementation. By supporting variable element sizes, this provides flexibility to computational processing with data structures of different precisions. To represent a 2D array of data, the group of array vector registers ZAR0~ZAR(NR-1) can be logically considered as a single entity assigned one of the array register identifiers ZA0~ZA(NA-1), and thus the 2D array is formed by elements unfolding in a single vector register corresponding to one dimension of the array, and elements of the other dimensions of the array striped across multiple vector registers.

[0043] As described above, the processing circuit 60 is configured to access the scalar register 70, the vector register 80, and / or the array storage 90 under the control of the instructions decoded by the decoder circuit 50. Further details of this latter arrangement will be described here with reference to Figure 3A, which simply provides one exemplary embodiment of how the array storage may be accessed, taking into account access to the square 2D array within the array storage in particular.

[0044] In the illustrated embodiment, the square 2D array within the array storage 90 is configured as an array 205 with n × n storage elements / location 200, where n is an integer greater than 1. In this embodiment, n is 16, which means that the granularity of access to the storage location 200 is 1 / 16 of the total storage of the 2D array, either in the horizontal array direction or the vertical array direction.

[0045] From the perspective of the processing circuit, the n×n array is accessible as n linear (one-dimensional) vectors in a first direction (e.g., the horizontal direction as depicted) and n linear vectors in a second array direction (e.g., the vertical direction as depicted). Therefore, the n×n storage locations are accessible from the perspective of the processing circuit 60 as 2n linear vectors for each of the n data elements.

[0046] The array of storage locations 200 is accessible by access circuits 210, 220, column selection circuit 230, and row selection circuit 240, under the control of a control circuit 250 that communicates with at least the processing circuit 60 and optionally with the decoder circuit 50.

[0047] Referring to Figure 3B, the n linear vectors in the first direction (horizontal or "H" direction as depicted) are, in the case of an exemplary square 2D array designated "ZA1" (note that there may be two or more such 2D arrays provided within the array storage 90, e.g., ZA0, ZA1, ZA2, etc., as will be considered below), each of the 16 data elements 0 to F (in hexadecimal), which in this embodiment may be referred to as ZA1H0 to ZA1H15. The same underlying data stored in the 256 entries (16 × 16 entries) of the array storage 90ZA1 in Figure 3B may instead be referred to as ZA1V0 to ZA1V15 in the second direction (vertical or "V" direction as depicted). For example, note that data element 260 is item F in ZA1H0 but is referred to as item 0 in ZA1V15. It should be noted that the use of "H" and "V" does not imply any spatial or physical layout requirements for the storage of data elements constituting the array storage 90, and is irrelevant in any exemplary application whether the 2D array in the array storage stores row data or column data.

[0048] Figure 4A illustrates the cross product operation. The cross product operation can take two vectors, A and B, as input, which can be stored in a vector register file as described above. The result of the cross product operation is a matrix (e.g., a 2D array).

[0049]

number

[0050] Figure 4B illustrates a matrix multiplication operation. Specifically, Figure 4B shows an operation involving the multiplication of two matrices C and D (which can be stored, for example, in vector registers (e.g., one row or one column is held in each register) or array storage circuits) to generate matrix CD. As can be seen from the figure, the result of multiplying two n×n matrices together is an n×n matrix (more generally, an n×k matrix multiplied by a k×m matrix yields an n×m matrix).

[0051] There are several ways to compute the elements of the output matrix CD, but a technique typically used by processors is to perform a multiplicative cross product operation and accumulate (add) the results together. For example, to perform the matrix multiplication shown in Figure 4B, the processing circuit may first compute the cross product of the leftmost column i of matrix A and the topmost row w of matrix B in order to generate 16 cross product results and store the cross product results in a 4x4 array in array storage. Then, the processing circuit may compute the cross product of the next column j of matrix A and the next row x of matrix D in order to generate another 16 cross product results that will be added to the cross product results already stored in the array. This process then generates the last two pairs of vectors in order to produce the final result CD.

[0052]

number

[0053] Therefore, matrix multiplication can be performed by executing a multiplicative cross product operation and accumulating the results; for example, this can be done by executing one or more multiplicative cross product instructions. Note that the order in which pairs of vectors are multiplied together is not limited to the order described above, and the cross product can be calculated in any order. In addition, it is not necessary to perform the cross product operation sequentially.

[0054] Apparatus and method are provided that can perform cross product operations on vectors of complex numbers according to the techniques described herein. As mentioned above, there are many computational tasks that require complex number arithmetic, such as in digital signal processing (DSP) algorithms, 5G communication infrastructure applications, and high-performance computing (HPC) applications. In many cases, complex number multiplication is required, and considering the computational resource requirements that are typically needed to perform such complex number multiplication operations, it is desirable to provide techniques to accelerate such multiplication operations and thereby improve performance / throughput. By supporting the execution of cross product operations using complex numbers, performance can be significantly improved, for example, in situations where a large number of complex number multiplication operations are required.

[0055] In accordance with the techniques described herein, one or more variants of a complex-valued cross product instruction are provided for execution by a data processing device. Such a complex-valued cross product instruction specifies first and second source vector operands, each containing a plurality of source data elements, where each source data element is a complex number formed from a real part and an imaginary part. Furthermore, the complex-valued cross product instruction specifies a two-dimensional array of data blocks in the array storage 90 as the destination operand. In response to such a complex-valued cross product instruction, the processing circuit 60 performs a cross product operation using the source data elements of both source operands to generate a plurality of result data elements. Each result data element is a complex number formed from a real part and an imaginary part, where each real part and each imaginary part of each result data element is associated with one of the data blocks in the specified two-dimensional array of data blocks and used to update the value of that associated data block. For example, you can specify a cumulative or subtractive variant, in which case each real and imaginary part of each resulting data element is added to or subtracted from the value currently held in the associated data block.

[0056] In the first variant of the complex-valued cross product instruction, a standard cross product operation is specified, which may result in a one-to-one correspondence between each part of each resulting data element and the associated data block in the two-dimensional array. On the other hand, according to alternative or additional variants of the complex-valued cross product instruction, a cross product sum operation may be specified by the instruction, in which case the real and imaginary parts of multiple resulting data elements may be associated with the same data block in the two-dimensional array and used to update the values ​​in that data block.

[0057] Significant performance improvements can be achieved by specifying a single instruction to instruct the processing circuit to perform an cross product operation on a vector of complex numbers. Firstly, prior to this technique, it was usually necessary to execute multiple vector instructions to perform a multiplication operation on a vector of complex numbers. Given the limitations on the instruction coding space, it is important to use the instruction coding space wisely. The format of the instruction coding and the function represented by each instruction can be defined according to the instruction set architecture (ISA). The ISA represents an agreed-upon framework between a hardware manufacturer that produces processing hardware for a given processor implementation and a software developer that writes code to run on that hardware, so that code written according to the ISA functions correctly on hardware that supports the ISA.

[0058] When designing an ISA, significant design challenges may arise in determining the set of processing operations that should be supported in the ISA and the instruction encoding to represent those operations. In principle, there may be a wide variety of different types of processing operations that could be useful to support several program applications, but it may not be possible to represent all possible data processing operations that could be useful to a particular programmer within the available encoding space. Increasing the instruction bit width will result in additional circuit area and power consumption each time an instruction is stored somewhere in the processor or transferred via a wired processing path between logic elements, so there may be a limit to the number of bits available to encode each instruction. To limit hardware and power costs, the instruction bit width may be chosen so as to leave insufficient opcode space to represent all possible data processing operations when considering the need to encode operand values ​​through register specifiers and / or immediate values. Therefore, design decisions must be made regarding which subset of operations is most important to support, and any operations that cannot be supported by a single instruction must be performed using a set of multiple instructions that have equivalent functionality when executed together. Therefore, design decisions made by ISA designers when planning the instruction coding of an ISA can have a significant impact on the real-world performance achieved by the processing hardware when running a particular program, depending on whether the instructions are available to support the desired operations.

[0059] Therefore, any technique that can improve the efficiency of representing a given set of operations within the instruction set's encoding space can be extremely valuable in improving overall performance when that ISA is later implemented on a hardware device. Even if it only saves one bit of encoding space, and that bit can be reused for other purposes (e.g., providing an additional opcode bit, thereby doubling the number of different operations that can be represented), this is extremely valuable. This is because an increase in the types of operations supported allows programmers to leverage it to perform more operations in a single instruction, thereby improving processing performance. Thus, even if the gain in encoding efficiency seems small, resulting in only one bit of additional encoding space becoming available, it actually has a significant impact on the performance achieved by the processing device. Providing complex-valued cross product instructions within an ISA has proven to be very beneficial in terms of encoding efficiency. Furthermore, providing such complex-valued cross product instructions within an ISA can result in significant performance benefits because it reduces the number of instructions that need to be executed to perform the required functionality.

[0060] Secondly, in addition to the advantages arising from the use of a single instruction, the instructions defined herein also enable performing cross product operations on vectors of complex numbers and accumulating the results in a two-dimensional array. This allows for efficient use of processing resources and provides a highly flexible approach. For example, such an approach makes it easy to incorporate accumulation or subtraction operations when performing calculations. This can be very beneficial in many exemplary scenarios where a large number of multiplication operations performed on complex numbers are required. For example, by using the same destination operand (i.e., the same two-dimensional array of data blocks) for multiple instances of the complex-valued cross product instruction, a particularly efficient mechanism can be provided for performing matrix multiplication operations using vectors of complex numbers.

[0061] In accordance with the techniques described herein, within each source vector operand, the real and imaginary parts of various source data elements are interleaved with respect to one another, thereby enabling the logical grouping of source data elements required for various computational blocks in the processing circuit and supplying them to those computational blocks, thereby resulting in a particularly efficient implementation. Furthermore, within at least one dimension of the two-dimensional array forming the destination operand, the real and imaginary parts of multiple result data elements are associated with data blocks such that the real parts of those result data elements are interleaved with the imaginary parts of those result data elements, thereby further improving implementation efficiency by reducing the complexity of routing between computational blocks and associated data blocks in the two-dimensional array.

[0062] The block diagram in Figure 5 and the flowchart in Figure 6 are used to illustrate the operations performed by the processing circuit when executing a complex-valued cross product instruction according to a particular exemplary embodiment. As shown in Figure 5, the vector register file 80 provides a plurality of vector registers that can be used to store vectors of data elements. The complex-valued cross product instruction is configured to identify a first source vector operand 300 and a second source vector operand 320, each source vector operand containing a plurality of source data elements, each source data element being a complex number formed from a real part and an imaginary part. As previously stated, in some implementations, the complex-valued cross product instruction may also specify one or more predicate registers 325 in the predicate register file 75, each specified predicate register associated with one of the source vector operands and used to identify whether any of the data elements in that source vector operand should be excluded from the data processing operation to be performed.

[0063] As shown in Figure 6, when a complex-valued cross product instruction or a complex-valued cross product sum instruction is detected, it is decoded by the decoder circuit 50 in step 400 to generate a control signal to be issued to the processing circuit 60. These control signals identify the type of cross product operation to be performed and also identify the vector registers 300, 320 that provide the source data elements of the first and second source operands, and an optional predicate register 325 that provides predicate information. In step 405, the predicate information is evaluated to determine whether any of the source data elements should be excluded from the cross product (or cross product sum) operation.

[0064] In step 410, an input manipulation circuit 340 provided in conjunction with the processing circuit 60 is used to select an appropriate input for each of the dot product circuits 350 provided by the processing circuit 60. This selection is made considering the variant of the cross product instruction to be performed. An input manipulation circuit used in an exemplary implementation will be described later with reference to Figure 11, but in an exemplary implementation, the real and / or imaginary parts of one or more source data elements may be inverted as needed, and the order of the real and imaginary parts of one or more source data elements may also be reversed, in order to ensure that the dot product circuit 350 produces appropriate result data elements considering the type of cross product operation to be performed.

[0065] In step 415, a dot product circuit 350 is used to perform a dot product operation to generate multiple result data elements, each result data element consisting of a real part and an imaginary part. If the predicate information indicates that one or more source data elements are not subject to the operation, the dot product circuit using those excluded source data elements may be configured not to perform a dot product operation using those excluded source data elements, or it may be configured to perform the operation as usual, but the result data elements based on those excluded source data elements will be prevented from updating the contents of the two-dimensional array 380 in the array storage 90.

[0066] Subsequently, in step 420, each real and imaginary part (except those excluded by predicate information) of each result data element is used to update the values ​​in each associated data block of the two-dimensional array 380. In one exemplary implementation, this is achieved by using an accumulator circuit 360, which accumulates the result data element with the existing value in the two-dimensional array and generates an updated value for storage in the two-dimensional array 380 using an array update circuit 370. If a variant of a complex-valued cross product instruction is used that requires subtracting a result from the existing contents of the two-dimensional array, in one exemplary implementation, this is achieved by appropriate manipulation of the inputs by an input manipulation circuit 340 before those inputs are supplied to the dot product circuit 350. Thus, the result data element generated by the dot product circuit 350 can be added by the accumulator circuit 360 to the existing value in the two-dimensional array, generating an updated value corresponding to the value produced by the specified subtraction operation.

[0067] In one exemplary implementation, multiple instances of a dot product circuit are used by the processing circuit to perform a complex-valued cross product operation. A two-input dot product circuit 450 is schematically shown in Figure 7 and performs the calculation shown in Figure 7. As can be seen from the figure, the value of the destination data block Z is multiplied by x1. * y1 and x2 * It is updated by adding y2 (note that an accumulation circuit (not explicitly shown in Figure 7) is used to accumulate the output of the two-input dot product with the existing data value of data block Z). To reduce the complexity of the following figures, such accumulation circuits are also omitted from them, but it is understood that they are provided in conjunction with various dot product circuits to perform the necessary accumulation of the dot product output with the corresponding existing data value.

[0068] As shown in Figure 8, a pair of such two-input dot product circuits 455, 460 can be used to generate the real and imaginary parts, respectively, of the resulting data element "c" produced by multiplying a first complex number "a" by a second complex number "b". As can be seen, each dot product circuit 455, 460 receives both the real and imaginary parts of the complex numbers "a" and "b". The first dot product circuit 455 generates the updated real part (c_re) of the resulting data element "c" by performing the calculation shown below element 455 in Figure 8, where the imaginary part of the complex number "b" is inverted. Similarly, the dot product circuit 460 receives the real and imaginary parts of the complex number "b" in reverse order, so its dot product circuit generates the updated imaginary part (c_im) of the resulting data element "c" by performing the calculation shown below element 460 in Figure 8 (as mentioned earlier, the necessary accumulating circuits are not explicitly shown in the figure). Therefore, the real and imaginary parts of the calculated result are accumulated in each data block of the two-dimensional array, and any existing real and imaginary values ​​stored in those data blocks can be updated.

[0069] As schematically shown in Figure 9, the dot product circuits of Figure 8 can be duplicated as needed to provide a calculation block associated with each data block in the two-dimensional array 490, each dot product circuit receiving the real and imaginary parts of one source data element from the first source vector register 470 and the real and imaginary parts of one source data element from the second source vector register 480. As shown in Figure 9, predicate registers 475, 485 can be provided as needed in association with each source vector register to specify predicate information for each data element. In the example shown in Figure 9, it can be seen that each source vector contains two data elements, and therefore two items of predicate information can be provided to each source vector. Furthermore, each source data element contains a real part and an imaginary part. As can be seen from Figure 9, each of the eight dot product circuits performs a dot product operation, resulting in four updated result data elements, each containing a real part and an imaginary part.

[0070] Figure 10 schematically shows an input manipulation circuit 510 that may be provided in relation to each pair of dot product circuits 500 and 505 used to generate the real and imaginary parts of the resulting data elements for updating the values ​​in the corresponding data blocks of the two-dimensional array. In this example, the input manipulation circuit 510 is used to perform the necessary operations for performing the calculation described above with reference to Figure 8, so that the imaginary part of the second data element b1 is inverted before being fed into the dot product circuit 500, and the real and imaginary parts of the second data element b1 are swapped before being fed into the dot product circuit 505.

[0071] In a more common implementation, the input manipulation circuit can be configured to support the execution of several different variants of a complex-valued cross product instruction using the same underlying dot product circuit. One such implementation is shown as an example in Figure 11. As can be seen, an input manipulation circuit 520, which may be provided in relation to a first dot product circuit used to compute the real part of the resulting data element, generates both the original and inverted versions of the real and imaginary parts of the input data element (the inverted version is generated using inverters 535, 545), and then the multiplexing circuits 540, 550 select the appropriate real and imaginary values ​​to pass to the associated dot product circuit, depending on the variant of the instruction being executed. An input manipulation circuit 530, provided in relation to a second dot product circuit in the pair of dot product circuits (this second dot product circuit is used to generate the imaginary part of the resulting data element), operates in a similar manner and again generates both the original and inverted versions of the real and imaginary parts of the input data element (the inverted version is generated using inverters 555, 565). However, the order of the real and imaginary parts of the input data elements is further reversed by the input manipulation circuit 530. Similar to the input manipulation circuit 520, the input manipulation circuit 530 uses multiplexing circuits 560, 570 to select the appropriate real and imaginary values ​​to pass to the associated dot product circuit, depending on the variant of the instruction being executed.

[0072] Using the input operation circuit of Figure 11, it is possible to implement any of the instruction variants schematically shown with reference to Figures 12A to 12C, in addition to the variants described above with reference to Figure 8. The configuration shown in Figure 8 allows for the execution of a complex-valued cross product with an accumulation operation (for example, when the pair of dot product circuits in Figure 8 is duplicated as shown in Figure 9), while the same pair of dot product circuits can be used to allow for the execution of a complex-valued cross product with a subtraction operation, as shown in Figure 12A. In particular, the dot product circuits 455, 460 perform the calculation shown below their blocks in Figure 12A by inversion performed by inverters 600, 605, 610, and swapping the real and imaginary parts of the data element "b" before it is supplied to the second dot product circuit 460.

[0073] Similarly, as shown in Figure 12B, it is also possible to perform a complex-valued cross product with cumulative operations when operand "a" is conjugate by using the input operation circuit of Figure 11. As previously mentioned, the conjugate of a complex number is formed by inverting the sign of the imaginary part. The substantial conjugation of operand "a" is actually achieved in the example of Figure 12B through appropriate manipulation of operand "b". In particular, as shown, the imaginary part of operand "b" is not inverted before being fed into the dot product circuit 455 (in contrast to the approach adopted in Figure 8), and the real part of operand "b" is inverted by inverter 610 before being fed into the dot product circuit 460 (again, in contrast to the approach adopted in Figure 8). As a result, the two dot product circuits 455 and 460 perform the calculation shown below their elements in Figure 12B.

[0074] Furthermore, as shown in Figure 12C, it is also possible to perform a complex-valued cross product with subtraction when operand "a" is conjugate by using the input operation circuit of Figure 11. Here again, the substantial conjugation of operand "a" is actually achieved in the example of Figure 12C through appropriate manipulation of operand "b". In particular, as shown, the real and imaginary parts of operand "b" are inverted by inverters 600 and 615 before being fed into the dot product circuit 455, and the imaginary part of operand "b" is inverted by inverter 605 before being fed into the dot product circuit 460. As a result, the two dot product circuits 455 and 460 perform the calculation shown below their elements in Figure 12C.

[0075] In one exemplary implementation, each of the dot product circuits required to perform the above operations can be implemented by reusing existing multiplier-based circuits already provided by the device to support the execution of cross product operations on real vectors. As an exemplary embodiment, Figure 13 shows a 4x4 two-dimensional array 670 of data blocks, with a multiplier / adder circuit ("P") associated with each data block. Then, two source vector operands 650, 660, each containing four real-valued data elements, can be subjected to a cross product operation to generate updated values ​​for the 4x4 two-dimensional array 670 of data blocks. If necessary, predicate registers 655, 665 can be provided associated with each source vector operand, and since each vector contains four data elements, four items of predicate information can be provided in each predicate register.

[0076] As schematically shown in Figure 13, the 675 multiplier and adder circuits, used in combination with an adder circuit to combine their outputs, can implement each of the two-input dot product circuits schematically shown in Figure 9. By comparing Figure 13 with Figure 9, it can be seen that when implementing a complex-valued cross product using the same circuit, two vectors of two complex-valued data elements can be supplied as inputs instead of two vectors of four real-valued data elements. This provides a particularly efficient implementation because the same underlying circuit can be used to perform cross product operations on both real and complex vectors, simply by appropriately reconfiguring the basic circuit blocks as needed.

[0077] In one exemplary implementation, the apparatus described herein may also perform an exterior sum operation on a vector of complex numbers, and in particular, the apparatus may be configured to perform a complex-valued exterior sum instruction. Here again, a dot product circuit can be used for this purpose. Figure 14 shows an 8-input dot product circuit that may be provided for performing a dot product operation on a vector of two real data elements, each vector containing eight real data elements. As shown in Figure 15, a pair of such circuits can also be used to generate the real and imaginary parts of a resulting data element based on four data elements of a first vector operand and four data elements of a second vector operand, each of which is a complex number and therefore has a real and an imaginary part. Thus, a pair of 8-input dot product circuits is used to calculate the 4-input dot product of complex values. Thus, each of the dot product circuits 705, 710 performs the calculation shown below these elements in Figure 15 (in combination with an accumulation circuit, which is not explicitly shown in the figure, as previously mentioned).

[0078] Therefore, when such an array of dot product circuits is used in relation to a two-dimensional array 740 as shown in Figure 16, the cross product operation can be performed with respect to two source vector operands 720, 730 of complex-valued data elements, where again, predicate registers 725, 735 can be specified in relation to each source vector operand, if desired. In this particular example shown in Figure 16, each source vector operand contains eight data elements, and therefore, eight items of predicate information can be provided by each predicate register 725, 735. The resulting data elements can then be accumulated within the illustrated two-dimensional array 740.

[0079] Figure 17 schematically shows a block of circuit 750, along with two instances 705' and 710' of the 8-input dot product circuit, and associated input operation circuits for rearranging and inverting the relevant portion of one of the source data elements of the source vector operands input to those dot product circuits. It will be understood that this circuit may be duplicated four times to implement the functionality shown in Figure 16.

[0080] In the examples in Figures 15-17, it is assumed that each dot product circuit uses four data elements from each source operand, but this is not a requirement, and it will be understood that in other examples, a different number of source data elements may be consumed by each dot product circuit. Generally, when performing an outer sum product operation, the size of the source data elements is smaller than the size of the result data elements, and the number of complex-valued products produced is given by the ratio of the element size width of the result data elements to that of the input data elements. In the examples in Figures 15-17, the result data elements have four times the width of the input data elements, and therefore four complex-valued results are produced.

[0081] Figure 18 shows possible implementations of simulators. While the aforementioned examples implement the invention in terms of apparatus and methods for operating specific processing hardware that supports the technique, it is also possible to provide an instruction execution environment according to the examples described herein, which is implemented using a computer program. Such a computer program is often referred to as a simulator, insofar as it provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 815, optionally running a host operating system 810 and supporting a simulator program 805. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments may be provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such techniques may be justified in certain circumstances, such as when it is desirable to run native code on a different processor for reasons of compatibility or reuse. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or it may provide an instruction execution environment typically associated with a different hardware architecture. An overview of the simulation is provided in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990, USENIX Conference, pp. 53-63.

[0082] To the extent that the examples are described above with reference to specific hardware configurations or features, in simulated implementations, equivalent functionality may be provided by preferred software configurations or features. For example, a particular circuit may be provided as computer program logic in a simulated implementation. Similarly, memory hardware such as registers or caches may be provided as software data structures in a simulated implementation. Furthermore, the physical address space used to access memory 30 within the hardware device 10 may be emulated as a simulated address space, which is mapped by the simulator 805 to a virtual address space used by the host operating system 810. In configurations where one or more of the hardware elements mentioned in the above examples reside in host hardware (e.g., host processor 815), some simulated implementations may use the host hardware if preferred.

[0083] The simulator program 805 may be stored in a computer-readable storage medium (which may be a non-temporary medium) and provides a virtual hardware interface (instruction execution environment) to the target code 800 (which may include an application, operating system, and hypervisor), the virtual hardware interface being the same as the hardware interface of the hardware architecture modeled by the simulator program 805. Thus, program instructions of the target code 800 can be executed from within the instruction execution environment using the simulator program 805, so that a host computer 815 that does not actually possess the hardware features of the device 10 considered above can emulate these features. The simulator program may also include a processing program logic 820 that emulates the behavior of the processing circuit 60, an instruction decoding program logic 825 that emulates the behavior of the instruction decoder circuit 50, and an array storage emulation program logic 822 that maintains data structures to emulate the array storage 90. Thus, the techniques described herein can be executed in software by the simulator program 805 in the example of Figure 18.

[0084] In this application, the phrase "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that an element of the device must be modified in any way to provide the defined operation.

[0085] While exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to those exact embodiments, and that various changes, additions, and modifications can be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, various combinations of the features of the dependent claims can be made together with the features of the independent claims without departing from the scope of the present invention.

Claims

1. It is a device, A processing circuit that performs vector operations, An instruction decoder circuit that decodes an instruction from a set of instructions in order to control the processing circuit for performing the vector operation specified by the instruction, An array storage comprising storage elements for storing data blocks, wherein the array storage is configured to store at least one two-dimensional array of data blocks accessible to the processing circuit when the vector operation is performed, The set of instructions includes a complex numerical cross product instruction specifying a first source operand, a second source operand, and a destination operand, each of which the first and second source operands is a vector operand containing a plurality of source data elements, each source data element being a complex number formed from a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks in the array storage. The processing circuit, in response to the complex-valued cross product instruction, performs a cross product operation using the source data element of the first source operand and the source data element of the second source operand to generate a plurality of result data elements, wherein each result data element is a complex number formed from a real part and an imaginary part, and each real part and each imaginary part of each result data element is associated with one of the data blocks in the given two-dimensional array of data blocks and used to update the value of the associated data block. Device.

2. The apparatus according to claim 1, wherein both the first source operand and the second source operand are configured to interleave the real part of the plurality of source data elements and the imaginary part of the plurality of source data elements.

3. The apparatus according to claim 1 or 2, wherein, within at least one dimension of the given two-dimensional array of the data block, the real and imaginary parts of a plurality of result data elements are associated with the data block such that the real parts of the plurality of result data elements are interleaved with the imaginary parts of the plurality of result data elements.

4. The processing circuit comprises a dot product circuit associated with each data block in the given two-dimensional array of data blocks, The dot product circuit associated with a given data block is configured to perform a dot product operation using the real and imaginary parts of at least one source data element of the first source operand and at least one source data element of the second source operand to generate the required portion of at least one resulting data element used to update the value of the given data block. The apparatus according to any one of claims 1 to 3.

5. The apparatus according to claim 4, further comprising an input operation circuit associated with each data block in the given two-dimensional array of data blocks, wherein the input operation circuit associated with the given data block is controlled in response to the complex-valued cross product instruction to perform an input operation operation to adjust how the real and imaginary parts of at least one source data element are supplied to the dot product circuit associated with the given data block, so as to ensure that the execution of the dot product operation produces the required portion of the at least one resulting data element used to update the value of the given data block.

6. The aforementioned input operation circuit is An inverter circuit for inverting the value of at least one portion of the at least one source data element, and A sorting circuit for swapping the order of the real and imaginary parts of at least one source data element, The apparatus according to claim 5, comprising at least one of the following.

7. The apparatus according to claim 5 or 6, wherein a plurality of variants of the complex-valued cross product instruction are supported by the apparatus, and the input operation performed by the input operation circuit associated with the given data block depends on the variant of the complex-valued cross product instruction being performed, thereby ensuring that the dot product operation performed by the dot product circuit associated with the given data block generates the required portion of the at least one resulting data element used to update the value of the given data block.

8. The apparatus according to claim 7, wherein the input operation circuit associated with the given data block is configured to generate a plurality of candidate variants of the real and imaginary parts of the at least one source data element, and the input operation circuit further comprises a multiplexer circuit controlled to select which of the candidate variants to supply to the dot product circuit associated with the given data block, depending on the variant of the complex value cross product instruction being executed.

9. The apparatus according to claim 7 or 8, wherein the plurality of variants of the complex-valued cross product instruction include a non-conjugate variant in which the complex number forming the source data elements of both the first source operand and the second source operand is used when performing the cross product operation, and at least one conjugate variant in which the conjugate of the complex number forming the source data elements of at least one of the first source operand and the second source operand is used when performing the cross product operation.

10. The apparatus according to any one of claims 7 to 9, wherein the plurality of variants of the complex-valued cross product instruction include an accumulation variant in which each real part and each imaginary part of each generated result data element is added to the current value of the associated data block in order to form an updated value of the associated data block, and a subtraction variant in which each real part and each imaginary part of each generated result data element is subtracted from the current value of the associated data block in order to form an updated value of the associated data block.

11. The apparatus according to any one of claims 5 to 10, wherein the input operation circuit associated with the given data block is configured to perform operations on at least one source data element of only one of the first source operand and the second source operand used by the dot product circuit associated with the given data block.

12. The aforementioned complex-valued cross product instruction includes a complex-valued cross product sum instruction, The real parts of multiple result data elements have the same associated data blocks within the two-dimensional array of data blocks, and the processing circuit is configured to combine the real parts of the multiple result data elements in order to update the values ​​of the same associated data blocks. The imaginary parts of multiple result data elements have further identical associated data blocks within the two-dimensional array of data blocks, and the processing circuit is configured to combine the imaginary parts of the multiple result data elements in order to update the values ​​of the further identical associated data blocks. The apparatus according to any one of claims 1 to 11.

13. The processing circuit is configured to provide a plurality of multiplier-based circuits configured to perform a real cross product operation using the real numbers of the first and second vectors in response to a real cross product instruction specifying a first real vector and a second real vector, wherein each multiplier-based circuit generates one real result data element in a matrix of real result data elements generated when performing the real cross product operation. The dot product circuit associated with each data block in the given two-dimensional array of data blocks is configured, in response to the complex-valued cross product instruction, to reuse some of the multiplier-based circuits among the multiple multiplier-based circuits, together with a combination circuit for combining the outputs from those multiple multiplier-based circuits, to generate the required portion of the at least one resulting data element used to update the value of that data block. The apparatus according to any one of claims 1 to 12, as dependent on claim 4.

14. The apparatus according to any one of claims 1 to 13, wherein the complex-valued cross product instruction includes at least one predicate operand for enabling one or more source data elements to be identified as being excluded from the cross product operation.

15. It is a method, Using a processing circuit to perform vector operations, Decoding an instruction from a set of instructions in order to control the processing circuit for executing the vector operation specified by the instruction, The array storage includes a storage element for storing data blocks, and is configured to store at least one two-dimensional array of data blocks accessible to the processing circuit when performing the vector operation, and includes using such array storage. The set of instructions includes a complex numerical cross product instruction specifying a first source operand, a second source operand, and a destination operand, each of which the first and second source operands is a vector operand containing a plurality of source data elements, each source data element being a complex number formed from a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks in the array storage. The method includes using the processing circuit to perform an cross product operation using the source data element of the first source operand and the source data element of the second source operand in response to the complex value cross product instruction to generate a plurality of result data elements, each result data element being a complex number formed from a real part and an imaginary part, each real part and each imaginary part of each result data element being associated with one of the data blocks in the given two-dimensional array of data blocks and used to update the value of the associated data block. method.

16. A computer program for controlling a host data processing device to provide an instruction execution environment, The processing program logic that executes vector operations, Instruction decoding program logic that decodes the instruction from a set of instructions in order to control the processing program logic for executing the vector operation specified by the instruction, Includes an array storage emulation program logic that emulates an array storage having storage elements for storing data blocks, and configured to store at least one two-dimensional array of data blocks accessible to the processing program logic when performing the vector operation, The set of instructions includes a complex numerical cross product instruction specifying a first source operand, a second source operand, and a destination operand, each of which the first and second source operands is a vector operand containing a plurality of source data elements, each source data element being a complex number formed from a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks in the array storage. The processing program logic, in response to the complex numerical cross product instruction, performs a cross product operation using the source data element of the first source operand and the source data element of the second source operand to generate a plurality of result data elements, wherein each result data element is a complex number formed from a real part and an imaginary part, and each real part and each imaginary part of each result data element is associated with one of the data blocks in the given two-dimensional array of data blocks and used to update the value of the associated data block. Computer program.

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