Reducing voltage droop by limiting the allocation of work blocks to the calculation circuit.

Abstract

Apparatus and method are provided for efficiently managing voltage droop between duplicate computing circuits of an integrated circuit. In various embodiments, the integrated circuit includes a plurality of duplicate computing circuits, each containing circuits for processing tasks grouped into work blocks. When a scheduling window begins, the scheduler determines a threshold number of idle computing circuits that can be activated simultaneously, based on one or more of the following: the number of active computing circuits, the operating clock frequency, the measured operating temperature, the number of pending work blocks, and the application identifier. If the scheduler determines that there is a count of idle computing circuits greater than or equal to the threshold number, the scheduler limits the number of idle computing circuits that can be activated at one time to the threshold number.

Description

[Background technology]

[0001] (Explanation of related technologies) Various computing devices utilize heterogeneous integration, which combines multiple types of integrated circuits (ICs) to provide system functionality. These multiple functions include audio / video (A / V) data processing, other advanced data-parallel applications for medical and business fields, instruction processing for general-purpose instruction set architectures (ISAs), digital, analog, mixed signal, and radio-frequency (RF) functions. Various system packaging options exist for integrating multiple types of ICs. Some computing devices use system-on-a-chip (SOCs), while others package smaller, higher-yield chips as larger chips within multi-chip modules (MCMs). Still others utilize die stacking technology and silicon interposers to create three-dimensional integrated circuits (3D ICs) that vertically stack two or more semiconductor dies within a system-in-package (SiP).

[0002] Regardless of the options for system packaging, the voltage droop of the latest ICs has become a design issue that increases with each generation of semiconductor chips. Voltage droop constraints are a problem not only for portable computers and mobile communication devices, but also for high-performance superscalar microprocessors that include multiple processor cores (cores) and multiple pipelines within the cores. The geometric dimensions of the devices and metal paths in each generation of cores are decreasing. The superscalar design increases the density of integrated circuits on the die with multiple pipelines, larger caches, and more complex logic. Therefore, the number of nodes and buses that switch every clock cycle increases significantly.

[0003] Parasitic inductance increases transmission line effects on the chip such as ringing and reduction of propagation delay. Also, simultaneous switching of wide buses causes significant voltage drops when the supply pins service all of the line buffers on the bus. This voltage droop ΔV is proportional to the equation L di / dt, where L is the parasitic inductance and di / dt is the time rate of change of current consumption. When a large number of nodes in addition to the bus are switched simultaneously, significant voltage drops occur. Currently, nodes that hold a logic high value experience a voltage droop that reduces their voltage value below the minimum threshold. In the case of memories and latches without a recovery circuit configuration, the stored value is lost.

[0004] One way to reduce voltage droop is to lower the operating clock frequency of the integrated circuit. However, this degrades performance. In addition, node capacitance switching is reduced by disabling the clock to certain blocks and / or circuits within the semiconductor chip using qualified enable signals during periods of non-use. However, during use of these circuits, simultaneous switching of numerous nodes and signal lines occurs again, and the voltage droop problem may still exist. Another way to reduce voltage droop is to place an external capacitor between the power supply leads. This external capacitance creates a passive bypass that reduces supply line oscillation caused by external inductance. However, it does not significantly reduce oscillation caused by internal inductance.

[0005] Another method to reduce inductance effects involves placing on-chip capacitors between internal power supply leads. The capacitors act as bypasses, similar to external capacitors. However, for this to be effective, internal capacitors are very large and require a significant portion of the chip area. This method is undesirable when minimizing die area is required.

[0006] In light of the above, methods and systems for efficiently managing the voltage droop of integrated circuits are desired. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic block diagram of a device that manages voltage droop between replication calculation circuits in an integrated circuit. [Figure 2] This is a schematic block diagram of a graph showing the voltage droop at the power reference level of an integrated circuit. [Figure 3] This is a schematic block diagram of a graph showing the number of active computing circuits as a function of time in an integrated circuit. [Figure 4] This is a schematic block diagram of a method for efficiently managing the voltage droop of multiple computing circuits in an integrated circuit. [Figure 5]This is a schematic block diagram of a computing system that efficiently manages the voltage droop of multiple computing circuits in an integrated circuit. [Figure 6] This is a schematic block diagram of an integrated circuit that efficiently manages the voltage droop of multiple computing circuits. [Figure 7] This is a schematic block diagram of a scheduler that manages voltage droop between the replication calculation circuits of an integrated circuit. [Figure 8] This is a schematic block diagram of a system-in-package (SiP) that manages the voltage droop of multiple computing circuits in an integrated circuit. [Modes for carrying out the invention]

[0008] While the present invention is open to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed, but rather, the invention encompasses all modifications, equivalents, and alternatives that fall within the scope of the invention as defined by the appended claims.

[0009] The following specification includes numerous specific details to provide a full understanding of the invention. However, those skilled in the art should recognize that the invention can be carried out without these specific details. In some examples, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the invention. Furthermore, for the sake of simplicity and clarity of explanation, please understand that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are exaggerated relative to others.

[0010] A device and method are intended for efficiently managing the voltage droop of multiple computing circuits in an integrated circuit. In various embodiments, the integrated circuit includes multiple duplicated computing circuits, each containing a circuit for processing work blocks. Tasks performed by the integrated circuit are grouped into work blocks, where a “work block” is a unit of work performed in an atomic manner. The granularity of a work block can include a single instruction of a computer program, multiple instructions, or a wavefront containing multiple work items executed simultaneously on multiple execution lanes of a computing circuit. A scheduler assigns work blocks to idle computing circuits, which are then activated and process the assigned work blocks.

[0011] When a scheduling window begins, the scheduler determines a value for a threshold number of idle compute circuits that can be allowed to be activated simultaneously. In some embodiments, the scheduler determines this threshold number based on one or more of the following: the number of active compute circuits, the total number of compute circuits, the number of stalled compute circuits, the number of compute circuits that have most recently completed executing a work block, the operating clock frequency, the measured operating temperature, the number of pending work blocks, any measured existing voltage droop, the queue usage value of the queue of compute circuits that stores assigned work blocks, and an application identifier that specifies the type of application (and therefore the type of work block) being processed by the corresponding compute circuit. If the scheduler determines that there is a count of idle compute circuits equal to or greater than the threshold number, the scheduler allocates a number of work blocks equal to the threshold number to the idle compute circuits. In other words, the scheduler limits the number of idle compute circuits that can be activated at one time to the threshold number.

[0012] In some embodiments, the scheduler modifies the scheduling rate. During a given time period, the scheduler limits the total number of idle computing circuits that can be allocated work blocks and activated to process the allocated work blocks. In one embodiment, the scheduler defines the time period as a specific number of clock cycles. At the end of the time period, such as the expiration of the period from the most recent scheduling window, the scheduler re-evaluates the scheduling based on the updated parameters. Further details of these techniques for reducing voltage droop in multiple computing circuits of an integrated circuit are provided in the following description of Figures 1 to 8.

[0013] Referring to Figure 1, a schematic block diagram of a device 100 for managing voltage droop between duplicate computing circuits of an integrated circuit is shown. In the illustrated embodiment, the device 100 includes a control block 140 and at least two modules, such as modules 110A to 110B, which include circuit configurations configured to perform (or “execute”) tasks (e.g., based on the execution of instructions, the detection of signals, the movement of data, the generation of signals and / or data, etc.). Tasks are grouped into work blocks. As used herein, a “work block” is a unit of work performed in an atomic manner. In some embodiments, the granularity of a work block includes a single instruction of a computer program. In other embodiments, the granularity of a work block includes multiple work items that are executed simultaneously on the hardware of multiple execution lanes of the computing circuit. In such embodiments, a work block may also be called a “wavefront,” which will be briefly described further. The control block 140 includes a scheduler 142 and a power manager 144. The control block 140 transmits operating parameters and assigned tasks 150 to module 110A. Furthermore, the control block 140 transmits the operating parameters and the assigned task 152 to module 110B. The control block 140 receives the performance metric 130 from module 110A and the performance metric 132 from module 110B.

[0014] Module 110A includes partition 120A containing semiconductor dies 122A-122B (or dies 122A-122B). Module 110B includes partition 120B containing dies 122C-122D. In some embodiments, each of dies 122A-122B and 122C-122D includes one or more computing circuits. For example, die 122A includes computing circuits 124A and 124B (or computing circuits 124A-124B), and die 122C includes computing circuits 124C and 124D (or computing circuits 124C-124D). Although not shown, dies 122B and 122D may also include one or more computing circuits. In various embodiments, the hardware, such as the circuit configuration of each of dies 122B and 122C-122D, is an instantiated copy of the circuit configuration of die 122A. Only two modules 110A-110B are shown, and only two dies are shown inside each of partitions 120A-120B, but other numbers of modules and computing circuits used by the device 100 are possible and intended, and these numbers are based on design requirements.

[0015] Each of modules 110A to 110B is assigned a power domain by the power manager 144. In some embodiments, each of modules 110A to 110B uses its own power domain. In such embodiments, the operating parameters in information 150 and 152 are distinct values. In other embodiments, modules 110A to 110B share the same power domain. In such embodiments, the operating parameters in information 150 and 152 are the same value. Depending on the embodiment, the power manager 144 selects the same or separate power management state for each of modules 110A to 110B. As used herein, “power management state” is any of a plurality of “P states” or any of a plurality of power performance states, including a set of operating parameters such as operating clock frequency and operating power supply voltage.

[0016] Each power domain includes at least P-state operating parameters such as operating power supply voltage and operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to the clock generation circuit configuration and power reference. These control signals are also included in information 150, 152. In one embodiment, the “active calculation circuits” of calculation circuits 124A-124B and 124C-124D use non-zero values ​​for the operating clock frequency and operating power supply voltage to execute their assigned work blocks. The “idle calculation circuits” of calculation circuits 124A-124B and 124C-124D have no assigned work blocks and are typically clock-gated; otherwise, the idle calculation circuits have their connections to the clock generation circuit configuration disabled. In some embodiments, the idle calculation circuits have their connections to the power reference level (or power rail) disabled. For example, a power switch is disabled, which disconnects the idle calculation circuit from the power rail. In other embodiments, the idle calculation circuits are clock-gated only, and the idle calculation circuits maintain their connections to the power reference level.

[0017] In some embodiments, the functionality of the device 100 is included as one die among several dies on a system-on-a-chip (SOC). In other embodiments, the functionality of the device 100 is implemented by several separate dies manufactured on separate silicon wafers and arranged in a system package known as a multi-chip module (MCM). Other components of the device 100 are not shown for the sake of clarity. For example, a memory controller, one or more input / output (I / O) interface circuits, an interrupt controller, one or more phase-locked loops (PLLs) or other clock generation circuit configurations, one or more levels of cache memory subsystems, and various other computing circuits may be used by the device 100 but are not shown. In various embodiments, the device 100 is used in desktops, portable computers, mobile devices, servers, peripheral devices, etc. The device 100 can communicate with an external general-purpose central processing unit (CPU) which includes a circuit configuration for executing instructions according to a predetermined general-purpose instruction set architecture (ISA). Furthermore, the device 100 can communicate with various other external circuit configurations, such as one or more of the following: a digital signal processor (DSP), a display controller, various application-specific integrated circuits (ASICs), a multimedia engine, etc.

[0018] As mentioned above, tasks performed by the device 100 can be grouped into work blocks, which are units of work performed atomically. The granularity of a work block can include a single instruction of a computer program, which can be divided by the device 100 into two or more microoperations (micro-ops). The granularity of a work block can also include one or more instructions of a subroutine. Furthermore, the granularity of a work block can include wavefronts assigned to the circuit configuration of multiple execution lanes of calculation circuits 124A-124B and 124C-124D when these calculation circuits are implemented as single-instruction multiple-data (SIMD) circuits. In such embodiments, a specific combination of the same instruction and a particular data item among multiple data items is called a "work item." A work item is also called a thread. In one embodiment, each of the calculation circuits 124A-124B and 124C-124D is a SIMD circuit containing 64 execution lanes. Therefore, each of the calculation circuits 124A-124B and 124C-124D (or SIMD circuits) can process 64 threads simultaneously. In other embodiments, the calculation circuits 124A-124B and 124C-124D include other types of circuit configurations that provide different functionality when executed on a different type of assigned work block.

[0019] In one embodiment, the scheduler 142 receives work blocks to be allocated to computing circuits 124A-124B and 124C-124D and allocates them based on load balancing. In one embodiment, the scheduler 142 is a command processor of a graphics processing unit (GPU), the work blocks are wavefronts, and the scheduler 142 retrieves wavefronts from a buffer such as system memory. Other circuit configurations, such as a general-purpose central processing unit (CPU), store wavefronts in a buffer and send an indicator to device 100 that pending wavefronts are stored in the buffer. In other embodiments, the scheduler 142 is part of a different type of circuit configuration other than a GPU, and the scheduler 142 receives work blocks from a different type of circuit configuration other than a CPU.

[0020] In some embodiments, scheduler 142 allocates work blocks to partitions 120A and 120B in a round-robin manner. Work blocks allocated to calculation circuits 124A-124B of die 122A are received by scheduler 125. Work blocks allocated to calculation circuits 124C-124D of die 122C are received by scheduler 127. The following description describes further scheduling steps, such as allocating work blocks to calculation circuits 124A-124B and 124C-124D. The following description describes these further scheduling steps performed by schedulers 125 and 127, but in other embodiments, schedulers 125 and 127 are absent, and the following further scheduling steps are performed by scheduler 142. In yet another embodiment, these schedulers 125 and 127 are absent, and the next further scheduling step is performed by schedulers (not shown) within partitions 120A and 120B.

[0021] In one embodiment, the operating parameters of modules 110A and 110B may have different values ​​from each other by a difference exceeding a threshold. In one example, modules 110A and 110B share one or more power rails that provide one or more power reference levels, but module 110B may operate at a clock frequency that is half or a quarter of the clock frequency used by module 110A. It may be advantageous for scheduler 142 to perform a further scheduling step of assigning work blocks to calculation circuits 124A-124B and 124C-124D in order to reduce voltage droop on one or more power rails used by modules 110A-110B. However, in such an embodiment, the latency of communication between scheduler 142 and calculation circuits 124A-124B and 124C-124D is below a threshold. For example, the calculation circuits 124A-124B and 124C-124D can send the queue usage values ​​of parameters 126 and 128 to the scheduler 142 with latency below a threshold.

[0022] In other embodiments, the operating parameters of modules 110A and 110B have values that differ from each other by less than a threshold such that separate schedulers 125 and 127 use overlapping scheduling windows. This overlap enables schedulers 125 and 127 to allocate work blocks to corresponding compute circuits of compute circuits 124A - 124B and 124C - 124D to reduce the voltage droop of one or more power rails shared by modules 110A - 110B. In some embodiments, the circuit configuration of scheduler 125, for execution, allocates the work blocks received from scheduler 142 to compute circuits 124A - 124B of die 122A. As shown, scheduler 125 transmits the work blocks to compute circuits 124A - 124B of die 122A as part of information 126. Similarly, the circuit configuration of scheduler 127 allocates the received work blocks to compute circuits 124C - 124D of die 122C for execution. As shown, scheduler 127 transmits the work blocks to compute circuits 124C - 124D of die 122C as part of information 128. In various embodiments, schedulers 125 and scheduler 127 allocate work blocks to corresponding compute circuits of compute circuits 124A - 124B and 124C - 124D to reduce the voltage droop of one or more power rails used by modules 110A - 110B.

[0023] Each of the schedulers 125 and 127 can determine when a corresponding scheduling window has begun. The following description is directed towards scheduler 125. However, scheduler 127 includes a circuit configuration that performs similar steps. As previously mentioned, in other embodiments, scheduler 142 performs the following steps, but includes a circuit configuration that simultaneously uses both the operational parameters of information 150 and 152 and the queue usage information of both information 126 and 128. In one embodiment, to determine when a scheduling window has begun, scheduler 125 determines that a certain period of time has elapsed since the most recent assignment of work blocks to the calculation circuits 124A-124B of die 122A was performed. In response to determining when a scheduling window has begun, scheduler 125 determines a threshold number of idle calculation circuits of calculation circuits 124A-124B that may be allowed to be activated simultaneously. Idle calculation circuits are activated when the connection to one or more of the clock generation circuit configurations and power rails is reactivated. In some embodiments, the scheduler 125 determines the threshold number of idle calculators based on one or more of the following: the number of active calculators, the operating clock frequency, the measured operating temperature, the queue usage of the queue of calculators that store assigned work blocks (information 126), and an application identifier that specifies the type of application being processed by the corresponding calculator (and therefore the type of work block).

[0024] When the scheduler 125 determines that there are counts of idle calculation circuits equal to or more than the threshold number of idle calculation circuits, the scheduler 125 allocates a number of work blocks equal to the threshold number to the idle calculation circuits of the calculation circuits 124A to 124B. In other words, the scheduler 125 restricts the number of idle calculation circuits that can be activated at one time in the calculation circuits 124A to 124B to the threshold number. In one example, the apparatus 100 has a total of 96 calculation circuits with 24 calculation circuits each in dies 122A to 122B and 122C to 122D. Die 122A has 16 calculation circuits in an idle state and 8 calculation circuits that have been activated and are already processing the assigned work blocks. The circuit configuration of the scheduler 125 can allocate 8 calculation circuits simultaneously in a clock cycle, but the threshold number for this specific clock cycle (or this specific scheduling window) is 4. Therefore, the scheduler 125 allocates work blocks to only 4 idle calculation circuits instead of 8 idle calculation circuits. This restriction on the number of calculation circuits to be activated reduces the voltage droop between the modules 110A to 110B.

[0025] In some embodiments, the scheduler 125 changes the scheduling rate. During a predetermined time period, the scheduler 125 restricts the total number of idle calculation circuits to which work blocks can be allocated and activated to process the allocated work blocks. In one embodiment, the scheduler 125 defines the time period as a specific number of clock cycles. The scheduler 125 can determine to allocate work blocks to the idle calculation circuits at a rate of two idle calculation circuits every other clock cycle during the time period. At the end of the time period, the scheduler 125 re-evaluates the scheduling based on the updated parameters. For example, the scheduler 125 redefines the threshold number of idle calculation circuits based on one or more updated values among the number of active calculation circuits, the operating clock frequency, the measured operating temperature, the queue usage status of the information 126, and any new application identifiers.

[0026] The queue usage information 126 includes the number of available queue entries (or slots) in the queues of the calculation circuits 124A to 124B. In one embodiment, these queues of the calculation circuits 124A to 124B are implemented as first-in, first-out (FIFO) buffers. Each queue entry in the queue can store an allocated work block received from the scheduler 142. Each queue entry is sometimes called a “slot”. A slot stores the program state of the allocated work block. In various embodiments, the calculation circuits 124A to 124B maintain a count of available slots or queue entries in the queues that store the allocated work blocks. The calculation circuits 124A to 124B send this count as information 126 to the scheduler 125. In some embodiments, when the scheduler 125 allocates multiple work blocks, such as eight work blocks, in a first scheduling window, the calculation circuits 124A to 124B complete these eight allocated work blocks before the subsequent second scheduling window begins. However, in other embodiments, the calculation circuits 124A to 124B may not complete one or more of these eight allocated work blocks before the subsequent second scheduling window begins. In order to avoid unintentionally scheduling more work blocks than the threshold number of idle calculation circuits in the subsequent second scheduling window, the scheduler 125 performs scheduling using the updated queue usage information 126.

[0027] When a corresponding calculation circuit among calculation circuits 124A to 124B begins executing any of its assigned work blocks in its slots, this calculation circuit uses the stored program state. In one embodiment, the stored program state includes a program counter and a pointer to a work item. If the instructions and data for a work item are not yet available in the calculation circuit's instruction cache and data cache, the calculation circuit uses the stored program state to fetch the instructions and data for the work item of the assigned work block. During one or more cache misses in the instruction cache and data cache, the latency required to repair the cache misses may keep the assigned work block in its slot when the next scheduling window begins. Therefore, already assigned work units have not yet completed execution. Depending on the latency required to repair the cache misses, it is possible that already assigned work blocks have not yet started execution. The calculation circuit sends the updated number of available slots (or other indicators of queue usage) to the scheduler 125 as part of the information 126. The scheduler 125 assigns eight work blocks to the calculation circuit 124A, but by the time another scheduling window arrives, the calculation circuit 124A may have completed only six of the eight assigned work blocks, rather than all eight.

[0028] If the above information is not available, such as the updated number of available slots as part of information 126, the scheduler 125 may unintentionally allocate more work blocks than the threshold number of idle calculation circuits in a subsequent scheduling window. If the above information is available, in one embodiment, the scheduler 125 will not allocate any additional work blocks until all previously allocated work blocks have been completed. Thus, the scheduler 125 will not allocate work blocks for one or more subsequent scheduling windows. In another embodiment, the scheduler 125 updates the threshold number of idle calculation circuits for subsequent scheduling windows based on the received queue usage of calculation circuits 124A to 124B provided in information 126. Each of the queue usage (or queue usage value) can be expressed as the number of available (unoccupied or free) queue entries for the corresponding queue, the number of occupied (valid data has been allocated) queue entries for the corresponding queue, the ratio of occupied queue entries to the total number of queue entries for the corresponding queue, the ratio of available queue entries to the total number of queue entries for the corresponding queue, etc.

[0029] In one embodiment, the device 100 has a total of 64 calculation circuits, with 16 calculation circuits in each of the dies 122A-122B and 122C-122D. In the first scheduling window, each of the 16 calculation circuits is idle, and the scheduler 125 determines that the threshold number of idle calculation circuits is 8. Although there are enough work blocks to assign to all 16 calculation circuits, the scheduler 125 assigns 8 work blocks to die 122A instead of 16 work blocks. This assignment of work blocks by the scheduler 125 reduces voltage droop in modules 110A-110B that share a power rail.

[0030] During the subsequent second scheduling window, die 122A has eight active computing circuits and eight idle computing circuits. Scheduler 125 determines that the threshold number for idle computing circuits (or the number of idle computing circuits) for assigning work blocks is 4. Therefore, scheduler 125 assigns four work blocks to the four computing circuits of die 122A, rather than assigning eight work blocks to eight computing circuits. This assignment of work blocks by scheduler 125 reduces voltage droop in modules 110A-110B that share the power rail. However, during execution, two of these four computing circuits have work block executions that are stalled due to one or more instruction cache misses and data cache misses. Without queue usage information 126, during the next (third) scheduling window, using the ratio of four idle computing circuits to at least 16 computing circuits in total, scheduler 125 determines that the updated threshold number for idle computing circuits is 2. However, after instruction cache misses and / or data cache misses are repaired, the two previously stalled compute circuits can begin execution after the third scheduling window is complete. Combining these two compute circuits (which were previously allocated during the second scheduling window) with the two compute circuits that are currently receiving work blocks from scheduler 125 during the third scheduling window results in a total of four compute circuits that can begin execution. This number of four compute circuits that can begin execution after the third scheduling window is complete exceeds the threshold number of two for updated idle compute circuits in the third scheduling window.

[0031] To avoid the above scenario where the number of updated idle computing circuits exceeds 2 for the third scheduling window, the scheduler 125 uses the queue usage information 126. Using the queue usage information 126, the scheduler 125 recognizes that during the third scheduling window, two of the four computing circuits to which the work block was previously assigned have stalled execution of the work block, or have not started execution using the arithmetic logic unit (ALU) and other computing circuit configurations by the time the third scheduling window begins. Therefore, the scheduler 125 determines that the number of updated idle computing circuits is 0, not 2. As a result, after the completion of the third scheduling, the number of computing circuits that can start execution exceeds two, making it impossible to draw enough current to produce a voltage droop greater than the voltage threshold. Since two computing circuits (previously assigned during the second scheduling window) may remain stalled, there may be no computing circuits to start execution after the third scheduling window, or they may not start execution by the time the subsequent fourth scheduling window begins.

[0032] Alternatively, in the third scheduling window, the scheduler 125 determines the updated threshold number of idle computing circuits based on additional information in information 126, such as the number of computing circuits that have completed execution. In one embodiment, during the third scheduling window, the scheduler 125 receives an indicator from information 126 that three of the previously allocated computing circuits (allocated during the first scheduling window) have completed their allocated work blocks, and these three computing circuits return to the idle state. The scheduler 125 is also aware of two other computing circuits (allocated during the second scheduling window) that are either stalled or simply performing memory access, but have not yet started execution by the ALU by the time the third scheduling window begins. Therefore, during this third scheduling window, the scheduler 125 determines that the total number of idle computing circuits is the sum of four idle computing circuits that have not yet been allocated work blocks, two stalled computing circuits, and three computing circuits that have returned from the active state to the idle state. This total is nine idle computing circuits. This total of nine idle calculation circuits is greater than the four idle calculation circuits determined without considering information 126, which includes indicators of two stalled calculation circuits and three calculation circuits that have returned from an active state to an idle state. Based on the total of nine idle calculation circuits, the scheduler 125 determines that the threshold number of idle calculation circuits is five. This threshold number of five is greater than the four idle calculation circuits determined without considering information 126, and less than the nine idle calculation circuits determined using information 126. Using information 126 to determine the threshold number of idle calculation circuits for assigning work blocks enables the scheduler 125 to assign work blocks to calculation circuits in a way that reduces voltage droop in modules 110A-110B that share a power rail.

[0033] Referring to Figure 2, a schematic block diagram of Graph 200, which shows the voltage droop at the power reference level of the integrated circuit, is shown. Graph 200 shows the power supply voltage 202 over time. Power supply voltage 202 is the power reference level on the power rail of the integrated circuit. During the operation of the integrated circuit, three different voltage droops 210, 212, and 214 occur over time. Simultaneous switching of the wide bus can cause a significant voltage drop in the power supply voltage 202 when the corresponding power rail supplies a large amount of current to circuit configurations such as buffers of the wide bus connected to the power rail. This voltage drop, also called "voltage droop," is expressed as ΔV, which is proportional to the equation L di / dt, where L is the parasitic inductance and di / dt is the rate of change over time of current consumption from the power rail. In addition to the wide bus, nearly simultaneous switching of many other nodes of the integrated circuit can also consume a large amount of current from the shared power rail. When this switching occurs, a significant voltage drop can occur relative to the power supply voltage 202.

[0034] As illustrated, a voltage droop 210 occurs at time t0 (or time t0), a voltage droop 212 occurs at time t1, the power supply voltage 202 begins to decrease again at time t2, and a voltage droop 214 occurs at time t3. The voltage droop 210 at time t0 occurs when many nodes are switched on simultaneously, such as when a considerable number of idle calculation circuits are activated at the same time. In one embodiment, the power supply voltage 202 is 900 millivolts (mV) and the voltage droop 210 is 300 mV. Nodes that have previously stored a Boolean logic high value may have their node voltage significantly reduced so that it appears as a Boolean logic low value in the circuit configuration. Node voltage glitches and even data loss may occur.

[0035] When multiple idle computing circuits are activated, the power supply voltage 202 can temporarily return to its original value. However, simultaneous switching of several wide buses and nodes when the application is handled by multiple active computing circuits causes a voltage droop 212 at time t1 and a voltage droop 214 at time t3. These voltage droops 212 and 214 are not as large as voltage droop 210. External capacitors are placed between power rails to create a passive bypass that reduces power rail oscillation due to external inductance. On-die capacitors are placed between power rails on the semiconductor die to reduce the internal inductance effect. These on-die capacitors are typically large and consume on-die area to be effective.

[0036] Furthermore, the calculation circuit includes a circuit configuration that implements reactive solutions to voltage droop, such as detecting and reducing the rate of change of current consumption di / dt over time. In some embodiments, these reactive solutions include one or more of a temperature sensor and a current consumption measuring sensor. For benefit, and to prevent voltage droop from dropping the node voltage below a minimum threshold, these reactive solutions have the requirement that the current reduction begins within a given time window. These capacitor and reactive circuit configuration solutions cannot be very effective against voltage droop 210 due to rapid initial occurrence when multiple idle calculation circuits are activated. To reduce voltage droop 210, the scheduler proactively limits the number of idle calculation circuits that are allowed to be activated simultaneously.

[0037] In some embodiments, if the scheduler proactively limits the number of idle calculation circuits that are allowed to be activated simultaneously, the scheduler additionally uses output measurements from temperature sensors and optional voltage droop measurement circuits. These circuits can provide non-zero voltage droop measurements. In one embodiment, this type of information is included in information 126 (in Figure 1) to provide an index of any initial or existing voltage droop before and at time t0 in graph 200. For example, an integrated circuit has been running an application for a certain duration, and although it is before time t0, the work block for the next iteration of the subroutine has not yet been assigned, and due to the current operating temperature and existing non-zero voltage droop, the supply voltage 202 is already lower than its expected value. This lower supply voltage value before and at time t0 is used by the scheduler to determine the threshold number of idle calculation circuits and to assign work blocks to the calculation circuits.

[0038] Referring now to Figure 3, a schematic block diagram of Graph 300 is shown, illustrating the number of active compute circuits over time in an integrated circuit. Graph 300 shows the number of compute circuits activated over time. This number is equal to the number of work blocks currently being executed, as each activated compute circuit receives a work block. In some embodiments, a compute circuit is a SIMD circuit with multiple execution lanes in the integrated circuit, and a work block is a wavefront (or wave) containing multiple work items. Graph 300 includes waveforms 310 and 320. Waveform 310 shows the number of active compute circuits when the scheduler assigns work blocks to available compute circuits as quickly as possible. Waveform 320 shows the number of active compute circuits when the scheduler assigns work blocks in a way that reduces voltage droop.

[0039] In the illustrated embodiment, during the duration from time t0 to time t8, there are no activated computing circuits that complete a work block and return to an idle state. However, such events occur during other times. At time t0, the computing circuits are not yet activated. Therefore, waveforms 310 and 320 both show that zero computing circuits are active. Between times t0 and t1, the work blocks of the application that have started execution are retrieved and / or constructed by the external circuit configuration. The work blocks are sent to the scheduler. In some embodiments, regardless of the scheduling algorithm implemented by the scheduler's circuit configuration, the rate at which work blocks are allocated and computing circuits are activated is the same, due to the initial rate at which work blocks are received when the application starts execution. In other embodiments, the rates are already different.

[0040] In various embodiments, the scheduling algorithm corresponding to waveform 320 updates the rate at which work blocks are allocated and computing circuits are activated at specific time intervals. This time interval is shown between each of the marked times, such as time t1, time t2, time t3, etc. This time interval may include several clock cycles based on the currently used operating clock frequency. Between time t1 and t2, waveform 310 shows an increase in the rate at which work blocks are allocated and computing circuits are activated. Waveform 310 shows that this same higher rate is continuously used until the maximum number of available computing circuits are activated between time t4 and t5.

[0041] In contrast to waveform 310, waveform 320 indicates that the same rate used between times t0 and t1 continues between times t1 and t2. At times t0 and t1, the scheduler corresponding to waveform 320 determines that the number of pending work blocks to be allocated is less than the threshold number of idle computing circuits that can be activated simultaneously. Also, if the number of work blocks initially sent to the scheduler is already large, the number of pending work blocks to be allocated may be greater than or equal to the threshold number of idle computing circuits, and the rate shown by waveform 320 decreases. At time t2, waveform 320 indicates that the rate at which work blocks are allocated and computing circuits are activated increases compared to the rate used between times t0 and t2. At time t2, again, the scheduler corresponding to waveform 320 determines that the number of pending work blocks to be allocated is less than the threshold number of idle computing circuits that can be activated simultaneously. However, since the number of pending work blocks has increased, the rate shown by waveform 320 has increased.

[0042] At time t3, waveform 320 indicates that the rate at which work blocks are allocated and calculation circuits are activated decreases compared to the rate used previously. Here, the corresponding scheduler has determined that the count of idle calculation circuits is greater than or equal to this threshold number. The scheduler allocates work blocks only to the threshold number of idle calculation circuits, thereby reducing the rate at which work blocks are allocated and subsequently issued. Between times t3 and t4, the rate of change of current consumption from the power rail (di / dt) decreases as a result of this reduction in the rate at which work blocks are allocated and calculation circuits are activated. Therefore, the resulting voltage droop is reduced between times t3 and t4. In some embodiments, between times t3 and t4, the rate at which work blocks are allocated and calculation circuits are activated is 0, and therefore no further idle calculation circuits are activated. As a result, the rate di / dt becomes zero between times t3 and t4.

[0043] Note that in some embodiments, the scheduler updates over time the threshold number of idle calculators that can be activated simultaneously, based on one or more of the following: the number of pending work blocks, the number of activated calculators, the number of idle calculators, the queue usage of the queue of calculators that store allocated work blocks, an application identifier indicating the type of work performed by the activated calculators that execute the work blocks, the power domains and / or P states used by the activated calculators, etc. At times t4 and t6, the waveform 320 shows that the rate at which work blocks are allocated and calculators are activated increases, similar to the increase at time t2. At times t5 and t7, the waveform 320 shows that the rate at which work blocks are allocated and calculators are activated decreases, similar to the decrease at time t3.

[0044] Waveform 320 demonstrates that voltage droop can be reduced by decreasing the rate at which work blocks are allocated and compute circuits are activated simultaneously, while still maintaining a high level of performance. For example, the duration between the first time point in time when waveform 310 activates the maximum number of compute circuits between times t4 and t5, and the second time point in time when waveform 320 activates the maximum number of compute circuits between times t7 and t8, can be below a time threshold. It should also be noted that the scheduler corresponding to waveform 320 proactively reduces the rate at which work blocks are allocated and compute circuits are activated simultaneously based on values ​​collected during the time interval. For example, the rate reduction at time t3 is based on values ​​collected before time t3. Thus, the scheduler uses a proactive method rather than a reactive method. A reactive method includes an on-die measurement of current consumption and, based on whether the measurement exceeds a threshold, limits the scheduler to allocating work blocks or issuing instructions in activated compute circuits. It is possible and intended that integrated circuits reduce voltage droop by using proactive methods in combination with reactive methods.

[0045] Referring next to Figure 4, a schematic block diagram of method 400 for efficiently managing voltage droop in multiple computing circuits of an integrated circuit is shown. For illustrative purposes, the steps in this embodiment are shown in order. However, in other embodiments, some steps occur in a different order than those shown, some steps are performed simultaneously, some steps are combined with others, and some steps are absent.

[0046] The integrated circuit includes multiple duplicated compute circuits. The scheduler assigns work blocks to idle compute circuits, which are then activated and process the assigned work blocks. The scheduler detects when a scheduling window has begun (block 402). For example, the scheduler determines that a certain time period has elapsed since the most recent assignment of a work block. The scheduler determines a threshold number of idle compute circuits that can be activated simultaneously (block 404). In some embodiments, the scheduler determines this threshold number of idle compute circuits based on one or more of the following: the number of active compute circuits to which work blocks are assigned (or conversely, the number of idle compute units to which no work blocks are assigned), the total number of compute circuits, the number of stalled compute circuits, the number of compute circuits that have recently completed the execution of work blocks, the number of pending work blocks, any measured existing voltage droop, operating clock frequency, measured operating temperature, queue usage of the queue of compute circuits that store assigned work blocks, and application identifiers.

[0047] In one embodiment, the scheduler determines a threshold number of idle calculation circuits that can be activated simultaneously based on the ratio of the number of idle calculation circuits to the total number of calculation circuits. To determine the number of idle calculation circuits, the scheduler includes the number of calculation circuits that were previously assigned a work block but have not yet started executing the corresponding work block. To determine the number of idle calculation circuits, the scheduler also includes the number of calculation circuits that are executing a work block but have not yet completed the execution of the corresponding work block. In some embodiments, the scheduler reduces the threshold number of idle calculation circuits that can be activated simultaneously when the scheduler receives an indicator of an existing non-zero voltage droop measurement.

[0048] If the scheduler determines that the number of idle compute circuits is greater than or equal to a threshold number (conditional block 406: "yes"), the scheduler allocates a number of work blocks equal to the threshold number to the idle compute circuits (block 408). In other words, the scheduler limits the number of idle compute circuits that can be activated at one time to a threshold number. In various embodiments, the scheduler limits the number of idle compute circuits that can be activated simultaneously even when the scheduler receives an indicator of a power performance state that indicates that it should be done to allocate one of the pending work blocks to each of the idle compute circuits in order to maintain a certain throughput. In one example, the integrated circuit has a total of 24 compute circuits, 16 of which are idle, and 8 compute circuits are activated and have already processed their allocated work blocks. The scheduler's circuit configuration allows for the allocation of 8 compute circuits simultaneously in a clock cycle, but the threshold number for this particular clock cycle is 4. As mentioned above, the scheduler determines the threshold number of idle calculators based on one or more of the following: the number of active calculators, the total number of calculators, the number of stalled calculators, the number of calculators that have recently completed executing work blocks, the number of pending work blocks, any measured existing voltage droop, operating clock frequency, measured operating temperature, queue usage of the queue of calculators that store assigned work blocks, and application identifiers. Therefore, the scheduler assigns work blocks to only four idle calculators, not eight.

[0049] In some embodiments, the scheduler modifies the scheduling rate. During a given time period, the scheduler limits the total number of idle compute circuits to which work blocks can be assigned and activated to process the assigned work blocks. In one embodiment, the scheduler defines the time period as a specific number of clock cycles. The scheduler may decide to assign work blocks to idle compute circuits at a rate of two idle compute circuits every other clock cycle during the time period. At the end of the time period, the scheduler re-evaluates the scheduling based on updated parameters. For example, the scheduler redefines the threshold number of idle compute circuits based on the number of active compute circuits, the operating clock frequency, the measured operating temperature, the queue usage of the compute circuit queues that store assigned work blocks, and the updated value of any new application identifiers. The scheduler repeats the steps of blocks 402-406 of method 400.

[0050] If the scheduler determines that there are fewer idle compute circuits than the threshold number (conditional block 406: "No"), the scheduler allocates a number of work blocks to the idle compute circuits equal to or less than the count of idle compute circuits (block 410). If there are no data dependencies between the work blocks to be allocated and the work blocks already being executed, the scheduler allocates a number of work blocks equal to the count of idle compute circuits to the idle compute circuits. Otherwise, the scheduler allocates a number of work blocks less than the count of idle compute circuits to the idle compute circuits. The integrated circuit activates the idle compute circuits to which the work blocks have been allocated (block 412). The activated compute circuits execute the allocated work blocks (block 414).

[0051] Referring next to Figure 5, a schematic block diagram of a computing system 500 that efficiently manages the voltage droop of multiple computing circuits in an integrated circuit is shown. As illustrated, the computing system 500 includes a processor 510, memory 520, and a parallel data processor 530. In some embodiments, the functions of the computing system 500 are included as multiple components on a single die, such as a single integrated circuit. In other embodiments, the functions of the computing system 500 are included as multiple dies on a system-on-a-chip (SOC). In other embodiments, the functions of the computing system 500 are implemented by multiple separate dies that are manufactured on separate silicon wafers and arranged in a system package known as a multi-chip module (MCM). In various embodiments, the computing system 500 is used in desktops, portable computers, mobile devices, servers, peripheral devices, and the like.

[0052] The circuit configuration of the processor 510 processes instructions of a predetermined algorithm. Processing includes fetching instructions and data, decoding instructions, executing instructions, and storing results. In one embodiment, the processor 510 uses one or more processor cores having a circuit configuration for executing instructions according to a predetermined general-purpose instruction set architecture (ISA). In various embodiments, the processor 510 is a general-purpose central processing unit (CPU). The parallel data processor 530 uses one or more processor cores having a relatively broad single-instruction multiple data (SIMD) microarchitecture to achieve high throughput in highly data-parallel applications. In one embodiment, the parallel data processor 530 is a graphics processing unit (GPU). In other embodiments, the parallel data processor 530 is a different type of circuit configuration.

[0053] In various embodiments, the computing circuit 534 is a SIMD circuit having a circuit configuration of multiple execution lanes. The scheduler 532 schedules work blocks to the computing circuit 534 to reduce voltage droop in the computing circuit 534. In various embodiments, the scheduler 532 includes the functionality of scheduler 125 (or scheduler 127 or scheduler 142) (in Figure 1) and performs the described scheduling steps to generate the waveform 320 of graph 300 (in Figure 3). Such functionality reduces voltage droop, such as the voltage droop 210 (in Figure 2). Here, a work block is a wavefront (or wave) of multiple work items. The parallel data processor 530 is efficient for data parallel computing found in application loops, such as applications for manipulating, rendering, and displaying computer graphics. In this case, each data item of the wavefront is a pixel of an image. The application may also include molecular dynamics simulations, financial calculations, neural network training, etc. The highly parallel structure of the parallel data processor 530 is more effective than the general-purpose structure of the processor 510.

[0054] In various embodiments, threads are scheduled on either the processor 510 or the parallel data processor 530 so that each thread has the best instruction throughput, at least partially based on the runtime hardware resources of the processor 510 and the parallel data processor 530. In some embodiments, some threads are associated with general-purpose algorithms and are scheduled on the processor 510, while other threads are associated with parallel data computation-intensive algorithms, such as video graphics rendering algorithms, and are scheduled on the parallel data processor 530. The computation circuit 534 can be used for real-time data processing such as rendering multiple pixels, image blending, pixel shading, vertex shading, and geometry shading. Some threads are not video graphics rendering algorithms but still exhibit parallel data and intensive throughput. These threads have instructions that can operate simultaneously on a relatively large number of different data elements (or data items). Examples of these threads are threads for scientific computing, medical computing, financial computing, and cryptographic / decryption computing.

[0055] To change the scheduling of the above calculations from processor 510 to parallel data processor 530, a software development kit (SDK) and application programming interface (API) were developed to provide supported function calls for use with widely available high-level languages. The function calls provide an abstraction layer of the parallel implementation details of the parallel data processor 530. These details are hardware specific to the parallel data processor 530, but are hidden from developers to allow for more flexible description of software applications. Function calls in high-level languages ​​such as C, C++, FORTRAN, and Java® are translated into commands that are later processed by the hardware within the parallel data processor 530. Although a network interface is not shown, in some embodiments the parallel data processor 530 is used by remote programmers in a cloud computing environment.

[0056] The software application begins execution on the processor 510. Function calls within the application are translated into commands by a predetermined API. The processor 510 sends the translated commands to memory 520 and stores them in the ring buffer 522. The commands are arranged in groups called command groups. In some embodiments, processors 510 and 530 use a producer-consumer relationship, also known as a client-server relationship. The processor 510 writes commands to the ring buffer 522. The circuit configuration of the controller (not shown) of the parallel data processor 530 reads commands from the ring buffer 522. In some embodiments, the controller is the command processor of the GPU. The controller sends a work block to the scheduler 532, which assigns the work block to the compute circuit 534. This allows the parallel data processor 530 to process the commands and write the resulting data to the buffer 524. The processor 510 is configured to update the write pointer for the ring buffer 522 and provide a size for each command group. The parallel data processor 530 updates the read pointer for the ring buffer 522 to indicate the entry in the ring buffer 522 that will be used by the next read operation.

[0057] Referring to Figure 6, a schematic block diagram of an integrated circuit 600 for efficiently managing the voltage droop of multiple computing circuits is shown. In the illustrated embodiment, the integrated circuit 600 includes two partitions, such as partition 610 and partition 650. Each of partitions 610 and 650 includes components for processing work blocks. Partition 610 includes a cache memory 620 accessed by computing resources 630. Computing resources 630 include computing circuits 640A, 640B, 640C (or computing circuits 640A-640C). Partition 650 includes clients 660-662. The control block 670 includes a scheduler 672 and a power manager 674. In some embodiments, the scheduler 672 and power manager 674 have the same functions as the scheduler 142 and power manager 144 (in Figure 1). For example, in one embodiment, the scheduler 672 of control block 670 schedules work blocks on the calculation circuits 640A-640C of partition 610. In another embodiment, the scheduler 622 of partition 610 schedules work blocks on the calculation circuits 640A-640C. Either scheduler 672 or scheduler 622 schedules work blocks on the calculation circuits 640A-640C to reduce voltage droop on the calculation circuits 640A-640C. In various embodiments, scheduler 672 (or scheduler 622) includes the functionality of scheduler 125 (or scheduler 127 or scheduler 142 in Figure 1) and performs the scheduling steps described to generate the waveform 320 of graph 300 (in Figure 3). Such functionality reduces voltage droop, such as the voltage droop 210 (in Figure 2).

[0058] Communication mechanisms, memory controllers, interrupt controllers, and clock generation circuit configurations such as phase-locked loops (PLLs) are not shown for the sake of clarity. In some embodiments, the functionality of the integrated circuit 600 is provided as multiple components on a single die, such as a single integrated circuit. In one embodiment, the functionality of the device 100 is provided as one die among several dies on a system-on-a-chip (SOC). In other embodiments, the functionality of the integrated circuit 600 is provided by several separate dies manufactured on separate silicon wafers and arranged in a system package known as a multi-chip module (MCM). In various embodiments, the device 100 is used in desktops, portable computers, mobile devices, servers, peripheral devices, and the like.

[0059] In some embodiments, partitions 610 and 650 are each assigned to their respective power domains. In other embodiments, partitions 610 and 650 are each assigned to the same power domain. A power domain includes at least operating parameters such as the operating power supply voltage and the operating clock frequency. A power domain also includes control signals for enabling and disabling the clock generation circuit configuration and connections to one or more power references. In information 682, partition 610 receives the operating parameters of the first power domain from the power controller 670. In information 684, partition 650 receives the operating parameters of the second power domain from the power controller 670.

[0060] Clients 660-662 include various types of circuits such as a central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), and multimedia engine. Each of clients 660-662 can process work blocks of various workloads. In some embodiments, work blocks scheduled on partition 610 include wavefronts, while work blocks scheduled on partition 650 include instructions that operate on a single data item and are not grouped into wavefronts. Additionally, each of clients 660-662 can generate and service one or more of various requests, such as memory access read and write requests and cache snoop requests.

[0061] In one embodiment, the integrated circuit 600 is a graphics processing unit (GPU). The circuit configuration of the computing resource 630 in partition 610 handles highly data-parallel applications. The computing resource 630 includes multiple computing circuits 640A-640C, each having multiple lanes 642. In some embodiments, lanes 642 operate in lockstep. In various embodiments, the data flow within each of lanes 642 is pipelined. Pipeline registers are used to store intermediate results, and the circuit configuration for the arithmetic logic unit (ALU) performs integer operations, floating-point operations, Boolean logic operations, branch condition comparisons, etc. These components are not shown for the sake of clarity. Each of the computing circuits within a given row across lanes 642 is the same computing circuit. Each of these computing circuits operates on the same instruction but on different data associated with different threads. As previously mentioned, some work items are grouped into wavefronts for concurrent execution by multiple SIMD execution lanes, such as lanes 642 of computing circuits 640A-640C. Each data item is processed independently of the others, but the same sequence of operations of the subroutine is used.

[0062] As illustrated, each of the calculation circuits 640A to 640C includes a queue 643 for storing allocated work blocks, a register file 644, a local data store 646, and a local cache memory 648. In some embodiments, the local data store 646 is shared among the lanes 642 in each of the calculation circuits 640A to 640C. In other embodiments, the local data store is shared among the calculation circuits 640A to 640C. Thus, one or more lanes 642 in calculation circuit 640A can share result data with one or more lanes 642 in calculation circuit 640A, based on the operating mode. In one embodiment, the queue 643 is implemented as a first-in, first-out (FIFO) buffer. Each queue entry in the queue 643 can store allocated work blocks received from the scheduler 622 (or scheduler 672). Each queue entry is sometimes called a “slot”. A slot stores the program state of the allocated work block. In various embodiments, the computing circuits 640A-640C maintain a count of available slots or queue entries in a queue that stores allocated work blocks. The computing circuits 640A-640C transmit this count as information to the scheduler 622 (or scheduler 672). While an example of a single-instruction multiple data (SIMD) microarchitecture is shown for computing resource 630, other types of highly parallel data microarchitectures are possible and intended. The high parallelism provided by the hardware of computing resource 630 is used to render multiple pixels simultaneously, but it can also be used to process multiple data elements simultaneously for scientific computing, medical computing, financial computing, cryptographic / decryption computing, and other computing.

[0063] Clients 660-662 may include one or more of the following: analog-to-digital converters (ADCs), scan converters, video decoders, display controllers, and other computing circuits. In some embodiments, partition 660 is used for real-time data processing, while partition 650 is used for non-real-time data processing. Examples of real-time data processing include rendering multiple pixels, image blending, pixel shading, vertex shading, and geometry shading. Examples of non-real-time data processing include multimedia playback such as video decoding for encoded audio / video streams, background processing such as image scaling, image rotation, color space conversion, power-on initialization, and garbage collection. A controller (not shown) circuit configuration receives tasks. In some embodiments, the controller is the command processor of the GPU, and a task is a sequence of commands (instructions) for function calls of an application. Based on the task type of the received task, the controller assigns the task to one of the two partitions 610 and 650. Either scheduler 672 or 622 receives these tasks from the controller and, if these tasks have not yet been organized into work blocks, organizes them into work blocks and schedules work blocks on calculation circuits 640A to 640C to reduce voltage droop on calculation circuits 640A to 640C.

[0064] Referring next to Figure 7, a schematic block diagram of a scheduler 700 that manages voltage droop between duplicate computing circuits of an integrated circuit is shown. As illustrated, the scheduler 700 includes a table 710 and a control circuit configuration 730. The control circuit configuration 730 receives an input value 740 and generates work block assignments 750 for multiple duplicate computing circuits of the integrated circuit. The control circuit configuration 730 generates work assignments 750 to reduce voltage droop on one or more power rails used by the multiple duplicate computing circuits. The control circuit configuration 730 includes components 732-738 used to assign work blocks to the multiple duplicate computing circuits. In some embodiments, the computing circuit is a single-instruction multiple data (SIMD) circuit with multiple execution lanes, and the work block is a wavefront with multiple work items. The table 710 includes multiple table entries (or entries), each storing information in multiple fields such as at least fields 712-722. In some embodiments, one or more of the components and corresponding functions of the scheduler 700 are provided in a separate external circuit rather than within the scheduler 700. In various embodiments, the functions provided by the scheduler 700 are also provided by the scheduler 125 (or scheduler 127 or scheduler 142) (in Figure 1), the scheduler 532 (in Figure 5), the scheduler 672 (or scheduler 622) (in Figure 6), and the scheduler 812 (in Figure 8).

[0065] Table 710 is implemented by one of the following: flip-flop circuits, random access memory (RAM), associative memory (CAM), etc. Although it is shown that certain information is stored in fields 712-722 in a specific adjacent order, in other embodiments a different order may be used and different numbers and types of information may be stored. Field 712 stores status information, such as at least the valid bits and an indicator that the corresponding computing circuit is active or idle. Active computing circuits process assigned work blocks using the operating parameters of the assigned P state. An "idle computing circuit" is one which has no assigned work block and is typically clock-gated, or an idle computing circuit has its connection to the clock generation circuit configuration disabled. Field 714 stores an identifier that specifies one of several duplicate modules of the integrated circuit. Field 716 stores an identifier that specifies one of several dies within a particular module. Field 718 stores an identifier that specifies one of several computing circuits within a particular die.

[0066] Field 720 stores operating parameters of a specific power performance state (P state) currently used by the corresponding computing circuit, such as the operating power supply voltage and operating clock frequency. In one embodiment, one or more of the operating power supply voltage and operating clock frequency are used by the control circuit configuration 730 to generate a work block assignment 750. Field 722 stores other reporting information, such as an application identifier that specifies the type of application (and therefore the type of work block) being processed by the corresponding computing circuit. The application type can provide an indicator of the activity level or power consumption required to process the application's work block. Another example of information in field 722 is whether the first work block of the corresponding computing circuit is data-dependent on the second work block, and therefore whether both the first and second work blocks should be assigned to the corresponding computing circuit. Field 722 may store an indicator of the power rail if some of the computing circuits of the integrated circuit do not use the same power rail as the others.

[0067] The control circuit configuration 730 receives an input value 740, which is used in conjunction with values ​​stored in table 710 and configuration register 734 to generate a work block assignment 750. While specific numbers and types of input values ​​are illustrated, in other embodiments, different numbers and types of input values ​​may be used by the control circuit configuration 730. The input value 740 includes a period count 742, which is a timer output value that counts the number of clock cycles since the last time the control circuit configuration 730 generated a work block assignment 750. In another embodiment, configuration register 734 includes a timer that maintains this count value. The control circuit configuration 730 compares the period count 742 to a threshold period 738, and if a match occurs, the work block assignment selector 732 generates a work block assignment 750 using values ​​stored in table 710 and configuration register 734. In various embodiments, a match occurs if a threshold period 738 has elapsed since the most recent assignment of a work block to the idle calculation circuit 750.

[0068] In one embodiment, the period count 742 is a clock cycle count. In one embodiment, one or more of the external circuit configuration and the control circuit configuration 730 reset the period count 742 when the control circuit configuration generates a work block assignment 750. In one embodiment, the time period indicated by the threshold period 738 is shorter than the duration required for the computing circuit to complete the execution of the assigned work block. In other embodiments, the time period indicated by the threshold period 738 is longer than the duration required for the computing circuit to complete the execution of the assigned work block. In some embodiments, the control circuit configuration 730 maintains multiple values ​​for the threshold period 738 and selects a specific value based on one or more of the input value 740 and values ​​stored in the table 710. For example, the value of the threshold period 738 for a high-performance and high-power consumption application running on the computing circuit using high-performance P-state operating parameters may differ from the value of the threshold period 738 for a lower-performance and lower-power consumption application running on the computing circuit using lower-performance P-state operating parameters.

[0069] In some embodiments, the control circuit configuration 730 determines from table 710 the count of idle compute circuits on the same voltage rail 744 and the number of idle compute circuits on a separate voltage rail 746. In some embodiments, the number (count) of idle compute circuits on the same voltage rail 744 is based on the control circuit configuration 730 receiving the queue usage of the compute circuit queue that stores assigned work blocks. In other embodiments, when a compute circuit becomes idle, one or more of the configuration registers 734 and table 710, such as the compute circuit count 734, are updated, and one or more of the input values ​​744 and 746 are adjusted. If the available compute circuits use two or more activated power reference level rails (or power rails) (power switches connect power rails to compute circuits), the scheduler 700 can allocate work blocks among the available compute circuits across different power rails. Distributing the allocation of work blocks in this way helps reduce voltage droop on any one power rail. In such a case, the configuration register 734 may contain a separate set of registers for values ​​736-738 for each of the power rails.

[0070] If each of the available computing circuits uses a single shared voltage rail, input value 746 is not used. In such a case, configuration register 734 includes a single set of registers for values ​​736-738 for a single available power rail. In one embodiment, the number of pending work blocks 748 is provided by an external circuit configuration. In another embodiment, control circuit configuration 730 determines input value 748 from one or more applications being processed. The incoming application identifier 749 specifies the type of application (and therefore the type of work block) to be processed by one or more computing circuits. The application type can provide an indicator of the activity level or power consumption required to process the work block of the incoming application.

[0071] In some embodiments, the control circuit configuration 730 receives an indicator of operating temperature. In such embodiments, the integrated circuit provides a measured temperature value derived from measurements of analog and / or digital thermal sensors placed throughout the integrated circuit. If it is determined that the next assignment of a work block should be performed, such as when the period count 742 matches the threshold period 738, the hardware of the work block assignment selector 732 (or selector 732) generates a work block assignment 750 based on at least the input value 740 and the values ​​stored in table 710. To maximize performance, rather than assigning work blocks to the maximum number of available idle compute circuits, selector 732 assigns work blocks to a smaller number of available idle compute circuits. This smaller number is based on reducing the voltage droop on the power rails used by multiple compute circuits. This smaller number is represented by the threshold number of idle compute circuits 737 in the configuration register 734.

[0072] In some embodiments, the number of idle calculation circuits thresholds 737 is determined during testing and characterization of the integrated circuit, based on the input value 740 and one or more values ​​stored in the table 710. Each of these number of idle calculation circuits thresholds provides a voltage droop of a corresponding power supply reference level used by multiple calculation circuits, which is below a voltage threshold. Thus, one or more number of idle calculation circuits thresholds to be activated simultaneously at a given time are stored in one or more of the following: a table (separate from the table 710), another data structure, a memory storing firmware, and ROM (or EPROM). The selector 732 generates an index based on the input value 740 and one or more values ​​stored in the table 710, and then uses the generated index to retrieve the number of idle calculation circuits thresholds to be indexed in the table or other data structure and activated. The selector 732 stores this retrieved value in the configuration register 734 as the number of idle calculation circuits thresholds 737 in the programmable register of the configuration register 734. In another embodiment, the control circuit configuration 700 locally stores a data structure containing multiple values ​​for the number of thresholds 737 of the idle calculation circuit, and retrieves a value to be used for assignment based on a condition satisfied by one or more of the input values ​​740 and the values ​​stored in the table 710.

[0073] In some embodiments, the control circuit configuration 730 maintains a count 736 of idle calculation circuits among multiple calculation circuits that share a power reference level rail (power rail) in a configuration register 734. To maintain this count 736, selector 732 uses table 710 and any received updates of active / idle status information used to update table 710. If selector 732 determines that the period count 742 matches (or will never be less than) the threshold period 738, selector 732 ensures that the number of idle calculation circuits to which work blocks are allocated and activated does not exceed the threshold number of idle calculation circuits 737. For example, if selector 732 determines that the period count 742 matches (or will never be less than) the threshold period 738, and selector 732 determines that the count of idle calculation circuits 734 is greater than or equal to the threshold number of idle calculation circuits 737, selector The scheduler 700 or other external circuit configuration activates the assigned idle calculation circuits and provides these circuits with assigned work blocks to process. If the first work block of a corresponding calculation circuit is data-dependent on a second work block, and therefore both the first and second work blocks should be assigned to the corresponding calculation circuit, the selector 732 may assign fewer idle calculation circuits than the threshold number 737 for idle calculation circuits.

[0074] In one example, the integrated circuit contains 12 calculation circuits, and the count of idle calculation circuits on the same voltage rail 744 is 9 idle calculation circuits. Based on the operating conditions determined from the input value 740 and the values ​​stored in table 710, the control circuit configuration 730 determines that the threshold number of idle calculation circuits 737 is 6 idle calculation circuits. The number of pending work blocks 748 is 18. If the selector 732 determines that the period count 742 matches (or will never be less than) the threshold period 738, and that the count of idle calculation circuits 734 (9 calculation circuits) is greater than or equal to the threshold number of idle calculation circuits 737 (6 calculation circuits), the selector assigns the work block to the idle calculation circuit. However, instead of assigning the maximum number of 9 idle calculation circuits to 9 work blocks, the scheduler 700 assigns 6 idle calculation circuits (the threshold number of idle calculation circuits 737) to 6 work blocks. Therefore, the scheduler 700 reduces voltage droop on the power rails shared by the idle calculation circuits. For example, the scheduler 700 provides voltage droop on the power rails used by the 12 calculation circuits that is below a voltage threshold.

[0075] Due to data dependencies between work blocks, the scheduler 700 may assign only four or five work blocks to four or five idle calculation circuits, which is fewer than six idle calculation circuits with a threshold number of idle calculation circuits 737 and the maximum number of nine idle calculation circuits. If the number of pending work blocks 748 is 5, which is less than six idle calculation circuits with a threshold number of idle calculation circuits 737, the scheduler 700 can assign all five pending work blocks to five idle calculation circuits, provided that data dependencies do not reduce the number of assigned idle calculation circuits. In some embodiments, the integrated circuit is a graphics processing unit (GPU) or another parallel data processing circuit.

[0076] In one example, the integrated circuit contains eight chiplets, each chiplet contains six compute circuits, each compute circuit contains two SIMD circuits, and each SIMD circuit contains 64 execution lanes for executing 64 work items simultaneously. Therefore, there are 6,144 available execution lanes (64 × 2 × 6 × 8 = 6,144), so the integrated circuit can execute 6,144 work items simultaneously on 6,144 execution lanes. A wavefront (or wave) consists of 64 work items, and the scheduler 700 considers a wavefront to be a work block. Therefore, in this example, the scheduler 700 considers a SIMD circuit to be a compute circuit, and there are 96 compute circuits (2 × 6 × 8 = 96), so there are a maximum of 96 work blocks to execute simultaneously on the 96 compute circuits. For table 710, the scheduler 700 considers a chiplet to be a die and a compute circuit to be a module. In this example, the values ​​736-738 stored in configuration register 734 are updated based on one or more of the input value 740 and the values ​​stored in table 710.

[0077] Referring now to Figure 8, a schematic block diagram of a system-in-package (SiP) 800 that manages the voltage droop of multiple computing circuits in an integrated circuit is shown. In various embodiments, three-dimensional (3D) packaging is used within the computing system. This type of packaging is called a system-in-package (SiP). A SiP includes one or more three-dimensional integrated circuits (3D ICs). A 3D IC includes two or more layers of active electronic elements integrated into a single circuit both vertically and / or horizontally. In one embodiment, interposer-based integration is used, thereby placing the 3D IC next to a processor 810. Alternatively, the 3D IC is stacked directly on top of another IC.

[0078] Die stacking technology is a manufacturing process that enables the physical stacking of multiple separate silicon pieces (integrated chips) together within the same package, providing high bandwidth and low latency interconnects. In some embodiments, dies are stacked side-by-side on a silicon interposer or directly vertically on top of each other. One configuration of a SiP is to stack one or more semiconductor dies (or dies) next to and / or on top of a processor, such as a processor 810. In one embodiment, SiP 800 includes a processor 810 and modules 840A-840B. Module 840A includes a semiconductor die 820A and multiple three-dimensional (3D) semiconductor dies 822A-822B within a partition 850A. Although two dies are shown, in other embodiments, any number of dies can be used as stacked 3D dies.

[0079] Similarly, module 840B includes semiconductor die 820B and several 3D semiconductor dies 822C-822D within partition 850B. Although not shown, each of dies 822A-822B and dies 822C-822D includes one or more computing circuits. Scheduler 812 schedules work blocks on the computing circuits within dies 822A-822B and 822C-822D to reduce voltage droop on the computing circuits. In various embodiments, scheduler 812 includes the functions of scheduler 125 (or scheduler 127 or scheduler 142) (in Figure 1), scheduler 532 (in Figure 5), scheduler 672 (or scheduler 622) (in Figure 6), and scheduler 700 (in Figure 7). The scheduler 812 performs the described scheduling steps to generate the waveform 320 in graph 300 (Figure 3). Such a function reduces voltage droop, such as the voltage droop 210 (Figure 2).

[0080] Dies 822A to 822B within partition 850A share at least the same power rail. Dies 822A to 822B may also share the same clock signal. Dies 822C to 822D within partition 850B share at least the same power rail. Dies 822C to 822D may also share the same clock signal. In some embodiments, another module containing a die that is an instantiated copy of die 820A is located adjacent to the left of module 840A. This other die and die 820A may, and are intended to, share at least the same power rail.

[0081] Each of modules 840A to 840B communicates with the processor 810 through a horizontal low-latency interconnect 830. In various embodiments, the processor 810 is a general-purpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a field-programmable gate array (FPGA), or other data processing device. The in-package horizontal low-latency interconnect 830 provides a reduction in the length of interconnect signals compared to long off-chip interconnects, which would occur if a SiP were not used. The in-package horizontal low-latency interconnect 830 uses specific signals and protocols as if the processor 810 and chips such as modules 840A to 840B were implemented in separate packages on a circuit board. In some embodiments, the SiP 800 further includes back-side vias or through-bulk silicon vias 832 that reach external package connections 834. External package connections 834 are used for input / output (I / O) signals and power signals.

[0082] In various embodiments, multiple device layers are stacked on top of each other, having direct vertical interconnects 836 that tunnel them together. In various embodiments, the vertical interconnects 836 are multiple through-silicon vias that are brought together to form a through-silicon bus (TSB). The TSB is used as a vertical electrical connection that penetrates the silicon wafer. The TSB is an alternative interconnect to wiring junctions and flip-chip interconnects. The size and density of the vertical interconnects 836 that can tunnel between different device layers vary based on the underlying technology used to manufacture 3D ICs.

[0083] As illustrated, some of the vertical interconnects 836 do not pass through each of modules 840A-840B. Therefore, in some embodiments, the processor 810 does not have direct connections to one or more dies, such as die 822D in the illustrated embodiments. Thus, information routing depends on other dies in the SiP800. In various embodiments, dies 822A-822B and 822C-822D are chiplets. As used herein, “chiplet” is also called “intellectual property block” (or IP block). However, a “chiplet” is a semiconductor die (or die) that is manufactured separately from other dies and then interconnected with these other dies within a single integrated circuit in the MCM.

[0084] On a single silicon wafer, only multiple chiplets are manufactured as multiple instantiated copies of a specific integrated circuit configuration, and not together with other computing circuits that do not use these instantiated copies of the specific integrated circuit configuration. For example, a chiplet is not manufactured on a silicon wafer together with various other computing circuits on a larger semiconductor die such as an SoC. A first silicon wafer (or first wafer) is manufactured together with multiple instantiated copies of the integrated circuit configuration of a first chiplet, and this first wafer is diced using laser cutting technology to separate the multiple copies of the first chiplet.

[0085] A second silicon wafer (or second wafer) is manufactured with multiple instantiated copies of the integrated circuit configuration of the second chiplet, and this second wafer is diced using laser cutting techniques to separate the multiple copies of the second chiplet. The first chiplet provides a function different from that of the second chiplet. One or more copies of the first chiplet are placed in the integrated circuit, and one or more copies of the second chiplet are placed in the integrated circuit. The first and second chiplets are interconnected with each other in the corresponding MCM. Such a process replaces the process of manufacturing a third silicon wafer (or third wafer) having multiple copies of a single monolithic semiconductor die, the single monolithic semiconductor die containing the functions of the first and second chiplets as integrated computing circuits within that single monolithic semiconductor die.

[0086] The process yield of a single monolithic die on a silicon wafer is lower than the process yield of smaller chiplets on separate silicon wafers. In addition, semiconductor processes can be adapted to the specific type of chiplet being manufactured. With a single monolithic die, each die on the wafer is formed using the same manufacturing process. However, the high-cost process parameters of semiconductor manufacturers, which provide the fastest devices and smallest geometric dimensions beneficial for high-throughput circuit configurations on the die, may not be necessary for interface computing circuits. By using separate chiplets, designers can easily manufacture products in various performance categories by adding or removing chiplets for specific integrated circuits. In contrast, when using a single monolithic die, entirely new silicon wafers must be manufactured for different products. Dies 122A-122D (in Figure 1) and computing resource 630 or partition 610 (in Figure 6) can and are intended to be implemented as chiplets.

[0087] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions for implementing the method and / or mechanism are transported or stored on a computer-readable medium. Numerous types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (ROM, PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, computer-accessible storage media include any storage media that is accessible by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-Ray® discs. Examples of storage media include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (static RAM, SRAM), etc.), ROM, and flash memory, as well as non-volatile memory (e.g., flash memory) accessible via peripheral interfaces such as the Universal Serial Bus (USB) interface. Other examples of storage media include microelectromechanical systems (MEMS) and storage media accessible via communication media such as networks and / or wireless links.

[0088] Additionally, in various embodiments, program instructions include operational-level or register-transfer-level (RTL) descriptions of hardware functions in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII Stream Format (GDSII). In some cases, the descriptions are read by a synthesis tool that synthesizes the descriptions to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware, including the system. The netlist can then be arranged and routed to generate a dataset describing the geometric shapes applied to a mask. The mask can then be used in various semiconductor manufacturing processes to generate semiconductor circuits or circuits corresponding to the system. Alternatively, instructions on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, as needed. Additionally, instructions are used for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0089] Although the embodiments described above are explained in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. A plurality of calculation circuits, each of which includes a circuit configured to process a work block, Equipped with a circuit, The aforementioned circuit is Receiving one or more work blocks to be assigned to one or more of the aforementioned multiple calculation circuits, Determining the threshold number of idle calculation circuits that are allowed to be activated simultaneously, Assigning one or more of the above-mentioned work blocks to the idle calculation circuit in a number less than or equal to the threshold number, It is configured to do, Device.

2. The circuit is configured to determine a threshold number of idle calculation circuits that are permitted to be activated simultaneously, based on a comparison between the number of idle calculation circuits and the number of the plurality of calculation circuits. The apparatus according to claim 1.

3. The aforementioned circuit is This involves receiving an indicator of the number of computing circuits that have not yet started executing the previously assigned work block, Based at least in part on the aforementioned indicator, determine the threshold number of idle calculation circuits that are permitted to be activated simultaneously, It is configured to do, The apparatus according to claim 2.

4. The aforementioned circuit is To receive an indicator of the number of calculation circuits that have completed the execution of the work block, Based at least in part on the aforementioned indicator, determine the threshold number of idle calculation circuits that are permitted to be activated simultaneously, It is configured to do, The apparatus according to claim 2.

5. The circuit is configured to reduce the number of thresholds for idle calculation circuits that can be activated simultaneously in response to receiving an index of a non-zero voltage droop measurement. The apparatus according to claim 1.

6. The circuit is configured to compare the number of idle calculation circuits that can be activated simultaneously with the number of idle calculation circuits, depending on the expiration of the period from the most recent scheduling window. The apparatus according to claim 1.

7. Each of the aforementioned plurality of computing circuits is a single instruction multiple data (SIMD) circuit including multiple execution lanes, Each work block is a wavefront containing multiple work items. The apparatus according to claim 1.

8. The circuits of multiple calculation circuits process the work blocks, The scheduler circuit receives one or more work blocks to be assigned to one or more of the plurality of calculation circuits, The scheduler determines the threshold number of idle calculation circuits that are permitted to be activated simultaneously, The scheduler includes assigning one or more of the work blocks, in a number less than or equal to the threshold number, to the idle calculation circuit. method.

9. The scheduler includes determining a threshold number of idle calculation circuits that are permitted to be activated simultaneously, based on a comparison between the number of idle calculation circuits and the number of the plurality of calculation circuits. The method of claim 8.

10. The scheduler receives an indicator of the number of computing circuits that have not yet started executing a previously assigned work block, The scheduler includes determining, at least in part, the number of threshold idle calculation circuits that are permitted to be activated simultaneously, based on the indicator. The method of claim 9.

11. The scheduler receives an indicator of the number of calculation circuits that have completed the execution of the work block, The scheduler includes determining, at least in part, the number of threshold idle calculation circuits that are permitted to be activated simultaneously, based on the indicator. The method of claim 9.

12. The scheduler includes reducing the number of thresholds for idle calculation circuits that can be activated simultaneously in response to receiving an index of a non-zero voltage droop measurement. The method of claim 8.

13. The scheduler includes comparing the number of threshold idle calculation circuits that can be activated simultaneously with the number of idle calculation circuits, in accordance with the expiration of the period from the most recent scheduling window. The method of claim 8.

14. Each of the aforementioned plurality of computing circuits is a single instruction multiple data (SIMD) circuit including multiple execution lanes, Each work block is a wavefront containing multiple work items. The method of claim 8.

15. Processor and A plurality of chiplets, each of which includes one or more calculation circuits, each including a circuit configured to process a work block, A scheduler including a circuit, The aforementioned scheduler, Receiving one or more work blocks to be assigned to one or more calculation circuits of the aforementioned plurality of chiplets, Determining the threshold number of idle calculation circuits that are allowed to be activated simultaneously, Assigning one or more of the above-mentioned work blocks to the idle calculation circuit in a number less than or equal to the threshold number, It is configured to do the following: Computing system.

16. The scheduler is configured to determine a threshold number of idle calculation circuits that are permitted to be activated simultaneously, based on a comparison between the number of idle calculation circuits and the number of the plurality of chiplets. The computing system according to claim 15.

17. The aforementioned scheduler, This involves receiving an indicator of the number of computing circuits that have not yet started executing the previously assigned work block, Based at least in part on the aforementioned indicator, determine the threshold number of idle calculation circuits that are permitted to be activated simultaneously, It is configured to do the following: The computing system according to claim 16.

18. The aforementioned scheduler, To receive an indicator of the number of calculation circuits that have completed the execution of the work block, Based at least in part on the aforementioned indicator, determine the threshold number of idle calculation circuits that are permitted to be activated simultaneously, It is configured to do the following: The computing system according to claim 16.

19. The scheduler is configured to reduce the number of thresholds for idle calculation circuits that can be activated simultaneously in response to receiving an index of non-zero voltage droop measurements. The computing system according to claim 15.

20. The scheduler is configured to compare the number of idle calculation circuits that can be activated simultaneously with the number of idle calculation circuits, depending on the expiration of the period from the most recent scheduling window. The computing system according to claim 15.

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