Coated photonic integrated circuit (PIC) with output aperture

Abstract

A coated photonic integrated circuit (PIC) having output apertures is provided. The PIC comprises a PIC body, at least one input defined in the PIC body, one or more output sections defined in the exit side of the PIC body, and at least one waveguide defined in the PIC body, the at least one waveguide optically coupling at least one input section to each of the one or more output sections. A coating covers the outer surface of at least the exit side of the PIC body, and one or more apertures are formed through the coating. Each of the one or more apertures coincides with each of the one or more output sections. The coating is optically opaque or metallic.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the priority of U.S. Application No. 18 / 610,803, filed on Mar. 20, 2024, which claims the priority of U.S. Application No. 63 / 491,164, filed on Mar. 20, 2023, the contents of which are hereby incorporated by reference in their entirety.

[0002] Various embodiments relate to a PIC having etched and / or milled apertures respectively corresponding to one or more output portions of a photonic integrated circuit (PIC). Various embodiments relate to a PIC having etched and / or milled apertures respectively corresponding to one or more output portions of a PIC configured for quantum computing applications.

Background Art

[0003] In various systems, it is important that a laser beam and / or an optical beam can be delivered to a high - density one - dimensional or multi - dimensional array of locations with precise spacing and mode profile. In conventional PICs, a portion of the light provided to the PIC input may not be coupled into the guided mode, or the light may be scattered outside the guided mode as it passes through the PIC. Through applied effort, ingenuity, and innovation, many of the deficiencies of such conventional PICs have been solved by developing solutions configured according to embodiments of the present invention, and many examples thereof are described in detail herein.

Summary of the Invention

Means for Solving the Problems

[0004] An exemplary embodiment provides a coated PIC having one or more apertures, each formed via a coating corresponding to the respective output section of the PIC. The exemplary embodiment provides a method for manufacturing such a PIC, a system comprising such a PIC, and / or something similar. In the exemplary embodiment, the coated PIC, each having one or more output apertures, each corresponding to the respective output section of the PIC, is part of a beam delivery system for a quantum system, such as a quantum computer (e.g., a quantum charge-coupled device (QCCD) based quantum computer). In various embodiments, the PIC is coated with a metallic, optically opaque (with respect to the wavelength to which the waveguide of the PIC is configured to induce), and / or conductive coating.

[0005] According to one embodiment, a photonic integrated circuit (PIC) is provided. In an exemplary embodiment, the PIC comprises a PIC body, at least one input defined on one or more inlet sides of the PIC body, one or more output defined on one or more outlet sides of the PIC body, and at least one waveguide defined in the PIC body, the at least one waveguide optically coupling at least one input to each of the one or more output. The PIC further includes a coating covering the outer surface of at least one or more outlet sides of the PIC body. One or more openings are formed through the coating. Each of the one or more openings coincides with each of the one or more output. The coating is optically opaque or metallic.

[0006] In an exemplary embodiment, the coating further covers the outer surface of at least one side of the PIC body.

[0007] In an exemplary embodiment, the coating further covers the outer surface of at least one of the one or more inlet sides.

[0008] In an exemplary embodiment, the coating extends outward from the outer surface of the PIC body by a thickness ranging from 15 nm to 1 μm.

[0009] In an exemplary embodiment, at least one of one or more openings is etched or milled into the PIC body to form a first side wall, a second side wall, and a rear wall, and each output unit is positioned on the rear wall of at least one opening.

[0010] In an exemplary embodiment, each of one or more openings is etched or milled into the PIC body to form its respective side wall and rear wall, and each output unit is positioned on the respective rear wall of each opening.

[0011] In an exemplary embodiment, the sidewall angle between each sidewall and each rearwall of each etched and / or milled opening and the normal to each rearwall is in the range of -10 to 10 degrees.

[0012] In an exemplary embodiment, the length of each side wall in a direction substantially parallel to the radiation direction of one or more output units is configured to prevent the generation of diffraction patterns in the light emitted through one or more output units.

[0013] In an exemplary embodiment, the distance between the opposing side walls of each aperture is greater than the predicted mode field diameter of the light beam configured to be emitted and / or output by each output section.

[0014] In an exemplary embodiment, the PIC further includes one or more alignment feature portions formed on or within the PIC body and detectable through coding.

[0015] In an exemplary embodiment, the PIC body comprises one or more claddings surrounding at least one waveguide in a direction perpendicular to the radiation direction of at least one waveguide.

[0016] In an exemplary embodiment, at least one of the one or more output units includes a signal manipulation element.

[0017] In exemplary embodiments, one or more output units include a first output unit and a second output unit, the first waveguide is optically coupled to the first output unit, the second waveguide is optically coupled to the second output unit, and the PIC further includes a grooved baffle disposed in at least one of (a) between the first output unit and the second output unit, or (b) between at least a portion of the first waveguide and at least a portion of the second waveguide.

[0018] In another embodiment, a method for manufacturing a PIC is provided. In an exemplary embodiment, the method includes the steps of forming a PIC body including at least one input section, at least one output section, and at least one waveguide optically coupling the at least one input section to each output section of one or more output sections; depositing a coating (conformally) on the outer surface of one or more exit sides of the PIC body; and forming one or more openings through the coating. Each opening of the one or more openings coincides with each output section of one or more output sections. The coating is optically opaque or metallic.

[0019] In exemplary embodiments, one or more openings are formed by etching or milling.

[0020] In exemplary embodiments, one or more openings are formed using lithographic etching, a lift-off process, or shadow masking.

[0021] In an exemplary embodiment, one or more openings are formed using a focused ion beam (FIB).

[0022] In an exemplary embodiment, the coating further covers the outer surface of at least one side of the PIC body.

[0023] In an exemplary embodiment, at least one of the one or more openings is etched into the PIC body to form respective first sidewalls, respective second sidewalls, and respective rear walls, and each output portion is disposed on the respective rear wall of at least one opening.

[0024] In an exemplary embodiment, the coating extends outwardly from the outer surface of the PIC body by a thickness within the range of 15 nm to 1 μm.

[0025] In an exemplary embodiment, the coating is deposited on the outer surface using at least one of (a) sputter deposition, (b) atomic layer deposition (ALD), or (c) vapor deposition.

[0026] In an exemplary embodiment, the method further includes forming one or more alignment features on or within the PIC body before depositing the coating, and the one or more alignment features are detectable after the coating is deposited on the outer surface.

[0027] In an exemplary embodiment, at least one of the one or more alignment features is used in aligning the PIC body for etching the PIC body to form one or more etched and / or milled openings.

[0028] In an exemplary embodiment, the method further includes applying an adhesion layer to the outer surface before depositing the coating on the outer surface.

[0029] In an exemplary embodiment, the method further includes etching a groove configured to provide a groove baffle (e.g., when a coating is deposited thereon) before depositing a coating on an outer surface.

[0030] In an exemplary embodiment, at least one of the one or more output portions includes a signal manipulation element.

[0031] In an exemplary embodiment, the one or more output portions include a first output portion and a second output portion, a first waveguide is optically coupled to the first output portion, a second waveguide is optically coupled to the second output portion, and the PIC further includes a groove baffle disposed at least one of (a) between the first output portion and the second output portion or (b) between at least a portion of the first waveguide and at least a portion of the second waveguide.

[0032] According to another aspect, a quantum system is provided. In an exemplary embodiment, the quantum system includes a confinement device, one or more operation sources, and at least one beam delivery system configured to provide operation signals generated by the one or more operation sources to respective locations at least partially defined by the confinement device. The beam delivery system includes a PIC including a PIC body, at least one input portion defined at one or more input surfaces of the PIC body, one or more output portions defined in the PIC body, and at least one waveguide defined in the PIC body, the at least one waveguide optically coupling the at least one input portion to each of the one or more output portions. The PIC further includes a coating covering an outer surface of at least one or more exit side portions of the PIC body. One or more openings are formed through the coating. Each of the one or more openings coincides with each of the one or more output portions. The coating is optically opaque or metallic.

[0033] In an exemplary embodiment, the coating further covers the outer surface of at least one side of the PIC body.

[0034] In an exemplary embodiment, the coating further covers at least one outer surface of one or more inlet sides of the PIC body.

[0035] In an exemplary embodiment, the coating extends outward from the outer surface of the PIC body by a thickness ranging from 15 nm to 1 μm.

[0036] In an exemplary embodiment, at least one of one or more openings is etched or milled into the PIC body to form a first side wall, a second side wall, and a rear wall, and each output unit is positioned on the rear wall of at least one opening.

[0037] In an exemplary embodiment, each of one or more openings is etched or milled into the PIC body to form its respective side wall and rear wall, and each output unit is positioned on the respective rear wall of each opening.

[0038] In an exemplary embodiment, the sidewall angle between each sidewall and each rearwall of each etched and / or milled opening and the normal to each rearwall is in the range of -10 to 10 degrees.

[0039] In an exemplary embodiment, the length of each side wall in a direction substantially parallel to the radiation direction of one or more output units is configured to prevent the generation of diffraction patterns in the light emitted through one or more output units.

[0040] In exemplary embodiments, the distance between the opposing side walls of each etched and / or milled aperture is greater than the predicted mode field diameter of the light beam configured to be emitted and / or output by each output section.

[0041] In an exemplary embodiment, the PIC further includes one or more alignment feature portions formed on or within the PIC body and detectable through coding.

[0042] In an exemplary embodiment, the PIC body comprises one or more claddings surrounding at least one waveguide in a direction perpendicular to the radiation direction of at least one waveguide.

[0043] In an exemplary embodiment, at least one of the one or more output units includes a signal manipulation element.

[0044] In exemplary embodiments, one or more output units include a first output unit and a second output unit, the first waveguide is optically coupled to the first output unit, the second waveguide is optically coupled to the second output unit, and the PIC further includes a grooved baffle disposed in at least one of (a) between the first output unit and the second output unit, or (b) between at least a portion of the first waveguide and at least a portion of the second waveguide.

[0045] In an exemplary embodiment, the PIC is formed on a substrate that houses the confinement device.

[0046] In an exemplary embodiment, the PIC is formed on a substrate configured to be fixed to a substrate housing a containment device, or to be packaged together with the substrate housing the containment device.

[0047] Since the present invention has been described using general terminology, please refer to the attached drawings, which are not necessarily drawn to scale. [Brief explanation of the drawing]

[0048] [Figure 1A] This is a schematic diagram of an exemplary QCCD-based quantum computer system including a PIC, according to an exemplary embodiment. [Figure 1B] This is a schematic diagram of another exemplary QCCD-based quantum computer system including a PIC, according to an exemplary embodiment. [Figure 2] This is an exemplary top view of a PIC microcontroller according to an exemplary embodiment. [Figure 3] This is a cross-sectional view of the PIC shown in Figure 2 along line AA, according to an exemplary embodiment. [Figure 3A] This is a cross-sectional view of an exemplary PIC according to an exemplary embodiment. [Figure 4] Figure 2 is a view of the exit side of the PIC according to an exemplary embodiment. [Figure 5] Figure 2 is a perspective view of the PIC shown in an exemplary embodiment. [Figure 6] This is an enlarged perspective view of the portion of the PIC between two adjacent etched and / or milled apertures, according to an exemplary embodiment. [Figure 7A] This is a cross-sectional view of another exemplary PIC according to an exemplary embodiment. [Figure 7B] Figure 7A is an exemplary top view of a PIC microcontroller. [Figure 8A] This is an exit diagram of another exemplary PIC according to an exemplary embodiment. [Figure 8B] Figure 8A is an exemplary top view of a PIC microcontroller. [Figure 9] This flowchart shows a process, procedure, operation, and / or similar for manufacturing a PIC according to an exemplary embodiment. [Figure 10] This is a schematic diagram of an exemplary controller that may be used according to an exemplary embodiment. [Figure 11] This is a schematic diagram of an exemplary computing entity that may be used according to an exemplary embodiment. [Modes for carrying out the invention]

[0049] The present invention is described more fully below with reference to the accompanying drawings, which show some, but not all, embodiments of the invention. In fact, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described herein, but rather these embodiments are provided to satisfy the legal requirements to which this disclosure is applicable. In this specification, the terms “or” (also written as “ / ”) are used in both an alternative and a conjunctive sense unless otherwise indicated. The terms “exemplary” and “symbolic” are used as examples and do not indicate a level of quality. The terms “generally” and “approximately” refer, unless otherwise indicated, to the limits of engineering and / or manufacture, and / or the user’s ability to measure. Throughout, similar numbers indicate similar elements.

[0050] As described above, in various systems such as atomic systems or quantum systems, it is important to be able to deliver one or more laser beams to locations in a one-dimensional or multi-dimensional array of locations with respect to position, spacing, mode profile, polarization, frequency, and / or phase. For example, in atomic systems such as atomic clocks, Bose-Einstein condensate systems, trapped ion systems, QCCD-based quantum computers, and / or other atomic and / or quantum systems, high-precision and accurate laser beam delivery is important for various applications of the system, for operating the system, and / or similar.

[0051] In conventional PICs, some of the light supplied to the PIC input may not be coupled to the waveguide mode, or it may be scattered outside the waveguide mode as it passes through the PIC. For example, some of the light supplied to the PIC input may not be coupled to the waveguide via the input. In another example, some of the light propagating through the waveguide of the PIC may be scattered by the roughness of the waveguide edges. Some of the uncoupled and / or scattered light may propagate outside through the exit side of the PIC. This uncoupled light may cause optical crosstalk between the various outputs of the PIC. For example, the uncoupled and / or scattered light may interfere with the array of laser beams and / or optical beams supplied through the output of the PIC, resulting in increased scattering of light outside the array of laser beams and / or optical beams. For example, in some applications, it is desirable to have 60-70 dB of extinction between adjacent laser beams and / or optical beams output by the PIC. However, conventional PICs achieve approximately 50 dB of extinction between adjacent laser beams and / or optical beams output by the PIC. Therefore, there are technical issues regarding controlling, preventing, and / or eliminating uncoupled and / or scattered light from the PIC's output.

[0052] Various embodiments provide technical solutions to these technical problems. For example, in various embodiments, one or more output sections of the PIC are located within and / or corresponding to etched and / or milled apertures formed in the PIC body. In various embodiments, a metallic or optically opaque coating (with respect to the wavelength to which the waveguide of the PIC is configured to induce) is deposited, coated, and / or disposed on the outer surface of the PIC body. The etched and / or milled apertures extend through the coating to the PIC body to provide optical apertures through the coating. The coating prevents light from escaping from the exit side of the PIC between the etched and / or milled apertures. The geometric shape of the etched and / or milled apertures prevents light traveling in directions perpendicular and / or substantially non-parallel to the radiation direction of each output section of the PIC from being blocked or attenuated. Thus, light traveling in directions perpendicular and / or substantially non-parallel to the radiation direction of each output section of the PIC is prevented from reaching the image plane of each output section. As a result, extinction between adjacent laser beams and / or optical beams output by the PIC can reach over 60 dB, and the optical crosstalk of the PIC is substantially reduced.

[0053] Exemplary quantum computing system Various embodiments of PICs can be used in a wide range of applications, including atomic and quantum systems. For example, some embodiments provide a QCCD-based quantum computer comprising one or more PICs having a coating and etched and / or milled apertures formed through at least each coating.

[0054] Figure 1A provides a schematic diagram of an exemplary QCCD-based quantum computer system 100 according to an exemplary embodiment. The QCCD-based quantum computer system includes a PIC 500 located outside or adjacent to the low-temperature and / or vacuum chamber 40. Figure 1B provides a schematic diagram of an exemplary QCCD-based quantum computer system 100' according to another exemplary embodiment. The QCCD-based quantum computer system includes a PIC 500 located inside and / or adjacent to the low-temperature and / or vacuum chamber 40. Embodiments of a quantum computing system are envisioned that include one or more PIC 500s located outside and / or adjacent to the low-temperature and / or vacuum chamber 40, and one or more PIC 500s located inside and / or adjacent to the low-temperature and / or vacuum chamber 40. Furthermore, in an exemplary embodiment, the PIC 500 is formed on a substrate housing the confinement device 50. In another exemplary embodiment, the PIC 500 is formed on a substrate configured to be fixed to the substrate housing the confinement device 50, or to be packaged together with the substrate housing the confinement device 50.

[0055] In various embodiments, the quantum computer systems 100, 100' comprise a computing entity 10 and quantum computers 110, 110'. In various embodiments, the controller 30 of the quantum computer 110 may communicate with the computing entity 10 via one or more wired and / or wireless networks 20. In various embodiments, the quantum computers 110, 110' comprise the controller 30, a cryogenic and / or vacuum chamber 40 housing a confinement device 50 (e.g., an ion trap and / or similar), one or more manipulators 70 (e.g., one or more laser systems), one or more beam delivery systems 68 configured to deliver manipulator signals generated by the manipulators 70 to locations at least partially defined by the confinement device 50, and / or similar. In various embodiments, the confinement device 50 is a confinement device configured to confine one or more atoms, ions, molecules, quantum particles, and / or similar, and the manipulators are configured to provide manipulator signals to one or more parts of the confinement device 50 via optical paths defined by the beam delivery systems 68. In various embodiments, the operation signal may be used to initialize one or more objects (e.g., atoms, ions, molecules, quantum particles, and / or similar) into qubit space, perform a cooling operation, perform a measurement operation, provide one or more gate signals, and / or similar. In various embodiments, the operation source 70 comprises one or more laser systems configured to provide one or more operation signals (e.g., laser beams and / or laser pulses and / or optical beams and / or optical pulses) to one or more locations at least partially defined by the confinement device 50 in order to perform one or more quantum gates (e.g., quantum logic gates) or other quantum operations. In various embodiments, the quantum gates may be one-qubit gates, two-qubit gates, and / or similar.In various embodiments, one or more gate signals may be provided via a beam delivery system 68, which may include one or more PICs 500, to one or more locations at least partially defined by the confinement device 50.

[0056] In various embodiments, the computing entity 10 is configured to allow a user to provide input to a quantum computer system 100, 100' (for example, through the user interface of the computing entity 10) and to receive, display, and / or similar output from the quantum computer systems 100, 100'. The computing entity 10 may communicate with a controller 30 via one or more wired or wireless networks 20. For example, the computing entity 10 may be configured to provide a quantum circuit to the controller 30 for execution by the quantum computer 110, 110', and the controller 30 may provide the computing entity 10 with the results of executing one or more quantum circuits.

[0057] In various embodiments, the controller 30 is configured to control the confinement device 50, a cooling and / or vacuum system (not shown) that controls the temperature and pressure within the cryogenic and / or vacuum chamber 40, an operating source 70, and / or other components of the quantum computers 110, 110' (e.g., an optical collection system configured to "read" the output of the quantum computers). In various embodiments, the controller 30 is configured to control various components of the quantum computers 110, 110' according to executable instructions, command sets, and / or similar provided by the computing entity 10 and / or generated by the controller 30. In various embodiments, the controller 30 is configured to receive output from the quantum computers 110, 110' (e.g., from the optical collection system) and provide the output and / or the results of processing the output to the computing entity 10.

[0058] Coated PIC with exemplary output aperture Figures 2, 3, 4, 5, and 6 provide various diagrams of an exemplary PIC500 having a coating 540 with one or more etched and / or milled openings 556 (e.g., 556A, 556B) formed through at least one coating. In the illustrated embodiment, the outer surface 526 of the PIC body 520 is coated with conformal coating 540.

[0059] In various embodiments, the PIC 500 comprises a PIC body 520. In various embodiments, the PIC body 520 may be formed on and / or from a substrate. The PIC body 520 includes an inlet side 502 and an outlet side 504. One or more input sections 510 (e.g., 510A, 510B) are located in the inlet side 502. One or more output sections 550 (e.g., 550A, 550B) are located in the outlet side 504. One or more waveguides 530 (e.g., 530A, 530B) optically couple one or more input sections 510 to the respective output sections of one or more output sections 550. In various embodiments, at least one of the one or more output sections 550 includes a signal manipulation element. In various embodiments, the signal manipulation element is a grating (e.g., a grating coupler), a metasurface, a diffractive optical element (DOE), or other optical element configured to influence one or more optical properties (e.g., wavelength / frequency, polarization, phase delay, propagation direction, focal position, and / or similar) of the light beam emitted and / or output by the output unit 550.

[0060] In exemplary embodiments, the input section 510 may be located on two or more sides of the PIC body 520. For example, in some embodiments, the PIC body 520 includes two or more inlet sides. In exemplary embodiments, the output section 550 may be located on two or more sides of the PIC body 520. For example, in some embodiments, the PIC body 520 includes two or more outlet sides.

[0061] In various embodiments, the input unit 510 is configured to couple a laser beam and / or laser pulse and / or optical beam and / or optical pulse to the respective waveguide 530. For example, the laser beam and / or laser pulse and / or optical beam and / or optical pulse may be generated by the operating source 70 and supplied to the respective input unit 510 via optical fiber, bulk optics, waveguide, and / or similar. The input unit 510 couples the laser beam and / or laser pulse and / or optical beam and / or optical pulse to the respective waveguide 530.

[0062] In various embodiments, the waveguide 530 is formed within the PIC body 520. For example, in various embodiments, it includes a first cladding 522 (e.g., bottom oxide) and a second cladding 524 (e.g., top oxide). In exemplary embodiments, the waveguide 530 is sandwiched between the first cladding 522 and the second cladding 524. For example, the first cladding 522 and the second cladding 524 surround the waveguide 530 in a direction perpendicular to the propagation direction of the laser beam and / or laser pulse and / or optical beam and / or optical pulse passing through the respective waveguide 530. In various embodiments, the PIC body 520, the first cladding 522, and / or the second cladding 524 are made from and / or include glass, one or more oxides (e.g., SiO2, SiO2TEOS), dielectric material, air / vacuum, and / or similar materials. In various embodiments, the waveguide is formed from the waveguide material 534. For example, the waveguide material 534 may be a laser-treated portion of the PIC body 520 and / or another material that is deposited or formed on the second cladding 524 to form the waveguide 530, and then shaped (using photolithography, mask etching, and / or similar) before the first cladding 522 is deposited or formed on the second cladding 524 or waveguide 530. In various embodiments, the waveguide material 534 includes one or more of SiN, Si, Al2O3, TiO2, and / or other waveguide materials. In various embodiments, the first cladding 522 and / or the second cladding 524 have a thickness in the range of 1 μm to 100 μm. In various embodiments, the first cladding 522 and / or the second cladding 524 have a thickness in the range of 1 μm to 50 μm. In an exemplary embodiment, the first cladding 522 is thicker than the second cladding 524. For example, the first cladding may be the substrate on which the PIC is formed in an exemplary embodiment.

[0063] In various embodiments, the waveguide 530 includes and / or is optically coupled to one or more optical elements 532 (e.g., 532A, 532B). In various embodiments, one or more optical elements 532 include beam splitters, beam couplers, modulators, filters, diffractive optical components, amplifiers, and / or similar. For example, one or more optical elements 532 corresponding to and / or coupled to the waveguide 530 are configured to adjust laser beams and / or laser pulses and / or optical beams and / or optical pulses as they propagate along the waveguide 530 from their respective inputs 510 to their respective outputs 550.

[0064] In various embodiments, the coating 540 is arranged and / or deposited on the outer surface 526 of the PIC body 520. In various embodiments, the coating 540 is optically opaque (at the wavelengths to which the waveguide 530 is configured to guide) and / or is a metallic coating. For example, the coating may be made from titanium nitride (TiN), gold, aluminum, and / or other materials, metals, and / or alloys that are conductive under the operating conditions of the PIC 500 and / or optically opaque to the wavelengths to which the waveguide 530 is configured to guide. For example, the coating 540 of a PIC 500 configured to operate in a low-temperature and / or vacuum chamber 40 may differ from the coating of a PIC configured to operate outside the low-temperature and / or vacuum chamber 40, considering the different temperatures and / or pressures of the respective operating conditions.

[0065] In various embodiments, the coating 540 is a conformal coating applied and / or deposited on the outer surface 526 of the PIC body 520 after the formation of the waveguide 530 and any optical elements 532 of the PIC 500, and before etching of the etched and / or milled apertures 556. In various embodiments, the PIC body 520 is encased and / or sealed within the coating 540 except for the input section 510. In an exemplary embodiment, the coating 540 is applied only to the exit side 504 of the PIC body 520. In an exemplary embodiment, the coating 540 is applied to the outer surface 526 of the exit side 504 of the PIC body 520 and to the outer surface 526 of one or more sides 506 of the PIC body 520 (e.g., 506A, 506B, 506C, 506D). As used herein, a side 506 of the PIC body 520 is any side of the PIC body other than the inlet side 502 and the exit side 504. In various embodiments, the coating 540 is applied to the outer surface of one or more inlet side portions 502. The coating 540 is etched and / or milled to form etched and / or milled openings 556 through the coating 540. In exemplary embodiments, the etched and / or milled openings 556 correspond to and / or optically align with an input portion 510 or an output portion 550.

[0066] In various embodiments, the coating 540 acts to block, absorb, reflect, and / or attenuate light within the PIC body 520 that is not coupled to the waveguide 530 or that has been scattered from the waveguide 530 to the outside. For example, the coating 540 may block, absorb, reflect, and / or attenuate any light that is attempting to leave the PIC body 520 and is not part of the waveguide modes of the laser beam and / or laser pulses propagating in the radiation direction 1 of each output section, as well as the optical beam and / or optical pulses. In an exemplary embodiment, the coating 540 extends from the outer surface of the PIC body 520 by a thickness that is at least one absorption depth of light of wavelengths for which the waveguide 530 is designed to guide within the material of the coating 540. In an exemplary embodiment, the coating 540 extends from the outer surface of the PIC body 520 by a thickness ranging from 15 nm to 1 μm.

[0067] The PIC500 further comprises one or more etched and / or milled openings 556 that are etched through at least the coating 540 and optionally down to the PIC body 520. For example, each etched and / or milled opening 556 is etched through at least the coating 540 and optionally down to the PIC body 520 to form a first side wall 553 (e.g., 553A, 553B), a second side wall 554 (e.g., 554A, 554B), and a rear wall 552 (e.g., 552A, 552B). The first side wall 553 and the second side wall 554 extend from the opposing edge of the rear wall 552 (e.g., in the radial direction 1 of the output section 550 corresponding to the etched and / or milled opening 556). The output section 550, corresponding to the etched and / or milled opening 556, is located on the rear wall 552 of the etched and / or milled opening 556. In an exemplary embodiment, the etched and / or milled opening 556 corresponds to the input section 510, which is located on the rear wall 552 of the etched and / or milled opening 556.

[0068] In various embodiments, the etched and / or milled aperture 556 is a conformal aperture. For example, in various embodiments, the etched and / or milled aperture 556 is concentric with respect to the output section 550 of the waveguide 530. In exemplary embodiments, the etched and / or milled aperture is in contact with the PIC structure (e.g., waveguide 530, and / or similar).

[0069] In various embodiments, the width w of the etched and / or milled aperture 556 is defined in a direction parallel (at least locally) to the length of the exit side 504 of the PIC500 (y-direction shown in Figures 2 and 4) and laterally and / or perpendicular to the radiation direction 1 of the output section 550 (x-direction shown in Figures 2 and 4). In various embodiments, the total length s of the etched and / or milled aperture 556 is defined in a direction parallel (at least locally) to the height of the exit side 504 of the PIC500 (z-direction shown in Figure 4) and laterally and / or perpendicular to the radiation direction 1 of the output section 550 (x-direction shown in Figure 2). As should be understood, the radiation direction 1 of the output section 550 is the direction in which the laser beam and / or laser pulse and / or optical beam and / or optical pulse propagate as they exit the output section 550. Thus, the width w is the distance between two opposite or opposing side walls of the aperture, and the total length s is the distance between two different opposite or opposing side walls of the aperture. For example, the width w is measured across the opening 556 in a first direction, and the total length s is measured across the opening 556 in a second direction that is approximately perpendicular to the first direction.

[0070] In exemplary embodiments, the width w of the etched and / or milled aperture 556 is the width of the back wall 552. In various embodiments, the width w and / or total length s of the etched and / or milled aperture 556 is greater than the predicted mode field diameter of the laser beam and / or laser pulse and / or optical beam and / or optical pulse exiting the respective output section. For example, the mode field diameter (MFD) of a laser beam and / or laser pulse and / or optical beam and / or optical pulse defines the surface through which 90% of the power of the laser beam and / or laser pulse and / or optical beam and / or optical pulse passes when it exits the output section 550. In various embodiments, the width w and / or total length s is greater than the MFD but less than twice the MFD. In various embodiments, the width w and / or total length s is greater than the MFD but less than 1.5 times the MFD. In various embodiments, the width w and / or total length s is in the range of 5 μm to 40 μm (including 5 μm and 40 μm). In various embodiments, the width w and / or total length s is in the range of 15 μm to 30 μm (including 15 μm and 30 μm).

[0071] In exemplary embodiments, the MFD defines a lower limit to the range in which w can be selected. In exemplary embodiments, the upper limit to the range in which width w and / or total length s can be selected is determined by determining the desired and / or maximum allowable spot size of the laser beam and / or laser pulse and / or optical beam and / or optical pulse on the image plane (e.g., at each location at least partially defined by the confinement device 50), and then tracing that spot size backward through the portion of the beam delivery system positioned between the output unit 550 of the PIC500 and the image plane (e.g., at each location). The MFD in the output unit 550 can be determined by tracing the change in spot size backward from the image plane through any magnification, focusing, and / or defocusing effects of any optical elements of the beam delivery system 68 positioned between the output unit 550 of the PIC500 and the image plane. In various embodiments, the MFD in the output unit 550 defines a lower limit to the range in which width w can be selected.

[0072] In various embodiments, the length l of the etched and / or milled opening 556 is defined in a direction parallel to the radial direction 1 of the output section 550. In exemplary embodiments, the length l is such that the etched and / or milled opening 556 extends only through the coating 540 (for example, the PIC body 520 itself is not etched and / or milled). In exemplary embodiments, the length l is such that the etched and / or milled opening 556 extends within the PIC body 520. For example, in various embodiments, the length l is determined, designed, and / or configured to be greater than or equal to the thickness of the coating 540.

[0073] In various embodiments, the length l is determined, designed, and / or configured based on the requirements of the mechanical process used to form the etched and / or milled opening 556. For example, the length l is determined, designed, and / or configured to be greater than the dicing chip-out score (e.g., about 1 to 100 μm) and / or the polishing score (e.g., 0.1 to 1 μm).

[0074] In various embodiments, the length l is determined, designed, and / or configured based on the facet angle of the exit side 504 of the PIC body before the formation of the etched and / or milled opening, and how much material needs to be removed (e.g., from the PIC body 520) to correct the facet angle. As used herein, the facet angle is the angle between a plane perpendicular to the radiation direction 1 of the waveguide and the plane defined by the exit side 504 of the PIC body 520. In exemplary embodiments, the facet angle φ is selected to prevent Fresnel reflection. In exemplary embodiments, the facet angle φ is selected to deliver the beam and / or pulse to an inclined viewport. In various embodiments, the facet angle φ is in the range of -10 to 10 degrees (including -10 and 10 degrees), but angles outside that range may also be used depending on the application. In various embodiments, the facet angle φ is in the range of -1 to 1 degree (including -1 and 1 degrees). In exemplary embodiments, the facet angle φ is in the range of -0.5 degrees to 0.5 degrees (including -0.5 degrees and 0.5 degrees). In various embodiments, etching and / or milling of the opening 556 is performed to provide a desired facet angle φ.

[0075] In various embodiments, length l is determined, designed, and / or configured to prevent the formation of diffraction patterns due to the interaction of the laser beam and / or laser pulse and / or optical beam and / or optical pulse emanating from the output unit 550 with the side walls 553, 554. In various embodiments, length l is determined, designed, and / or configured to absorb, block, reflect, and / or attenuate light emanating from the PIC 500 (e.g., via the first side wall 553, the second side wall 554, the back wall 552, and the output unit 550) that is not propagating in a direction parallel to the radiation direction 1. For example, length l may be determined, designed, and / or configured to prevent at least a portion of the light emanating from the PIC 500 propagating transversely to the radiation direction 1 to the etched and / or milled aperture 556 from emanating from the etched and / or milled aperture 556 toward the confinement device 50. For example, in an exemplary embodiment, at least a portion of the light that propagates transversely to the radiation direction 1 and exits the aperture 556 etched and / or milled from the PIC 500 is absorbed by the PIC body 520 and / or coating 540 and exits the aperture. In various embodiments, the length l is in the range of 1 μm to 20 μm (including 1 μm and 20 μm). In an exemplary embodiment, the length l is in the range of 1 μm to 5 μm (including 1 μm and 5 μm).

[0076] Figure 6 provides an enlarged view of a portion of the etched and / or milled opening 556, including a portion of the first side wall 553B. In the illustrated embodiment, the first side wall 553B is not perpendicular to the rear wall 552B. For example, a side wall angle θ is formed between the first side wall 553B and the normal 558 to the rear wall 552B. In various embodiments, the second side wall 554B forms a side wall angle θ equivalent to the respective normal 558 to the rear wall 552B. For example, the distance between the first side wall 553B and the second side wall 554B may increase as the distance from the rear wall 552B increases in the radial direction 1. In various embodiments, the side wall angle θ is in the range of -10 degrees to 10 degrees (including -10 degrees and 10 degrees), but angles outside this range may also be used depending on the application. In various embodiments, the side wall angle θ is in the range of -1 degree to 1 degree (including -1 degrees and 1 degree). In an exemplary embodiment, the side wall angle θ is within the range of -0.5 degrees to 0.5 degrees (including -0.5 degrees and 0.5 degrees).

[0077] In various embodiments, as shown in Figure 6, the edges of the side walls 553, 554 are rounded and / or chamfered as a result of redeposition of material from the etching and / or milling process. In various embodiments, the width w of the opening 556 is determined and / or selected considering the redeposition of the opening onto the side walls 553, 554.

[0078] In various embodiments, the etched and / or milled apertures 556 are positioned based on the location of each output unit 550 of the PIC500. As should be understood, the location of the output unit of the PIC500 is determined based on a location at least partially defined by a confinement device 50 configured to provide the respective laser beam and / or laser pulse and / or optical beam and / or optical pulse, and any element of a beam delivery system 68 positioned between the location at least partially defined by the confinement device 50 configured to provide the respective laser beam and / or laser pulse and / or optical beam and / or optical pulse and the output unit. In various embodiments, the location of the etched and / or milled apertures 556 is defined by a lithography process that defines each output unit 550 of the PIC500.

[0079] In an exemplary embodiment, an adhesion layer 545 is placed between the PIC body 520 and the coating 540. For example, if the material of the coating 540 does not naturally adhere to the material of the PIC body 520, the adhesion layer 545 may be applied and / or placed on the PIC body 520, and then the coating 540 may be applied and / or placed on top of it. For example, the adhesion layer 545 comprises a thin layer (e.g., thinner than the coating 540) of a material that naturally adheres to both the material of the PIC body 520 and the material of the coating 540. For example, in an exemplary embodiment in which the PIC body 520 comprises glass (e.g., SiO2) formed on a Si substrate and the coating 540 comprises gold, an adhesion layer 545 comprising titanium, chromium, aluminum, or another metal that adheres to glass may be used to improve the adhesion of the coating 540 to the PIC body 520.

[0080] In various embodiments, the PIC500 comprises one or more alignment feature portions 560. For example, the alignment feature portion 560 is formed on the PIC body 520 before the deposition of the coating 540 on the PIC body 520. The coating 540 is a conformal coating, and the alignment feature portion 560 is sized to be detectable after the coating 540 has been applied and / or deposited on the PIC body 520. In various embodiments, the alignment feature portion 560 is configured for use in aligning the PIC500 for etching of etched and / or milled openings 556, for use in atomic systems, quantum systems, or other systems (e.g., quantum computing systems 100, 100'), for use in a test environment, and / or similar purposes.

[0081] In various embodiments, the PIC500 includes one or more etching arrangement feature sections 562. In various embodiments, the etching arrangement feature section 562 may be an alignment feature section of one or more alignment feature sections 560. In various embodiments, the etching arrangement feature section 562 is configured to guide the etching of at least a portion of the etched and / or milled opening 556. For example, the etching arrangement feature section 562 may be used as an etching guide when performing etching to generate, form, and / or define the side walls 553, 554 of the etched and / or milled opening 556.

[0082] In various embodiments, the alignment feature area 560 and / or the etching placement feature area 562 are topographic features such as an upward step, downward step, ridge, multidimensional groove or multidimensional ridge (e.g., a plus sign or X as shown in Figures 2 and 5), and / or similar. In various embodiments, the alignment feature area and / or the etching placement feature area 562 have a height, depth, and / or thickness in the range of 100 nm to 1 μm (relative to the outer surface 526 of the PIC body 520). For example, the height, depth, and / or thickness of the alignment feature area 560 and / or the etching placement feature area 562 are configured to ensure that the alignment feature area 560 and / or the etching placement feature area 562 are detectable after the coating 540 has been applied and / or placed on the PIC body 520.

[0083] In various embodiments, PIC500' is parallel to and / or not perpendicular to the propagation direction of waveguide 530. For example, Figure 3A shows a cross-sectional view of PIC500' similar to PIC500 shown in Figure 3. PIC500' includes a third optical element 532C, which is a coupler (e.g., a lattice coupler) that couples light exiting the waveguide so that the light propagates in the radiation direction 1'. For example, the coupler guides light propagating through waveguide 530 to the coupler (third optical element 532C) to the outside of waveguide 530 in the radiation direction 1' so that the light exits PIC500' through output section 550. For example, the light coupled from waveguide 530 by the coupler (optical element 532C) propagates (e.g., in free modes) through a portion of the cladding 522, through the back wall 552, and exits through the opening 556 of output section 550.

[0084] In various embodiments, the width w (measured in the x-direction in Figure 3A) and the total length s (measured in the y-direction in Figure 3A) of the etched and / or milled aperture 556 are, respectively, greater than the predicted mode field diameter of the laser beam and / or laser pulse and / or optical beam and / or optical pulse exiting the respective output unit 550. For example, in an exemplary embodiment, any dimension or distance between opposing side walls (e.g., 553, 554) of the aperture 556 is greater than the predicted mode field diameter of the laser beam and / or laser pulse and / or optical beam and / or optical pulse exiting the respective output unit 550.

[0085] In various embodiments, the PIC500 may include output sections at two or more exit sides. For example, the cross-sectional view of the PIC500 shown in Figure 3 and the cross-sectional view of the PIC500' shown in Figure 3A may be cross-sectional views of the same PIC taken at different positions in the y-direction of the PIC.

[0086] In various embodiments, the PIC500, 500' includes one or more grooved baffles 570, as shown in Figures 7A, 7B, 8A, and 8B. For example, Figures 7A and 7B show an exemplary PIC500' that includes a grooved baffle 570 positioned between adjacent output sections 550A, 550B and having an exit side 504 that is parallel to and / or not perpendicular to the propagation direction of the waveguide 530. For example, a portion of the waveguide layer may be divided into two waveguides 530A, 530B through a first cladding 522, for example, by grooves 575 etched at least partially through the waveguide layer. The edges of the grooves 575 (e.g., the bottom and sidewalls) are coated with a coating 540 to form a grooved baffle 570 that prevents light from the first waveguide 530A from interacting with light from the second waveguide 530B within the PIC500'. For example, the groove baffle 570 prevents crosstalk between the optical channel corresponding to and / or containing waveguide 530A and the optical channel corresponding to and / or containing waveguide 530B.

[0087] In the illustrated embodiment, optical element 532D is optically coupled to the first waveguide 530A, and another optical element 532E is optically coupled to the second waveguide 530B. In various embodiments, the optical elements 532D and 532E are couplers (e.g., lattice couplers) configured to couple the light emanating from each waveguide 530A and 530B so that the light propagates in their respective radiation directions 1A and 1B. For example, the couplers guide the light propagating through each waveguide 530A and 530B emanating from each waveguide 530A and 530B in their respective radiation directions 1A and 1B so that the light exits PIC500' through their respective output sections 550A and 550B. For example, light coupled from waveguide 530A by the coupler (optical element 532D) propagates through a portion of the cladding 522 (for example, in free mode), passes through the back wall 552, and exits to the outside through the aperture 556A of the output section 550A. In another example, light coupled from waveguide 530B by the coupler (optical element 532E) propagates through a portion of the cladding 522 (for example, in free mode), and exits to the outside through the aperture 556B of the output section 550B.

[0088] Figures 8A and 8B show an exit end view and a top view of a PIC500 having a grooved baffle 570 positioned between two adjacent output sections 550A and 550B. The exit side 504 of the PIC500 is perpendicular to the propagation direction defined by waveguides 530A and 530B. In an exemplary embodiment, the grooved baffle 570 extends along at least a portion of the length of waveguides 530A and 530B. For example, the grooved baffle 570 may extend between parallel waveguides 530A and 530B over all and / or a portion of the length of waveguides 530A and 530B. In various embodiments, the grooved baffle 570 prevents crosstalk from occurring between parallel waveguides 530A and 530B.

[0089] In various embodiments, the groove baffle 570 is formed from grooves 575 conformally coated with coating 540. For example, a groove 575 extending to a depth t and having a width e in the PIC body 520 can be etched into the PIC body 520. For example, the groove 575 can be etched into the PIC body 520 to define a groove wall having a height t and a groove bottom having a width e. The groove wall and groove bottom extend the length of the groove. In various embodiments, the depth t of the groove 575 is in the range of 0.5 μm to 100 μm (including 0.5 μm and 100 μm). For example, in an exemplary embodiment, the depth t of the groove 575 is in the range of 1 μm to 20 μm (including 1 μm and 20 μm). In various embodiments, the width e of the groove 575 is in the range of 0.5 μm to 100 μm (including 0.5 μm and 100 μm). In an exemplary embodiment, the coating 540 is not applied to the groove 575, and the groove 575 itself acts as a groove baffle 570. In another exemplary embodiment, the groove 575 is filled with the coating 540 and / or another material having a high extinction coefficient and / or absorption coefficient.

[0090] Exemplary method for manufacturing a coated PIC with an output aperture Figure 9 provides a flowchart illustrating various processes, procedures, operations, and / or similar for manufacturing a PIC500. Starting in step 902, the PIC body 520, waveguides 530, and optional optical elements 532 of the waveguides are formed and / or manufactured. For example, in an exemplary embodiment, a second cladding 524 is formed and / or deposited (e.g., on a substrate and / or similar) and one or more waveguides 530 and / or optical elements 532 are formed on the second cladding 524. Then, a first cladding 522 is formed and / or deposited together with the second cladding 524 to surround the waveguides 530 and, optionally, the optical elements 532. The resulting PIC body 520 includes the waveguides 530 defined and / or formed inside it. In various embodiments, the first cladding 522 and / or the second cladding 524 are thermally grown or deposited by at least one of PECVD, sputtering, or vapor deposition techniques. In various embodiments, one or more layers of waveguide material 534, on which the waveguide 530 is formed and / or patterned, are deposited using PECVD, CVD, sputtering, ALD, vapor deposition, and / or similar.

[0091] In another exemplary embodiment, for example, the PIC body 520 is formed from a cladding material. To provide a PIC body 520 having waveguides 530 defined and / or formed inside, one or more waveguides 530 and / or optical elements 532 are formed and / or embedded within the PIC body 520. As should be understood by those skilled in the art, the PIC body 520, waveguides 530, and any optical elements 532 may be formed and / or manufactured using a variety of techniques depending on the application.

[0092] In various embodiments, manufacturing the PIC body 520 includes performing die and edge polishing steps. For example, the exit side 504, the inlet side 502, and / or one or more sides 506 of the PIC body 520 may be polished (e.g., using mechanical polishing, chemical mechanical polishing, and / or similar).

[0093] In step 904, one or more alignment feature portions 560 and / or etched arrangement feature portions 562 are formed on the PIC body 520. For example, the PIC body 520 may be etched to form one or more alignment feature portions 560 and / or etched arrangement feature portions 562. For example, a material may be deposited on the PIC body 520 to form one or more alignment feature portions 560 and / or etched arrangement feature portions 562. For example, a layer of material may be deposited on a portion of the outer surface 526 of the PIC body 520 and then etched using photolithography and / or mask etching to form the alignment feature portions 560 and / or etched arrangement feature portions 562. In an exemplary embodiment, the alignment feature portions 560 and / or etched arrangement feature portions 562 are formed using a lift-off process or a damascene process.

[0094] In step 906, one or more grooves 575 are etched into the PIC body 520. For example, the grooves 575 may be etched between parallel waveguides and / or parallel optical paths defined through each portion of the PIC body 520. In various embodiments, the grooves 575 are etched to a depth t and a width e. In various embodiments, the depth t of the groove 575 is in the range of 0.5 μm to 100 μm. For example, in an exemplary embodiment, the depth t of the groove 575 is in the range of 1 μm to 20 μm. In various embodiments, the width e of the groove 575 is in the range of 0.5 μm to 100 μm.

[0095] In various embodiments, steps 904 and 906 may be performed simultaneously. For example, a single lithography step and / or mask and etching step may be used to form the groove and the aligned feature portion. In another example, steps 904 and 906 may be performed at separate times. In an exemplary embodiment, step 906 is performed before step 904.

[0096] In step 908, if necessary or desired, the adhesive layer 545 is applied and / or deposited on the outer surface 526 of the PIC body 520. In various embodiments, the adhesive layer 545 is applied and / or deposited over the entire outer surface 565 of the PIC body 520. If grooves 575 are present, the adhesive layer 545 is also applied to the edges or walls of the grooves 575.

[0097] In step 910, the coating 540 is applied and / or deposited on the outer surface 526 (and / or adhesive layer 545) of the PIC body 520. In an exemplary embodiment, the deposition of the coating 540 is conformal. For example, the coating is applied and / or deposited conformally on one or more surfaces of the PIC body 520.

[0098] For example, a metallic and / or optically opaque coating (at wavelengths in which the waveguide is configured to guide light) is applied and / or deposited on the outer surface 526 (and / or adhesive layer 545) of the PIC body 520. In various embodiments, the coating 540 is applied and / or deposited over the entire outer surface 526 (or adhesive layer 545) of the PIC body 520. In various embodiments, the coating 540 is deposited using conformal deposition techniques. For example, in exemplary embodiments, the coating is applied and / or deposited using sputtering deposition techniques, atomic layer deposition (ALD) techniques, and / or vapor deposition techniques. In various embodiments, the coating 540 is deposited to a thickness (e.g., extending from the outer surface 526 of the PIC body 520) that is the absorption depth of light at wavelengths in which the waveguide 530 is designed to guide light within the material of the coating 540. In an exemplary embodiment, the coating 540 is deposited to a thickness in the range of 100 nm to 1 μm (for example, extending from the outer surface 526 of the PIC body 520).

[0099] In an exemplary embodiment in which one or more grooves are etched into the PIC body 520, conformal deposition of the coating 540 is such that the edges or walls of the grooves 575 are also coated, providing each groove baffle 570.

[0100] In step 912, one or more etched and / or milled openings 556 are formed. For example, the PIC 500 (e.g., the PIC body 520 and coating 540) is etched to form the etched and / or milled openings 556. In various embodiments, the etched and / or milled openings 556 are etched to form and / or define a first side wall 553, a second side wall 554, and a rear wall 552. In exemplary embodiments, the etched and / or milled openings 556 are formed and / or etched using a focused ion beam (FIB) etching technique. For example, a beam of argon may be used to mill the etched and / or milled openings 556. In exemplary embodiments, the etched and / or milled openings 556 are formed using a lift-off technique. In exemplary embodiments in which a lift-off technique is used to form an etched and / or milled opening 556, the length l of the opening may be substantially equal to the thickness of the coating 540 (for example, the etched and / or milled opening 556 may not extend into the PIC body 520). In various embodiments, the location in which the etched and / or milled opening 556 is etched is determined at least partially on the etching arrangement feature 562.

[0101] In various embodiments, the etched and / or milled aperture 556 is etched to have a width w in the range of 5 μm to 40 μm (including 5 μm and 40 μm). In various embodiments, the etched and / or milled aperture 556 is etched to have a width w in the range of 15 μm to 30 μm (including 15 μm and 30 μm). In various embodiments, the etched and / or milled aperture 556 is etched to have a length l in the range of 1 μm to 20 μm (including 1 μm and 20 μm). In an exemplary embodiment, the etched and / or milled aperture 556 is etched to have a length l in the range of 1 μm to 5 μm (including 1 μm and 5 μm). In an exemplary embodiment, the width w is greater than the expected mode field diameter of the light beam expected to exit each output section 550.

[0102] In exemplary embodiments, the etched and / or milled aperture 556 is etched to have a total length s (for example, in the z direction as shown in Figures 3 and 4, or in the y direction as shown in Figure 3A) that is substantially the same as or less than the depth d of the PIC 500 to which the coating 540 is applied. In various embodiments, the length of the etched and / or milled aperture 556 is greater than the predicted mode field diameter of the light beam expected to exit each output section 500.

[0103] In various embodiments, the etched and / or milled opening 556 is etched such that the respective first sidewalls 553, second sidewalls 554, and rear wall 552 are smooth. In various embodiments, the etched and / or milled opening 556 is etched such that the respective first sidewalls 553 and second sidewalls 554 are substantially planar. In various embodiments, the etched and / or milled opening 556 is etched such that the rear wall 552 is one of planar, concave, or convex, depending on the application.

[0104] In various embodiments, openings through the coating 540 (and the adhesive layer 545, if present) corresponding to one or more input sections 510 may also be etched and / or formed via shadow masking. For example, to allow a laser beam and / or laser pulse and / or optical beam and / or optical pulse to enter each input section 510 of the PIC500, openings may be etched through the coating 540 (and the adhesive layer 545, if present).

[0105] In various embodiments, the opening 556 is formed at least partially by a technique other than etching or milling. For example, in an exemplary embodiment, the opening 556 is formed via shadow masking. For example, in such an embodiment, a mask is applied to the location on the exit side 504 where the opening 556 is to be formed, before the coating is deposited on the outer surface of the PIC body 520. When the coating 540 is deposited on the outer surface of the PIC body 520 (e.g., on the outer surface of the exit side 504), the coating does not adhere to the mask, and the opening 556 is formed through the coating 540.

[0106] Technical advantages In conventional PICs, some of the light supplied to the PIC input may not be coupled to the waveguide mode, or it may be scattered outside the waveguide mode as it passes through the PIC. For example, some of the light supplied to the PIC input may not be coupled to the waveguide via the input. In another example, some of the light propagating through the waveguide of the PIC may be scattered by the roughness of the waveguide edges. Some of the uncoupled and / or scattered light may propagate outside through the exit side of the PIC. This uncoupled light may cause light intensity away from the main peak position on the image plane. For example, the uncoupled and / or scattered light may interfere with the array of laser beams and / or optical beams supplied through the output of the PIC, resulting in increased scattering of light outside the array of laser beams and / or optical beams. For example, in some applications, it is desirable to have 60-70 dB of extinction between adjacent laser beams and / or optical beams output by the PIC. However, in conventional PICs, the extinction between adjacent laser beams and / or optical beams output by the PIC is at best 50 dB. Therefore, there are technical issues regarding controlling, preventing, and / or eliminating uncoupled and / or scattered light from the PIC's output.

[0107] Various embodiments provide technical solutions to these technical problems. For example, in various embodiments, one or more output sections of the PIC are located within and / or corresponding to etched and / or milled apertures formed in the PIC body. In various embodiments, a metallic or optically opaque coating (at wavelengths configured to be induced by the waveguides of the PIC) is deposited, coated, and / or disposed on the outer surface of the PIC body. The etched and / or milled apertures extend through the coating to the PIC body to provide optical apertures through the coating. The coating prevents light from escaping from the exit side of the PIC between the etched and / or milled apertures. The geometric shape of the etched and / or milled apertures prevents light traveling in directions perpendicular and / or substantially non-parallel to the radiation direction of each output section of the PIC from being blocked or attenuated. Thus, light traveling in directions perpendicular and / or substantially non-parallel to the radiation direction of each output section of the PIC is prevented from reaching the image plane of each output section. As a result, extinction between adjacent laser beams and / or optical beams output by the PIC can reach 60 dB or more. Therefore, the embodiments disclosed herein provide technical improvements to the technical field of PICs and beam delivery systems.

[0108] Example Controller In various embodiments, the quantum computers 110, 110' include a controller 30 configured to control various elements of the quantum computers 110, 110'. In various embodiments, the controller 30 may be configured to cause the quantum computers 110, 110' to perform various operations (e.g., computational operations such as gate operations, cooling operations, transport operations, qubit interaction operations, qubit measurement operations, leakage suppression operations, and / or similar). For example, the controller 30 may be configured to cause an operation source 70 to provide operation signals to an object (e.g., an atom, ion, molecule, quantum particle, and / or similar) confined and / or captured within the confinement device 50. For example, the controller 30 may be configured to cause the operation source 70 to provide a laser beam and / or laser pulse and / or optical beam and / or optical pulse to perform, for example, one or more quantum gates, read the quantum state of an object, perform resonant laser cooling of an object, and / or similar. In various embodiments, the controller 30 may be configured to control a cryogenic system and / or vacuum system that controls the temperature and pressure within the cryogenic and / or vacuum chamber 40, an operating source 70, and / or other systems that control environmental conditions within the cryogenic and / or vacuum chamber 40 (e.g., temperature, humidity, pressure, and / or similar), and / or may be configured to manipulate and / or induce a controlled evolution of the quantum state of one or more objects confined by the confinement device 50.

[0109] As shown in Figure 10, in various embodiments, the controller 30 may comprise a variety of controller elements, including a processing element 205, a memory 210, a driver controller element 215, a communication interface 220, an analog-to-digital converter 225, and / or similar. For example, the processing element 205 may comprise a programmable logic device (CPLD), a microprocessor, a coprocessing entity, an application-specific instruction set processor (ASIP), an integrated circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, other processing devices and / or circuits, and / or similar, as well as a controller. The term "circuit" may refer to an entirely hardware embodiment or a combination of hardware and computer program products. In an exemplary embodiment, the processing element 205 of the controller 30 comprises and / or communicates with a clock.

[0110] For example, memory 210 may include non-temporary memory such as volatile and / or non-volatile memory storage, such as one or more of the following: hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, and / or similar. In various embodiments, memory 210 may store qubit records corresponding to the qubits of a quantum computer (e.g., in a qubit record data store, qubit record database, qubit record table, and / or similar), calibration tables, executable queues, computer program code (e.g., in one or more computer languages, dedicated controller languages, and / or similar). In an exemplary embodiment, the execution of at least a portion of computer program code stored in memory 210 (for example, by processing element 205) causes the controller 30 to perform one or more steps, operations, processes, procedures, and / or similar described herein for tracking the phases of atomic objects in an atomic system and causing the phase adjustment of one or more operating sources and / or signals generated thereby.

[0111] In various embodiments, the driver controller element 215 may include one or more drivers and / or controller elements, each configured to control one or more drivers. In various embodiments, the driver controller element 215 may comprise drivers and / or driver controllers. For example, a driver controller may be configured to cause one or more corresponding drivers to operate according to executable instructions, commands, and / or similar that are scheduled and executed by the controller 30 (e.g., by the processing element 205). In various embodiments, the driver controller element 215 enables the controller 30 to operate servos, operating sources 70 (e.g., laser systems), vacuum and / or cryogenic systems, and / or similar. In various embodiments, the drivers may be laser drivers, microwave drivers, vacuum component drivers, cryogenic system and / or vacuum system component drivers, current drivers, and / or similar. For example, the driver and / or driver controller may be configured to cause a magnetic field generating device (e.g., a circuit coupled to a voltage source (e.g., a current driver or voltage driver), a permanent magnet, and / or a combination thereof) to generate a magnetic field having a specific direction and magnitude in one or more regions and / or locations at least partially defined by the confinement device 50. In various embodiments, multiple regions and / or locations (e.g., confinement zones) at least partially defined by the confinement device 50 may be defined. In various embodiments, the controller 30 includes means for communicating and / or receiving signals from a camera, MEM camera, CCD camera, photodiode, photomultiplier tube, and / or similar. For example, the controller 30 may include one or more analog-to-digital converter elements 225 configured to receive signals from one or more optical receiver components, calibration sensors, and / or similar.

[0112] In various embodiments, the controller 30 may include a communication interface 220 for interfaceing with and / or communicating with the computing entity 10. For example, the controller 30 may include a communication interface 220 for receiving executable instructions, command sets, and / or similar from the computing entity 10 and for providing the computing entity 10 with outputs received from the quantum computer 110 (e.g., from an optical collection system) and / or the results of processing those outputs. In various embodiments, the computing entity 10 and the controller 30 may communicate directly via wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0113] Exemplary Computing Entity Figure 11 provides a descriptive schematic diagram of an exemplary computing entity 10 that can be used in conjunction with embodiments of the present invention. In various embodiments, the computing entity 10 is configured to allow a user to provide input to quantum computers 110, 110' (e.g., through the user interface of the computing entity 10) and to receive, display, analyze, and / or similar outputs from the quantum computers 110, 110'. For example, a user may operate the computing entity 10 to generate and / or program quantum algorithms and / or quantum circuits so that a controller 30 can receive quantum algorithms and / or quantum circuits and cause the quantum computers 110, 110' to execute the quantum algorithms and / or quantum circuits.

[0114] As shown in Figure 11, the computing entity 10 may include an antenna 312, a transmitter 304 (e.g., wireless), a receiver 306 (e.g., wireless), and a processing element 308 that provides signals to the transmitter 304 and receiver 306 and receives signals from the transmitter 304 and receiver 306, respectively, which may be collectively referred to as a transceiver. The signals provided to and received by the transmitter 304 and receiver 306 may include signaling information / data that conforms to applicable wireless system air interface standards for communicating with various entities such as a controller 30, other computing entities 10, and / or similar. In this regard, the computing entity 10 may be able to operate using one or more air interface standards, communication protocols, modulation types, and access types. For example, computing entity 10 may be configured to receive and / or provide communications using wired data transmission protocols such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data Services Interface Standard over Cable (DOCSIS), or any other wired transmission protocol.Similarly, Computing Entity 10 supports General-Purpose Packet Radio Services (GPRS), Universal Mobile Communications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA®), Pan-European Digital Mobile Telephone System (GSM), GSM Evolution High Speed ​​Data Rate (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long-Term Evolution (LTE), Evolution Universal Terrestrial Radio Access Network (E-UTRAN), Evolution Data Optimized (EV-DO), High Speed ​​Packet Access (HSPA), High Speed ​​Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), and Wi-Fi. Computing entity 10 may be configured to communicate over a wireless external communication network using any of the following protocols: Direct, 802.16 (WiMAX), Ultra Wideband (UWB), Infrared (IR) protocol, Near Field Communication (NFC) protocol, Wibree, Bluetooth protocol, Wireless Universal Serial Bus (USB) protocol, and / or any other wireless protocol. Computing entity 10 may use such protocols and standards to communicate using Boundary Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP over TLS / SSL / Secure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), Hypertext Markup Language (HTML), and / or similar.

[0115] Through these communication standards and protocols, the computing entity 10 can communicate with various other entities using concepts such as unstructured add-on service information / data (USSD), short message service (SMS), multimedia messaging service (MMS), dual-tone multi-frequency signaling (DTMF), and / or subscriber identification module dialer (SIM dialer). The computing entity 10 can also download changes, add-ons, and updates to its firmware, software (including, for example, executable instructions, applications, and program modules), and operating system. In various embodiments, the computing entity 10 includes one or more network interfaces 320 configured to communicate with one or more wired and / or wireless networks 20 (e.g., a controller 30 and / or one or more other computing entities 10).

[0116] The computing entity 10 may also include a user interface device having one or more user input / output interfaces (e.g., a display 316 and / or speaker / speaker driver coupled to the processing element 308, as well as a touchscreen, keyboard, mouse, and / or microphone coupled to the processing element 308). For example, the user output interface may be configured to provide applications, browsers, user interfaces, dashboards, screens, web pages, pages, and / or similar words used herein interchangeably, which run on and / or are accessible through the computing entity 10, in order to trigger the display or audible presentation of information / data, and for interaction with that display or audible presentation via one or more user input interfaces. The user input interface may include any of several devices that enable the computing entity 10 to receive data, such as a keypad 318 (hard or soft), a touch display, a voice / speech or motion interface, a scanner, a reader, or other input device. In embodiments including a keypad 318, the keypad 318 may include (or trigger the display of) conventional numerals (0-9) and associated keys (#, *) and other keys used to operate the computing entity 10, and may include a complete set of alphanumeric keys, or a set of keys that can be activated to provide a complete set of alphanumeric keys. In addition to providing input, the user input interface may be used to activate or deactivate certain functions, such as a screen saver and / or sleep mode. Through such input, the computing entity 10 may collect information / data, user interaction / input, and / or similar.

[0117] The computing entity 10 may also include volatile memory or storage 322 and / or non-volatile memory or storage 324, which can be embedded and / or made removable. For example, non-volatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, and / or similar. Volatile memory may be RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, and / or similar. Volatile and non-volatile storage or memory may store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, executable instructions, and / or similar for implementing the functionality of the computing entity 10.

[0118] conclusion Many modifications and other embodiments of the invention described herein will be recalled by those skilled in the art who are interested in the invention and who benefit from the teachings presented in the foregoing description and the associated drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Certain terms are used herein, but they are used in a general and descriptive sense only and not for limiting purposes. [Explanation of Symbols]

[0119] 1. Radial direction 1' Radial direction 1A Radiation direction 1B Radial direction 10 Computing Entities 20. Wired or wireless network 30 controllers 40 Low-temperature and / or vacuum chamber 50 Confinement device 68 Beam Delivery Systems 70 Operation source 100 QCCD-based quantum computer systems 100' QCCD-based quantum computer system 110 Quantum Computers 110' Quantum Computer 304 Transmitter 306 Receiver 308 processing elements 312 Antenna 316 displays 318 Keypad 320 network interfaces 322 Volatile memory or storage 324 Non-volatile memory or storage 500 PIC 500' PIC 502 Entrance side 504 Exit side 506 Side view 506A side 506B side 506C side 506D side view 510 Input section 510A Input Section 510B Input Section 520 PIC body 522 First cladding, cladding 524 Second cladding 526 Exterior 530 Waveguides 530A waveguide 530B waveguide 530A waveguide 530B waveguide 532 Optical elements 532A Optical Element 532B Optical Element 532C Third optical element 532D optical element 532E Optical Element 534 Waveguide Materials 540 Coating, Conformal Coating 545 Adhesion layer 550 Output section 550A output section 550B Output Section 553 First side wall 552 Back wall 552A Back wall 552B Back wall 553A First side wall 553B First side wall 554 Second side wall 554A Second side wall 554B Second side wall 556 Etched and / or milled openings, openings 556A Etched and / or milled openings 556B Etched and / or milled openings 558 Normal 560 Alignment Feature Section 562 Etched arrangement features 570 groove baffle 575 Groove

Claims

1. A photonic integrated circuit (PIC), PIC body and At least one input section defined on one or more inlet sides of the PIC body, One or more output sections defined at one or more outlet sides of the PIC body, At least one waveguide defined in the PIC body, wherein the at least one waveguide optically couples the at least one input section to the respective output sections of the one or more output sections, A coating covering the outer surface of at least one or more outlet sides of the PIC body, wherein one or more openings are formed through the coating, each of the one or more openings coincides with each of the one or more output sections, and the coating is optically opaque or metallic. A photonic integrated circuit (PIC) equipped with this feature.

2. The PIC according to claim 1, wherein the coating further covers the outer surface of at least one of (a) at least one side of the PIC body, or (b) at least one of the one or more inlet sides.

3. The PIC according to claim 1, wherein the coating extends outward from the outer surface of the PIC body by a thickness in the range of 15 nm to 1 μm.

4. The PIC according to claim 1, wherein the one or more output units comprises a first output unit and a second output unit, the at least one waveguide comprises a first waveguide and a second waveguide, and the PIC further comprises a grooved baffle disposed between (a) the first output unit and the second output unit, or (b) at least a portion of the first waveguide and at least a portion of the second waveguide.

5. The PIC according to claim 1, wherein each of the one or more openings is etched or milled into the PIC body to form its respective side wall and rear wall, and each of the output units is positioned on the respective rear wall of each of the openings.

6. The PIC according to claim 5, wherein the length of each of the side walls in a direction substantially parallel to the radiation direction of the one or more output units is configured to prevent the generation of a diffraction pattern in the light emitted through the one or more output units.

7. The PIC according to claim 5, wherein the distance between the opposing side walls of each of the openings is greater than the predicted mode field diameter of the light beam configured to be output by each of the output units.

8. The PIC according to claim 1, further comprising one or more alignment feature portions formed on or within the PIC body and detectable through the coding.

9. The PIC according to claim 1, wherein the PIC body comprises one or more claddings surrounding the at least one waveguide in a direction perpendicular to the radiation direction of the at least one waveguide.

10. The PIC according to claim 1, wherein at least one of the one or more output units comprises a signal manipulation element.

11. A method for manufacturing a photonic integrated circuit (PIC), wherein the method is The steps of forming a PIC body including at least one input section, one or more output sections, and at least one waveguide that optically couples the at least one input section to each of the output sections of the one or more output sections, A step of conformally depositing a coating on the outer surface of one or more exit sides of the PIC body, wherein the coating is optically opaque or metallic. A step of forming one or more openings through the coating, wherein each of the one or more openings coincides with each of the output sections of the one or more output sections. Methods that include...

12. The method according to claim 11, wherein the one or more openings are formed using etching or milling techniques.

13. The method according to claim 11, wherein the one or more openings are formed using lithography etching, a lift-off process, or shadow masking.

14. The method according to claim 11, wherein the one or more openings are formed using a focused ion beam (FIB).

15. The method according to claim 11, wherein the coating further covers the outer surface of at least one side of the PIC body.

16. The method according to claim 11, wherein the coating is deposited on the outer surface using at least one of (a) sputter deposition, (b) atomic layer deposition (ALD), or (c) vapor deposition.

17. The method according to claim 11, further comprising the step of forming one or more alignment features on or within the PIC body before depositing the coating, wherein the one or more alignment features are detectable after the coating has been deposited on the outer surface.

18. The method according to claim 17, wherein at least one of the one or more alignment features is used in the alignment of the PIC body for etching the PIC body to form the one or more etched and / or milled openings.

19. Before depositing the coating on the outer surface, A step of etching grooves configured to provide groove baffles when the coating is deposited, or Step of applying an adhesive layer to the outer surface. The method according to claim 11, further comprising at least one of the following.

20. It is a quantum system, Confinement device and One or more sources of operation, A beam delivery system configured to provide operating signals generated by one or more operating sources to each location defined by the confinement device, The beam delivery system comprises a photonic integrated circuit (PIC), and the PIC is PIC body and The PIC body comprises at least one input section defined, One or more output sections defined at one or more outlet sides of the PIC body, At least one waveguide defined in the PIC body, wherein the at least one waveguide optically couples the at least one input section to the respective output sections of the one or more output sections, A coating covering the outer surface of at least one or more outlet sides of the PIC body, wherein one or more openings are formed through the coating, each of the one or more openings coincides with each of the one or more output sections, and the coating is optically opaque or metallic. A quantum system equipped with these features.

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