Recovery circuit

Abstract

The recovery circuit includes a buffer and filter module that receives a sampling signal with droop between spikes over a time interval from a sample-and-hold circuit and outputs a regulated signal with droop. The recovery circuit includes an AC inverter and extractor module that removes the DC component of the regulated signal and provides an inverted AC component signal with a signal boost equal in magnitude and duration to the droop in the regulated signal. The recovery circuit also includes a summing amplifier that combines the regulated signal and the inverted AC component signal to provide an output signal with a substantially constant voltage over a time interval.

Description

Technical Field

[0001] This specification relates to a recovery circuit for a sample and hold circuit. (Government Interests) This invention was made under a government contract. Accordingly, the United States government has rights in this invention as specified by that contract.

Background Art

[0002] A sample and hold circuit is an electronic circuit used to sample an analog signal at a specific instant and hold its value for a certain period of time. A sample and hold circuit can be employed in an analog-to-digital converter (ADC) to capture an analog signal and convert it into a digital signal that can be processed by a digital system.

[0003] The basic operation of a sample and hold circuit includes two stages, namely, a sampling stage and a hold stage. In the sampling stage, the input analog signal is temporarily connected to a capacitor, and the capacitor is charged to the input voltage level. Thereby, a sample of the input signal at a specific instant is captured. In the hold stage, the switch connecting the input analog signal to the capacitor is opened, and the voltage on the capacitor is held constant by a buffer amplifier. Thereby, the analog signal is "frozen" in time and held at a constant level for a certain period of time so that the analog signal can be accurately measured or converted into a digital signal.

Summary of the Invention

[0004] The first example relates to a recovery circuit including a buffer and filter module that receives a sampling signal having droops between spikes over a time interval from a sample-and-hold circuit and outputs a regulated signal having droops. The recovery circuit also includes an AC inverter and extractor module that removes the DC component of the regulated signal and provides an inverted AC component signal having signal boosts equal in magnitude and duration to the droops in the regulated signal. The recovery circuit includes an summing amplifier that combines the regulated signal and the inverted AC component signal to provide an output signal having a substantially constant voltage over a time interval.

[0005] The second example relates to a sample-and-hold recovery circuit (SHARC) which includes a sample-and-hold circuit that supplies a sampled signal over a time interval in response to an input signal and a trigger signal. The sampled signal has a droop between voltage spikes that coincide with the pulse in the trigger signal. SHARC also includes a recovery circuit which has a buffer and filter module that receives the sampled signal and outputs a regulated signal that has a droop between boosts over a time interval. The recovery circuit also includes an AC inverter and extractor module which removes the DC component of the regulated signal and provides an inverted AC component signal that has a signal boost equal in magnitude and duration to the droop in the regulated signal. The recovery circuit further includes an summing amplifier which combines the regulated signal and the inverted AC component signal to provide an output signal with a substantially constant voltage over a time interval.

[0006] A third example relates to a power supply including a controller that provides a control signal. The power supply also includes a digital-to-analog converter (DAC) that provides multiple input signals in response to the control signal. The input signals have voltages that vary by at least 5% over a certain time interval. The power supply also includes multiple sample-and-hold recovery circuits that provide separate output signals in response to the multiple input signals. The output signals have voltages that vary by less than 0.002% over a certain time interval. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of the sample-and-hold recovery circuit (SHARC). [Figure 2A] This is a diagram of the SHARC circuit. [Figure 2B] This is a diagram of the SHARC circuit. [Figure 3] Figures 2A and 2B show graphs plotting the voltage as a function of time for the SHARC signal. [Figure 4] This diagram shows a system including a multi-channel power supply. [Modes for carrying out the invention]

[0008] This disclosure relates to a sample-and-hold recovery circuit. SHARC includes a sample-and-hold circuit that supplies a sampled signal over a time interval (e.g., at least 0.2 seconds) in response to an input signal and a trigger signal. More specifically, the voltage of the sampled signal fluctuates by about 5% to about 10% (e.g., about 8%) or more over the time interval. The sampled signal has a droop between voltage spikes that coincide with pulses in the trigger signal. The sample-and-hold circuit may be implemented using conventional sample-and-hold circuits, such as a sample-and-hold circuit having a capacitor of about 10 microfarads (μF) or less.

[0009] SHARC also includes a recovery circuit with a buffer and filter module that receives a sampled signal and outputs a tuned signal having droop during boosts (crescents) over time intervals. The tuned signal has droop to the mean that matches the droop of the sampled signal. The recovery circuit also includes an AC inverter and extractor module that extracts the AC component of the tuned signal by removing the DC component of the tuned signal, providing an inverted AC component signal with a signal boost to the mean equal in magnitude and duration to the droop in the tuned signal. That is, the inverted AC component signal and the tuned signal are mirror images of each other. The recovery circuit also includes an add-on amplifier that combines the tuned signal and the inverted AC component signal to provide an output signal (also referred to as the recovery signal) with a nearly constant voltage over time intervals. The nearly constant voltage is approximately equal to the mean. In some examples, the nearly constant voltage of the output signal shows variation of less than 0.002% over time intervals. Thus, SHARC's recovery circuit compensates for voltage droop over time intervals without requiring a large capacitor in the sample-and-hold circuit.

[0010] Figure 1 is a block diagram of the SHARC100. The SHARC100 has an analog input voltage V IN and trigger signal V TRIGGER The system includes a sample-and-hold circuit 104 that receives the trigger signal V. The sample-and-hold circuit 104 is a conventional sample-and-hold circuit. The sample-and-hold circuit 104 receives the trigger signal V. TRIGGER The input voltage V at a specific instant as defined by IN It is configured to capture and hold the input voltage. The sample-and-hold circuit 104 outputs a signal for a certain period of time that has a voltage approximately equal to its instantaneous input voltage.

[0011] More specifically, the sample-and-hold circuit 104 has two operations: sampling and holding. In sampling, the input voltage V IN It is sampled at a specific instant. The hold operation is performed when the input voltage VIN It can be performed by a switch that connects to a sampling capacitor. In the hold operation, in response to the input voltage V IN having been sampled, a switch controlled by a trigger signal V TRIGGER disconnects the sampling capacitor from the input voltage V IN , and the capacitor holds the sampled voltage level. The output of the sample-and-hold circuit is the voltage level held in the capacitor, and usually provides a sampling signal 106 that is buffered by an operational amplifier (op-amp) and has a low-impedance output.

[0012] As the capacitor of the sample-and-hold circuit 104 discharges (during the hold operation), the voltage output of the sample-and-hold circuit 104 decreases, and this decrease is referred to as droop. The droop rate depends on the discharge time constant of the capacitor, which is determined by the value of the capacitor and the input resistance of the buffer amplifier. The droop can be suppressed by using a capacitor with a larger value or a buffer amplifier with a lower input resistance, but this can lead to other problems such as a slower settling time or increased noise. The sampling signal 106 is represented as a sawtooth wave to indicate this droop. Therefore, the sampling signal 106 includes spikes and droops over a certain time interval (e.g., 0.2 seconds or more). The sampling signal has a voltage that varies by about 5% to about 15% or more, and in some examples about 8%, based on the time interval.

[0013] Therefore, to compensate for the droop of the sample-and-hold circuit 104, SHARC 100 includes a recovery circuit 108. The recovery circuit includes a buffer and filter 112 (buffer and filter module) that receives the sampling signal 106 of the sample-and-hold circuit 104. The buffer and filter 112 is a circuit that buffers the sampling signal 106 of the sample-and-hold circuit 104 and filters out unwanted noise and / or frequency components from the sampling signal 106. The buffer section of the buffer and filter 112 isolates the sampling signal 106 from the load and adjusts the sampling signal 106. The filter section of the buffer and filter 112 removes unwanted frequency components from the sampling signal 106 and outputs an adjusted signal 116. The adjusted signal 116 is output to the AC inverter and extractor 120 and the summing amplifier 124. The adjusted signal 116 has a droop during the boost around the average value over a time interval.

[0014] The AC inverter and extractor 120 (AC inverter and extractor module) removes (filters) the DC component of the adjustment signal 116 to provide an AC signal. This AC signal is inverted and output as an inverted AC component signal 128. As used herein, the term “inverted AC component signal” refers to a signal that is a mirror image of another signal with respect to its mean value (for example, a mirror image of the mean value of the adjustment signal 116). Thus, the inverted AC component signal 128 has a boost in time intervals where the adjustment signal has a droop and a droop in time intervals where the adjustment signal has a boost (crescent).

[0015] The summing amplifier 124 combines the adjustment signal 116 and the inverted AC component signal 128 (by addition) to generate an output signal 132 having a voltage approximately equal to the average value of the adjustment signal 116 and the inverted AC component signal 128. The summing amplifier 124 includes an operational amplifier and an input resistor. The operational amplifier adds the AC difference between the adjustment signal 116 and the inverted AC component signal 128, which are connected to the inverting input of the operational amplifier via the input resistor. The output of the operational amplifier of the summing amplifier 124 is the output signal 132.

[0016] During operation, when the sampling signal 106 droops, the adjustment signal 116 has a corresponding droop (falling edge signal) and boost (rising edge signal). However, the inverted AC component signal 128 has a boost (rising edge signal) simultaneously with the droop of the adjustment signal 116, and a droop simultaneously with the boost of the adjustment signal 116 (because the inverted AC component signal 128 has an inverted polarity with respect to the adjustment signal 116 with respect to the average value). Since the AC component polarities of the adjustment signal 116 and the inverted AC component signal 128 are opposite, the AC difference between the adjustment signal 116 and the inverted AC component signal 128 (corresponding to the output signal 132) is the input signal V without droop during the hold time interval of the sample-and-hold circuit 104. IN This becomes equal to . That is, the output signal 132 suppresses droop in the sampled signal 106 without requiring an increase in the capacitance of the capacitor in the sample-and-hold circuit 104 and / or without reducing the input impedance of the operational amplifier in the sample-and-hold circuit 104. Therefore, the recovery circuit 108 can be used to improve the operating performance of the sample-and-hold circuit 104.

[0017] Figures 2A and 2B show exemplary circuit diagrams of SHARC200 that can be used to implement SHARC100 in Figure 1. More specifically, Figure 2A shows the sampling signal V SAMP Figure 2B shows a sample-and-hold circuit 204 that provides the sampled signal V. SAMP In response to the output signal V OUT The recovery circuit 208, which provides a recovery signal (also referred to as a recovery signal), is shown.

[0018] The sample-and-hold circuit 204 can be used to implement the sample-and-hold circuit 104 in Figure 1. The sample-and-hold circuit 204 includes an input operational amplifier 212 connected as a buffer, with the output terminal and the inverting input of the input operational amplifier 212 connected to node 216. The non-inverting input of the input operational amplifier 212 is connected to the analog input voltage V INIt is connected to the input voltage V. IN This is supplied from a DC voltage source 218 connected to an electrically neutral node 220 (e.g., ground). In some examples, the DC voltage source 218 represents the output of a digital-to-analog converter (DAC).

[0019] The term “connect” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable a functional relationship consistent with the description in this disclosure. For example, if device A generates a signal to control device B to perform an operation, in the first example, device A is connected to device B, or in the second example, device B is controlled by device A via a control signal generated by device A, if the intervening component C does not substantially alter the functional relationship between device A and device B.

[0020] Node 216 is connected to resistor 224. Resistor 224 has a resistance of approximately 10 ohms. Unless otherwise specified, “approximately” preceding a value in this specification means ±10 percent of the specified value. Resistor 224 is connected to the positive input terminal of switch 228 of sample-and-hold circuit 204. Switch 228 may be implemented by a transmission gate, also known as a pass gate. Thus, switch 228 may be implemented by a pair of complementary field-effect transistors (FETs), such as one N-channel FET (N-FET) and one P-channel FET (P-FET). Switch 228 is triggered by a trigger signal V generated by the control logic for SHARC200. TRIGGER It is controlled by the trigger signal V. TRIGGER This determines the duration of the sample period and hold period, ensuring that switch 228 opens and closes at the correct timing. More specifically, the trigger signal V TRIGGERThe power is supplied from a pulse voltage source 232, which is connected in series with resistor 236 and to an electrically neutral node 220. Resistor 236 has a resistance of approximately 200 ohms in some examples and is connected to the positive control node of switch 228. The negative control node of switch 228 is connected to the electrically neutral node 220. The output terminal of switch 228 (e.g., the negative terminal) is connected to the capture node 240.

[0021] Capture node 240 is connected to resistor 244, capacitor 248, and the non-inverting input of operational amplifier 252. Resistor 244 has a resistance of approximately 10 megaohms (MΩ). Resistor 244 represents the leakage current. Capacitor 248 may have a capacitance of approximately 10 microfarads (μF) or less. Operational amplifier 252 is connected in a buffer configuration, and the output terminal and inverting input of operational amplifier 252 are connected to sample node 256.

[0022] In operation, the sample-and-hold circuit 204 has two stages, namely a sampling stage and a hold stage. In the sampling stage, the trigger signal V TRIGGER The signal is pulsed (high voltage stage), and the input voltage V IN It is connected to capacitor 248 via switch 228, and capacitor 248 is connected to the input voltage V IN It is charged to the value of . The duration of the sampling stage is determined by the trigger signal V TRIGGER It is controlled by the period of the trigger signal V. TRIGGER It has a pulse width of approximately 1 millisecond (ms).

[0023] Trigger signal V TRIGGER In response to the voltage becoming low, the sampling stage is completed, switch 228 is opened, and the outputs of input op-amps 212 and 252 are disconnected. Furthermore, in response, capacitor 248 holds the voltage supplied to op-amp 252 as a charge, and the output of op-amp 252 on sample node 256 is the sampled signal V SAMP This is the result. However, (trigger signal VTRIGGER When capacitor 248 discharges during the hold stage (which is in a lower stage), the sampling signal V SAMP The signal also drops, causing droop at the output of the sample-and-hold circuit 204.

[0024] Sampling signal V SAMP To compensate for the droop, SHARC200 includes a recovery circuit 208 shown in Figure 2B. The recovery circuit 208 includes a buffer and filter 258 (buffer and filter module). The buffer and filter 258 includes a resistor 260 connected to sample node 256. Resistor 260 is also connected to node 264, which is connected to the non-inverting input of op-amp 266 and capacitor 268 of buffer and filter 258. Resistor 260 has a resistance of approximately 10 kilohms (kΩ). Capacitor 268 has a capacitance equal to the capacitance of capacitor 248 in some examples, i.e., a capacitance of approximately 1 μF or less. Capacitor 268 is also connected to an electrically neutral node 220. Op-amp 266 is configured as a buffer, and the output terminal and non-inverting input of op-amp 266 are connected to node 270. The voltage at node 270 is the adjustment signal V CON That is the case.

[0025] In operation, the buffer and filter 258 receive the sampling signal V output from the sample-and-hold circuit 204. SAMP Buffer the sampled signal V SAMP Unwanted noise and / or frequency components are removed, and the adjusted signal V is sent to node 270. CON To provide.

[0026] Adjustment signal V CONThe power is supplied to the AC inverter and extractor 274 and the summing amplifier 278. The AC inverter and extractor 274 (AC inverter and extractor module) includes a resistor 282 connected to node 270. Resistor 282 has a resistance of approximately 2 kΩ. Resistor 282 is also connected to the inverting input of the operational amplifier 286. The non-inverting input of the operational amplifier 286 is connected to the electrically neutral node 220. The output terminal of the operational amplifier 286 is connected to node 288, which is also connected to a feedback resistor 290 connected between the output terminal and the inverting input of the operational amplifier 286. The feedback resistor 290 has a resistance of approximately equal to the resistance of resistor 282, and in some examples, the feedback resistor 290 has a resistance of approximately 2 kΩ. Node 288 is also connected to a capacitor 294. Capacitor 294 has a capacitance of approximately equal to the capacitance of capacitor 268, i.e., a capacitance of approximately 10 μF or less. Capacitor 294 is also connected to node 302, which receives the inverted AC component signal V as the output of the AC inverter and extractor 274. INV To provide.

[0027] During operation, the AC inverter and extractor 274 receive the adjustment signal V CON Remove the DC component and adjust the signal V CON The droop and boost are inverted, and at node 302, the inverted AC component signal V INV It is configured to form a boost. Inverted AC component signal V INV The boost in this case is controlled by the adjustment signal V CON The droop in this case is mirror-reversed. Furthermore, the inverted AC component signal V INV The droop in this case is the adjustment signal V CON The boost in this case is mirrored.

[0028] Adjustment signal V on node 270 CON (Output of buffer and filter 258) and the inverted AC component signal V on node 302 INV (The output of the AC inverter and extractor 274) is supplied to the summing amplifier 278. More specifically, (the adjustment signal V CONNode 270 (which has) is connected to resistor 306 of summing amplifier 278, (inverted AC component signal V INV Node 302 (which has the following characteristics) is connected to resistor 310 of summing amplifier 278. The resistance values ​​of resistors 306 and 310 are the same, for example, about 10kΩ. Resistors 306 and 310 are also connected to node 314, and node 314 is connected to the non-inverting input of op-amp 318 of summing amplifier 278. Op-amp 318 is configured as a buffer, and the output terminal and inverting input of op-amp 318 are connected to the output node 322 of summing amplifier 278. Therefore, the non-inverting input of op-amp 318 receives the adjustment signal V CON A portion of the and inverted AC component signal V INV It receives a portion of the output signal V from SHARC200. The output node of op-amp 318 receives the output signal V from SHARC200. OUT It provides (or is also called a recovery signal).

[0029] In operation, the summing amplifier 278 receives the adjustment signal V CON Inverted AC component signal V INV It is then combined with the inverted AC component signal V. INV The adjustment signal V CON The AC component signal V has a boost during the time interval in which it has a droop, and also has an inverted AC component signal V INV Because the adjustment signal has droop during the time intervals in which it has boost, the boost and droop cancel each other out, resulting in an output signal V with a nearly constant voltage. OUT A formation is created.

[0030] Figure 3 shows Graph 400, which plots the signal voltage (in volts (V)) in SHARC200 as a function of time in microseconds (μs) over a certain time interval. In the illustrated example, the time interval is 0.2 seconds. In other examples, the time interval may be longer or shorter. As shown in Graph 400, the sampling signal V (for example, at sample node 256 in Figures 2A and 2B) SAMP It has a sawtooth shape that oscillates between 1.0V and 1.1V. More specifically, the sampling signal V SAMP The trigger signal V TRIGGERIt has a droop between the pulse and the voltage spike that coincides with it.

[0031] Furthermore, the adjustment signal V (for example, at node 270 in Figure 2B) CON It oscillates between approximately 1.0055V and 1.0045V. Adjustment signal V CON It has droop and boost relative to an average value of approximately 1.005V. Furthermore, the inverted AC component signal V INV It also oscillates between approximately 1.0055V and 1.0045V. Inverted AC component signal V INV It has boost and droop that coincide with the mean value. Inverted AC component signal V INV The boost is controlled by the adjustment signal V CON It coincides with the droop, and the inverted AC component signal V INV The droop is the adjustment signal V CON This matches the boost. In this way, the adjustment signal V CON and the inverted AC component signal V INV They are mirror images of each other. Furthermore, the output signal V OUT It has an average value and fluctuates by less than 0.0001V.

[0032] As an alternative explanation, consider segment 410 of graph 400. In segment 410, as shown in the figure, the sampling signal V SAMP The droop in this case is the adjustment signal V CON In the same region, a droop is generated following the boost (due to the charging and discharging of capacitor 268), and as a result, the adjustment signal has a parabolic shape in segment 410. However, the inverted AC component signal V INV This involves a droop followed by a boost across the same segment 410, and this droop and boost are controlled by the adjustment signal V CON It has the opposite magnitude to the boost and droop in this case. Therefore, the adjustment signal V CON and the inverted AC component signal V INV By adding these together, the sampling signal V SAMP Output signal V that compensates for droop in OUT Therefore, (sampling signal V SAMPUnlike conventional sample signals where the voltage fluctuation is 10% (because it fluctuates between 1.0V and 1.1V), the output signal V OUT The variation is approximately 0.002%. Therefore, as shown by Graph 400, the SHARC200 in Figures 2A and 2B can be employed to provide high-precision output voltages, achieving a significant performance improvement compared to conventional sample-and-hold circuits such as the sample-and-hold circuit 104 in Figure 1 and / or the sample-and-hold circuit 204 in Figure 2A.

[0033] Figure 4 shows a system 500 including a K-channel power supply 504, where K is an integer greater than 1, and the K-channel power supply is a multi-channel power supply. In some examples, K is an integer greater than 80, such as 100 or greater. The K-channel power supply 504 includes a controller 508, such as a microcontroller. The K-channel power supply 504 includes a K-channel DAC 512. The K-channel power supply 504 also includes K SHARC516s (labeled SHARC 1...SHARC K) connected to the K-channel DAC 512. The K SHARC516s are implemented by SHARC100 in Figure 1 and / or SHARC200 in Figures 2A and 2B.

[0034] The controller 508 supplies a control signal to the K-channel DAC 512. In response to the control signal, the K-channel DAC 512 receives the input signal V IN The signal is supplied to the corresponding SHARC516. The K-channel DAC512 can be an 8-20 bit DAC in various examples. The controller 508 and the K-channel DAC512 receive the input signal V. IN It is configured to pulse sequentially (for example, from SHARC 1(516) to SHARC K(516)). In some examples, each input signal V IN This is the input signal V shown in Figure 4. IN It has a waveform similar to that of [another waveform].

[0035] Input signal V IN In response, K SHARC516s output the corresponding output signal V OUT(such as those shown and described in FIGS. 2A, 2B, and 3). More specifically, a given SHARC 516 (e.g., SHARC 1 to SHARC K) samples an input signal V OUT as described with respect to FIGS. 1, 2A, 2B, and 3, and generates an output signal V IN that compensates for the loop in the intermediate sampling signal V SAMP . OUT

[0036] The output signal V OUT is supplied to an output control 520 controlled by a controller 508. The output control may include, for example, an amplifier that adjusts the current and / or voltage of each output signal V OUT . The output control 520 may generate K channel outputs (labeled CH 1....CH K) that can be used to drive a load.

[0037] The above description is an example. Of course, it is impossible to describe all possible combinations of components or methods, but those skilled in the art will recognize that many more combinations and substitutions are possible. Accordingly, the present disclosure is intended to embrace all such alternative forms, modifications, and variations that fall within the scope of this application, including the appended claims. As used herein, the term "includes" means including but not limited to, and the term "including" means including but not limited to. The term "based on" means at least partially based on. Further, if the present disclosure or the claims describe "a", "first", or "another" component, or components equivalent thereto, it should be construed to include one or more of such components, and does not necessarily require or exclude more than two components.

Claims

1. It is a recovery circuit, A buffer and filter module that receives a sampling signal with droop between spikes over a certain time interval from a sample-and-hold circuit and outputs a droop-containing adjustment signal. An AC (hereinafter referred to as AC) inverter and extractor module that removes the DC component of the adjustment signal and provides an inverted AC component signal having a signal boost equal in magnitude and duration to the droop in the adjustment signal, A recovery circuit comprising: an additive amplifier that combines the adjustment signal and the inverted AC component signal to provide an output signal having a substantially constant voltage over the time interval.

2. The recovery circuit according to claim 1, wherein the time interval is at least 0.2 seconds.

3. The recovery circuit according to claim 2, wherein the output signal has a voltage that fluctuates by about 0.002% or less over the time interval.

4. The recovery circuit according to claim 3, wherein the sampling signal varies by at least 8% over the time interval.

5. The recovery circuit according to claim 1, wherein the buffer and filter module includes a given capacitor having a capacitance equal to the capacitance of the other capacitors in the sample-and-hold circuit.

6. The recovery circuit according to claim 5, wherein the AC inverter and extractor module include an operational amplifier (hereinafter referred to as an op-amp), and the op-amp receives a portion of the adjustment signal at the inverting input of the op-amp.

7. The recovery circuit according to claim 6, wherein the operational amplifier is a given operational amplifier, the summing amplifier includes another operational amplifier, and the other operational amplifier receives a portion of the adjustment signal and a portion of the inverted AC component signal at the non-inverting input of the other operational amplifier.

8. The recovery circuit according to claim 5, wherein the capacitance of the given capacitor is 10 microfarads or less.

9. A sample-and-hold recovery circuit, A sample-and-hold circuit that provides a sampled signal over a certain time interval in response to an input signal and a trigger signal, wherein the sampled signal has a droop between voltage spikes that coincide with the pulse in the trigger signal, It is a recovery circuit, A buffer and filter module that receives the sampling signal and outputs an adjustment signal having droop and boost over the time interval, An AC (hereinafter referred to as AC) inverter and extractor module that removes the DC component of the adjustment signal and provides an inverted AC component signal having a signal boost equal in magnitude and duration to the droop in the adjustment signal, A sample-hold recovery circuit comprising: a recovery circuit including an summing amplifier that synthesizes the adjustment signal and the inverted AC component signal to provide an output signal having a substantially constant voltage over the time interval; and a recovery circuit.

10. The sample-hold recovery circuit according to claim 9, wherein the time interval is at least 0.2 seconds.

11. The sample-and-hold recovery circuit according to claim 10, wherein the output signal has a voltage that fluctuates by about 0.002% or less over the time interval.

12. The sample-hold recovery circuit according to claim 11, wherein the sampling signal varies by at least 8% over the time interval.

13. The sample-and-hold recovery circuit according to claim 9, wherein the buffer and filter modules include a given capacitor having a capacitance equal to the capacitance of the other capacitors in the sample-and-hold circuit.

14. The sample-hold recovery circuit according to claim 13, wherein the AC inverter and extractor module include an operational amplifier (hereinafter referred to as an op-amp), and the op-amp receives a portion of the adjustment signal at the inverting input of the op-amp.

15. The sample-hold recovery circuit according to claim 14, wherein the operational amplifier is a given operational amplifier, the summing amplifier includes another operational amplifier, and the other operational amplifier receives a portion of the adjustment signal and a portion of the inverted AC component signal at the non-inverting input of the other operational amplifier.

16. The sample-hold recovery circuit according to claim 13, wherein the capacitance of the other capacitor is 10 microfarads or less.

17. It is a power source, A controller that provides control signals, A digital-to-analog converter (DAC) that provides a plurality of input signals in response to the control signal, wherein the plurality of input signals have a voltage that fluctuates by at least 5% over a certain time interval, and the digital-to-analog converter (DAC) A power supply comprising a plurality of sample-and-hold recovery circuits that provide output signals in response to a plurality of input signals, wherein the output signals have a voltage that fluctuates by 0.002% or less over the time interval.

18. The power supply according to claim 17, wherein the time interval is at least 0.2 seconds.

19. The power supply according to claim 17, wherein the plurality of sample-hold recovery circuits include at least 80 sample-hold recovery circuits.

20. The power supply according to claim 17, wherein each of the plurality of sample-hold recovery circuits includes a capacitor having a capacitance of 10 microfarads or less.

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