System and method for allocating memory resources using multifactor feedback control

Abstract

The method includes determining the write amplification factor for a specific NAND-based memory device and a host coupled to the NAND-based memory device, and calculating the host's bandwidth. Based on the write amplification factor and the host's bandwidth, the resources of the NAND-based memory device are allocated between the host and the NAND-based memory device's garbage collection process.

Description

Technical Field

[0001] Introduction This disclosure relates to allocating memory resources using multifactor feedback control. More specifically, this disclosure relates to allocating memory resources between host and internal garbage collection operations in certain classes of memory devices.

Summary of the Invention

[0002] In some embodiments, the method includes using a processing circuit to determine a write amplification factor for a particular NAND-based memory device and a host coupled to the NAND-based memory device, using the processing circuit to calculate the host bandwidth, and using the processing circuit to allocate resources of the NAND-based memory device based on the write amplification factor and the host bandwidth.

[0003] In some embodiments, the NAND-based memory device is a solid state drive, and in some embodiments, the resources may be at least one of a buffer, a CPU, or a die. In some embodiments, calculating the host bandwidth includes calculating the number of write operations transmitted to the NAND-based memory device by the host over a period of time. Calculating the host bandwidth may further include calculating a moving average of the number of write operations.

[0004] In some embodiments, the score may be calculated based on the write amplification factor and the host bandwidth, and resources may be allocated based on the score. Resources may be further allocated based on the amount of unused space in the NAND-based memory device. For example, a decrease in the amount of unused space results in allocating more resources to the internal garbage collection process of the NAND-based memory device.

[0005] In some embodiments, the system includes a host, a NAND-based memory device, and processing circuitry. The processing circuitry determines the write amplification factor for the NAND-based memory device and the host coupled to the NAND-based memory device, calculates the bandwidth of the host, and allocates resources for the NAND-based memory device based on the write amplification factor and the host bandwidth.

[0006] In some embodiments, a non-temporary computer-readable medium stores program code that, at runtime, performs a method including a procedure for determining a write amplification factor for a particular NAND-based memory device and a host coupled to that NAND-based memory device, a procedure for calculating the bandwidth of the host, and a procedure for allocating resources for the NAND-based memory device based on the write amplification factor and the bandwidth of the host. [Brief explanation of the drawing]

[0007] This disclosure, in one or more different embodiments, is described in detail with reference to the following drawings. The drawings are provided solely for illustrative purposes and illustrate typical or exemplary embodiments. These drawings are provided to facilitate the understanding of the concepts disclosed herein and should not be considered as limiting the breadth, scope, or applicability of these concepts. It should be noted that for clarity and ease of illustration, these drawings are not necessarily made to scale.

[0008] [Figure 1] The diagrams below illustrate a system, according to some embodiments of this disclosure, that includes a host device and a NAND-based memory device that functions as a storage device for the host device.

[0009] [Figure 2] The following are block diagrams of exemplary solid-state drive devices according to some embodiments of the present disclosure.

[0010] [Figure 3] The following are illustrative diagrams of data flows using feedback control to allocate resources in a NAND-based memory device, according to some embodiments of this disclosure.

[0011] [Figure 4] The following are illustrative graphs of a function of free space in a NAND-based memory device over a period of time, without feedback control for reallocating resources, according to some embodiments of the present disclosure.

[0012] [Figure 5] The present disclosure shows line graphs representing the free space and corresponding bias of a NAND-based memory device according to some embodiments of this disclosure.

[0013] [Figure 6] The present disclosure provides an exemplary graph of a function of free space in a NAND-based memory device over a period of time, with feedback control for reallocating resources, according to some embodiments of this disclosure.

[0014] [Figure 7] The following are illustrative diagrams of data flows using weighted feedback control 750 to allocate resources in a NAND-based memory device, according to some embodiments of the present disclosure.

[0015] [Figure 8] The flowcharts illustrate exemplary steps for allocating resources to a specific NAND-based memory device using feedback control, according to some embodiments of the present disclosure.

[0016] [Figure 9] A flowchart illustrating exemplary steps for allocating resources to a NAND-based memory device according to some embodiments of this disclosure is shown. [Modes for carrying out the invention]

[0017] In certain classes of memory devices, host bandwidth may occasionally mismatch with memory device bandwidth, resulting in greater performance variability (measured, for example, by input / output activity per second between the host and memory device). If the memory device bandwidth is too high, performance may be negatively affected. If the host bandwidth is too high, it may exceed the memory device capacity, potentially causing physical damage to the memory device. For example, quad-level cell (QLC) flash memory devices can store more data per cell than triple-level cell (TLC) flash memory devices, but differences in physical characteristics lead to greater performance variability and bandwidth mismatches in specific cells. This specification provides a system and method for allocating resources between a NAND-based memory device and a host using feedback control to maintain consistent host performance despite flash cell performance variability. It will be understood that the features of this disclosure may also be applicable to other classes of memory devices other than NAND-based memory devices.

[0018] The feedback control algorithm may calculate a score based on the internal characteristics of the memory device, other factors related to the host, the memory device, or both, or any combination thereof. In some embodiments, the write amplification factor of the memory device, the amount of unused space in the memory device, a moving average of the host's bandwidth over a period of time (e.g., the number of read and write operations by the host every 250 ms), other suitable factors or physical characteristics, or a combination thereof, may be used to generate the score. The score indicates how resources are allocated between the host and the memory device.

[0019] In some embodiments, a write amplification factor may be used to determine a desired bandwidth ratio between the host and the memory device, or the host bandwidth may be used to determine the actual bandwidth ratio between the host and the memory device. The score may be calculated by dividing the actual bandwidth ratio by the desired bandwidth ratio. In one such embodiment, a higher score may result in more resources being allocated to the memory device's garbage collection process, any other suitable process on the memory device, or any combination thereof, while a lower score may result in more resources being allocated to the host. In some embodiments, the feedback control algorithm may use a range of one or more scores to determine how resources are allocated. If the score is in the first range of 0.95 to 1.05, no resource allocation adjustment occurs. If the score is in the second range of 0.5 to 1.5 (but not in the first range), resource adjustment occurs. For example, if the score is greater than 1, more resources will be allocated to the garbage collection process. If the score is outside the second range, a greater resource adjustment occurs. For example, if the score is greater than 1.5, more resources will be allocated to the garbage collection process than if the score were in the range of 1 to 1.5.

[0020] Figure 1 shows an exemplary diagram of a system 100, according to some embodiments of the present disclosure, which includes a host device 103 and a NAND-based memory device 105 that functions as a storage device for the host device 103. As shown, the host device 103 is coupled to a solid-state drive (SSD) 105 via one or more buses 113 using a non-volatile memory express (NVMe) over peripheral component interconnect express (PCIe). However, it should be understood that any other suitable protocol or combination of protocols may be used. For example, such protocols may include serial attached small computer system interface (SAS), serial advanced technology attachment (SATA), any other suitable protocol, or any combination thereof.

[0021] The host device 103 includes a host controller 102, a memory 104, and an input / output (I / O) circuit 112. The host controller 102 may include one or more central processing units (CPUs), or one or more programmable logic arrays (PLAs), one or more field programmable gate arrays (FPGAs), one or more complex programmable logic devices (CPLDs), any other suitable controller, or any combination thereof, such as other configurable controllers. The memory 104 may include random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, any other suitable memory, or a combination thereof. The I / O circuit 112 may include a PCIe adapter communicatively coupled to the host interface 124 of the NAND-based memory device 105 using NVMe over the PCIe protocol on the bus 113. In some embodiments, the I / O circuit 112 may also include an adapter communicatively coupled to one or more client devices 101, and the host device 103 may store information received from the one or more client devices 101 in the NAND-based memory device 105. As shown, the memory 104 may include a host buffer 106 and a virtual logical block address (LBA) table 108. Further, in some embodiments, as specified by the NVMe protocol, the memory 104 may also implement other buffers such as a submission queue (SQ) and a completion queue (CQ) for submitting and completing NVMe commands (e.g., write commands, read commands, any other suitable commands, or a combination thereof).

[0022] The NAND-based memory device 105 includes a controller 114, resources 115, non-volatile memory (NVM) 122, a host interface 124, and processing circuitry 126. The NAND-based memory device 105 includes resources 115 for performing read and write operations between the host 103 and the NAND-based memory device 105, and for performing overhead operations required within the NAND-based memory device 105 (e.g., a garbage collection process on the NAND-based memory device 105). As referred to herein, resources 115 are allocated via processing circuitry 126 between the overhead operations of the host 103 and the NAND-based memory device 105, and it will be understood that the allocation of resources 115 may be changed (e.g., as a result of a feedback control process described later). Resources 115 include at least a die 116, a central processing unit (CPU) 118, and a buffer 120, but it will be understood that resources 115 may include other suitable elements necessary to perform the operations described above. In some embodiments, the NVM122 may comprise one or more packages of die 116. Each of the die 116 may comprise multiple memory cells (e.g., NAND memory cells), each capable of storing one or more bits of information. As will be understood by those skilled in the art, the memory cells may be organized into pages, and the pages may be organized into blocks (e.g., erasable units). In some embodiments, a buffer 120 may temporarily store information to be written to the NVM122, and the CPU 118 may write the information from the buffer 120 to the NVM122.

[0023] In some embodiments, the NAND-based memory device 105 may be configured as an NVMe PCIe solid-state drive (SSD), and thus the NAND-based memory device 105 can be coupled to a host 103 in a communicative manner using the PCIe protocol over bus 113. As described below, Figure 2 provides an example of such a configuration of the NAND-based memory device 105 as an SSD.

[0024] FIG. 2 shows a block diagram 200 of an exemplary solid state drive device 202 according to some embodiments of the present disclosure. As described above, the solid state drive device 202 is a NAND-based memory device and may be communicatively coupled to an external host using a configuration similar to that of FIG. 1. The exemplary solid state drive device 202 includes a processing circuit 204, a controller 211, and an NVM 218 (e.g., this may be the NVM 122 of FIG. 1) and has a corresponding output 220, although it will be understood that in other embodiments, other visual and / or physical components may be included or substituted.

[0025] The processing circuit 204 may be, for example, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), random access memory (RAM), read-only memory (ROM), any other suitable processing circuit, or a combination thereof. The processing circuit 204 includes a processor 206, an instruction buffer 208, and a resource 210. The resource 210 may include a die 212, a CPU 214, and a buffer 216. The resource 210 may also be, for example, resource 115 in Figure 1, and die 212, CPU 214, and buffer 216 may be die 116, CPU 118, and buffer 120, respectively. It will also be understood that the resource 210 is allocated between internal overhead operations such as a garbage collection process (e.g., via the processor 206) and other operations such as read and write operations from an externally coupled host. The processor 206 may reallocate the resource 210 (for example, in response to the feedback control system output), and in some embodiments, the instruction buffer 208 may be used to temporarily store the allocated instruction given by the processor 206 until the resource 210 has finished its current operation. In some embodiments, the instruction buffer 208 may be used to store instructions received from the controller 211, as described below.

[0026] The controller 211 includes a control manager 213 configured to link with the processing circuit 204 and transmit control signals to the processing circuit 204. In some embodiments, the processing circuit 204 may perform a process of allocating memory resources using multifactor feedback control. In some embodiments, the controller 211 may provide the processing circuit 204 with a period indicating the time between each iteration of the feedback control loop. In some embodiments, a host (e.g., host 103 in Figure 1) may be communicatively coupled to the solid-state drive device 202, and the controller 211 may be connected to a host interface (e.g., host interface 124) that receives read and write operation requests from the host and provides instruction management to the processing circuit 204 accordingly.

[0027] Figure 3 shows an illustrative diagram 300 of a data flow for allocating resources to a NAND-based memory device using feedback control 350, according to some embodiments of the present disclosure. Resources may be allocated between the garbage collection process of the NAND-based memory device and a communicably coupled host (for example, in resource allocation 360). The NAND-based memory device may be, for example, the solid-state drive device 202 in Figure 2 and connected to the host device 103 in Figure 1. In another preferred example, the NAND-based memory device may be the NAND-based memory device 105 in Figure 1. The coupling between the host and the NAND-based memory device may be the coupling process described in Figure 1. The data flow illustrated in diagram 300 may be executed, for example, by the processing circuit 204 in Figure 2. Although Figure 3 is described in the context of a particular structure, component, and process of the present disclosure, and a particular data flow is illustrated in Figure 3, it will be understood that in some embodiments, one or more steps may be changed, moved, deleted or added, and the data flow illustrated in Figure 3 may be modified.

[0028] The execution of the data flow in diagram 300 begins by determining the free space 302, the write amplification factor 304, and the period 306. The free space 302 of the NAND-based memory device (i.e., also referred herein as the available indirection unit, AIU, or amount of unused space) represents the amount of available storage in the memory device. Operations between the host and the memory device, such as read and write operations from the host, may decrease the free space of the memory device, while the internal garbage collection process by the memory device may increase the free space. It will be understood that decreasing the free space 302 (for example, so that the memory device approaches its logical capacity) may result in a decrease in the performance of the memory device, physical damage to the memory device, or a combination thereof. However, increasing the free space 302 also inevitably results in a decrease in the performance of the memory device. Therefore, in some embodiments, an optimal free area may be established that maximizes the performance of the NAND-based memory device (for example, by calculating input / output operations per second (IOP)) while also providing a sufficient free area margin to prevent device failure. If the free area 302 is larger than the optimal free area, more resources (e.g., buffers, dies, or CPU) may be allocated to the host, resulting in more read / write operations on the memory device. If the free area 302 is smaller than the optimal free area, more resources may be allocated to the garbage collection process of the NAND-based memory device. In some embodiments, the desired bandwidth ratio may be biased based on the amount of free area relative to the optimal free area.

[0029] The write amplification factor 304 of the memory device represents the ratio of data written to storage within the memory device to data written to the memory device by the host. For example, a write amplification factor of 4 indicates that for every unit of data written to the memory device by the host, 4 units of data are written to the memory device.

[0030] Time period 306 represents the time between each iteration of the data flow illustrated in diagram 300. For example, as shown, in each period 306, the free space 302 is updated, which inevitably leads to a new iteration of the feedback control process 350. However, it will be understood that other processes may also be calculated or determined in period 306. In some embodiments, for example, the number of write operations sent by the host to the NAND-based memory device between period 306 and the previous period may also be calculated. It will be understood that period 306 may be adjusted; for example, if period 306 is 250 ms, the feedback control process 350 may be crude, and reducing period 306 to 10 ms instead may result in a more refined feedback control process 350, at the cost of requiring more computation.

[0031] Subsequently, the desired bandwidth ratio 308 is calculated based on the free space 302 and the write amplification factor 304, although it will be understood that in other preferred embodiments, the desired bandwidth ratio 308 may be based on more or fewer factors or processes. For example, the desired bandwidth ratio 308 may be based on either the free space 302 or the write amplification factor 304 alone. Furthermore, it will be understood that when the free space 302 is updated every period 306, the desired bandwidth 308 is always recalculated based on the newly determined free space 302.

[0032] The data flow in diagram 300 includes a system operation 310 that describes the operation of the NAND-based memory device. In some embodiments, the system operation 310 includes, in each period 306, at least one or more write operations sent to the memory device by the host, one or more operations performed by the garbage collection process of the NAND-based memory device, or a combination thereof.

[0033] Continuing in the data flow of diagram 300, the host bandwidth 322 is determined by calculating a moving average of the write operations sent by the host to the NAND-based memory device. In some embodiments, the host bandwidth 322 may be a moving average of write operations, which may be determined by calculating the total number of write operations sent by the host to the memory device over a period 306 (e.g., during system operation 310). In some embodiments, the host bandwidth 322 may be calculated by further dividing the moving average by the period 306 (to obtain units of operations per unit of time) or by applying any known technique for calculating bandwidth. In each period 306, the number of write operations sent by the host to the memory device is recalculated, and the host bandwidth 322 is redetermined accordingly.

[0034] The NAND-based memory device bandwidth 324 is determined similarly to the host bandwidth 322. However, instead of the total number of host write operations, the total number of operations performed by the garbage collection process of the NAND-based memory device is divided by the period 306.

[0035] The desired bandwidth ratio 308, host bandwidth 322, and NAND-based memory device bandwidth 324 are then used in feedback control 350, which determines resource allocation 360. In feedback control 350, the actual bandwidth ratio is calculated based on the host bandwidth 322 and the NAND-based memory device bandwidth 324. Subsequently, an arbitration score is calculated based on the desired bandwidth ratio 308 and the actual bandwidth ratio. In some embodiments, the arbitration score may be the actual bandwidth ratio divided by the desired bandwidth ratio 308.

[0036] In some embodiments, the feedback control 350 may have or utilize different input factors, different outputs, different calculations, or combinations thereof. For example, the feedback control 350 may use a score based only on the write amplification factor 304 and the host bandwidth 322. In some embodiments, the feedback control 350 may not include score determination, and the resource allocation 360 may be determined based only on the free space 302. In some embodiments, the write amplification factor and the host bandwidth may be further weighted, and the arbitration score may be based on the weighted write amplification factor and the weighted host bandwidth. The sum of the weights may be equal to 1, and the weights may be adjusted based on the free space 302 (e.g., at each iteration of the feedback control 350).

[0037] The result of the data flow in diagram 300 is resource allocation 360, which allocates resources of the NAND-based memory device between the host and the memory device's garbage collection process. In some embodiments, resource allocation 360 may be proportional to an arbitration score calculated by feedback control 350. For example, if the score is calculated by dividing the actual bandwidth ratio by a desired bandwidth ratio 308, an increase in the score results in more resources being allocated to the garbage collection process, and a decrease in the score results in more resources being allocated to the host. In some embodiments, a range of scores may be used to determine resource allocation. For example, if the score is calculated by dividing the actual bandwidth ratio by a desired bandwidth ratio 308, no resource reallocation occurs if the score is between a first range of 0.95 and 1.05. If the score is between a second range of 0.5 and 1.5 (but not included in the first range), resource reallocation occurs, and if the score is greater than 1, more resources are allocated to the memory device's garbage collection process. If the score falls outside the second range, a larger resource allocation occurs. For example, a score greater than 1.5 results in more resources being allocated to the memory device garbage collection process than would be allocated for a score between 1 and 1.5.

[0038] Figure 4 shows an exemplary graph 400 of a function 402 of free space in a NAND-based memory device over a period of time, without a feedback control process for reallocating memory device resources, according to some embodiments of the present disclosure. In particular, exemplary graph 400 includes a function 402 of free space over time, includes an optimal free space 404, and illustrates an exemplary comparison of the free space represented by function 402 and the optimal free space 404 in a NAND-based memory device without a feedback control process. It will be understood that the free space represented by function 402 may be, for example, the free space 302 shown in Figure 3.

[0039] Graph 400 includes a horizontal axis representing time and a vertical axis corresponding to the free space of the memory device (i.e., the free space is represented by the number of AITs). As shown, function 402 illustrates how the free space of the memory device changes over time. Since an increase in free space leads to a decrease in performance, and a decrease in free space also leads to the possibility of physical damage to the memory device and a decrease in performance, a NAND-based memory device has an optimal free space 404 that represents the AIT required to maximize the performance of the memory device (e.g., as shown in Figure 3 above and determined by IOPs).

[0040] Figure 5 shows a line graph 500 representing the free space and corresponding bias 510 of a NAND-based memory device according to several embodiments of the present disclosure. In particular, Figure 5 illustrates how the bias 510 changes in response to changes in the free space (e.g., moving left and right on axis 501) in a system that allocates resources of a NAND-based memory device using feedback control (e.g., the data flow described in Figure 3). The exemplary line graph 500 includes axis 501, optimal free space 502, increased free space 504, urgent reduction free space 506, and critical reduction free space 508.

[0041] Line graph 500 has an axis 501 representing AIT (e.g., free space) in a NAND-based memory device. It will be understood that the free space in a NAND-based memory device may be, for example, the free space 302 shown in Figure 3. Further understanding is that moving to the left on the axis results in an increase in free space, and moving to the right results in a decrease in free space. Furthermore, the optimal free space 502 corresponds to the optimal free space 402 shown in Figure 4. Therefore, the increased free space 504 indicates that the free space is higher than the optimal amount, and the urgently reduced free space 506 and critically reduced free space 508 indicate that the free space is lower than the optimal amount.

[0042] The bias 510 represents the absolute value obtained by subtracting the percentage of resources allocated to the garbage collection process of the NAND-based memory device from the percentage of resources allocated to the host. For example, in increased free space 504, the bias 510 may be 20%, and in urgently decreased free space 506, the bias 510 may be 10%. However, as shown in Figure 3, an increase in free space results in more resources being allocated to the host. Therefore, in increased free space 504, a bias 510 of 20% would be understood to mean that an additional 20% of resources are allocated to the host compared to the resources allocated to the garbage collection process. In urgently decreased free space 506, a bias 510 of 10% means that an additional 10% of resources are allocated to garbage collection compared to the resources allocated to the host. In critically reduced free space 508, the bias 510 is 100%, which indicates that all resources are allocated to the garbage collection process.

[0043] It will be understood that bias 510 is not necessarily linearly proportional to the available space. For example, if the output of a feedback control process depends on calculating an arbitration score and then determining the range in which that score exists, then bias 510 is not a linear process.

[0044] In some embodiments, critically decreased free space 508 may represent the logical capacity, physical capacity, or both of the NAND-based memory device (for example, performing additional write operations on the memory device may result in physical damage). Therefore, in order to prevent the free space from decreasing beyond critically decreased free space 508, the rate of change of the bias 510 may be increased in the urgently decreased free space 506. For example, if the free space decreases from the optimal free space 502, the bias 510 may change at a first rate. If the free space decreases below the urgently decreased free space 506, the bias 510 may change at a second rate higher than the first rate.

[0045] Figure 6 shows an exemplary graph 600 of a function 602 of free space in a NAND-based memory device over a period of time, with a feedback control process for reallocating memory device resources, according to some embodiments of the present disclosure. In particular, the exemplary graph 600 illustrates an exemplary comparison of free space represented by function 602 and optimal free space 604 in a NAND-based memory device, with a feedback control process, including a function 602 of free space over time, and an optimal free space 604 (for example, function 602 and optimal free space 604 may have designs and functions corresponding to function 402 and optimal free space 404 in Figure 4, respectively). It will be understood that the free space represented by function 602 may be, for example, the free space 302 shown in Figure 3.

[0046] As shown, for most of the time (time is represented by the horizontal axis in graphs 600 and 400), the absolute distance from function 602 to the optimal free area 604 is smaller than the absolute distance from function 402 to the optimal free area 404 at the corresponding time. In some embodiments, at the optimal free area 604, the feedback control process allocates resources equally between the host and the garbage collection process of the NAND-based memory device. As the free area decreases (e.g., below the optimal free area 604), the feedback control process allocates more resources to the garbage collection process, resulting in an increase in the free area. As the free area increases (e.g., above the optimal free area 604), the feedback control process allocates more resources to the host's read / write operations, resulting in a decrease in the free area.

[0047] Figure 7 shows an illustrative diagram 700 of a data flow using weighted feedback control 750 to allocate resources for a NAND-based memory device, according to several embodiments of the present disclosure. Resources may be allocated between the garbage collection process of the NAND-based memory device and a communicably coupled host (for example, in resource allocation 760). The NAND-based memory device may be, for example, the solid-state drive device 202 in Figure 2, and may be connected to the host device 103 in Figure 1. In another preferred example, the NAND-based memory device may be the NAND-based memory device 105 in Figure 1. The coupling between the host and the NAND-based memory device may be the coupling process described in Figure 1. The data flow illustrated in diagram 700 may be executed, for example, by the processing circuit 204 in Figure 2. Although Figure 7 is described in the context of a particular structure, component, and process of the present disclosure, and a particular data flow is illustrated in Figure 7, it will be understood that in some embodiments, one or more steps may be changed, moved, deleted or added, and the data flow illustrated in Figure 7 may be modified.

[0048] The execution of the data flow in diagram 700 begins by determining the free space 702 and the write amplification factor 704. The free space 702 may be, for example, the free space 302 in Figure 3, and the write amplification factor 704 may be the write amplification factor 304. The desired bandwidth ratio 708 (for example, the desired bandwidth ratio 308 in Figure 3) may be calculated based on the free space 702 and the write amplification factor 704, but it will be understood that the desired bandwidth ratio 708 may be based on more or fewer factors or processes.

[0049] The free space 702 may be used to determine the bandwidth weights 712 and the ratio weights 714. In some embodiments, the bandwidth weights 712 may be a number between 0 and 1, and the ratio weights 714 may be the result of subtracting the bandwidth weights 712 from 1. In some embodiments, as the free space 702 approaches the target, the optimal free space (e.g., the optimal free space 402 shown in Figure 4), the bandwidth weights 712 may increase and the ratio weights 714 may decrease accordingly.

[0050] The data flow in diagram 700 also includes host bandwidth 722 and garbage collection bandwidth 724 (for example, that of a NAND-based memory device), where host bandwidth 722 may be host bandwidth 322 in Figure 3, and garbage collection bandwidth 724 may be NAND-based memory bandwidth 324 in Figure 3. As shown in Figure 3, host bandwidth 722 and garbage collection bandwidth 724 may be determined based on system operation (for example, system operation 310 in Figure 3) occurring in parallel with the feedback control data flow. Host bandwidth 722 may be averaged over a period (for example, period 306 in Figure 3) to determine a moving average host bandwidth, and the measured host bandwidth 722 may then be divided by the determined moving average host bandwidth to calculate a bandwidth score 730. The bandwidth score 730 may therefore measure, for example, how closely the measured host bandwidth 722 matches the moving average host bandwidth. For example, a bandwidth score of 730 equal to 1 may indicate that the host bandwidth matches the moving average host bandwidth, and may also indicate that the host IOPs are consistent.

[0051] The host bandwidth 722, garbage collection bandwidth 724, and desired bandwidth ratio 708 are then used to determine the ratio score 740. In some embodiments, the actual bandwidth ratio may be calculated based on the host bandwidth 722 and the garbage collection bandwidth 724. The actual bandwidth ratio may then be divided by the desired bandwidth ratio 708 to calculate the ratio score 740. The ratio score 740 may measure how closely the actual bandwidth ratio matches the desired bandwidth ratio 708. For example, a ratio score 740 equal to 1 may indicate that the actual bandwidth ratio matches the desired bandwidth ratio 708 and that the free space 702 is consistent.

[0052] The bandwidth score 730, ratio score 740, bandwidth weight 712, and ratio weight 714 are then used as inputs in the weighted feedback control 750, although it will be understood that the weighted feedback control 750 may have more or fewer preferred inputs. In the weighted feedback control 750, the arbitration score may be calculated as a weighted average based on the input elements. In some embodiments, the bandwidth score 730 may be multiplied by the bandwidth weight 712, and the ratio score may be multiplied by the ratio weight 714, and the arbitration score may be determined by adding the two resulting values.

[0053] The result of data flow 700 is resource allocation 760, which allocates resources for the NAND-based memory device between the host and the memory device's garbage collection process. In some embodiments, resource allocation 760 may be proportional to the arbitration score calculated by feedback control 750. In some embodiments, an increase in the score results in more resources being allocated to the garbage collection process, and a decrease in the score results in more resources being allocated to the host. In some embodiments, a range of scores may be used to determine resource allocation. For example, if the score is between a first range of 0.95 and 1.05, no resource reallocation occurs. If the score is in a second range of 0.5 and 1.5 (but not included in the first range), resource reallocation occurs, and if the score is greater than 1, more resources are allocated to the memory device's garbage collection process. If the score is outside the second range, a larger resource allocation occurs. For example, a score greater than 1.5 results in more resources being allocated to the memory device's garbage collection process than for scores between 1 and 1.5. Based on resource allocation 760, the host bandwidth 722 and garbage collection bandwidth 724 to be used in the next iteration of data flow 700 are then determined using the corresponding system operation in the NAND-based memory device.

[0054] Figure 8 shows a flowchart of exemplary steps for allocating resources to a specific NAND-based memory device using feedback control, according to some embodiments of the present disclosure. The steps of the flowchart 800 illustrated in Figure 8 may be performed, for example, by the processing circuit 204 in Figure 2. Although Figure 8 is described in the context of the specific structures, components, and processes of the present disclosure, and although a specific order and flow of steps is illustrated in Figure 8, it will be understood that in some embodiments one or more steps may be changed, moved, deleted or added, and the order of the steps illustrated in Figure 8 may be changed.

[0055] An exemplary step for allocating resources to a NAND-based memory device begins in step 802, where the write amplification factor for the NAND-based memory device and the host coupled to the memory device is determined. The write amplification factor represents the ratio of data written to storage in the memory device to data written to the memory device by the host. For example, if the write amplification factor is 4, it means that for every unit of data written to the memory device by the host, 4 units of data in the memory device are used to store the unit of data written by the host. The process may then proceed to step 804.

[0056] In step 804, the host bandwidth is calculated. The host bandwidth may be calculated using any known technique for calculating bandwidth, or it may be based on the number of write operations from the host to the memory device over a period of time. In some embodiments, the number of write operations from the host to the memory device may be determined for each period, and the host bandwidth may be recalculated accordingly for each period. The process may then proceed to step 806.

[0057] In step 806, resources for the NAND-based memory device are allocated based on the write amplification factor and the host bandwidth. The resources may be at least one of the die, CPU, or buffer, and the resources are allocated at least between the host and the garbage collection process of the NAND-based memory device.

[0058] It will be understood that Figure 8 illustrates the exemplary steps for a single iteration of the feedback control process for allocating resources to a NAND-based memory device. However, it will be understood that allocating resources may directly result in changes to the write amplification factor, host bandwidth, other relevant factors, or combinations thereof. Therefore, the steps in Figure 8 may be repeated to create a feedback control loop, where, after resource allocation, the host write amplification factor and bandwidth are recalculated, and resources are further reallocated based on the newly determined write amplification factor and host bandwidth.

[0059] Figure 9 shows a flowchart 900 of exemplary steps in which resources of a NAND-based memory device are allocated in a particular embodiment. As shown in Figure 7, the steps of the flowchart 900 illustrated in Figure 9 may be performed by the processing circuit 204 in Figure 2. Furthermore, although a particular order and flow of steps is illustrated in Figure 9, it will be understood that in some other embodiments, one or more steps may be changed, moved, deleted, or added, and the order of the steps illustrated in Figure 9 may be changed.

[0060] An exemplary step for determining how the resources of the memory device are allocated begins in step 902, where a desired bandwidth ratio is calculated based on the free space (i.e., the number of available indirection units) and the write amplification factor. However, it will be understood that the desired bandwidth ratio may be calculated based on different factors in other embodiments. For example, the desired bandwidth ratio may be calculated based solely on the write amplification factor. The process may then proceed to step 904.

[0061] In step 904, the actual bandwidth ratio is calculated based on host write statistics to the NAND-based memory device and NAND-based memory write statistics. For example, the statistics may be a moving average of writes over a period of time. In another preferred example, any known technique may be further applied to the moving average to determine the host bandwidth and the NAND-based memory device bandwidth. The actual bandwidth ratio may be determined, for example, by dividing the host bandwidth by the NAND-based memory device bandwidth, but it will be understood that the actual bandwidth ratio may be determined using other preferred processes. Once the actual bandwidth ratio is calculated, the process may then proceed to step 906.

[0062] In step 906, the arbitration score is calculated based on the desired bandwidth ratio and the actual bandwidth ratio. For example, the actual bandwidth ratio may be divided by the desired bandwidth ratio. However, it will be understood that in other embodiments, in different processes, other factors may be used and / or substituted to calculate the score. For example, the score may be calculated based only on the write amplification factor and the host bandwidth. In some embodiments, the write amplification factor and the host bandwidth may be further weighted, and the arbitration score may be based on the weighted write amplification factor and the weighted host bandwidth. The sum of the weights may be equal to 1, and the weights may be adjusted based on available space.

[0063] The process then proceeds to step 908, where the arbitration score determined in step 906 is compared to a first range. For example, if the score is the actual bandwidth ratio divided by the desired bandwidth ratio, a suitable first range may be 0.95 to 1.05. If the score is within the first range (yes in step 908), the process proceeds to step 910, where it is determined that no adjustment to resource allocation occurs, and the process loops back to step 902. If the score is not within the first range (no in step 908), the process may then proceed to step 912.

[0064] In step 912, the arbitration score may then be compared to a second range. If the score is the actual bandwidth ratio divided by the desired bandwidth ratio, a preferred second range may be 0.5 to 1.5. If the score is within the second range (yes in step 912), the process proceeds to step 914, where a small adjustment to the resource allocation occurs, and then loops back to step 902. If the score is not within the second range (no in step 912), the process proceeds to step 916, where a larger adjustment to the resource allocation occurs, and then loops back to step 902. For example, in the particular embodiment shown in Figure 9, if the score is greater than 1, more resources are allocated to the garbage collection process for the NAND-based memory device, and if the score is less than 1, more resources are allocated to the host.

[0065] The matters described above are merely illustrative of the principles of this disclosure, and various modifications may be made by those skilled in the art without departing from the scope of this disclosure. The embodiments described above are presented for illustrative purposes only and are not intended to be limiting. This disclosure can take many other configurations other than those expressly described herein. Accordingly, this disclosure is not limited to the methods, systems, and apparatus expressly disclosed, but is intended to include variations and modifications thereof that are included in the spirit of the following paragraphs.

[0066] While some parts of this disclosure may refer to examples, such references are solely for the purpose of providing context to this disclosure and do not constitute any determination of the state of the art.

Claims

1. A step of using a processing circuit to determine the write amplification factor for a specific NAND-based memory device and a host coupled to the NAND-based memory device; A step of calculating the bandwidth of the host using the processing circuit; and The process involves using the processing circuit to allocate resources to the NAND-based memory device based on the write amplification factor and the host's bandwidth. A method for providing this.

2. The step of allocating the resources of the NAND-based memory device based on the write amplification factor and the host's bandwidth is: A step of calculating a score based on the light amplification factor and the bandwidth of the host; and The step of allocating the resources of the NAND-based memory device based on the score. The method according to claim 1, comprising:

3. The steps for calculating the aforementioned score are: A step of determining a desired bandwidth ratio based on the light amplification factor; a step of determining an actual bandwidth ratio based on the bandwidth of the host; and a step of calculating the score based on the actual bandwidth ratio and the desired bandwidth ratio. The method according to claim 2, including the method described in claim 2.

4. The method according to claim 2, wherein the score is further based on a weighted average of the light amplification factor and the bandwidth of the host.

5. The method according to claim 4, wherein the write amplification factor and the host bandwidth are weighted based on the amount of unused free space.

6. The method according to claim 1, wherein the NAND-based memory device is a solid-state drive.

7. The method according to claim 1, wherein the step of calculating the bandwidth of the host includes the step of calculating the number of write operations transmitted by the host to the NAND-based memory device over a certain period of time.

8. The method according to claim 7, wherein the step of calculating the bandwidth of the host further comprises the step of calculating a moving average of the number of write operations.

9. The method according to claim 1, wherein the step of allocating the resources of the NAND-based memory device is further based on the amount of unused area of ​​the NAND-based memory device.

10. The method according to claim 9, wherein the reduction in the amount of unused area results in allocating more of the resources to the garbage collection process of the NAND-based memory device.

11. The method according to any one of claims 1 to 10, wherein the resource is at least one of a buffer, a CPU, or a die.

12. host; NAND-based memory device; Processing circuit A system comprising: The write amplification factor is determined for the NAND-based memory device and the host coupled to the NAND-based memory device; The bandwidth of the aforementioned host is calculated; The resources of the NAND-based memory device are allocated based on the write amplification factor and the bandwidth of the host. A system designed for that purpose.

13. The procedure for allocating the resources of the NAND-based memory device based on the write amplification factor and the host bandwidth is as follows: A procedure for calculating a score based on the light amplification factor and the bandwidth of the host; and Procedure for allocating the resources of the NAND-based memory device based on the score. The system according to claim 12, including the above.

14. The system according to claim 12, wherein the NAND-based memory device is a solid-state drive.

15. The system according to claim 12, wherein the procedure for calculating the bandwidth of the host includes a procedure for calculating the number of write operations transmitted by the host to the NAND-based memory device over a period of time.

16. The system according to claim 12, wherein the procedure for calculating the bandwidth of the host further includes a procedure for calculating a moving average of the number of write operations.

17. The system according to claim 12, wherein the procedure for allocating the resources of the NAND-based memory device is further based on the amount of unused area of ​​the NAND-based memory device.

18. The system according to claim 17, wherein a reduction in the amount of unused area results in more resources being allocated to the NAND-based memory device.

19. The system according to any one of claims 12 to 18, wherein the resource is at least one of a buffer, a CPU, or a die.

20. At runtime: A procedure for determining the write amplification factor for a specific NAND-based memory device and a host coupled to the NAND-based memory device; A procedure for calculating the bandwidth of the host using a processing circuit; and A procedure for using the processing circuit to allocate resources of the NAND-based memory device based on the write amplification factor and the host bandwidth. A computer program that includes program code that causes a processor to execute a method that includes the following.

21. The procedure for allocating the resources of the NAND-based memory device based on the write amplification factor and the host bandwidth is as follows: A procedure for calculating a score based on the light amplification factor and the bandwidth of the host; and Procedure for allocating the resources of the NAND-based memory device based on the score. A computer program according to claim 20, having the following characteristics.

22. The computer program according to claim 20, wherein the NAND-based memory device is a solid-state drive.

23. The computer program according to claim 20, wherein the procedure for calculating the bandwidth of the host includes a procedure for calculating the number of write operations transmitted by the host to the NAND-based memory device over a period of time.

24. The computer program according to claim 23, wherein the procedure for calculating the bandwidth of the host further comprises a procedure for calculating a moving average of the number of write operations.

25. The computer program according to claim 20, wherein the procedure for allocating the resources of the NAND-based memory device is further based on the amount of unused area of ​​the NAND-based memory device.

26. The computer program according to claim 25, wherein a reduction in the amount of unused area results in more resources being allocated to the NAND-based memory device.

27. The computer program according to any one of claims 20 to 26, wherein the resource is at least one of a buffer, a CPU, or a die.

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