Methods for improving the quality of silicon-containing materials

Abstract

Exemplary methods for forming silicon and carbon-containing materials may include providing a silicon-containing precursor in a processing area of ​​a semiconductor processing chamber. A substrate may be housed within the processing area of ​​the semiconductor processing chamber. The method may also include providing a hydrogen-containing precursor in the processing area. The method may also include generating plasma effluents of the silicon-containing precursor and the hydrogen-containing precursor in the processing area. The plasma effluents can be generated at frequencies exceeding 15 MHz. The method may also include depositing the silicon-containing material onto a substrate.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 192,557, "METHODS TO IMPROVE QUALITY SILICON - CONTAINING MATERIALS," filed on March 29, 2023, which is hereby incorporated by reference in its entirety.

[0002] Technical Field

[0002] This technology relates to deposition processes and chambers. More particularly, this technology relates to methods for manufacturing silicon - containing materials with improved film quality.

Background Art

[0003] Background

[0003] Integrated circuits are enabled by processes that create complex patterned layers of material on a substrate surface. Manufacturing patterned materials on a substrate requires controlled methods for forming and removing materials. The properties of the materials can affect how the device operates and also how the films are removed relative to each other. Plasma - enhanced deposition can create films with specific properties. Many of the films formed require additional processing to adjust or enhance the material properties of the film in order to provide appropriate properties.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high - quality devices and structures. These needs and others are addressed by this technology.

Summary of the Invention

[0005] Summary

[0005] An exemplary method for forming silicon and carbon-containing materials may include providing a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be housed within the processing area of ​​the semiconductor processing chamber. The method may include providing a hydrogen-containing precursor to the processing area. The method may include generating plasma effluent of the silicon-containing precursor and plasma effluent of the hydrogen-containing precursor in the processing area. The plasma effluent can be generated at a frequency above 15 MHz. The method may include depositing the silicon-containing material onto a substrate.

[0006]

[0006] In some embodiments, the silicon-containing precursor may be or may include tetraethyl orthosilicate (TEOS). The hydrogen-containing precursor may be about 5% or less of the total flow rate of the precursor supplied to the processing area. The plasma power can be maintained at 1000 W or less while generating plasma effluent of the silicon-containing precursor and the hydrogen-containing precursor. During this method, the temperature in the semiconductor processing chamber can be maintained at about 600°C or less. During this method, the pressure in the semiconductor processing chamber can be maintained at about 30 Torr or less. This method may include performing post-deposition treatment on the silicon-containing material. By performing post-deposition treatment, the oxygen content in the silicon-containing material can be increased. Post-deposition treatment may include exposing the silicon-containing material to ultraviolet light. Post-deposition treatment may include annealing the silicon-containing material in the presence of a second hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor.

[0007]

[0007] Some embodiments of the present technology encompass semiconductor processing methods. The method may include providing a silicon-containing precursor into a processing area of ​​a semiconductor processing chamber. A substrate may be housed in the processing area of ​​the semiconductor processing chamber. The method may include generating a plasma effluent of the silicon-containing precursor within the processing area. The method may include depositing a silicon-containing material onto the substrate. The method may include performing a post-deposition treatment on the silicon-containing material. Performing a post-deposition treatment increases the oxygen content in the silicon-containing material.

[0008]

[0008] In some embodiments, the substrate may define one or more features. Plasma effervescence can be generated at frequencies above 15 MHz. The method may include providing a hydrogen-containing precursor to the processing area. The hydrogen-containing precursor may be molecular hydrogen (H2) or may contain molecular hydrogen (H2). Post-deposition treatment may include exposing the silicon-containing material to ultraviolet light in the presence of an inert precursor or an oxygen-containing precursor. Post-deposition treatment may include annealing the silicon-containing material at a temperature of about 600°C or less.

[0009]

[0009] Some embodiments of the present technology encompass semiconductor processing methods. The method may include providing a silicon-containing precursor into a processing area of ​​a semiconductor processing chamber. A substrate may be housed in the processing area of ​​the semiconductor processing chamber. The method may include providing a hydrogen-containing precursor into the processing area. The method may include generating plasma emissions of the silicon-containing precursor and plasma emissions of the hydrogen-containing precursor in the processing area. The plasma emissions can be generated at frequencies above 15 MHz. The method may include depositing a silicon-containing material onto a substrate. The method may include performing a post-deposition treatment on the silicon-containing material. By performing a post-deposition treatment, the oxygen content in the silicon-containing material can be increased.

[0010]

[0010] In some embodiments, the hydrogen content in the silicon-containing material can be reduced by performing post-deposition treatment. This method may include stopping the flow of silicon-containing precursor and hydrogen-containing precursor before performing post-deposition treatment.

[0011]

[0011] Such technologies can offer many advantages over conventional systems and technologies. For example, by utilizing higher frequency power, the deposition characteristics of silicon-containing materials can be improved. Furthermore, by performing post-deposition treatment on the deposited silicon-containing material, the quality of the silicon-containing material can be further improved. These and other embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0012]

[0012] The nature and advantages of the disclosed technology will be further understood by referring to the remainder of the specification and the drawings.

[0013] [Figure 1]

[0013] This is a top view of an exemplary processing system according to some embodiments of the present technology. [Figure 2]

[0014] This is a schematic cross-sectional view of an exemplary plasma system according to several embodiments of this technology. [Figure 3]

[0015] The operation of an exemplary semiconductor processing method according to several embodiments of this technology is shown. [Figure 4A]

[0016] According to several embodiments of this technology, material layers are included, and the resulting exemplary schematic cross-sectional structure is shown. [Figure 4B]

[0015] An exemplary schematic cross-sectional structure, which includes and is produced by some embodiments of the technology of the present invention, is shown. [Modes for carrying out the invention]

[0014]

[0017] Some of the diagrams are included as circuit diagrams. Please understand that the diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include exaggerated material for illustrative purposes.

[0015]

[0018] In the attached diagrams, similar components and / or features may have the same reference label. Furthermore, various components of the same type can be distinguished according to their reference designation by letters that distinguish similar components from each other. Where only the first reference designation is used herein, the description is applicable to any of the similar components having the same first reference designation, regardless of the letters.

[0016] Detailed explanation

[0019] During semiconductor processing, materials can be deposited for gap-filling operations such as step filling in 3D NAND applications. These materials can be deposited by plasma-enhanced chemical vapor deposition (PECVD). As device sizes continue to shrink, the properties of the plasma may make it difficult to deposit materials such as silicon-containing materials on the sidewalls of the features being filled with sufficiently high quality. Materials deposited with lower quality than desired may be less resistant to etching operations than materials deposited in the center of the features being filled. Poor quality materials on the sidewalls may etch faster than other materials, potentially resulting in uneven material remaining throughout the previously filled features.

[0017]

[0020] This technology can overcome these problems by providing silicon-containing materials characterized by higher quality, either in their as-deposited state or after post-deposit processing. By performing deposition at higher plasma frequencies, the quality of sidewall materials can be improved. Furthermore, by including hydrogen-containing precursors during deposition, film interactions can lead to the creation of high-quality silicon-containing materials, particularly in the sidewalls. This technology also includes post-deposit operations to further modify the deposited film. Post-deposit operations can also reorganize the structure of the deposited silicon-containing material. For example, post-deposit operations can reorganize the bonds within the material, resulting in a higher-quality material. This technology can overcome the natural tendency for material deposited in the sidewalls to be of lower quality than material deposited near the center of a feature.

[0018]

[0021] While the remaining disclosure routinely identifies specific deposition processes that utilize the disclosed technology, it will be readily apparent that the systems and methods are equally applicable to other deposition and washing chambers, as well as to processes that may occur in the chambers described. Therefore, the technology should not be considered limited to use with these specific deposition processes or chambers alone. Before describing additional details of embodiments of the technology, this disclosure describes one possible system and chamber that can be used to perform a deposition process according to embodiments of the technology.

[0019]

[0022] FIG. 1 shows a plan view of one embodiment of a processing system 100 for deposition, etching, firing, and curing chambers according to an embodiment. In the figure, a pair of front-opening unified pods 102 are received by a robot arm 104 and placed in a low-pressure holding area 106 before being positioned in one of the substrate processing chambers 108a-108f located in tandem sections 109a-109c to supply substrates of various sizes. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each of the substrate processing chambers 108a-108f can be equipped to perform several substrate processing operations, including forming a stack of semiconductor materials described herein, in addition to plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etching, pre-cleaning, degassing, orientation, and annealing, ashing, and other substrate processing.

[0020]

[0023] The substrate processing chambers 108a-108f can include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) can be used to deposit a dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-108b) can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-108f) can be configured such that dielectric films on the substrate deposit alternating laminates. Any one or more of the described processes can be performed in a chamber separated from the manufacturing system shown in various embodiments. Additional configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for dielectric films are contemplated by the system 100.

[0021]

[0024] Figure 2 shows a schematic cross-sectional view of an exemplary plasma system 200 according to several embodiments of the present technology. The plasma system 200 shows a pair of processing chambers 108 that can be mounted on one or more of the tandem sections 109 described above, and these processing chambers 108 include a lid stack component according to embodiments of the present technology, which will be further described below. The plasma system 200 may generally include a chamber body 202 having side walls 212, a bottom wall 216, and an internal side wall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A and 220B may be similarly configured and may include the same components.

[0022]

[0025] For example, the processing region 220B may have components included in the processing region 220A and may include a pedestal 228 positioned in the processing region through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a main body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, which can heat and control the substrate temperature at a desired processing temperature. The pedestal 228 may be heated by a remote heating element, such as a lamp assembly, or by other heating devices.

[0023]

[0026] The body of the pedestal 228 can be connected to the stem 226 by a flange 233. The stem 226 can electrically connect the pedestal 228 to the power output or power box 203. The power box 203 can include a drive system that controls the raising and movement of the pedestal 228 within the processing area 220B. The stem 226 can also include a power interface for supplying power to the pedestal 228. The power box 203 can also include an interface for power and temperature indicators, such as a thermocouple interface. The stem 226 can include a base assembly 238 adapted to removably connect to the power box 203. A circumferential ring 235 is shown on top of the power box 203. In some embodiments, the circumferential ring 235 can be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0024]

[0027] The rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing area 220B and can also be used to position a substrate lift pin 261 disposed through the body of the pedestal 228. The substrate lift pin 261 can selectively space the substrate 229 from the pedestal to facilitate the replacement of the substrate 229 using a robot utilized to transfer the substrate 229 into and out of the processing area 220B through the substrate transfer port 260.

[0025]

[0028] A chamber lid 204 may be connected to the top of the chamber body 202. The lid 204 may house one or more precursor distribution systems 208 connected thereto. The precursor distribution system 208 may include a precursor inlet passage 240, which can supply reactants and washing precursors into the processing area 220B through a dual-channel showerhead 218. The dual-channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 positioned in the middle of the faceplate 246. A radio frequency (RF) source 265 may be connected to the dual-channel showerhead 218, which can power the dual-channel showerhead 218 to facilitate the generation of a plasma region between the faceplate 246 and the pedestal 228 of the dual-channel showerhead 218. The dual-channel showerhead 218 and / or faceplate 246 may include one or more openings that allow the flow of precursors from the precursor distribution system 208 to the processing areas 220A and / or 220B. In some embodiments, the opening may include at least one of a linear opening and a conical opening. In some embodiments, an RF source may be connected to other parts of the chamber body 202, such as a pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be placed between the lid 204 and the dual-channel showerhead 218 to prevent the conduction of RF power to the lid 204. A shadow ring 206 that engages with the pedestal 228 may be placed around the pedestal 228.

[0026]

[0029] To cool the annular base plate 248 during operation, optional cooling channels 247 can be formed in the annular base plate 248 of the precursor distribution system 208. A heat transfer fluid (e.g., water, ethylene glycol, gas, etc.) can be circulated through the cooling channels 247 so that the base plate 248 can be maintained at a predetermined temperature. To prevent the side walls 201, 212 from being exposed to the processing environment in the processing area 220B, a liner assembly 227 can be positioned in the processing area 220B adjacent to the side walls 201, 212 of the chamber body 202. The liner assembly 227 may include a circumferential pumping cavity 225 which can be connected to a pumping system 264 configured to exhaust gases and by-products from the processing area 220B and to control the pressure within the processing area 220B. Multiple exhaust ports 231 can be formed on the liner assembly 227. The exhaust port 231 may be configured to allow gas to flow from the processing area 220B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200.

[0027]

[0030] Figure 3 shows an exemplary process in the semiconductor processing method 300 according to several embodiments of the present technology. Method 300 can be performed in a variety of processing chambers, including the processing system 200 described above, as well as any other chambers in which plasma deposition may be performed. Method 300 may include several optional operating steps, which may or may not be particularly associated with certain embodiments of the method according to the present technology. For example, many of the operating steps described are provided to offer a broader range of structure formation, but may not be critical to the technology or may be performed by alternative methods for ease of understanding.

[0028]

[0031] Method 300 may include additional operations before commencing the listed operations. For example, additional processing steps may include forming a structure on the semiconductor substrate, including both forming and removing material. The pre-processing steps may be performed in the chamber in which Method 300 may be carried out, or the processing may be carried out in one or more other processing chambers before the substrate is supplied to the semiconductor processing chamber in which Method 300 may be carried out. Nevertheless, Method 300 may optionally include transporting the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 200 described above, or another chamber that may include the components described above. The substrate may be placed on a substrate support, such as a pedestal 228, which may be located within a processing area of ​​a chamber, such as the processing area 220 described above. Method 300 illustrates the process schematically shown in Figures 4A and 4B, which will be described in conjunction with the process of Method 300. Figures 4A and 4B show only partial schematic diagrams of an exemplary structure 400, and it should be understood that the substrate 405 may include any number of additional materials and features having various properties and characteristics, as shown in the figures.

[0029]

[0032] As shown in Figure 4A, the substrate 405 can be any number of materials on which deposition can be performed. The substrate 405 may be a dielectric material containing silicon, germanium, silicon oxide, or silicon nitride, a metallic material, or any number of combinations of these materials, or may contain these materials, and may be a substrate or a material formed on the substrate. Various materials can be formed on the substrate 405. For example, material 410 can be formed on the substrate 405. As shown, material 410 may contain features 415. The aspect ratio of feature 410, or the ratio of the depth of the feature to the width or diameter of the formed feature, may be about 1:1 or greater, about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, or greater. Although only one feature 410 is shown, it should be understood that in exemplary structures according to embodiments of the present invention, any number of features 410 may be defined along the structure. In this embodiment, the structure 400 may be a 3D NAND structure.

[0030]

[0033] Method 300 includes a deposition process such as a PECVD operation, which can form a silicon-containing material on a substrate with improved material quality of the feature sidewalls. Method 300, shown in Figure 3, includes introducing one or more precursors into a semiconductor processing chamber in operation step 305, thereby supplying a precursor or precursor material to the processing area of ​​the semiconductor processing chamber, which contains a substrate such as a substrate 405.

[0031]

[0034] In embodiments, the precursor supplied in operation 305 may be a silicon-containing precursor or may contain a silicon-containing precursor. The silicon-containing precursor that can be used in operation step 305 of Method 300 may be any number of silicon-containing precursors or may contain any number of silicon-containing precursors. For example, the silicon-containing precursor may be silane (SiH4), disilane (Si2H6), trisilane (Si3H8), silicon tetrachloride (SiCl4), tetraethyl orthosilicate (TEOS), or any other precursor capable of forming a silicon-containing material such as silicon oxide (SiO) material, or may contain these. In embodiments of the present technique, higher-order silanes can be used, but the increased hydrogen content in the deposited material may lead to gas release in subsequent operations.

[0032]

[0035] In an optional step 310, Method 300 may include providing a hydrogen-containing precursor to a processing area. In embodiments, the hydrogen-containing precursor may be provided together with a silicon-containing precursor. The hydrogen-containing precursor and the silicon-containing precursor may be mixed before being provided to the processing area. However, it is conceivable that the hydrogen-containing precursor and the silicon-containing precursor may be left separate before being provided to the processing area. The hydrogen-containing precursor that can be used in the optional step 310 of Method 300 may be any number of hydrogen-containing precursors or may include any number of hydrogen-containing precursors. For example, the hydrogen-containing precursor may be molecular hydrogen (H2), water vapor (H2O), or any other precursor useful for forming silicon-containing materials such as silicon oxide (SiO) materials, or may include these.

[0033]

[0036] The precursors provided in operations 305 and / or 310 may also include any number of carrier gases, which may include nitrogen, helium, argon, or other noble, inert, or useful precursors. The carrier gases can be used to dilute silicon-containing or hydrogen-containing precursors, thereby reducing the deposition rate and allowing for better control of the deposition. However, it is conceivable that the precursors may also be provided without other gases.

[0034]

[0037] In the embodiment, the flow rate of the hydrogen-containing precursor may affect the deposition of the silicon-containing material. If the flow rate of the hydrogen-containing precursor is high, additional hydrogen may be incorporated into the deposited material, which may lead to gas release in subsequent operations, as described above. Therefore, the hydrogen-containing precursor can constitute about 5% or less of the total flow rate of the precursor supplied to the processing area, for example, about 4.5% or less, about 4% or less, about 3.5% or less, about 3% or less, about 2.5% or less, about 2% or less, about 1.5% or less, about 1% or less, or less of the total flow rate of the precursor. By supplying the hydrogen-containing precursor in operation step 310, the energy of the plasma formed thereafter, as described later, may increase. Furthermore, hydrogen can easily pass through the deposited material and remove dangling bonds from the material. Removing dangling bonds a strengthens the Si-O bond, leaving a high-quality silicon-containing material on the substrate 405.

[0035]

[0038] Precursors supplied to the processing area, such as silicon-containing precursors and hydrogen-containing precursors, can be used to generate plasma within the processing area of ​​the semiconductor processing chamber in operation step 315 of method 300. Plasma can be generated, for example, by supplying RF power to a faceplate to generate plasma within the processing area 220, but any other processing chamber capable of generating plasma can be used as well. In embodiments, plasma may be generated at frequencies of about 15 MHz or higher. Lower frequencies can also be used, but in some embodiments, unlike the operation of lower plasma frequencies, plasma generation at higher frequencies can increase the density of the plasma and therefore the density of the deposited material. Thus, plasma may be generated at frequencies of about 17 MHz or higher, about 19 MHz or higher, about 21 MHz or higher, about 23 MHz or higher, about 25 MHz or higher, about 27 MHz or higher, or higher.

[0036]

[0039] Furthermore, the plasma power can be maintained at approximately 1000W or less while generating plasma effluent of silicon-containing precursors and plasma effluent of hydrogen-containing precursors. Therefore, the plasma power can be maintained at approximately 900W or less, approximately 800W or less, approximately 700W or less, approximately 600W or less, approximately 500W or less, approximately 450W or less, approximately 400W or less, approximately 350W or less, approximately 300W or less, approximately 250W or less, approximately 200W or less, approximately 150W or less, approximately 100W or less, or less.

[0037]

[0040] As shown in Figure 4B, in operation step 320, method 300 may include depositing a silicon-containing material 420 on the substrate 405. The silicon-containing material 420 may be conformally deposited on the substrate 405, as in feature 415. In some embodiments, the deposition rate may be greater than 500 Å / min, and may be about 700 Å / min or more, about 1,000 Å / min or more, about 1,200 Å / min or more, about 1,400 Å / min or more, about 1,600 Å / min or more, about 1,800 Å / min or more, or about 2,000 Å / min or more. In some embodiments, additional energy can be added to the generated plasma by incorporating a hydrogen-containing precursor. Furthermore, hydrogen plasma effluent can easily pass through the silicon-containing material 420, removing dangling bonds from the silicon-containing material 420. Removing dangling bonds from the silicon-containing material 420 may lead to the formation of more Si-O bonds, particularly improving the quality of the silicon-containing material 420 in the sidewalls of feature 415. In some embodiments, high-frequency plasma (e.g., above 15 MHz) can be used to increase the density of plasma effluent. As the density of plasma effluent increases, dangling bonds are removed from the silicon-containing material 420, allowing for the formation of additional Si-O bonds.

[0038]

[0041] In some embodiments, the semiconductor processing chamber, pedestal, or substrate 405 is maintained at a temperature of about 250°C or higher, and in some embodiments, it may be maintained at a temperature of about 300°C or higher, about 320°C or higher, about 340°C or higher, about 360°C or higher, about 380°C or higher, about 400°C or higher, about 420°C or higher, about 440°C or higher, about 460°C or higher, about 480°C or higher, about 500°C or higher, about 520°C or higher, about 540°C or higher, about 560°C or higher, about 580°C or higher, or higher. Higher temperatures increase the formation of Si-O bonds, which may result in the deposition of higher quality silicon-containing material 420. However, due to thermal budget constraints, it may be necessary to maintain the semiconductor processing chamber, pedestal, or substrate 405 at a lower temperature. Therefore, in some embodiments, the semiconductor processing chamber, pedestal, or substrate 305 may be maintained at a temperature of about 600°C or less, and in some embodiments, it may be maintained at a temperature of about 580°C or less, about 560°C or less, about 540°C or less, about 520°C or less, about 500°C or less, or below.

[0039]

[0042] During the deposition of the silicon-containing material 420, the semiconductor processing chamber can be maintained at any pressure suitable for the formation of the silicon-containing material. For example, the pressure in the semiconductor processing chamber may be maintained at about 30 Torr or less, and in some embodiments, at about 28 Torr or less, about 26 Torr or less, about 24 Torr or less, about 22 Torr or less, about 20 Torr or less, about 18 Torr or less, about 16 Torr or less, about 14 Torr or less, about 12 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, about 4 Torr or less, about 2 Torr or less, or a pressure lower than that.

[0040]

[0043] Post-deposition treatment is not necessarily required to improve the quality of the silicon-containing material 420, but in some embodiments of Method 300, after deposition to a sufficient thickness, post-deposition treatment may be performed on the silicon-containing material 420 in an optional operation step 325. In embodiments, Method 300 may include stopping the flow of the silicon-containing precursor and / or the flow of the hydrogen-containing precursor before performing post-deposition treatment. Post-deposition treatment may be an optional operation step to improve the quality of the silicon-containing material 420. For example, post-deposition treatment can increase the oxygen content in the silicon-containing material 420 and / or decrease the hydrogen content in the silicon-containing material 420.

[0041]

[0044] For example, post-deposition processing may include exposing the silicon-containing material 420 to ultraviolet (UV) light. In some embodiments, UV exposure may be performed within the semiconductor processing chamber used for depositing the silicon-containing material 420. In additional embodiments, the substrate 405 containing the silicon-containing material 420 may be transported to another semiconductor processing chamber where the UV irradiation operation is performed. UV exposure may be carried out in the presence of an oxygen-containing precursor or an inert precursor. For example, the oxygen-containing precursor may be any oxygen-containing material such as molecular oxygen (O2) or ozone (O3). As an inert precursor, any inert substance such as argon, helium, or xenon can be used.

[0042]

[0045] In other embodiments, post-deposition processing may include annealing the silicon-containing material 420 on the substrate 405. In some embodiments, annealing may be performed in a semiconductor processing chamber used for depositing the silicon-containing material 420. In additional embodiments, the substrate 405 containing the silicon-containing material 420 may be transported to another semiconductor processing chamber where annealing is performed. Annealing may be performed in the presence of a hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor. The hydrogen-containing precursor may be any hydrogen-containing material, such as molecular hydrogen (H2). The nitrogen-containing precursor may be any nitrogen-containing material, such as molecular nitrogen (N2). The oxygen-containing precursor may be any oxygen-containing material, such as molecular oxygen (O2) or ozone (O3).

[0043]

[0046] By annealing the silicon-containing material 420 on the substrate 405, hydrogen and / or carbon can be released from the silicon-containing material 420. For example, when the silicon-containing material 420 is annealed in the presence of an oxygen-containing precursor, water vapor (H2O) and / or carbon dioxide (CO2) can be released from the silicon-containing material 420. Furthermore, when the silicon-containing material 420 is annealed in the presence of an oxygen-containing precursor, additional oxygen is added to the silicon-containing material, enabling additional Si-O bonds. Similarly, when the silicon-containing material 420 is annealed in the presence of a hydrogen-containing precursor, terminal hydroxyl (-OH) bonds are cleaved from the silicon-containing material 420. These terminal -OH bonds can then combine with the hydrogen-containing precursor, releasing gas as water vapor (H2O).

[0044]

[0047] The post-deposition treatment in the optional operation step 325 can be continued for a sufficient time to improve the quality of the silicon-containing material 420, such as the material on the sidewall of the feature 410. In embodiments, the time may be about 30 minutes or less, less than 28 minutes, about 26 minutes or less, about 24 minutes or less, about 22 minutes or less, about 20 minutes or less, about 18 minutes or less, about 16 minutes or less, about 14 minutes or less, about 12 minutes or less, about 10 minutes or less, or less. Compared to conventional methods for improving the quality of the sidewall film, the post-deposition treatment of the present technology can interact with and process the deposited silicon-containing material 420 more easily.

[0045]

[0048] Unlike conventional methods for improving the quality of sidewall films, the post-deposition treatment of this technology allows for sufficient processing of the film at lower temperatures. For example, conventional nitrogen annealing may require processing at temperatures exceeding 600°C to process the deposited material. In some embodiments, the post-deposition treatment can be carried out at temperatures of approximately 250°C or higher for the semiconductor processing chamber, pedestal, or substrate 405, and in some embodiments, at temperatures of approximately 300°C or higher, approximately 320°C or higher, approximately 340°C or higher, approximately 360°C or higher, approximately 380°C or higher, approximately 400°C or higher, approximately 420°C or higher, approximately 440°C or higher, approximately 460°C or higher, approximately 480°C or higher, approximately 500°C or higher, approximately 520°C or higher, approximately 540°C or higher, approximately 560°C or higher, approximately 580°C or higher, or above. However, due to thermal budget constraints, it may be necessary to maintain the semiconductor processing chamber, pedestal, or substrate 405 at lower temperatures during post-deposition treatment. Therefore, in some embodiments, the semiconductor processing chamber, pedestal, or substrate 305 may be maintained at a temperature of about 600°C or less, and in some embodiments, it may be maintained at a temperature of about 580°C or less, about 560°C or less, about 540°C or less, about 520°C or less, about 500°C or less, or below.

[0046]

[0049] In some embodiments, post-deposition processing can be performed at a higher pressure than during the deposition of the silicon-containing material 420, and the semiconductor processing chamber can be maintained at any pressure suitable for forming the silicon-containing material. For example, the pressure in the semiconductor processing chamber may be maintained at about 400 Torr or higher, and in some embodiments, at pressures of about 420 Torr or higher, about 440 Torr or higher, about 460 Torr or higher, about 480 Torr or higher, about 500 Torr or higher, about 520 Torr or higher, about 540 Torr or higher, about 560 Torr or higher, about 580 Torr or higher, about 600 Torr or higher, about 620 Torr or higher, about 640 Torr or higher, about 660 Torr or higher, about 680 Torr or higher, about 700 Torr or higher, about 720 Torr or higher, about 740 Torr or higher, about 760 Torr or higher, or higher.

[0047]

[0050] This technology can reduce or significantly reduce both the average roughness and the range of roughness of the silicon-containing material 420. For example, generated hydrogen radicals can improve the surface roughness state by interacting with silicon-containing precursors during deposition. Furthermore, post-deposition treatment can modify the surface of the film by rearranging the bonds and reducing the surface roughness conditions. In embodiments, post-deposition treatment can increase the Si-O bonds in the silicon-containing material 420 to about 3 at.% or more, for example, about 4 at.% or more, about 5 at.% or more, about 6 at.% or more, about 7 at.% or more, about 8 at.% or more, or more.

[0048]

[0051] By manufacturing silicon-containing materials according to embodiments of this technology, the hardness and elastic modulus of the silicon-containing materials can be made higher than those obtained by conventional PECVD deposition methods. For example, in some embodiments, this technology can manufacture materials characterized by a Young's modulus of about 60 Gpa or higher, for example, about 65 Gpa or higher, about 70 Gpa or higher, about 75 Gpa or higher, about 80 Gpa or higher, about 85 Gpa or higher, about 90 Gpa or higher, or higher.

[0049]

[0052] The above description includes many details for illustrative purposes in order to provide an understanding of the various embodiments of the Technology. However, it will be obvious to those skilled in the art that certain embodiments may be carried out without some of these details, or with additional details.

[0050]

[0053] While several embodiments have been disclosed, those skilled in the art will understand that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the descriptions in the prior specification should not be considered to limit the scope of the Art.

[0051]

[0054] Where a range of values ​​is provided, unless explicitly stated otherwise in the context, each intermediary value between the upper and lower limits of that range is, of course, specifically disclosed down to the smallest unit of the lower limit. Narrower ranges between any two listed values ​​or between unlisted intermediary values ​​within a given range, and other listed or intermediary values ​​within such ranges, are included. The upper and lower limits of such narrower ranges may be included in or excluded from that range individually. Each range in which one, neither, or both of the limits are included is also included in the Art, although there may be limits that are specifically excluded within the given range. Where one or both of the limits are included in a given range, the range excluding one or both of the included limits is also included.

[0052]

[0055] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. For example, “a material” includes multiple such materials, and “the precursor” includes one or more precursors and their equivalents known to those skilled in the art, and so on.

[0053]

[0056] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or steps, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, Providing a silicon-containing precursor to the processing area of ​​a semiconductor processing chamber, wherein a substrate is housed within the processing area of ​​the semiconductor processing chamber, To provide a hydrogen-containing precursor in the aforementioned processing region, The process involves generating plasma effluent of the silicon-containing precursor and plasma effluent of the hydrogen-containing precursor in the processing region, wherein the plasma effluent is generated at a frequency exceeding 15 MHz, and the process involves generating plasma effluent of the silicon-containing precursor and plasma effluent of the hydrogen-containing precursor in the processing region. Depositing the silicon-containing material onto the substrate and A semiconductor processing method including [specific components].

2. The semiconductor processing method according to claim 1, wherein the silicon-containing precursor comprises tetraethyl orthosilicate (TEOS).

3. The semiconductor processing method according to claim 1, wherein the hydrogen-containing precursor comprises about 5% or less of the total flow rate of the precursor provided to the processing area.

4. The semiconductor processing method according to claim 1, wherein the plasma power is maintained at approximately 1000 W or less while generating plasma effluent of the silicon-containing precursor and plasma effluent of the hydrogen-containing precursor.

5. The semiconductor processing method according to claim 1, wherein the temperature inside the semiconductor processing chamber is maintained at approximately 600°C or less during the process.

6. The semiconductor processing method according to claim 1, wherein the pressure in the semiconductor processing chamber is maintained at approximately 30 Torr or less during the method.

7. The silicon-containing material is subjected to post-deposition treatment. The semiconductor processing method according to claim 1, further comprising:

8. The semiconductor processing method according to claim 7, wherein performing the post-deposition processing increases the oxygen content in the silicon-containing material.

9. The semiconductor processing method according to claim 7, wherein the post-deposition treatment includes exposing the silicon-containing material to ultraviolet light.

10. The semiconductor processing method according to claim 7, wherein the post-deposition treatment includes annealing the silicon-containing material in the presence of a second hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor.

11. A semiconductor processing method, Providing a silicon-containing precursor to the processing area of ​​a semiconductor processing chamber, wherein a substrate is housed within the processing area of ​​the semiconductor processing chamber, In the processing region, the plasma effluent of the silicon-containing precursor is generated, Depositing the silicon-containing material onto the substrate, Performing a post-deposition treatment on the silicon-containing material, wherein performing the post-deposition treatment increases the oxygen content in the silicon-containing material, and performing a post-deposition treatment on the silicon-containing material A semiconductor processing method including [specific components].

12. The semiconductor processing method according to claim 11, wherein the substrate defines one or more features.

13. The semiconductor processing method according to claim 11, wherein the plasma outflow is generated at a frequency exceeding 15 MHz.

14. The semiconductor processing method according to claim 11, further comprising providing a hydrogen-containing precursor to the processing region.

15. The hydrogen-containing precursor is molecular hydrogen (H ２ The semiconductor processing method according to claim 14, including ).

16. The semiconductor processing method according to claim 11, wherein the post-deposition treatment includes exposing the silicon-containing material to ultraviolet light in the presence of an inert precursor or an oxygen-containing precursor.

17. The semiconductor processing method according to claim 11, wherein the post-deposition treatment includes annealing the silicon-containing material at a temperature of about 600°C or less.

18. A semiconductor processing method, Providing a silicon-containing precursor to the processing area of ​​a semiconductor processing chamber, wherein a substrate is housed within the processing area of ​​the semiconductor processing chamber, To provide a hydrogen-containing precursor in the aforementioned processing region, The process involves generating plasma effluent of the silicon-containing precursor and plasma effluent of the hydrogen-containing precursor in the processing region, wherein the plasma effluent is generated at a frequency exceeding 15 MHz, and the process involves generating plasma effluent of the silicon-containing precursor and plasma effluent of the hydrogen-containing precursor in the processing region. Depositing the silicon-containing material onto the substrate, Performing a post-deposition treatment on the silicon-containing material, wherein performing the post-deposition treatment increases the oxygen content in the silicon-containing material, and performing a post-deposition treatment on the silicon-containing material A semiconductor processing method including [specific components].

19. The semiconductor processing method according to claim 18, wherein performing the post-deposition processing reduces the hydrogen content in the silicon-containing material.

20. The semiconductor processing method according to claim 18, further comprising stopping the flow of the silicon-containing precursor and the flow of the hydrogen-containing precursor before performing the post-deposition processing.

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