Direct hybrid bonding in topographic packaging

Abstract

A direct bond interconnect in a topographic package and a method for manufacturing it. The topographic package has a first die that is hybrid-bonded to a substrate, and the first die is located at a first device level. A second die is located above the first die in a second device level, and the second die is hybrid-bonded to the first die. The topographic package further has a third die located above the second die in a third device level, and the third die is hybrid-bonded to the top surface of the second device level.

Description

[Technical Field]

[0001] This technical field relates to integrated circuit packages / integrated components having multiple dies. [Background technology]

[0002] A miniature electronic assembly generally includes one or more integrated circuit (IC) dies (hereinafter referred to as "chips") which are preferably packaged to be connectable to an external device, such as a system board. One or more such IC dies may be mounted on a circuit platform, such as a wafer for wafer-level packaging ("WLP"), a printed circuit board ("PB"), a printed wiring board ("PWB"), a printed circuit board ("PCB"), a printed wiring assembly ("PWA"), a printed circuit assembly ("PCA"), a package substrate, an interposer, or a chip carrier. In addition, one IC die may be mounted on another IC die. An interposer is an IC die or other form of electronic component, and an interposer is often a passive or active IC die, the latter including one or more active devices (e.g., transistors, while the former may or may not include active or passive devices). Furthermore, an interposer may be formed without circuit elements, such as capacitors, resistors, or active devices, as is the case with PWBs. In addition, the interposer may have at least one through-substrate via. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] Conventional methods for fabricating IC packages are expensive. For example, conventional methods involve numerous dielectric layer deposition and numerous chemical and mechanical polishing steps. Furthermore, conventional methods can take a long time for deep dielectric cavity etching and also for deep cavity metal filling. All of these steps increase process costs.

[0004] Therefore, it is desirable and useful to provide structures and methods for manufacturing topographic packages, such as topographic packages formed by direct hybrid bonding that addresses these challenges. [Means for solving the problem]

[0005] The present invention provides a direct bond interconnect in a topographic package and a method for manufacturing it. The topographic package has a first die hybrid-bonded to a substrate, the first die positioned at a first device level. A second die is positioned above the first die at a second device level, the second die hybrid-bonded to the first die. The topographic package further has a third die positioned above the second die at a third device level, the third die hybrid-bonded to the top surface of the second device level.

[0006] Next, specific examples of the invention will be described with reference to the following drawings, but these drawings are provided for illustrative purposes only and do not limit the invention. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1B] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1C] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1D] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1E]This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1F] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1G] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1H] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1I] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1J] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1K] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1L] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1M] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1N] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 10] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 1P] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 2A] This is a cross-sectional view of another method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 2B]A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 2C] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 2D] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 2E] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 2F] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 2G] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3A] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3B] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3C] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3D] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3E] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3F] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 3G] A cross-sectional view of another method of manufacturing an exemplary topographic package in accordance with several disclosed embodiments. [Figure 4A]This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4B] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4C] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4D] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4E] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4F] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4G] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4H] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4I] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 4J] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5A] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5B] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5C] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5D]This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5E] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5F] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5G] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5H] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5I] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5J] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5K] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5L] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5M] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5N] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 5O] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6A] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6B]This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6C] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6D] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6E] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6F] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6G] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6H] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6I] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 6J] This is a cross-sectional view of a method for manufacturing an exemplary topographic package according to some of the disclosed embodiments. [Figure 7A] This is a process flowchart illustrating a method for manufacturing an exemplary topographic package according to several embodiments of the disclosed technology. [Figure 7B] This is a process flowchart illustrating a method for manufacturing an exemplary topographic package according to several embodiments of the disclosed technology. [Figure 8] This is a process flowchart of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. [Figure 9] This is a process flowchart of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. [Figure 10A] This is a process flowchart of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. [Figure 10B] This is a process flowchart of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. [Figure 11A] This is a process flowchart of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. [Figure 11B] This is a process flowchart of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. [Figure 12] This is a schematic cross-sectional view of an integrated circuit. [Figure 13A] This is a schematic diagram of a process for forming a direct hybrid bonded structure without intervening adhesives, according to several embodiments. [Figure 13B] This is a schematic diagram of a process for forming a direct hybrid bonded structure without intervening adhesives, according to several embodiments. [Modes for carrying out the invention]

[0008] The following disclosure provides numerous different embodiments or examples to embody many different features of the problem being addressed. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, illustrative and not limiting to the invention. For example, the following description of attaching or forming a first feature portion on a second feature portion may include embodiments in which the first and second feature portions are formed in direct contact, and further, preferred embodiments may include additional feature portions being formed between the first and second feature portions so that they do not form direct contact. In addition, the disclosure may repeat reference numbers and / or reference numerals in various embodiments. This repetition is for the purpose of making the description easy to understand and keeping the drawings simple, and does not in itself indicate relationships between the various embodiments and / or configurations described.

[0009] Furthermore, spatially relative terms, such as "below," "below," "on the lower side," "above," and "upper side," may be used in this specification to facilitate explanation when describing the relationship between one element or feature and another, as shown in the drawings. Such spatially relative terms are intended to include different orientations of the device in use or operation, in addition to the orientation shown in the drawings. The device may be in a different orientation (90° rotated or another orientation), and therefore, the spatially relative terms used herein should be interpreted accordingly.

[0010] The following description pertains to topographic packages. A topographic package includes two or more semiconductor dies positioned at different device levels from one another. For example, and as will be described in detail below, a topographic package may include a second die positioned vertically directly above a first die, a third die positioned vertically above the first and second dies, a second and / or third die positioned vertically above the first die but only partially overlapping it horizontally, and a second and / or third die positioned vertically above the first die but not overlapping it horizontally.

[0011] Figure 12 shows a conventional integrated circuit 1201. The integrated circuit is fabricated on the front surface of a semiconductor wafer substrate 100. The first part of the fabrication process forms individual electrical components (e.g., transistors, resistors, capacitors) 1206. This first device part of the fabrication process is called the front-end-of-line (FEOL) process. The second part of the integrated circuit fabrication process, the back-end-of-line (BEOL) process, is typically performed after the completion of the FEOL process. In the BEOL process, a stack of alternating dielectric and metallization layers is typically formed, during which interconnects 1210 and vias 1208 are formed. The interconnect has power lines that send power to and receive power from the device, and signal lines used to receive data from the device. Signal lines are sometimes broadly referred to as signal distribution networks (SDNs), and power lines are sometimes referred to as power distribution networks (PDNs). Furthermore, during BEOL, pad contacts 106 are formed for bonding the chip to a package or circuit board. The integrated circuit 1201 may further have solder bumps 1202 that allow the integrated circuit 1201 to be attached to a circuit board or another integrated circuit.

[0012] Various embodiments disclosed herein relate to direct-bonded structures, such as integrated circuits 1201, in which two or more elements can be directly bonded to each other without an intervening adhesive. Figures 13A and 13B schematically illustrate a process for forming a direct hybrid bonded structure without an intervening adhesive according to several embodiments. In Figures 13A and 13B, the bonded structure 101 has two elements 103, 105 that can be directly bonded to each other at a bond interface 110 (i.e., can be directly bonded to each other without an intervening adhesive). The two or more miniature electronic elements 103, 105 (e.g., semiconductor elements, such as integrated circuit dies, wafers, passive devices, individual active devices, such as power switches, etc.) may be stacked or bonded to each other to form the bonded structure 101. The conductive feature portion 107a of the first element 103 (e.g., a contact pad, an exposed end of a via (e.g., a TSV), or a through-substrate electrode) is preferably electrically connected to the corresponding conductive feature portion 107b of the second element 105. Any suitable number of elements can be stacked in the bonded structure 101. For example, a third element (not shown) can be stacked on the second element 105, and a fourth element (not shown) can be stacked on the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) may be stacked laterally adjacent to each other along the first element 103. In some embodiments, the additional elements stacked laterally are preferably smaller than the second element. In some embodiments, the additional elements stacked laterally are preferably less than half the size of the second element.

[0013] In some embodiments, elements 103 and 105 are directly bonded to each other without adhesive. In various embodiments, a nonconductive field region containing a nonconductive material or dielectric can act as a first bonding layer 109a of the first element 103, and this first bonding layer is preferably directly bonded to a corresponding nonconductive field region containing a nonconductive material or dielectric that acts as a second bonding layer 109b of the second element 105 without adhesive. The nonconductive layer bonding layers 109a and 190b are preferably placed on the respective front surfaces 115a and 115b of the device portions 111a and 111b of the elements 103 and 105, for example, the semiconductor (e.g., silicon) portions. Active devices and / or circuit components are preferably patterned within or on the device portions 111a and 111b, and / or arranged in different ways. The active devices and / or circuit components are preferably located on or near the front surfaces 115a, 115b of the device portions 111a, 111b, and / or on or near the back surfaces (back sides) 117a, 117b opposite the device portions 111a, 111b. The bonding layer is preferably provided on the front and / or back surfaces of the element. The nonconductive material may be referred to as the nonconductive bonding region or bonding layer 109a of the first element 103. In some embodiments, the nonconductive bonding layer 109a of the first element 103 is preferably directly bonded to the corresponding nonconductive bonding layer 109b of the second element 105 using dielectric-dielectric bonding technology. For example, non-conductive bonds or dielectric-dielectric bonds are often formed without adhesives using direct bonding techniques disclosed in at least U.S. Patent No. 9,564,414, No. 9,391,143, and No. 10,434,749, which are incorporated herein by reference and whose entire contents are incorporated herein by reference for all purposes.It should be noted that in various embodiments, the bonding layers 109a and / or 109b may consist of a non-conductive material, such as a dielectric, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic despite containing carbon. In some embodiments, the dielectric does not contain polymer materials, such as epoxy, resin, or molding materials.

[0014] In some embodiments, the device portions 111a and 111b may have significantly different coefficients of thermal expansion (CTE) to define a heterogeneous structure. The difference in CTE between the device portions 111a and 111b, and especially between the bulk semiconductors of the device portions 111a and 111b, typically the single-crystal portions, may be greater than 5 ppm or greater than 10 ppm. For example, the difference in CTE between the device portions 111a and 111b may be in the range of 5 ppm to 101 ppm, 5 ppm to 40 ppm, 10 ppm to 101 ppm, or 10 ppm to 40 ppm. In some embodiments, one of the device portions 111a and 111b may consist of a photoelectron single-crystal material, an optical piezoelectric or pyroelectric photoelectron single-crystal material useful for pyroelectric applications (including perovskite materials), and the other of the device portions 111a and 111b may consist of a more conventional substrate material. For example, one of the device parts 111a, 111b may be made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other of the device parts 111a, 111b may be made of silicon (Si), quartz, fused silica glass, sapphire, or glass. In some other specific embodiment, one of the device parts 111a, 111b may be made of a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the device parts 111a, 111b may be made of a non-group III-V semiconductor material, such as silicon (Si), or another material with approximately the same CTE, such as quartz, fused silica glass, sapphire, or glass.

[0015] In various embodiments, the direct hybrid bond may be formed without an intervening adhesive. For example, the non-conductive bonding surfaces 113a and 113b may be polished to a high degree of smoothness. The bonding surfaces 113a and 113b may be polished to a high degree of smoothness, for example, using chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 113a and 113b may be less than 30 Årms. For example, the roughness of the bonding surfaces 113a and 113b may be in the range of approximately 0.1 Årms to 15 Årms, 0.5 Årms to 10 Årms, or 1 Årms to 5 Årms. The bonding surfaces 113a and 113b may be activated by cleaning them and exposing them to plasma and / or an etching agent. In some embodiments, the surfaces 113a and 113b may be end-bound with chemical species after or during activation (e.g., during a plasma and / or etching process). While not theoretically bound, in some embodiments, the activation process may be carried out to break chemical bonds at the bonding surfaces 113a and 113b, and the end-bound process may introduce additional chemical species at the bonding surfaces 113a and 113b that improve the bonding energy during direct bonding. In some embodiments, activation and end-bound are carried out in the same step, for example, by using a plasma to activate and end-bound the bonding surfaces 113a and 113b. In some embodiments, the bonding surfaces 113a and 113b may be end-bound in a separate process from the activation process to provide additional chemical species that enable direct bonding. In some embodiments, the end-bound chemical species may contain nitrogen. For example, the bonding surfaces 113a and 113b may be exposed to a nitrogen-containing plasma. Furthermore, in some embodiments, the bonding surfaces 113a and 113b may be exposed to fluorine. For example, one or more fluorine peaks may be present at or near the bond interface 119 between the first element 103 and the second element 105.Thus, in the direct-bonded structure 101, the bonding interface 119 between the two non-conductive materials (e.g., the first and second bonding layers 109a, 109b) can constitute an extremely smooth interface with a high nitrogen content and / or fluorine peak at the bond interface 119. Examples of additional activation and / or end-forming treatments can be found throughout U.S. Patents 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated herein by reference and whose entire contents are incorporated herein by reference for all purposes. The roughness of the polished bonding surfaces 113a, 113b is preferably slightly rough after the activation process (e.g., about 1 Årms to 30 Årms, 3 Årms to 20 Årms, or as rough as possible).

[0016] In various embodiments, the conductive feature portion 107a of the first element 103 may also be directly bonded to the corresponding conductive feature portion 107b of the second element 105 without adhesive (for example, without solder or other conductive adhesive interposed between the conductive feature portions 107a and 107b). For example, direct hybrid bonding techniques can be used to provide a conductor-conductor direct bond along a bond interface 119, which includes a directly covalent non-conductive-conductive (e.g., dielectric-dielectric) surface prepared as described above. In various embodiments, conductor-conductor (e.g., conductive feature portion 107a-conductive feature portion 107b) direct bonds and dielectric-dielectric hybrid bonds may be formed using direct bonding techniques disclosed in at least U.S. Patent No. 9,716,033 and No. 9,852,988, each of which is incorporated herein by reference and whose entire contents are incorporated herein by reference. In the direct hybrid bonding embodiments described herein, the conductive feature portion is provided within the non-conductive bonding layer, and both the conductive and non-conductive feature portions are prepared for direct hybrid bonding by, for example, the planarization, activation, and / or end-binding treatments described above. Thus, the bonding surface prepared for direct hybrid bonding includes both the conductive and non-conductive feature portions.

[0017] For example, non-conductive (e.g., dielectric) bonding surfaces 113a, 113b (e.g., inorganic dielectric surfaces) are preferably prepared and directly bonded to each other without intervening adhesive as described above. Conductive contact features (e.g., conductive features 107a, 107b, which are preferably at least partially surrounded by non-conductive dielectric field regions within bonding layers 109a, 109b) are also preferably directly bonded to each other without intervening adhesive. In various embodiments, the conductive features 107a, 107b may consist of separate pads or traces at least partially embedded within the non-conductive field regions. In some embodiments, the conductive contact features may consist of exposed contact surfaces of through-substrate vias (e.g., through-silicon vias (TSVs)). In some embodiments, the conductive feature portions 107a and 107b are often recessed below the outer (e.g., upper) surface (non-conductive bonding surface 113a and 113b) of the dielectric field region or the non-conductive bonding layer 109a and 109b, for example, by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or 4 nm to 10 nm. The recess is often located in or near the middle or center of the cavity in which the conductive feature portions 107a and 107b are provided, and additionally or alternatively, it is often provided to extend along the side of the cavity in which the conductive feature portions 107a and 107b are provided. In various embodiments, prior to direct bonding, the recess in the opposing elements is often sized such that the total gap between the opposing contact pads is less than 15 nm or less than 10 nm. In some embodiments, the non-conductive bonding layers 109a and 190b are often directly bonded to each other at room temperature without adhesive, and then the bonded structure 101 is annealed. During annealing, the conductive feature portions 107a and 107b expand and come into contact with each other, thereby forming a metal-to-metal direct bond.Beneficial, the Direct Bond Interconnect, i.e., DBI® technology, commercially available from Adeia, Inc. in San Jose, California, allows high-density conductive feature portions 107a, 107b to be connected to each other across the direct bond interface 119 (for example, with small or fine pitches for a regular array). In some embodiments, the pitch of the conductive traces embedded in the bonding surface of one of the conductive feature portions 107a, 107b, for example, one of the bonded elements 103, 105, is preferably less than 101 microns or less than 10 microns, and even less than 2 microns. For some applications, the ratio of the pitch of the conductive feature portions 107a, 107b to one of the dimensions of the bonding pad (e.g., diameter) is less than 20, less than 10, less than 5, or less than 3, and in some cases preferably less than 2. In other applications, the width of the conductive trace embedded in one of the bonding surfaces 108a, 108b of the bonded element may be in the range of 0.3 microns to 20 microns, for example, in the range of 0.3 microns to 3 microns. In various embodiments, the conductive feature portions 107a, 107b and / or traces may be made of copper, nickel, gold, indium, silver or an alloy thereof, but other metals and alloys may be suitable. For example, the conductive feature portions disclosed herein, for example, the conductive feature portions 107a, 107b may be made of metal nanoparticles (for example, copper nanoparticles).

[0018] Thus, in the direct bonding process, it is preferable to directly bond the first element 103 to the second element 105 without an intervening adhesive. In some configurations, the first element 103 may consist of a standalone element, such as a standalone integrated device die. In other configurations, the first element 103 may consist of a carrier or substrate (e.g., wafer) containing multiple (e.g., tens, hundreds or more) device regions that form multiple integrated device dies when isolated. In some embodiments, the first element may consist of a package or a standalone package. Similarly, the second element 105 may consist of a standalone element, such as a standalone integrated device die. In other configurations, the second element 105 may consist of a carrier (or substrate, wafer) or a package. Accordingly, some embodiments disclosed herein can be used for wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W), package-to-wafer (P2W), package-to-package, die-to-flat panel, and package-to-flat panel bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers are preferably directly bonded to each other (e.g., direct hybrid bonding) and then isolated using a suitable isolation process. After isolation, the side edges of the isolated structures (e.g., the side edges of two bonded elements) are preferably located substantially on the same plane, and such side edges may include markers indicating a common isolation process for the bonded structures (e.g., saw marks if a saw isolation process is used).

[0019] As described herein, the first element 103 and the second element 105 can be directly bonded to each other without adhesive, which differs from the vapor deposition process and consequently results in a structurally different interface compared to vapor deposition. In one application, the width of the first element 103 in the bonded structure is approximately the same as the width of the second element 105. In some other embodiments, the width of the larger element in the bonded structure 101 may differ from the width of the smaller element. Similarly, the width or area of ​​the larger of the first and second elements 103,105 in the bonded structure is preferably at least 10% larger than the width or area of ​​the smaller of the first and second elements 103,105. Thus, the first and second elements 103,105 may consist of non-vapor-deposited elements. Furthermore, unlike vapor-deposited layers, the direct bonded structure 101 may include defect regions along the bond interface 119 where nanoscale voids (nanovoids) are present. Nanovoids may form as a result of activation of bonding surfaces 113a,113b (e.g., exposure to plasma). As described above, the bond interface 119 may contain concentrates of material resulting from the activation and / or final chemical treatment process. For example, in some embodiments utilizing nitrogen plasma for activation, a nitrogen peak may occur at the bond interface 119. The nitrogen peak can be detected using a secondary ion mass spectrometer (SIMS). In various embodiments, for example, nitrogen-terminated treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) can be used to replace the OH groups on the hydrolysis (OH-terminated) surface with NH2 molecules, thereby creating a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may occur at the bond interface 119. In some embodiments, the bond interface 119 may be made of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond may be made of covalent bonds, which are stronger than van der Waals bonds.The bonding layers 108a and 108b preferably have polished surfaces that have been flattened to a high degree of smoothness.

[0020] In various embodiments, the metal-metal bond between conductive feature portions 107a and 107b is preferably bonded such that metal crystals grow inward across the bond interface 119. In some embodiments, the metal is or contains copper, and the copper preferably has crystal grains oriented along the <111> crystal plane to improve copper diffusion across the bond interface 119. In some embodiments, the conductive feature portions 107a and 107b preferably contain a nanotwinned copper crystal structure, which can aid in the coalescence of the conductive feature portions during annealing. The bond interface 119 preferably extends substantially completely to at least a portion of the bonded conductive feature portions 107a and 107b, so that there is substantially no gap between the nonconductive bonding layers 108a and 108b at or near the bonded conductive feature portions 107a and 107b. In some embodiments, the barrier layer may be provided beneath and / or surrounding the conductive feature portions 107a, 107b (which may, for example, contain copper). However, in other embodiments, the barrier layer may not be provided beneath the conductive feature portions 107a, 107b, as described, for example, in U.S. Patent No. 11,195,748, which is incorporated herein by reference and whose entire contents are part of this specification for all purposes.

[0021] Beneficially, the hybrid bonding techniques described herein enable the realization of extremely fine pitches between adjacent conductive feature portions 107a, 107b and / or small pad sizes. For example, in various embodiments, the pitch p between adjacent conductive feature portions 107a (or 107b) (i.e., the distance between edges or centers, as shown in Figure 13A) may be in the range of 0.5 to 10 microns, 0.75 to 25 microns, 1 to 25 microns, 1 to 10 microns, or 1 to 5 microns. Furthermore, the larger lateral dimension (e.g., pad diameter) may also be small, for example, in the range of 0.25 to 30 microns, 0.25 to 5 microns, or 0.5 to 5 microns.

[0022] As described above, the non-conductive bonding layers 109a and 109b are preferably directly bonded to each other without adhesive, and then the bonded structure 101 is preferably annealed. During annealing, the conductive feature portions 107a and 107b expand and come into contact with each other, thereby forming a metal-to-metal (intermetallic) direct bond. In some embodiments, the materials of the conductive feature portions 107a and 107b can interdiffuse during the annealing process.

[0023] Figures 1A to 1P are schematic cross-sectional views of a method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. Referring to Figure 1A, it is preferable to prepare a substrate 100 or carrier. The substrate 100 can be made of any suitable material, such as silicon (Si), a Group III-V semiconductor, such as gallium arsenide (GaAs), a Group II-VI semiconductor, such as cadmium selenide (CdSe), cadmium telluride (CdTe), ceramic, a carbon-based substrate, such as diamond, silicon carbide (SiC), germanium (Ge), Sil-xGex, or others. A semiconductor substrate 100 provided from an in-process wafer is outlined below, but any sheet or layered semiconductor material or dielectric, such as ceramic or glass, can be used as the substrate. In some configurations, the substrate 100 may consist of a package with or without partially or fully embedded dies or passive elements. As shown in Figure 1A, the substrate may include conductive contact features or contact pads 106, such contact pads enabling electrical contact with the front or top surface of the substrate 100. The back or bottom surface may have conductive lands or terminals configured to be coupled to another device, such as a system board or another electronic assembly, by any suitable electrical connection method (e.g., by solder balls, direct hybrid bonding, etc.).

[0024] Furthermore, as shown in Figure 1A, it is preferable that one or more first dies 102 be located at a first device level 150, and one or more second dies 104 be located at a second device level 152 above the first device level. In one embodiment, the second dies 104 are preferably smaller than the first dies 102, for example, the upper second die 104 has a smaller lateral footprint than the lower first die 102. In addition, as shown in Figure 1A, the first and second dies 102, 104 may have contact pads 106 located on the front surface, back surface, or both the front surface and back surface of the first and second dies 102, 104. In a preferred embodiment, the first die 102 is attached to the substrate 100 by hybrid bonding, and the second die 104 is attached to the first die 102 by hybrid bonding.

[0025] Referring to Figure 1B, the first dielectric layer 108 is preferably deposited or adhered onto the substrate 100, the first die 102, and the second die 104. The first dielectric layer 108 is made of an inorganic dielectric, such as silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO3N4). x N y ), or any other suitable dielectric material. As shown in Figure 1B, the first dielectric layer 108 is preferably deposited on the first and second die levels, for example, on the first and second dies 102, 104 of each die stack.

[0026] Referring to Figure 1C, the upper surface of the first dielectric layer 108 is planarized. Any suitable planarization method, such as chemical mechanical polishing (CMP), can be used.

[0027] Referring to Figure 1D, it is preferable to deposit the second dielectric layer 110 on the first dielectric layer 108. The second dielectric layer 110 is preferably composed of the same type of dielectric material as the first dielectric layer 108 or a different type of dielectric material.

[0028] Referring to Figure 1E, the upper surface of the second dielectric layer 108 is planarized. Any suitable planarization method, such as the CMP method, can be used.

[0029] Referring to Figure 1F, it is preferable to deposit the third dielectric layer 112 on the second dielectric layer 110. The third dielectric layer 112 is preferably composed of the same material as the first and second dielectric layers 108,110 or a different dielectric material.

[0030] Referring to Figure 1G, the upper surface of the third dielectric layer 112 is planarized. Any suitable planarization method, such as CMP, can be used. As shown in the figure above, three dielectric layers 112 are deposited. However, any number of dielectric layers, for example, four, five, six or more layers, can be deposited.

[0031] Referring to Figure 1H, via holes 114 are formed through the first, second, and third dielectric layers 108, 110, and 112, so that some of the via holes 114 contact the substrate 100, some of the via holes 114 contact the first die 102, and some of the via holes 114 contact the second die 104. The via holes 114 may be placed on any portion of the second die 104. In some embodiments, the contact pads 106 can be arranged, for example, in a ball grid array pattern around the peripheral portion of the second die 104, or, as a variation, essentially across the entire surface of the second die 104. As shown, the die 104 has a smaller footprint than the first die 102. Therefore, the contact pads 106 as a whole are arranged in an array around the periphery of the first die 102. However, the second die 104 may have an additional bond pad within the inner portion of its surface, thereby enabling direct contact between the first die 102 and the second die 104. The via holes 114 can be formed by any suitable method, such as reactive ion etching (RIE) or chemical wet etching.

[0032] Referring to Figure 1I, a barrier layer / adhesive layer 116 / 117 is deposited, and as a result, the barrier layer / adhesive layer 116 / 117 conformally covers the surface of the via hole 114. Next, metallization 118 is deposited on the barrier layer / adhesive layer 116 / 117, thereby forming dielectric through-vias TDVa, TDVb, TDVc that extend to the substrate 100 and the first and second dies 102, 104. The barrier layer / adhesive layer 116 / 117 can be conformally deposited using any suitable method, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). In one embodiment, the barrier layer / adhesive layer 116 / 117 consists of a separate barrier layer 116 and an adhesive layer 117. Suitable materials for the barrier layer 116 include, but are not limited to, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride. The adhesive layer 117 may be a seed layer made of the same material as the metallization layer 118, or the adhesive layer 117 may be a dielectric layer, such as SiNx or SiOx. The metallization layer 118 can be made of, for example, copper, nickel, gold, silver, indium, tantalum, tungsten, their alloys, and their silicides.

[0033] Referring to Figure 1J, CMP is performed to remove excess metallization material and excess barrier / adhesion layer 116 / 117 material. CMP also planarizes the surface of the third dielectric layer 112, thereby forming a bonding surface 148 suitable for hybrid bonding.

[0034] Referring to Figures 1K to 1M, the third dies 120, 122, 124, 126, 128, 130, 134, and 138 are preferably directly hybrid-bonded to the topographic package in various configuration examples. The third dies 120, 122, 124, 126, 128, 130, 134, and 138 are preferably located at a third device level separate from the first and second device levels. For example, the third die 120 includes the substrate 100 and electrical connections TDVa, TDVb, and TDVc to the first die 102 at the first device level and to the second die 104 at the second device level. The third die 120 also includes the substrate 100 and electrical connections to the second die 104 at the second device level. In some embodiments, the third die 120 has only an electrical connection to the substrate 100, and as a result, the TDV connected to the third die 124 bypasses the first and second dies 102 and 104. Furthermore, in the illustrated embodiment, the third die 126 has only an electrical connection to the second die 104. In one embodiment, the third die 126 is directly hybrid bonded to the second die 104. That is, through-dielectric vias TDVc are preferably not used. In Figure 1L, the third die 128 has electrical connections to the substrate 100, the first die 102 at the first device level, and the second die 104 at the second device level. As shown in the figure, the third die 128 preferably has a larger footprint than the second die 104 located below it.

[0035] The third die 130 is a chiplet attached to the dielectric layer 112 (e.g., by direct bonding) and electrolytically connected to the substrate 100 by TDVs, e.g., TDVa. The chiplet is a small integrated circuit die with a dedicated function. The chiplet may be part of a processing module that constitutes a larger integrated circuit, such as a computer processor. Rather than manufacturing a processor on a single piece of silicon with the desired number of cores, the chiplet allows manufacturers to construct a large integrated circuit using a large number of small chips. The third die 134 is electrically connected to the first die 102 and the second die 104. In some embodiments, an upper bond pad 136 is often provided on the upper surface of the dielectric layer 112, thereby providing electrical connections (e.g., power, ground, signal, etc.) to the topographic package via electrical connectors, e.g., wire bonds, ribbon interconnects, etc. In some embodiments, the bond pad 136 may serve as a test pad for testing one or more functions of the illustrated die.

[0036] Referring to Figure 1N, one or more fourth dies 142 are hybrid-bonded to third dies 120, 122, 124, 126, 128, and 134 at a fourth device level separate from the first, second, and third device levels.

[0037] Referring to Figure 1O, the protective layer 144 is preferably deposited on the topographic package. In one embodiment, a number of topographic packages are fabricated simultaneously on a single wafer. In this embodiment, the protective layer 144 helps protect the topographic packages when they are separated into individual topographic packages. Figure 1O shows a reconfigured wafer with two completed cells. A solid S is preferably formed between the completed cells, and the cells are preferably separated along such a street. Separation can be carried out by any suitable method, such as sawing, laser cutting, etching, plasma cutting, or any combination thereof. In various embodiments, the protective layer 144 is preferably made of an organic protective layer, such as a photoresist material.

[0038] Referring to Figure 1P, one embodiment of a topographic package is shown having a redistribution layer (RDL) 146 between the top surface of a third dielectric layer 112 and the third dies 120, 122, 124, 126, 128, 130, 134. The RDL preferably has one or more dielectric layers (e.g., inorganic dielectric layers, e.g., silicon oxide, silicon nitride, etc.) and conductive traces or pads at least partially embedded in the dielectric layers. The RDL 146 can transmit signals (or power and ground) laterally during the trace to connect the dies laterally spaced apart from one another. When the integrated circuit is manufactured, it typically has a set of I / O pads wire-bonded to the pins of the package. The redistribution layer is an extra wiring layer provided on the chip, which allows bonding out from different locations on the chip, thereby simplifying chip-to-chip bonding. RDL can also be used to distribute contact points around the die so that thermal stress can be diffused.

[0039] Conventional methods for forming topographic packages are costly. These methods require the deposition of many dielectric layers and subsequent intermediate planarization steps. Conventional methods also require long times for deep dielectric cavity etching and for deep dielectric cavities. This embodiment can be implemented with relatively few dielectric deposition steps, and as a result, with relatively few intermediate planarization steps. Furthermore, this embodiment provides vias for bonding to the substrate 100, the first die 102, and the second die 104, thereby improving the communication between dies 102 and 104 and enhancing performance. In addition, by using direct hybrid bonding, good integration and fine pitch can be achieved.

[0040] Figures 2A to 2J are schematic cross-sectional views of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. This method is sometimes referred to as the mask-through plating method. Referring to Figure 2A, it is preferable to prepare a substrate 100, as in the first embodiment. As shown in Figure 2A, the substrate preferably has contact pads 106 that enable electrical contact with the substrate 100. Also, as shown in Figure 2A, it is preferable that one or more first dies 102 are located at a first device level 150, and one or more second dies 104 are located at a second device level 152 above the first device level. In one embodiment, the second die 104 is preferably smaller than the first die 102. Furthermore, as shown in Figure 2A, the first and second dies 102, 104 preferably have contact pads 106 located on the front surface, back surface, or both the front surface and back surface of the first and second dies 102, 104. In a preferred embodiment, the first die 102 is attached to the substrate 100 by hybrid bonding, and the second die 104 is attached to the first die 102 by hybrid bonding.

[0041] Referring to Figure 2B, it is preferable to deposit the seed layer 201 on the substrate 100. The seed layer 201 is preferably made of the same material as the metallization layer 118, which will be described below. Next, it is preferable to deposit the photoresist layer 202 on the seed layer 201.

[0042] Referring to Figure 2C, the next step is to pattern the photoresist layer 202 to form via holes 114 that extend to the substrate 100, the first die 102, and the contact pads 106 on the second die 104. The photoresist layer may be either a negative photoresist in which the portion of the photoresist exposed to light is insoluble in the photoresist developer, or a positive photoresist in which the portion of the photoresist exposed to light is soluble in the photoresist developer. The patterned photoresist layer 202 forms a mask penetration portion that gives rise to the name of the method as an embodiment.

[0043] Referring to Figure 2D, a conductive material is deposited within the via hole 114 to form a via 118. The via can be formed by ALD, CVD, or any other suitable method.

[0044] Referring to Figure 2E, it is preferable to remove the photoresist layer 202. The removal of the photoresist layer 202 is preferably carried out by a wet chemical etching process or ashing. In addition, the remaining seed layer 201 is also removed.

[0045] Referring to Figure 2F, the low-CTE dielectric layer 204 is preferably deposited on the substrate 100, the first substrate 102, and the second die 104. In some embodiments, the low-CTE material has a CTE of 14 ppm / °C or less at room temperature. In other embodiments, the CTE is 10 ppm / °C or less. For comparison, the high-CTE material preferably has a CTE greater than 15 ppm / °C, for example, 15 to 30 ppm / °C. In some embodiments, the first low-stress dielectric layer 501 may consist of two or more dielectric layers. For example, a layer of material with a CTE of 12 to 20 ppm / °C may be covered with a material with a CTE of less than 12 ppm / °C, thereby improving the toughness of the structure. In one embodiment, the low-CTE dielectric layer 204 may consist of particles embedded in a polymer. For example, the low-CTE dielectric layer 204 may consist of SiO2 particles embedded in a resin or polyimide matrix. In some embodiments, the particles in the resin may contain aluminum nitride (AlN) or carbon to improve heat transfer and provide good thermal conductivity. Other particle and matrix materials may also be used.

[0046] Referring to Figure 2G, it is preferable to planarize the top surface of the low-CTE dielectric layer 204. Planarization is best performed using CPM.

[0047] Referring to Figure 2H, it is preferable to deposit the bonding dielectric layer 206 on a planar low-CTE dielectric layer 204. The bonding dielectric layer 206 is made of an inorganic dielectric, such as silicon oxide SiO2, silicon nitride Si3N4, or silicon oxynitride (SiO3N4). x N y ), or any other suitable dielectric material can be used.

[0048] Referring to Figure 2I, the conductive contact feature portion 208 is preferably formed in the bonding dielectric layer 206. The conductive feature portion 208 may be made of the same material as the via 118, or it may be made of a different conductive material. The conductive feature portion enables electrical contact between the third layer die (described below) and the substrate 100, the first die 102, and the second die 104. In various embodiments, a cavity is preferably formed in the dielectric layer 206, and the conductive feature portion 208 is preferably deposited into the cavity. In some embodiments, the dielectric layer 206 and the conductive feature portion 208 are preferably planarized and prepared for direct hybrid bonding as described herein. In other embodiments, the conductive feature portion may consist of a wire bond pad, and a bonding wire (not shown) can electrically connect the conductive feature portion 208 to another device or die.

[0049] Referring to Figure 2J, in the first embodiment, any of the third dies 120, 122, 124, 126, 128, 130, 134, and 138 described above may be hybrid-bonded to the bonding dielectric layer 206 and the conductive feature portion 208. Furthermore, as in the first embodiment, one or more fourth dies 142 may be hybrid-bonded to the third dies 120, 122, 124, 126, 128, and 134 at the fourth device level. This embodiment offers many of the advantages of the previous embodiments, but also offers the additional advantage of not requiring multiple dielectric deposition and multiple intermediate planarization steps. Using a single photoresist mask penetration simplifies the process, reduces the number of steps, and thus reduces costs.

[0050] Figures 3A to 3G are schematic cross-sectional views of another method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. With respect to Figure 3A, as with the embodiments described above, it is preferable to have a substrate 100 on which the first and second dies 102, 104 are hybrid-bonded. Furthermore, the substrate 100, the first die 102 and the second die 104 may have contact pads 106 disposed on the front surface, back surface, or both the front surface and back surface of the first and second dies 102, 104.

[0051] Referring to Figure 3B, it is preferable to print the via 118 onto the contact pad 106. The via 118 can be printed by 3D printing or any other suitable printing method, such as screen printing. The via 118 is preferably made of copper, silver, nickel, or an alloy thereof. In one embodiment, the via 118 consists of nanoparticles. The nanoparticles are preferably in the particle size range of about 1 nm to 1000 nm, for example, in the range of 10 nm to 500 nm, or for example, in the range of 50 nm to 250 nm. In various embodiments, half of the nanoparticles have a particle size of less than 100 nm. By directly printing the via 118 onto the contact pad 106, multiple dielectric layer deposition steps and multiple planarization steps can be eliminated. Furthermore, it is not necessary to form a mask penetration as in the method described above.

[0052] Referring to Figure 3C, it is preferable to heat the in-process package shown in Figure 3B to sinter the nanoparticles. That is, when the nanoparticles are heated to a sufficient temperature over a sufficient period of time, they aggregate and become solid without liquefying. In this way, the via 118 obtains structural integrity and improved conductivity. After heating, it is preferable to deposit the low-CTE dielectric layer 204 on the substrate 100, the first die 102, the second die 104, and the conductive feature portion 208. Alternatively, the low-CTE dielectric layer 204 may be deposited prior to the sintering of the nanoparticles. As described above with respect to the second embodiment, the low-CTE dielectric layer 204 preferably consists of SiO2 particles embedded in a resin or polyimide matrix.

[0053] Referring to Figure 3D, it is preferable to planarize the top surface of the low-CTE dielectric layer 204. Planarization is best performed, for example, by CMP.

[0054] Referring to Figure 3E, it is preferable to deposit the bonding dielectric layer 206 on a planar low-CTE dielectric layer 204. The bonding dielectric layer 206 is made of an inorganic dielectric, such as silicon oxide SiO2, silicon nitride Si3N4, or silicon oxynitride (SiO3N4). x N y ), or any other suitable dielectric material can be used.

[0055] Referring to Figure 3F, it is preferable to form the conductive feature portion 208 in the bonding dielectric layer 206. The conductive feature portion 208 may be made of the same material as the via 118, or it may be made of a different conductive material. The conductive feature portion enables electrical contact with the substrate 100, the first die 102, and the second die 104.

[0056] Referring to Figure 3G, in the first embodiment, it is preferable to hybrid bond any of the third dies 120, 122, 124, 126, 128, 130, 134, and 138 described above to the bonding dielectric layer 206 and the conductive feature portion 208. Furthermore, as in the first embodiment, it is preferable to hybrid bond one or more fourth dies 142 to the third dies 120, 122, 124, 126, 128, and 134 at the fourth device level.

[0057] As described above, this embodiment is advantageous because it eliminates the need for the deposition of numerous dielectric layers and multiple planarization steps by directly printing the vias 118 onto the contact pad 106. Furthermore, it eliminates the need to form mask penetrations as in the method described above.

[0058] Figures 4A to 4Jh are schematic cross-sectional views of a method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. With respect to Figure 44, as in the embodiments described above, it is preferable to prepare a substrate 100 on which the first and second dies 102, 104 are hybrid-bonded. Furthermore, it is preferable that contact field pads 106 are formed on the front surface, back surface, or both the front surface and back surface of the substrate 100, the first die 102, and the second die 104. As in the embodiments described above, it is preferable that the contact field pads 106 are positioned on the front surface, back surface, or both the front surface and back surface of the first and second dies 102, 104.

[0059] Referring to Figure 4B, the organic layer 402 is preferably deposited on the substrate 100, the first die 102, and the second die 104. The organic layer 402 can be composed of a dielectric, such as a resin, polyimide, or any other suitable organic dielectric. In some configurations, the resin is preferably composed of granular material. In some embodiments, the organic material is preferably composed of a liquid crystal polymer. The organic layer is preferably spin-coated, laminated, or formed by other known methods. In some embodiments, the low CTE of the organic layer 402 is less than 20 ppm / °C or less than 10 ppm / °C.

[0060] Referring to Figure 4C, it is preferable to form the via holes 114 in the organic layer 402. In one embodiment, it is preferable to form a photolithography mask (not shown) on the organic layer 402 and the via holes 114 formed by chemical wet etching or dry etching, such as reactive ion etching or laser ablation. After the via holes 114 are formed, it is preferable to remove the photolithography mask.

[0061] Referring to Figure 4D, it is preferable to form the metallization layer in the via hole 114 and on the organic layer 412. As in the previous embodiment, it is preferable to deposit the barrier / adhesive layer 116 / 117 prior to the deposition of the metallization layer 118. In one embodiment, the metallization layer 118 may consist of metal nanoparticles, such as copper, nickel, silver, or alloys thereof. It is preferable to anneal the formed metallization layer at a high temperature before the planarization step. In one embodiment, the via hole 114 can be filled using 3D printing or any other suitable printing method.

[0062] Referring to Figure 4E, it is preferable to flatten the top surface of the in-process topographic package to remove excess metallization material and barrier / adhesive material.

[0063] Referring to Figure 4F, it is preferable to flatten the top surface of the in-process topographic package to remove excess metallization material and barrier / adhesive material.

[0064] Referring to Figure 4G, it is preferable to deposit the bonding dielectric layer 106 on the planar top surface of the in-process topographic package. The bonding dielectric layer 206 consists of silicon oxide SiO2, silicon nitride Si3N4, and silicon oxynitride SiO2. x N y , or can be made of any other suitable dielectric material.

[0065] Referring to Figure 4H, it is preferable to form the conductive feature portion 208 in the bonding dielectric layer 206. The conductive feature portion 208 may be made of the same material as the via 118, or it may be made of a different conductive material. The conductive feature portion enables electrical contact with the substrate 100, the first die 102, and the second die 104.

[0066] Referring to Figures 4I and 4J, in the first embodiment, it is preferable to hybrid bond any of the third dies 120, 122, 124, 126, 128, 130, 134, and 138 described above to the bonding dielectric layer 206 and the conductive feature portion 208. Furthermore, as in the first embodiment, it is preferable to hybrid bond one or more fourth dies 142 to the third dies 120, 122, 124, 126, 128, and 134 at the fourth device level.

[0067] This embodiment includes substantially the same mask penetration portion as the embodiment shown in Figures 2A to 2J. However, instead of depositing the metallization layer 118 using ALD or CVD, the metallization layer 118 can be printed by, for example, 3D printing, screen printing, or any other suitable printing method.

[0068] Figures 5A to 5O are schematic cross-sectional views of a method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. This embodiment of the method may be referred to as a selective dielectric wet etching method. With respect to Figure 5A, as with the embodiments described above, it is preferable to prepare a substrate 100 on which the first and second dies 102 and 104 are hybrid-bonded. Furthermore, it is preferable that contact field pads 106 are formed on the front surface, back surface, or both the front surface and back surface of the substrate 100, the first die 102, and the second die 104. As with the embodiments described above, it is preferable that the contact field pads 106 are positioned on the front surface, back surface, or both the front surface and back surface of the first and second dies 102 and 104.

[0069] Referring to Figure 5B, it is preferable to deposit the low-CTE dielectric layer 204 on the substrate 100, the first die 102, and the second die 104. As mentioned above, the low-CTE dielectric layer 204 is preferably composed of particles embedded in a polymer. For example, the low-CTE dielectric layer 204 is preferably composed of SiO2 particles embedded in a resin or polyimide matrix.

[0070] Referring to FIG. 5B, the first low stress dielectric layer 501 may be deposited on the substrate 100, the first die 102, and the second die 104. Typically, the stress of PECVD SiO2 is about 350 MPa, and this stress can be said to be as high as 800 MPa during compression. In some embodiments, the first low stress dielectric layer 501 has a stress of less than 200 MPa. In other embodiments, the first low stress dielectric layer 501 has a stress of 100 MPa. In other embodiments, the first low stress dielectric layer 501 has a stress of less than 40 MPa (which can be said to be the stress during compression). In some embodiments, the low stress dielectric layer 501 has a stress in the range from 20 MPa to 100 MPa. In some embodiments, the tensile modulus of the first dielectric layer 501 may be in the range from 1 GPa to 70 GPa. In other embodiments, the tensile modulus of the first dielectric layer 501 may be in the range from 4 GPa to 50 GPa. In other embodiments, the tensile modulus of the first dielectric layer 501 may be in the range from 14 GPa to 40 GPa. The first low stress dielectric layer 501 may be silicon oxide SiO2, silicon nitride Si3N4, silicon oxynitride SiO x N y , or any other suitable dielectric. The first low stress dielectric layer 501 preferably has a thickness in the range from 10 microns to 50 microns to reduce stress.

[0071] Referring to FIG. 5C, a planarization layer 503 may be deposited on the first low stress dielectric layer 501. In this embodiment, the planarization layer 503 may be made of an insulating material, such as a polymer material, such as a photoresist, a resin, or a polyimide.

[0072] Referring to FIG. 5D, a portion of the planarization layer 503 is removed, thereby exposing a portion of the first low stress dielectric layer 501. Specifically, the level of the planarization layer 503 is lowered below the top surface of the first low stress dielectric layer 501 on the first and second dies 102, 104. The removal may be performed, for example, by ashing, thereby exposing the planarization layer 503 to an oxygen plasma.

[0073] Referring to Figure 5E, the top portion of the first low-stress dielectric layer 501 exposed by planarizing the in-process topographic package is thinned. Planarization is preferably achieved by CMP.

[0074] Referring to Figure 5F, the planarization layer 503 is removed. Removal is preferably achieved by wet chemical etching, ashing, or other known methods.

[0075] Referring to Figure 5G, it is preferable to deposit the second low-stress dielectric layer 502 on the first low-stress dielectric layer 501. The second low-stress dielectric layer 502 is composed of silicon oxide SiO2, silicon nitride Si3N4, and silicon oxynitride SiO2. x N y , or any other suitable dielectric material. The second low-stress dielectric layer 502 preferably has a thickness ranging from 10 to 50 microns to reduce stress.

[0076] Referring to Figure 5H, the second low-stress dielectric layer 502 is covered with a planarization layer 503. The planarization layer is preferably made of the same type of material used in the step shown in Figure 5C.

[0077] Referring to Figure 5I, a portion of the planarization layer 503 is removed, thereby exposing a portion of the second low-stress dielectric layer 502. In particular, the level of the planarization layer 503 is lowered below the top surface of the second low-stress dielectric layer 502 on the first and second dies 102, 104. The removal is preferably carried out by ashing, for example.

[0078] Referring to Figure 5J, the top portion of the exposed second low-stress dielectric layer 502 is thinned by planarizing the in-process topographic package. Planarization is preferably performed by CMP.

[0079] Referring to Figure 5K, the planarization layer 503 is removed. Removal is preferably carried out by wet chemical etching or ashing.

[0080] Referring to Figure 5L, vias 118 are formed in the first and second low-stress dielectric layers 501 and 502, so that some of the via holes 114 contact the substrate 100, some of the via holes 114 contact the first die 102, and some of the via holes 114 contact the second die 104. The via holes 114 can be formed by any suitable method, such as RIE or chemical wet etching.

[0081] Referring to Figure 5M, it is preferable to deposit a barrier layer / adhesive layer 116 / 117 so that the barrier layer / adhesive layer 116 / 117 conformally covers the surface of the via hole 114. Next, it is preferable to deposit a metallization layer 118 on the barrier layer / adhesive layer 116 / 117. The barrier layer / adhesive layer 116 / 117 can be conformally deposited using any suitable method, such as ALD and CVD. In one embodiment, the barrier layer / adhesive layer 116 / 117 consists of separate barrier layer 116 and adhesive layer 117. Suitable materials for the barrier layer 116 include, but are not limited to, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride. The adhesive layer 117 is preferably a seed layer composed of the same material as the metallization layer 118.

[0082] Referring to Figure 5N, chemical mechanical polishing is performed to remove excess metallization layer 118 material and excess barrier / adhesive layer 116 / 117 material. CMP also planarizes the surface of the third dielectric layer 112, thereby forming a surface suitable for hybrid bonding.

[0083] Referring to Figure 5O, in the first embodiment, it is preferable to hybrid bond any of the third dies 120, 122, 124, 126, 128, 130, 134, and 138 described above to the bonding dielectric layer 206 and the conductive feature portion 208. Furthermore, as in the first embodiment, it is preferable to hybrid bond one or more fourth dies 142 to the third dies 120, 122, 124, 126, 128, and 134 at the fourth device level.

[0084] In this method, the polymer planarization layer 503 is used in combination with the wet etching of the low-stress dielectric layers 501 and 502. Planarization of the polymer planarization layer 503 is easier and faster than planarization of the low-stress dielectric layers 501 and 502. Furthermore, wet etching of the low-stress dielectric layers 501 and 520 is easier and cheaper than using CMP. Thus, as a result of this method, an inexpensive package can be obtained.

[0085] Figures 6A to 6K are schematic cross-sectional views of a method for manufacturing an exemplary topographic package according to some embodiments of the disclosed technology. This embodiment may be referred to as the mixed dielectric coating in topography method. With respect to Figure 6A, as in the embodiments described above, it is preferable to prepare a substrate 100 on which the first and second dies 102, 104 are hybrid-bonded. Furthermore, as shown in Figure 6A, it is preferable that the first and second dies 102, 104 have contact field pads 106 located on the front surface, back surface, or both the front surface and back surface of the first and second dies 102, 104.

[0086] Referring to Figure 6B, it is preferable to deposit the first dielectric layer 108 on the substrate 100, the first die 102, and the second die 104. The first dielectric layer 108 is made of silicon oxide SiO2, silicon nitride Si3N4, and silicon oxynitride SiO2. x N y, or any other suitable dielectric material. In this embodiment, the thickness of the first dielectric layer 108 is in the range of 1 micron to 5 microns.

[0087] Referring to Figure 6C, it is preferable to deposit the organic layer 402 on the first dielectric layer 108. The organic layer 402 can be made of a dielectric, such as a resin, polyimide, or any other suitable organic dielectric.

[0088] Referring to Figure 6D, a portion of the organic layer 402 is removed, thereby exposing a portion of the first dielectric layer 108. In particular, the level of the organic layer 402 is lowered below the top surface of the first dielectric layer 108 on the first and second dies 102,104. The removal is preferably achieved by ashing, for example.

[0089] Referring to Figure 6E, the exposed portion of the first dielectric layer 108 is thinned. Planarization is preferably achieved by wet etching, for example.

[0090] Referring to Figure 6F, it is preferable to deposit the bonding dielectric layer 206 on the exposed first dielectric layer 108 and organic layer 402. The bonding dielectric layer 206 is made of silicon oxide SiO2, silicon nitride Si3N4, and silicon oxynitride SiO2. x N y , or any other suitable dielectric material.

[0091] Referring to Figure 6G, via holes 114 are formed in the bonding dielectric layer 206, the first dielectric layer 108, and the organic layer 402, so that some of the via holes 114 contact the substrate 100, some of the via holes 114 contact the first die 102, and some of the via holes 114 contact the second die 104. The via holes 114 can be formed by any suitable method, for example, RIE or chemical wet etching.

[0092] Referring to Figure 6H, it is preferable to deposit the barrier layer / adhesive layer 116 / 117 so that the barrier layer / adhesive layer 116 / 117 conformally covers the surface of the via hole 114. Next, it is preferable to deposit the metallization layer 118 on the barrier layer / adhesive layer 116 / 117. The barrier layer / adhesive layer 116 / 117 can be conformally deposited using any suitable method, such as ALD and CVD. In one embodiment, the barrier layer / adhesive layer 116 / 117 consists of separate barrier layer 116 and adhesive layer 117. Suitable materials for the barrier layer 116 include, but are not limited to, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride. The adhesive layer 117 is preferably a seed layer composed of the same material as the metallization layer 118.

[0093] Referring to Figure 6I, chemical mechanical polishing is performed to remove excess metallization layer 118 material and excess barrier / adhesion layer 116 / 117 material. CMP also planarizes the surface of the bonding dielectric layer 206, thereby forming a surface suitable for hybrid bonding.

[0094] Referring to Figure 6J, in the first embodiment, it is preferable to hybrid bond any of the third dies 120, 122, 124, 126, 128, 130, 134, and 138 described above to the bonding dielectric layer 206 and the conductive feature portion 208. Furthermore, as in the first embodiment, it is preferable to hybrid bond one or more fourth dies 142 to the third dies 120, 122, 124, 126, 128, and 134 at the fourth device level.

[0095] The method according to this embodiment includes the deposition of a standard dielectric layer 108 and an organic layer 402. The processing of the organic layer 402 is easier and less expensive than conventional methods for forming a topographic package.

[0096] Figures 7A and 7B are process flowcharts showing a method 700 for manufacturing a topographic package according to several embodiments. Referring to step 702, a first die 102 is hybrid-bonded to a substrate 100. Referring to step 704, a second die 104 is hybrid-bonded to the first die 102, the second die 104 having a smaller surface area than the first die 102, and contact pads 106 are formed on the substrate 100, the first die 102, and the second die 104. Referring to step 706, a photoresist layer 202 is deposited on the substrate 100, the first die 102, and the second die 104. Referring to step 708, the photoresist layer 202 is patterned to form via holes 114 leading to the contact pads 106. Referring to step 710, a conductive material is deposited into the via holes 114 to form conductive vias 118 within the via holes 114. Referring to step 712, the photoresist layer 202 is removed. Referring to step 714, the low CTE dielectric layer 204 is deposited on the substrate 100, the first and second dies 102, 104, and the conductive vias 118. Referring to step 716, the top surface of the low thermal expansion dielectric layer 204 is planarized to expose the conductive vias 118. Referring to step 718, a bonding dielectric layer 206 is deposited on the low CTE dielectric layer 204. Referring to step 720, vias 118, 208 are formed in the low CTE dielectric layer 204. Referring to step 722, the third dies 120, 122, 124, 126, 128, 130, 134, 138 are hybrid bonded to the top surface of the low CTE dielectric layer 204 and the conductive vias 118.

[0097] Figure 8 is a process flowchart of another method for manufacturing an exemplary topographic package according to several embodiments. Referring to step 802, a first die 102 is hybrid-bonded to the substrate 100. Referring to step 804, a second die 104 is hybrid-bonded to the first die, the second die 104 having a smaller surface area than the first die 102, and contact pads 106 are formed on the substrate 100, the first die 102, and the second die 104. Referring to step 806, vias 118 are printed on the substrate 100 and the first and second dies 102, 104, the vias 118 being made of conductive nanoparticles. Referring to step 808, the conductive nanoparticles are heated to sinter them. Referring to step 810, a low CTE dielectric layer 204 is deposited on the substrate 100, the first and second dies 102, 104, and the vias 118. Referring to step 812, the top surface of the low-CTE dielectric layer 204 is planarized to expose the vias 118. Referring to step 814, the bonding dielectric layer 206 is deposited on the low-CTE dielectric layer 204. Referring to step 816, the vias 118 are formed in the low-CTE dielectric layer 204. Referring to step 818, at least the third dies 120, 122, 124, 126, 128, 130, 134, 138 are hybrid-bonded to the top surface and conductive features of the low-CTE dielectric layer 204.

[0098] Figure 9 is a process flowchart of another method for manufacturing an exemplary topographic package according to several embodiments. Referring to step 902, a first die 102 is hybrid-bonded to the substrate 100. Referring to step 904, a second die 104 is hybrid-bonded to the first die 102, the second die 104 having a smaller surface area than the first die 102, and contact pads 106 are formed on the substrate 100, the first die 102, and the second die 104. Referring to step 906, an organic layer 402 is deposited on the substrate 100, the first die 102, and the second die 104. Referring to step 908, a conductive material is printed into via holes 114 and on the top surface of the organic layer 402 to form vias in the via holes, the conductive material comprising conductive nanoparticles. Referring to step 910, a conductive material is printed into the via holes 114 and covering the top surface of the organic layer 402 to form vias in the via holes 114, the conductive material consisting of conductive nanoparticles. Referring to step 912, the conductive material is sintered. Referring to step 914, excess conductive material is removed from the top surface of the organic layer 402. Referring to step 916, a bonding dielectric layer 206 is formed on the top surface of the organic layer 402 and the top surface of the vias 118. Referring to step 918, a contact pad 106 is formed in the bonding dielectric layer 206 using the damascene method. Referring to step 920, at least third dies 120, 122, 124, 126, 128, 130, 134, 138 are hybrid-bonded to the prepared top surface of the low CTE dielectric layer 204 and the vias 118.

[0099] Figures 10A and 10B are process flowcharts of another method for manufacturing an exemplary topographic package according to several embodiments. Referring to step 1002, a first die 102 is hybrid-bonded to the substrate 100. Referring to step 1004, a second die 104 is hybrid-bonded to the first die 102, the second die 104 having a smaller surface area than the first die 102, and contact pads 106 are formed on the substrate 100, the first die 102, and the second die 104. Referring to step 1006, a first low-stress dielectric layer 501 is deposited on the substrate 100, the first die 102, and the second die 104. Referring to step 1008, a first planarization layer 503 is deposited on the first low-stress dielectric layer 501. Referring to step 1010, a portion of the first planarization layer 503 is removed. Referring to step 1012, the top portion of the first low-stress dielectric layer 501 is selectively wet-etched. Referring to step 1014, the remainder of the first planarization layer 503 is removed. Referring to step 1016, the second low-stress dielectric layer 502 is deposited on the first low-stress dielectric layer 501. Referring to step 1018, the second planarization layer 503 is deposited on the second low-stress dielectric layer 502. Referring to step 1020, a portion of the second planarization layer 503 is removed. Referring to step 1022, the top portion of the second low-stress dielectric layer 502 is selectively wet-etched. Referring to step 1024, the second low-stress dielectric layer 502 is planarized. Referring to step 1026, the first and second low-stress dielectric layers 501, 502 are selectively etched to form via holes 114 within the first and second low-stress dielectric layers 501, 502, and the contact pads 106 are exposed on the first and second dies 102, 104 and the substrate 100. Referring to step 1028, adhesive layers 116 / 117 are deposited into the via holes 114. Referring to step 1030, a metal layer 118 is deposited in the via holes 114. Referring to step 1032, excess metal layer 118 is removed. Referring to step 1034, one or more additional dies are hybrid-bonded to the prepared bonding surface of the second low-stress dielectric layer 502 and the vias 118.

[0100] Figures 11A and 11B are process flowcharts of another method for manufacturing an exemplary topographic package according to several embodiments. Referring to step 1102, a first die 102 is hybrid-bonded to the substrate 100. Referring to step 1104, a second die 104 is hybrid-bonded to the first die 102, the second die 104 having a smaller surface area than the first die 102, and contact pads 106 are formed on the substrate 100, the first die 102, and the second die 104. Referring to step 1106, a first dielectric layer 108 is deposited on the substrate 100. Referring to step 1108, a low-stress polymer layer 402 is deposited on the first dielectric layer 108. Referring to step 1110, a portion of the stress polymer layer 402 is removed. Referring to step 1112, the top portion of the first dielectric layer 108 is selectively wet-etched. Referring to step 1114, the bonding dielectric layer 206 is deposited on the first dielectric layer 108 and the low-stress polymer layer 402. Referring to step 1116, via holes 114 are formed in the bonding dielectric layer 206, the low-stress polymer layer 402 and the first dielectric layer 108, exposing the pads on the first die 102, the second die 104 and the substrate 100. Referring to step 1118, a barrier layer is formed in the via holes 114. Referring to step 1120, a metal layer is deposited in the via holes 114 to form vias 118. Referring to step 1122, excess metal is removed. Referring to step 1124, the third dies 120, 124, 126, 128, 130, 134, and 138 are hybrid-bonded to the top surfaces of the bonding dielectric layer 206 and the vias 118.

[0101] In some embodiments, the conductive via 114 may consist of an incompletely charged via cavity, for example, a cavity containing a conformally charged conductive layer. After the planarization and cleaning steps, the coated charged layer 206 can line the inside of the incompletely charged via and plug the via opening. In practice, it is preferable to planarize the coated dielectric layer 206 and then pattern the dielectric layer 206 to form a cavity for the conductive feature portion 208. In some embodiments, the formed dielectric layer 206 may consist of a redistribution layer formed on the top surface of the die 104. In some embodiments, the conductive feature portion of the redistribution layer is connected to the via 118 of the present invention.

[0102] Unless otherwise explicitly stated in the context, throughout the original specification and claims, “comprise” (often translated as “having”), “comprising”, “include” (often translated as “including”), and “including” should be understood in an inclusive sense, i.e., “including, but not limited to,” rather than in an exclusive or exhaustive sense. The expression “combined” as commonly used herein refers to two or more elements that may be either directly combined or combined by one or more intermediate elements. Similarly, the expression “linked” as commonly used herein refers to two or more elements that may be either directly linked or linked by one or more intermediate elements. In addition, when used in this application, “in this specification”, “above (or above)”, “below (or below)”, and similar terms refer to the entire application and not to any particular part thereof. Furthermore, where a first element is described as "on" or "covering" a second element, as used herein, the first element may directly be on or covering the second element, resulting in the first and second elements being in direct contact with each other, or the first element may be indirectly located on or covering the second element, resulting in one or more elements being interposed between the first and second elements. Where the context allows, the terms used in the above detailed descriptions, whether singular or plural, may also include plural or singular forms, respectively. The term "or" when referring to a list of two or more items includes the following interpretations of the term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0103] Furthermore, conditional words used in the original specification, such as in particular "can" (sometimes translated as "it would be preferable"), "could" ("may be possible"), "might" ("might be possible"), or "may" ("may be possible"), and "for example" as used herein, generally mean, unless otherwise specified or understood differently in the context in which they are used, that a particular embodiment includes certain features, elements, and / or steps, while other embodiments do not include certain features, elements, and / or steps. Thus, such conditional words generally do not suggest that the features, elements, and / or steps are required to some extent in one or more embodiments.

[0104] While certain embodiments have been described, these embodiments are provided for illustrative purposes only and are not intended to limit the scope of this disclosure. Indeed, the novel apparatus, methods, and systems described herein can be embodied in various other forms, and various omissions, substitutions, and modifications of the forms of methods and systems described herein can be implemented without departing from the spirit of the disclosure. For example, while blocks (framed portions) are provided in a given arrangement, modified embodiments can implement similar functions with different components and / or circuit topologies, and some blocks can be omitted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be embodied in various different ways. Any appropriate combination of elements and actions of the various embodiments described above can be combined to provide another embodiment. The claims of the appended claims and their equivalents include such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. It is an electronic component, The device has a first die that is directly hybrid bonded to a first substrate, the first die being positioned at the first device level, The device has a second die positioned at the second device level above the first device, the second die being directly hybrid bonded to the first die. An electronic component having a third die positioned at a third device level above the second die, wherein the third die is directly hybrid bonded to the top surface of the second device level.

2. The electronic component according to claim 1, wherein the third die is electrically connected to the first die, the second die, and the first substrate by conductive vias.

3. The electronic component according to claim 2, wherein one or more of the electrical connection parts are made of sintered conductive nanoparticles.

4. The electronic component according to claim 1, further comprising an interposer disposed between the second die and the third die.

5. The electronic component according to claim 1, further comprising a redistribution layer disposed between the second die and the third die.

6. The electronic component according to claim 1, wherein the third die is mounted on a second substrate.

7. The device further comprises a fourth die positioned at the third device level, the fourth die being electrically connected to the first substrate and the second die, or Electrically connected only to the first substrate, or The electronic component according to claim 1, which is electrically connected only to the second die.

8. The electronic component according to claim 1, further comprising a fourth die positioned at a fourth device level.

9. The electronic component according to claim 6, wherein the fourth die is hybrid-bonded to the third die.

10. The electronic component according to claim 1, wherein the third die is made of a chiplet.

11. The electronic component according to claim 1, having at least one top pad located at the third device level.

12. The electronic component according to claim 1, further comprising a protective film applied to the top portion of the electronic component.

13. The electronic component according to claim 1, wherein the electronic component includes an oxide dielectric layer and a polymer dielectric layer, the oxide dielectric layer and the polymer dielectric layer are arranged above the first substrate and surround the first and second dies.

14. A method for manufacturing electronic components, The process includes the step of directly hybrid bonding a first die to a substrate, The process includes the step of directly hybrid bonding a second die to the first die, wherein the second die has a smaller surface area than the first die, and bond pads are formed on the substrate, the first die, and the second die. The process includes the step of depositing a photoresist layer on the substrate, the first die, and the second die, The step includes patterning the photoresist layer to form via holes that pass through the photoresist layer to the bond pad, The step includes applying a conductive material to the via hole to form a conductive via within the via hole, The step includes removing the photoresist layer, The process includes the step of depositing a low-CTE dielectric layer with a low coefficient of thermal expansion (CTE) onto the substrate, the first die, the second die, and the conductive vias. The step includes flattening the top surface of the low-CTE dielectric layer to expose the conductive vias, The process includes the step of depositing a bonding dielectric layer on the low CTE dielectric layer, The process includes the step of forming a conductive characteristic portion in the low CTE dielectric layer, A method comprising the step of directly hybrid bonding a third die to the top surface and conductive vias of the low CTE dielectric layer.

15. The method according to claim 14, further comprising the step of depositing a barrier layer and a seed layer before depositing the photoresist layer.

16. The method according to claim 14, wherein the low CTE dielectric layer comprises nanoparticles embedded in a polymer.

17. The method according to claim 16, wherein the nanoparticles are made of silica.

18. The method according to claim 14, wherein the conductive material in the via hole is made of copper, nickel, or an alloy thereof.

19. The method according to claim 15, wherein the polymer is epoxy or polyimide.

20. The method according to claim 14, wherein the low CTE dielectric layer comprises a plurality of layers.

21. The method according to claim 14, further comprising the step of forming the bonding dielectric layer over the low CTE dielectric layer.

22. The method according to claim 18, further comprising the step of forming a conductive feature portion in the bonding dielectric layer.

23. The method according to claim 14, further comprising the step of forming a redistribution layer covering the bonding dielectric layer.

24. The method according to claim 14, further comprising the step of applying a protective film.

25. It is an electronic component, A first die directly hybrid bonded to the substrate, A second die directly hybrid-bonded to the first die, An insulating material is provided covering the substrate and at least partially enclosing the first and second dies, A third die bonded to the insulating material, An electronic component having a first conductor that penetrates at least a portion of the insulating material and electrically connects the third die with at least one of the first die, the second die, and the substrate.

26. The electronic component according to claim 25, wherein an upper bond pad is formed on the top surface of a bonding dielectric layer, and the upper bond pad is configured to supply electricity to the electronic component.

27. The electronic component according to claim 25, wherein the first conductor is made of a conductive via.

28. The electronic component according to claim 26, further comprising additional vias for connecting the third die to at least one of the first die, the second die, or the substrate.

29. The electronic component according to claim 25, further comprising a wire bonding pad provided on the insulating material and a wire bond connected to the wire bonding pad.

30. A method for manufacturing electronic components, The process includes the step of hybrid bonding a first die to a substrate, The process includes the step of hybrid bonding a second die to the first die, wherein the second die has a smaller surface area than the first die, and bond pads are formed on the substrate, the first die, and the second die. The step includes forming an insulating material that covers the substrate and at least partially encloses the first and second dies, The process includes the step of directly hybrid bonding a third die to the insulating material, A method comprising the step of forming a first conductor that penetrates at least a portion of the insulating material and electrically connects the third die to at least one of the first die, the second die, and the substrate.

31. The method according to claim 30, wherein the insulating material comprises a polymer, an oxide, or a layer of an oxide and a layer of polymer.

32. The method according to claim 30, further comprising the step of forming an additional conductor for connecting the third die to at least one of the first die, the second die, or the substrate.

33. The method according to claim 30, wherein the step of forming the first conductor includes the step of printing nanoparticles.

34. The method according to claim 30, wherein the step of forming the insulating material includes the step of depositing a polymer with dielectric nanoparticles embedded within the polymer.

35. A method for manufacturing electronic components, The process includes the step of directly hybrid bonding a first die to a substrate, The process includes the step of hybrid bonding a second die to the first die, wherein the second die has a smaller surface area than the first die, and bond pads are formed on the substrate, the first die, and the second die. The process includes the step of printing vias onto the substrate and the first and second dies, wherein the vias are made of conductive nanoparticles. The step includes heating the conductive nanoparticles to sinter them, The process includes the step of depositing a low-CTE dielectric layer with a low coefficient of thermal expansion (CTE) onto the substrate, the first die, the second die, and the vias. The step includes flattening the top surface of the low-CTE dielectric layer to expose the vias, The process includes the step of depositing a bonding dielectric layer on the low CTE dielectric layer, The process includes the step of forming a conductive characteristic portion in the low CTE dielectric layer, A method comprising the step of directly hybrid bonding at least a third die to the top surface and the conductive feature portion of the low CTE dielectric layer.

36. The method according to claim 35, wherein the conductive nanoparticles are made of copper, silver, nickel, or an alloy thereof.

37. The method according to claim 35, wherein the conductive feature portion is printed using a 3D printer.

38. The method according to claim 35, wherein the low CTE dielectric layer consists of particles embedded in a polymer.

39. The low CTE dielectric layer is SiO 2 The method according to claim 38, comprising particles embedded in a resin or polymer matrix.

40. The bonding dielectric layer is silicon oxide (SiO 2 silicon nitride Si 3 N 4 or silicon oxynitride SiO x N y The method according to claim 38, comprising:

41. A method for manufacturing electronic components, The process includes the step of directly hybrid bonding a first die to a substrate, The process includes the step of directly hybrid bonding a second die to the first die, wherein the second die has a smaller surface area than the first die, and bond pads are formed on the substrate, the first die, and the second die. The step includes depositing the organic layer onto the substrate, the first die, and the second die, The step includes patterning the organic layer to form via holes leading to the bond pad, The process includes the step of printing a conductive material into the via hole and covering the top surface of the organic layer to form a via in the via hole, wherein the conductive material consists of conductive nanoparticles. The step includes sintering the conductive material, The process includes the step of removing excess conductive material from the top surface of the organic layer, The process includes the step of forming a bonding dielectric layer covering the top surface of the organic layer and the top surface of the via, The process includes the step of forming a bond pad in the bonding dielectric layer using the damascene method, A method comprising the step of directly hybrid bonding at least a third die to the top surface and vias of the bonding dielectric layer having a low coefficient of thermal expansion.

42. The method according to claim 41, further comprising the step of forming a protective layer covering the electronic component.

43. The method according to claim 41, further comprising the step of separating the electronic component into a single unit.

44. The method according to claim 41, wherein the step of sintering the conductive material is performed in microwaves or in a vacuum.

45. The method according to claim 41, wherein the conductive nanoparticles are made of silver, copper, nickel, or an alloy thereof.

46. A method for manufacturing electronic components, The process includes the step of directly hybrid bonding a first die to a substrate, The process includes the step of directly hybrid bonding a second die to the first die, wherein the second die has a smaller surface area than the first die, and bond pads are formed on the substrate, the first die, and the second die. The process includes the step of depositing a first low-stress dielectric layer on the substrate and the first and second dies, The process includes the step of depositing a first planarization layer on the first low-stress dielectric layer, The process includes the step of removing a portion of the first planarization layer, The process includes the step of selectively wet etching the top portion of the first low-stress dielectric layer, The process includes the step of removing the remaining portion of the first planarization layer, The process includes the step of depositing a second low-stress dielectric layer on the first low-stress dielectric layer, The process includes the step of depositing a second planarization layer on the second low-stress dielectric layer, The process includes the step of removing a portion of the second planarization layer, The process includes the step of selectively wet etching the top portion of the second low-stress dielectric layer, The process includes the step of planarizing the second low-stress dielectric layer, The process includes the steps of selectively etching the first and second low-stress dielectric layers to form via holes in the first and second low-stress dielectric layers, and exposing the bond pads on the first and second dies and the substrate, The step includes depositing an adhesive layer into the via hole, The step includes depositing a metal layer into the via hole, The process includes the step of removing an excess metal layer, A method comprising the step of directly hybrid bonding one or more additional dies to the second low-stress dielectric layer and vias.

47. The method according to claim 46, wherein the low-stress dielectric layer has a thickness of 10 to 50 microns.

48. The method according to claim 46, wherein the step of removing a portion of the first planarization layer comprises ashing.

49. The method according to claim 46, wherein the step of removing a portion of the second planarization layer comprises ashing.

50. The method according to claim 46, wherein the step of planarizing the second low-stress dielectric layer is performed by chemical mechanical polishing.

51. The method according to claim 46, further comprising the step of forming a barrier layer in the via hole before forming the adhesive layer.

52. The method according to claim 46, wherein the adhesive layer is a barrier layer.

53. The method according to claim 46, wherein the step of depositing a metal layer in the vias comprises atomic layer deposition (ALD) or chemical vapor deposition (CVD).

54. The method according to claim 46, further comprising the step of separating the electronic components to form separate electronic components.

55. The low stress dielectric layer is SiO 2 , Si 3 N 4 , or silicon oxynitride, the method according to claim 46.

56. The method according to claim 46, further comprising the step of forming a redistribution layer before hybrid bonding one or more additional dies.

57. A method for manufacturing electronic components, The process includes the step of directly hybrid bonding a first die to a substrate, The process includes the step of directly hybrid bonding a second die to the first die, wherein the second die has a smaller surface area than the first die, and bond pads are formed on the substrate, the first die, and the second die. The process includes the step of depositing a first dielectric layer on the substrate, The process includes the step of depositing a low-stress polymer layer on the first dielectric layer, The step includes removing a portion of the low-stress polymer layer. The process includes the step of selectively wet etching the top portion of the first dielectric layer, The process includes the step of depositing a bonding dielectric layer on the first dielectric layer and the low-stress polymer layer, The process includes the steps of forming via holes in the bonding dielectric layer, the low-stress polymer layer, and the first dielectric layer, and exposing the pads on the first die, the second die, and the substrate. The step includes forming a barrier layer in the via hole, The step includes depositing a metal layer in the via hole to form a via, The step includes removing excess metal, A method comprising the step of directly hybrid bonding a third die to the top surface of the bonding dielectric layer and the top surface of the vias.

58. The method according to claim 57, wherein the first dielectric layer has a thickness of 1 to 5 microns.

59. The method according to claim 57, wherein the barrier layer is also an adhesive layer.

60. The method according to claim 57, wherein the metal in the via is deposited by electroplating, electroless plating, atomic layer deposition (ALD), or chemical vapor deposition (CVD).

61. The method according to claim 57, wherein the low-stress polymer layer is made of polyimide.

62. The method according to claim 57, wherein the step of removing a portion of the low-stress polymer layer is performed in an oxygen plasma.

63. The method according to claim 57, comprising the step of forming a top bond pad on the top surface of the bonding dielectric layer.

64. The method according to claim 57, further comprising the step of forming an upper bond pad on the top surface of the bonding dielectric layer, wherein the upper bond pad is configured to supply electricity to an electrical component.

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