Integrated solution for deep contact gap filling of NAND

Abstract

A method for filling a via having a necking point includes the steps of: performing a pre-cleaning process to remove residue from the exposed surface of the metal layer at the bottom of the via and to restore the inner surface of the via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the via with a metal filler material.

Description

Technical Field

[0001] Embodiments of the present specification relate to a method used in the manufacture of electronic devices, and more particularly, to a process for filling deep contact gaps in NAND devices with high-quality tungsten (W).

Background Art

[0002] Tungsten (W) is widely used in the manufacture of integrated circuit (IC) devices to form conductive features that require relatively low electrical resistance and relatively high resistance to electromigration. For example, tungsten may be used as a metal filling material for forming source contacts, drain contacts, metal gate fills, gate contacts, interconnects (e.g., horizontal features formed on the surface of a dielectric material layer), and vias (e.g., vertical features formed through a dielectric material layer to connect other interconnect features disposed above and below the dielectric material layer). Tungsten is generally also used to form M0-level interconnects of IC devices, as well as bit lines and word lines used to address individual memory cells within a memory cell array of a three-dimensional NAND (3D NAND) device, because of its relatively low resistivity.

[0003] In next-generation NAND devices, the metal contact structure is transitioning from a single-stage tapered structure to a multi-stage structure with landing pads. It has been shown that conventional deposition processes such as chemical vapor deposition (CVD) have a problem in that when deep contact gaps such as a multi-stage structure with landing pads are filled with tungsten, voids or seams are formed in the filled tungsten.

[0004] Therefore, there is a need for a process that can fill deep contact gaps in NAND devices with tungsten (W) to form high-quality interconnects.

Summary of the Invention

[0005] Embodiments of the present disclosure provide a method for filling a via having a necking point. The method includes the steps of: performing a pre-cleaning process to remove residue from the exposed surface of the metal layer at the bottom of the via and to restore the inner surface of the via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the via with a metal filler material.

[0006] Embodiments of the present disclosure provide a method for filling vias having a necking point. The method includes the steps of: performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the liner layer below the necking point; and performing a metal filling process to fill the via with a metal filler material.

[0007] Embodiments of the present disclosure provide a method for filling vias having a necking point. The method includes the steps of: performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the liner layer below the necking point; and performing a metal filling process to fill the via with a metal filler material.

[0008] To enable a more detailed understanding of the above-mentioned features of this disclosure, a more specific description of this disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that since this disclosure may allow for other equally valid embodiments, the accompanying drawings only show exemplary embodiments of this disclosure and should therefore not be considered to limit its scope. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. [Figure 2] This is a schematic diagram of an exemplary intermediate process (MEOL) portion of a semiconductor structure according to one or more embodiments of the present disclosure. [Figure 3] This is a process flow diagram of a method for filling vias in a landing pad structure in a semiconductor structure according to a first embodiment of the present disclosure. [Figure 4A] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 3. [Figure 4B] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 3. [Figure 4C] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 3. [Figure 4D] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 3. [Figure 5] This is a process flow diagram of a method for filling vias in a landing pad structure in a semiconductor structure according to a second embodiment of the present disclosure. [Figure 6A] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 5. [Figure 6B] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 5. [Figure 6C] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 5. [Figure 6D]This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 5. [Figure 6E] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 5. [Figure 7] This is a process flow diagram of a method for filling vias in a landing pad structure in a semiconductor structure according to a third embodiment of the present disclosure. [Figure 8A] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 7. [Figure 8B] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 7. [Figure 8C] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 7. [Figure 8D] This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 7. [Modes for carrying out the invention]

[0010] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements and features of one embodiment are intended to be usefully incorporated into other embodiments without further detail.

[0011] Embodiments of this specification relate to methods used in the manufacture of electronic devices, and more particularly to a process for filling deep contact gaps in NAND devices with high-quality tungsten (W).

[0012] The method disclosed in this specification includes the step of filling a high aspect ratio via having a necking point with tungsten (W), starting from the selective deposition of tungsten (W) for filling the via from the bottom surface of the via below the necking point (e.g., tungsten (W), titanium nitride (TiN)), and ending with the metal filling of tungsten (W) for filling the remaining portion of the via. In the selective deposition, the via is filled with tungsten (W) in a bottom-up manner from the bottom surface of the via without forming voids or seams in the metal filling material.

[0013] Example of a processing system FIG. 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates within the processing system 100 can be processed in various chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., an atmospheric ambient environment such as may exist in a fab) and can be transferred between the various chambers. For example, substrates can be processed in various chambers maintained at a low pressure (e.g., about 300 Torr or less) or a vacuum environment without breaking the low pressure or vacuum environment during the various processes performed on the substrates within the processing system 100 and can be transferred between those chambers. Thus, the processing system 100 can provide an integrated solution for some processing of substrates.

[0014] In the example shown in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is configured to receive one or more forward-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 located at one end of the factory interface robot 134, configured to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0015] The load lock chambers 104 and 106 have ports 140 and 142, respectively, connected to the factory interface 102, and ports 144 and 146, respectively, connected to the transfer chamber 108. The transfer chamber 108 further has ports 148 and 150, respectively, connected to the holding chambers 116 and 118, and ports 152 and 154, respectively, connected to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has ports 156 and 158, respectively, connected to the holding chambers 116 and 118, and ports 160, 162, 164, and 166, respectively, connected to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 can be slit valve openings having slit valves for, for example, transferring substrates by transfer robots 112 and 114, and for sealing between each chamber to prevent gas from passing between them. Generally, each port is open to allow substrates to be transferred through it. Otherwise, the port is closed.

[0016] Load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via the port 140 or 142. Next, the gas and pressure control system evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the interiors of the transfer chambers 108, 110 and the holding chambers 116, 118 in a low pressure or vacuum environment (which may include an inert gas). Therefore, the evacuation of the load lock chamber 104 or 106 facilitates, for example, the transfer of the substrate between the ambient environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0017] With the substrate in the load lock chamber 104 or 106 under vacuum, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 via port 144 or 146. The transfer robot 112 can then transfer the substrate to and / or between any of the processing chambers 120, 122 via port 152, 154 for processing, and holding chambers 116, 118 via port 148, 150 for holding awaiting further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 via port 156 or 158 and transfer the substrate to and / or between any of the processing chambers 124, 126, 128, 130 via port 160, 162, 164, 166 for processing, and holding chambers 116, 118 via port 156, 158 for holding awaiting further transfer. The transfer and holding of substrates within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0018] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing the substrate. In some examples, processing chamber 120 can perform an etching process, processing chamber 122 can perform a cleaning process, and processing chambers 126, 128, and 130 can perform their respective epitaxial growth processes.

[0019] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. In operation, the system controller 168 enables data acquisition and feedback from each chamber and adjusts the performance of the processing system 100.

[0020] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. The CPU 170 may be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172 or non-transient computer-readable medium is accessible by the CPU 170 and may be one or more of the following: random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage. The support circuitry 174 is coupled to the CPU 170 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein may generally be implemented under the control of the CPU 170, for example, by the CPU 170 executing computer instruction code stored in memory 172 (or memory of a particular processing chamber) as a software routine. Once the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to execute the process according to various methods.

[0021] Other processing systems may have different configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device in the processing system.

[0022] Examples of semiconductor structures Figure 2 is a schematic diagram of an exemplary semiconductor structure 200, which may be a three-dimensional NAND (3D NAND) device having metal contacts.

[0023] The semiconductor structure 200 may include a first level L1 containing a metal layer 202 within a first dielectric layer 204 formed on a substrate 206, and a second level L2 containing interconnects 208 within a landing pad 210, with vias 212 formed within a stack of a second dielectric layer 214 and a third dielectric layer 216 formed on the second level L2. Within the landing pad 210, a liner layer 218 may be formed around the interconnects 208. The vias 212 may have a width of about 160 nm to about 240 nm and a depth of about 5 μm to about 20 μm. The landing pad 210 may have a necking point 220 near the interface between the second dielectric layer 214 and the third dielectric layer 216 by etching through the second dielectric layer 214 and the third dielectric layer 216 to form the vias 212. The necking point 220 may protrude into the via 212 by approximately 100 nm to 120 nm. The third dielectric layer 216 may have a thickness of approximately 800 nm to 1.2 μm. When the interconnect 208 formed within the via 212 is formed by a conventional deposition process such as chemical vapor deposition (CVD), it may have a void 208V below the necking point 220.

[0024] As used herein, the term “substrate” refers to a layer of material that serves as the basis for subsequent processing operations, and includes the surface to be cleaned. The substrate 206 may be a silicon-based material, or any suitable insulating or conductive material as needed. The substrate 206 may be crystalline silicon (e.g., Si <100> or Si <111> This may include materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0025] The metal layer 202 and interconnect 208 may be formed of tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo).

[0026] The first dielectric layer 204, the second dielectric layer 214, and the third dielectric layer 216 may each be formed of a dielectric material such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0027] The liner layer 218 may be formed of titanium nitride (TiN) or tungsten (W).

[0028] metal filling Figure 3 shows a process flow diagram of a method 300 for filling vias in a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown in Figure 2, according to a first embodiment of the present disclosure. Figures 4A, 4B, 4C, and 4D are cross-sectional views of the semiconductor structure 200 corresponding to various states of method 300. Figures 4A, 4B, 4C, and 4D show only partial schematic diagrams of the semiconductor structure 200, and it should be understood that the semiconductor structure 200 may include any number of transistor sections and additional materials having the configuration shown in the figures. Also note that although the method shown in Figure 3 is described sequentially, other process sequences including one or more operations that are omitted and / or added and / or rearranged in a different preferred order are also within the scope of embodiments of the present disclosure provided herein.

[0029] As shown in Figure 4A, the semiconductor structure 200 includes a first level L1 containing a metal layer 202 within a first dielectric layer 204 formed on a substrate 206, and a second level L2 containing a stack of a second dielectric layer 214 and a third dielectric layer 216, with vias 212 formed within the stack on the first level L1. The bottom of the vias 212 exposes the surface 202S of the metal layer 202. An interconnection 208 (not shown in Figure 4A) is formed within the vias 212.

[0030] By etching through the second dielectric layer 214 and the third dielectric layer 216 to form the via 212, a necking point 220 is formed within the via 212 near the interface between the second dielectric layer 214 and the third dielectric layer 216. The via 212 may have a width of approximately 160 nm to approximately 240 nm and a depth of approximately 5 μm to approximately 20 μm. The necking point 220 may protrude into the via 212 by approximately 100 nm to approximately 120 nm at a height of approximately 250 nm to approximately 300 nm from the bottom of the via (corresponding to the thickness of the third dielectric layer 216).

[0031] The metal layer 202 and interconnect 208 may be formed of tungsten (W) or molybdenum (Mo). The first dielectric layer 204, the second dielectric layer 214, and the third dielectric layer 216 may each be formed of a dielectric material such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0032] Method 300 begins with block 310 to perform a pre-cleaning process to remove residue from the exposed surface 202S of the metal layer 202 and restore the inner surface of the via 212 (e.g., the exposed surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212).

[0033] During the manufacturing of the second level L2, the semiconductor structure 200 may be exposed to air or other oxidizing environments, and therefore the surface 202S of the metal layer 202 may be oxidized. Furthermore, the etching process for forming vias 212 within the stack of the second dielectric layer 214 and the third dielectric layer 216 may leave residues such as chlorine residue or fluorine residue on the surface 202S of the metal layer 202, or damage the surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the vias 212. Therefore, before filling the vias 212 from the bottom (surface 202S of the metal layer 202) to form the interconnect 208, the surface 202S of the metal layer 202, the surface of the second dielectric layer 214, and the surface of the third dielectric layer 216 within the vias 212 are pre-cleaned.

[0034] The pre-cleaning process removes metal oxides (e.g., tungsten oxide (WO)) from the surface 202S of the metal layer 202. x The process may include a chemical immersion process for selectively removing metal oxides (e.g., tungsten fluoride (WF6), hydrogen (H2)) from the surface 202S of the metal layer 202, in which the surface 202S of the metal layer 202 is immersed in a precursor (e.g., tungsten fluoride (WF6), hydrogen (H2)) supplied in pulsed or continuous flow within a CVD / ALD processing chamber such as processing chambers 124, 126, 128, or 130 shown in Figure 1. xThe pre-cleaning process for selectively removing )) may be a plasma process using a plasma formed from a process gas containing hydrogen (H2) gas. The plasma process may be an inductively coupled plasma (ICP) process performed in a processing chamber such as processing chambers 124, 126, 128, or 130 shown in Figure 1, or a capacitively coupled plasma (CCP) process performed in a processing chamber such as processing chambers 124, 126, 128, or 130 shown in Figure 1.

[0035] A pre-cleaning process to restore the exposed surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212 may include a plasma treatment process using a plasma formed from a process gas containing oxygen (O2) gas. The plasma treatment process may be a capacitively coupled plasma (CCP) process performed in a processing chamber such as processing chambers 124, 126, 128, or 130 shown in Figure 1. The plasma treatment process may also be an inductively coupled plasma (ICP) process performed in a processing chamber such as processing chambers 124, 126, 128, or 130 shown in Figure 1.

[0036] In block 320, as shown in Figure 4B, a selective deposition process is performed to partially fill vias 212 from the exposed surface 202S of the metal layer 202 below the necking point 220 with metal filler material 402. The metal filler material 402 may be tungsten (W) or molybdenum (Mo).

[0037] In the selective deposition process, the metal filler material 402 selectively grows on the exposed surface 202S of the metal layer 202 and does not grow on the side walls of the vias 212 (e.g., silicon nitride (Si3N4) or silicon oxide (SiO2)). As a result, the vias 212 are filled with the metal filler material 402 in a bottom-up manner from the bottom surface 202S of the vias 212 without the formation of voids or seams within the metal filler material 402.

[0038] The selective deposition process may include a chemical vapor deposition (CVD) process using tungsten (W)-containing precursors such as tungsten hexafluoride (WF6) and hydrogen (H2) in a processing chamber such as the processing chamber 126 shown in Figure 1. The flow rate ratio of the tungsten (W)-containing precursor to the hydrogen (H2)-containing carrier gas may be about 0.001 to about 0.007 to ensure the selectivity of tungsten (W) deposition on the metal layer 202 (e.g., tungsten (W)).

[0039] The selective deposition process is carried out at temperatures of approximately 300°C to 500°C.

[0040] In block 330, as shown in Figure 4C, a liner deposition process is performed to form a liner layer 218 on the exposed inner surface of the via 212. The liner layer 218 may be formed of titanium nitride (TiN) or tantalum nitride (TaN) and can function as a nucleation layer on which a metal filler material 402, such as tungsten (W), grows in the subsequent metal filler process of block 340.

[0041] The liner deposition process may include an atomic layer deposition (ALD) process performed in a processing chamber such as processing chambers 124, 126, 128, or 130 shown in Figure 1, in which titanium (Ti)-containing metal precursors and nitrogen-containing precursors are alternately supplied to the semiconductor structure 200. In some embodiments, the metal-containing precursors are purged before the nitrogen-containing precursors are supplied. Examples of titanium (Ti)-containing metal precursors include inorganic compounds of titanium (Ti) such as titanium chloride (TiCl4), and organometallic compounds of titanium (Ti) such as tetrakis(dimethylamino)titanium (TDMAT, [(CH3)2N]4Ti). Examples of nitrogen-containing precursors are ammonia (NH3), diazene (N2H2), and hydrazine (N2H4).

[0042] In block 340, as shown in Figure 4D, a metal filling process is performed to fill the vias 212 with a metal filling material 402 such as tungsten (W) to form interconnects 208.

[0043] In the metal-filling process, the metal-filling material 402 grows from a liner layer 218 deposited on the inner surface of the via 212. The metal-filling process may include a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor such as tungsten hexafluoride (WF6) and a hydrogen (H2)-containing carrier gas in a processing chamber such as the processing chamber 126 shown in Figure 1. Furthermore, pulses of nitrogen-containing gases such as nitrogen (N2) radicals, ammonia (NH3), or nitrogen trifluoride (NF3) can be added between tungsten (W) depositions to suppress tungsten (W) deposition on the field (e.g., on the second dielectric layer 214) and allow the tungsten (W) to grow conformally from the liner layer 218 without forming seams.

[0044] The metal filling process is carried out at a temperature of approximately 350°C to 500°C, with a flow rate of approximately 200 sccm to 800 sccm of tungsten (W)-containing precursor and a flow rate of approximately 2000 sccm to 8000 sccm of hydrogen (H2)-containing carrier gas.

[0045] Figure 5 shows a process flow diagram of a method 500 for filling vias in a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown in Figure 2, according to a second embodiment of the present disclosure. Components substantially identical to those in the first embodiment are given the same reference numerals, and descriptions of repeated components may be omitted. Figures 6A, 6B, 6C, 6D, and 6E are cross-sectional views of the semiconductor structure 200 corresponding to various states of method 500. Figures 6A, 6B, 6C, 6D, and 6E show only partial schematic diagrams of the semiconductor structure 200, and it should be understood that the semiconductor structure 200 may include any number of transistor sections and additional materials having the configurations shown in the figures. Also note that while the method shown in Figure 5 is described sequentially, other process sequences including one or more operations that are omitted and / or added, and / or rearranged in a different preferred order are also within the scope of the embodiments of the present disclosure provided herein.

[0046] Method 500 begins with block 510, where a liner deposition process is performed to form a liner layer 602 on the exposed inner surface of the vias 212, as shown in Figure 6A. This liner deposition process is performed before a selective deposition process to fill the vias 212 below the necking point 220, so that the liner layer 602 is formed on the inner surfaces of the vias 212 above and below the necking point 220. The liner layer 602 may be formed of titanium nitride (TiN) or tantalum nitride (TaN).

[0047] The liner deposition process in block 510 is similar to or identical to the liner deposition process in block 330.

[0048] In block 520, as shown in Figure 6B, a liner pullback process is performed to remove the liner layer 602 above the necking point 220.

[0049] The liner pullback process may include a wet etching process or a dry etching process in an etching chamber, such as the processing chamber 122 shown in Figure 1.

[0050] In block 530, an optional pre-cleaning process is performed to restore the inner surface of the via 212 damaged in the liner pullback process of block 520 (for example, the exposed surface of the second dielectric layer 214 within the via 212). The pre-cleaning process in block 530 is similar to or identical to the pre-cleaning process in block 310.

[0051] In block 540, as shown in Figure 6C, a selective deposition process is performed to partially fill the via 212 with a metal filler material 402 such as tungsten (W) from the exposed surface of the liner layer 602 at the bottom of the via 212 below the necking point 220.

[0052] In the selective deposition process, the metal filler material 402 selectively grows on the exposed surface of the liner layer 602 and not on the sidewalls of the vias 212 (e.g., silicon nitride (Si3N4) or silicon oxide (SiO2)). As a result, the vias 212 below the necking point 220 are filled with the metal filler material 402 without forming voids or seams within the metal filler material 402.

[0053] The selective deposition process in block 540 is similar to or identical to the selective deposition process in block 320.

[0054] In block 550, as shown in Figure 6D, a liner deposition process is performed to form a liner layer 218 on the exposed inner surface of the via 212. The liner deposition process in block 550 is similar to or identical to the liner deposition process in block 330.

[0055] In block 560, as shown in Figure 6E, a metal filling process is performed to fill vias 212 with a metal filling material 402 such as tungsten (W) to form interconnects 208. The metal filling process is similar to or identical to the metal filling process in block 340.

[0056] Figure 7 shows a process flow diagram of a method 700 for filling vias in a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown in Figure 2, according to a third embodiment of the present disclosure. Components substantially identical to those in the first and second embodiments are given the same reference numerals, and descriptions of repeated components may be omitted. Figures 8A, 8B, 8C, and 8D are cross-sectional views of the semiconductor structure 200 corresponding to various states of the method 700. Figures 8A, 8B, 8C, and 8D show only partial schematic diagrams of the semiconductor structure 200, and it should be understood that the semiconductor structure 200 may include any number of transistor sections and additional materials having the configuration shown in the figures. Also note that while the method shown in Figure 7 is described sequentially, other process sequences including one or more operations that are omitted and / or added, and / or rearranged in a different preferred order are also within the scope of the embodiments of the present disclosure provided herein.

[0057] Method 700 begins with block 710, where a liner deposition process is performed to form a liner layer 602 on the exposed inner surface of via 212, as shown in Figure 6A. The liner deposition process in block 710 is the same as the liner deposition process in 510.

[0058] In block 720, as shown in Figure 6B, a liner pullback process is performed to remove the liner layer 602 above the necking point 220. The liner pullback process in block 720 is the same as the liner pullback process in block 520.

[0059] In block 730, as shown in Figure 8A, a fluorine-free tungsten (FFW) growth process is performed to selectively form a metal capping layer 802 on the exposed surface of the liner layer 602. The metal capping layer 802 may be formed of tungsten (W) with a thickness of approximately 20 Å to 40 Å, for example, approximately 20 Å, and can function as a nucleation layer on which metal-filling material 402 such as tungsten (W) grows in the subsequent selective deposition process of block 750.

[0060] The FFW growth process can include chemical vapor deposition (CVD) or atomic layer deposition (ALD), in which the surface of the liner layer 602 is immersed in a precursor containing tungsten chloride (WCl6) gas supplied in a pulsed flow into a processing chamber such as the processing chamber 122 shown in Figure 1.

[0061] In block 740, an optional pre-cleaning process is performed to restore the inner surface of the via 212 damaged in the liner pullback process of block 720 (for example, the exposed surface of the second dielectric layer 214 within the via 212). The pre-cleaning process in block 740 is similar to or identical to the pre-cleaning process in block 310.

[0062] In block 750, as shown in Figure 8B, a selective deposition process is performed to partially fill the via 212 with a metal filler material 402 such as tungsten (W) from the exposed surface of the metal capping layer 802 at the bottom of the via 212 below the necking point 220.

[0063] In the selective deposition process, the metal filler material 402 selectively grows on the exposed surface of the metal capping layer 802 and not on the sidewalls of the vias 212 (e.g., silicon nitride (Si3N4) or silicon oxide (SiO2)). As a result, the vias 212 below the necking point 220 are filled with the metal filler material 402 without forming voids or seams within the metal filler material 402.

[0064] The selective deposition process in block 750 is similar to or identical to the selective deposition process in block 320.

[0065] In block 760, as shown in Figure 8C, a liner deposition process is performed to form a liner layer 218 on the exposed inner surface of the via 212. The liner deposition process in block 760 is similar to or identical to the liner deposition process in block 330.

[0066] In block 770, as shown in Figure 8D, a metal filling process is performed to fill vias 212 with a metal filling material 402 such as tungsten (W) to form interconnects 208. The metal filling process is similar to or identical to the metal filling process in block 340.

[0067] Embodiments described herein provide a system and method for filling high aspect ratio vias having a necking point with tungsten(W) without forming voids or seams. The method includes selective deposition of tungsten(W) to fill the via from the bottom surface of the via below the necking point (e.g., tungsten(W), titanium nitride (TiN)) and metallic filling of tungsten(W) to fill the rest of the via. In selective deposition, the via is filled with tungsten(W) in a bottom-up manner from the bottom surface of the via without forming voids or seams in the metallic filling material.

[0068] While the above applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A method for filling vias having a necking point, A step of performing a pre-cleaning process to remove residue from the exposed surface of the metal layer at the bottom of the via and to restore the inner surface of the via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via, A step of performing a selective deposition process to partially fill the via with metal filler material from the exposed surface of the metal layer below the necking point, The steps include: performing a liner deposition process to form a liner layer on the exposed inner surface of the via; A step of performing a metal filling process to fill the via with the metal filling material and Methods that include...

2. The via has a width of 160 nm to 240 nm and a depth of 5 μm to 20 μm. The necking point protrudes into the via by 100 nm to 120 nm in height from the bottom of the via, which is 800 nm to 1.2 μm in thickness. The method according to claim 1.

3. The metal filling material comprises tungsten (W) or molybdenum (Mo), The liner layer contains titanium nitride (TiN), The dielectric layer is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), including hafnium-containing materials, zirconium-containing materials, aluminum-containing materials, lanthanum-containing materials, or combinations thereof, The method according to claim 1.

4. The aforementioned pre-cleaning process involves the exposed surface of the metal layer being treated with tungsten fluoride (WF) provided into the processing chamber. 6 ) or hydrogen (H 2 The method according to claim 1, comprising a chemical immersion process in which the immersion is immersed in a precursor containing ).

5. The aforementioned pre-cleaning process involves hydrogen (H 2 The method according to claim 1, comprising an inductively coupled plasma (ICP) process using a plasma formed from a process gas containing a gas.

6. The method according to claim 1, wherein the pre-cleaning process includes a plasma treatment process using a plasma formed from a process gas containing an oxygen (O 2 )-containing gas.

7. The aforementioned selective deposition process involves a tungsten (W)-containing precursor and hydrogen (H) 2 The process includes a chemical vapor deposition (CVD) process using a carrier gas containing tungsten (W) and hydrogen (H), wherein the tungsten (W)-containing precursor and the hydrogen (H)-containing carrier gas are used. 2 The method according to claim 1, wherein the flow rate ratio of the contained carrier gas is 0.001 to 0.

007.

8. The aforementioned metal filling process involves a tungsten (W) containing precursor, hydrogen (H 2 The method according to claim 1, comprising a chemical vapor deposition (CVD) process using a carrier gas containing ) and a nitrogen-containing gas.

9. A method for filling vias having a necking point, A step of performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding into the via; The steps include performing a liner pullback process to remove the liner layer above the necking point, A step of performing a selective deposition process to partially fill the via with metal filler material from the exposed surface of the liner layer below the necking point, A step of performing a metal filling process to fill the via with the metal filling material and Methods that include...

10. The metal filling material comprises tungsten (W) or molybdenum (Mo), The liner layer contains titanium nitride (TiN), The dielectric layer is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), including hafnium-containing materials, zirconium-containing materials, aluminum-containing materials, lanthanum-containing materials, or combinations thereof, The method according to claim 9.

11. A step of performing a pre-washing process to restore the inner surface of the via before the selective deposition process. The method according to claim 9, further comprising:

12. The aforementioned pre-cleaning process involves oxygen (O 2 The method according to claim 11, comprising a plasma processing process using a plasma formed from a process gas containing a gas.

13. The aforementioned selective deposition process involves a tungsten (W)-containing precursor and hydrogen (H) 2 The process includes a chemical vapor deposition (CVD) process using a carrier gas containing tungsten (W) and hydrogen (H), wherein the tungsten (W)-containing precursor and the hydrogen (H)-containing carrier gas are used. 2 The method according to claim 9, wherein the flow rate ratio of the contained carrier gas is 0.001 to about 0.

007.

14. The aforementioned metal filling process involves a tungsten (W) containing precursor, hydrogen (H 2 The method according to claim 9, comprising a chemical vapor deposition (CVD) process using a carrier gas containing ) and a nitrogen-containing gas.

15. A method for filling vias having a necking point, A step of performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding into the via; The steps include performing a liner pullback process to remove the liner layer above the necking point, The steps include: performing a fluorine-free tungsten (FFW) growth process to selectively form a metal capping layer on the exposed surface of the liner layer; A step of performing a selective deposition process to partially fill the via with metal filler material from the exposed surface of the metal capping layer below the necking point, A step of performing a metal filling process to fill the via with the metal filling material and Methods that include...

16. The metal filling material comprises tungsten (W) or molybdenum (Mo), The liner layer contains titanium nitride (TiN), The dielectric layer is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), including hafnium-containing materials, zirconium-containing materials, aluminum-containing materials, lanthanum-containing materials, or combinations thereof, The method according to claim 15.

17. A step of performing a pre-washing process to restore the inner surface of the via before the selective deposition process. The method according to claim 15, further comprising:

18. The aforementioned pre-cleaning process involves oxygen (O 2 The method according to claim 17, comprising a plasma processing process using a plasma formed from a process gas containing a gas.

19. The aforementioned selective deposition process involves a tungsten (W)-containing precursor and hydrogen (H) 2 The process includes a chemical vapor deposition (CVD) process using a carrier gas containing tungsten (W) and hydrogen (H), wherein the tungsten (W)-containing precursor and the hydrogen (H)-containing carrier gas are used. 2 The method according to claim 15, wherein the flow rate ratio of the contained carrier gas is 0.001 to 0.

007.

20. The aforementioned metal filling process involves a tungsten (W) containing precursor, hydrogen (H 2 The method according to claim 15, comprising a chemical vapor deposition (CVD) process using a carrier gas containing ) and a nitrogen-containing gas.

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