Method for etching high aspect ratio structures

Abstract

This specification discloses a method and system for etching high aspect ratio structures in a semiconductor processing chamber. In one embodiment, a method for patterning a substrate includes etching the substrate to form recesses, depositing a passivation layer on the sidewalls of the recesses, processing the passivation layer, and etching the recesses to a second depth. The substrate etching forms recesses to a first depth, on which a mask layer is placed. The processing of the passivation layer is for removing occluding material formed from etching byproducts on the mask layer. The recesses are etched to a second depth while maintaining minimal variation in the recess sidewall width.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to a semiconductor etching method and its system. More specifically, embodiments of the present disclosure relate to an etching method for fabricating high aspect ratio device structures.

Background Art

[0002] Description of Related Technology [[ID=1,4]]

[0002] In semiconductor manufacturing, integrated circuits (ICs) are formed on a semiconductor substrate through various manufacturing steps including etching. Conventional etching processes used for film stack etching utilize a single etching process to achieve a deep structure. By repeating these processes, the desired depth can be achieved at the expense of the desired vertical shape. These undesirable vertical profiles can lead to a decrease in device performance or device failure. Therefore, an improved method for etching high aspect ratio structures with a desired vertical profile is needed.

Summary of the Invention

[0003]

[0003] In this specification, a method and a system for etching a high aspect ratio structure in a semiconductor processing chamber are disclosed. In one example, the method of patterning a substrate includes etching the substrate to form a recess, depositing a passivation layer on the sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etching forms a recess to a first depth, and a mask layer is disposed on the substrate. The treatment of the passivation layer is for removing the blocking material formed from the etching by-products on the mask layer. The method includes etching the recess to a second depth while maintaining a minimum variation in the width of the recess sidewalls.

[0004]

[0004] In another embodiment, a method for patterning a substrate includes etching the substrate to remove a thin layer of oxide and expose a silicon-containing film stack; etching the substrate to form recesses in the film stack to a first depth; oxidizing the sidewalls of the recesses and the inner walls of the mask layer; exposing the sidewalls of the mask layer by controlled etching; and repeating the process to etch the recesses to a final depth while maintaining a vertical profile. The substrate comprises a mask layer placed on top of the film stack, the mask layer having an inner wall, the film stack is placed on the substrate, and etching the substrate includes generating a plasma from a mixed gas of Cl2, HBr, O2, and Ar, and exposing the substrate to the plasma for about 10 seconds to about 200 seconds. The method includes oxidizing the sidewalls of the recesses and the inner walls of the mask layer by exposing the substrate to the generated oxygen plasma for about 10 seconds to about 20 seconds, the inner walls of the mask layer having silicon-containing etching byproducts. The method includes exposing the sidewalls of a mask layer by controlled etching, the controlled etching including generating a plasma from a mixed gas of NF3, Ar, and O2, and exposing the substrate to the plasma for about 10 to 200 seconds. The method includes etching a recess to a final depth while maintaining a vertical profile of a first depth within 5 nanometers from the center of the recess, and etching the recess to a second depth.

[0005]

[0005] In yet another embodiment, a system for processing a semiconductor substrate comprises a chamber and a system controller. The chamber comprises a lid, a body, side walls, and a substrate support. The processing space is defined by the lid, body, and side walls of the chamber. The system controller is connected to the chamber and has a non-temporary computer-readable medium in which instructions are stored, which, when executed by the processor, cause the process to perform the steps of (a) etching the substrate to remove a thin layer of oxide and expose a silicon-containing film stack, (b) etching the substrate to form a recess to a first depth, (c) etching the substrate on which the mask layer is placed, (d) processing the passivation layer to remove occluding material formed from etching byproducts on the mask layer, and (e) etching the recess to a second depth while maintaining a minimum variation in the recess side wall width.

[0006]

[0006] In another embodiment, instructions are stored in a non-temporary computer-readable medium, and when executed by a processor, the instructions cause a process to perform the steps of the apparatus and / or method described above.

[0007]

[0007] To enable a more detailed understanding of the features of the present disclosure, which are briefly summarized above, a more detailed description of the present disclosure can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered to limit the scope of the present disclosure, and other equally valid embodiments may be permitted. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] This is a schematic side cross-sectional view of a plasma processing system according to one or more embodiments configured to carry out the methods described herein. [Figure 2]

[0009] This is a flowchart of a method for etching a high aspect ratio structure according to a particular aspect of the present disclosure. [Figure 3A-3H]

[0010] A schematic diagram of a device structure undergoing an etching process according to the method shown in Figure 2, relating to a specific aspect of this disclosure, is shown. [Figure 4]

[0011] The upper mask layer according to a specific aspect of this disclosure is shown. [Figure 5]

[0012] A cross-sectional view of a device formed according to a particular aspect of this disclosure is shown. [Figure 6]

[0013] A chart is shown representing the vertical profile of a device formed according to a particular aspect of this disclosure. [Modes for carrying out the invention]

[0009]

[0014] To facilitate understanding, the same reference numerals were used where possible to indicate identical elements common to multiple figures. It is assumed that elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0010]

[0015] Many of the details, dimensions, angles, and other features shown in the figures are merely illustrative of a particular implementation. Therefore, other implementations may have different details, components, dimensions, angles, and features without departing from the essence or scope of this disclosure. Furthermore, further implementations of this disclosure may be carried out without some of the detailed examples described below.

[0011]

[0016] This disclosure provides a method for etching high aspect ratio structures for use in three-dimensional (3D) dynamic random access memory (DRAM) devices. Reliably manufacturing high aspect ratio features has proven to be one of the key technical challenges for next-generation semiconductor devices. One method for forming high aspect ratio features uses a plasma-assisted etching process to form high aspect ratio openings in material layers, such as dielectric layers of a substrate or multilayer structures. Unfortunately, conventional etching processes used to fabricate high aspect ratio openings in multilayer structures utilize a single etching process that cannot achieve aspect ratios of 100:1 or higher while maintaining the desired critical dimensions. To address this problem, an iterative method of etching, adding passivation layers, and applying passivation layer treatment is employed to achieve a better vertical profile (e.g., while maintaining critical dimensions) while achieving a desired high aspect ratio structure of 100:1 or higher. This advantageously results in high aspect ratio structures within a 10-nanometer tolerance, enabling improved yield, reduced waste, increased processing efficiency, lower ownership costs, and the manufacture of uniform integrated circuits.

[0012]

[0017] Figure 1a is a schematic diagram of a plasma processing system 100 adapted to process a substrate 113 placed on a substrate support assembly 140 by generating plasma 111 in a processing space 134 of a plasma processing chamber 150. The plasma processing system 100 is configured to form an inductively coupled plasma (ICP), and the processing chamber 150 includes a coil 173 positioned above a portion of the processing space 134 such that at least a portion of the coil faces a bias electrode 114 also positioned in the substrate support assembly 140, which is located within the processing space 134. The bias electrode 114 is often referred to herein as the substrate support electrode. The ICP plasma processing source also includes a radio frequency (RF) generator 171 that supplies a tuned RF signal configured to ignite and maintain the plasma 111 formed in the processing space 134, electrically coupled to the upper coil 173 via an RF matcher 172. The bias electrode 114 is connected to a pulse voltage (PV) waveform generator 110, which is electrically connected to the bias electrode 114 via an RF filter 115 configured to prevent the RF signal from entering the PV waveform generator 110 during processing. In some embodiments, the RF generator 171 is configured to supply an RF waveform signal having a frequency of 1 megahertz (MHz) or more, or about 2 megahertz or more, for example, about 13.56 megahertz or more, via an RF matcher 172 connected to a coil 173.

[0013]

[0018] The processing chamber 150 typically includes a chamber body 130, which includes one or more side walls 131 and a chamber base 132, and together with a chamber lid 133, defines a processing space 134. The one or more side walls 131 and the chamber base 132 are generally sized and shaped to form structural supports for the elements of the processing chamber 150 and include materials configured to withstand pressure and energy applied to them while plasma 111 is generated in a vacuum environment maintained within the processing space 134 of the processing chamber 150 during processing. In one embodiment, the one or more side walls 131 and the chamber base 132 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy. A gas inlet 135, positioned to penetrate the chamber lid 133, is used to supply one or more processing gases to the processing space 134 from a processing gas source 119 that is in fluid communication with the gas inlet. The processing gases supplied by the processing gas source 119 include a reactive etchant gas and an inert gas. The pressure inside the processing chamber 150 is controlled using the amount of gas flow supplied from the vacuum pump 155 and the processing gas source 119. The substrate 113 enters and exits the processing space 134 through one or more openings (not shown) in the side walls 131. One or more openings in the side walls 122 are sealed with slit valves (not shown) during plasma processing of the substrate 113.

[0014]

[0019] The substrate support assembly 140 may include a substrate support 105 (e.g., an ESC substrate support) and one or more bias electrodes connected to the PV waveform generator 110. In some embodiments, the substrate support assembly 140 may further include a support structure 106 which includes a support base for supporting the substrate support 105, an insulating plate, and a grounding plate connected to a chamber base 132. The support base is electrically insulated from the chamber base 132 by the insulating plate, and the grounding plate is interposed between the insulating plate and the chamber base 132. The substrate support 105 may be thermally connected to and placed on a support base configured to regulate the temperature of the substrate support 105 during processing.

[0015]

[0020] Typically, the substrate support 105 is formed from a dielectric material (e.g., a bulk sintered ceramic material such as a corrosion-resistant metal oxide or metal nitride material). In embodiments of this specification, the substrate support assembly 140 further includes a bias electrode 114 embedded within its dielectric material. In one configuration, the bias electrode 114 is a chucking electrode used to fix (i.e., chuck) the substrate 113 to the substrate support surface of the substrate support assembly 140 and to bias the substrate 113 to the processing plasma 111 using one or more pulsed voltage biasing schemes. Typically, the bias electrode 114 is formed from one or more conductive components (e.g., one or more metal meshes, foils, plates, or a combination thereof). In some embodiments, the bias electrode 114 is also electrically coupled to a clamp network configured to supply a chucking voltage, such as a static DC voltage between approximately -5000V and approximately +5000V.

[0016]

[0021] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 127, memory 128, and support circuitry 129. The system controller 126 is used to control process sequences and methods used to process the substrate 113, including the substrate processing method described herein. The CPU 127 is a general-purpose computer processor configured for use in an industrial environment for controlling the processing chamber and its associated subprocessors. The memory 128 described herein, generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuitry 129 is conventionally connected to the CPU 127 and includes a cache, clock circuitry, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (software programs) and data can be coded and stored in memory 128 to instruct the processor in the CPU 127. Software programs (or computer instructions) readable by the CPU 127 in the system controller 126 determine which tasks can be executed by the components in the processing chamber 100. Typically, a software program readable by the CPU 127 in the system controller 126 includes code, which, when executed by the processor (CPU 127), performs tasks related to the plasma processing method described herein. The program may include instructions used to control various hardware and electrical components within the processing chamber 150 and processing system 100 in order to perform various processing tasks and various processing sequences used to carry out the method described herein.

[0017]

[0022] As described above, the PV waveform generator 110 is adapted to provide a voltage waveform to one or more electrodes, such as a bias electrode 114, located within the processing chamber 150. In some embodiments, each PV waveform generator 110 is configured to supply DC power of 1 to 25 kilowatts (kW) to the electrodes at a voltage between 100 and 10,000 volts, for example, between 1,000 and 5,000 volts.

[0018]

[0023] The system controller 126 and support circuitry are configured to control and / or adjust the voltage waveform generated by the PV waveform generator 110. The PV waveform generator 110, system controller 126, and support circuitry can adjust several electrical parameters used to change one or more of the voltage waveform characteristics, such as frequency, waveform shape, and applied voltage on-time, during the pulse duration of the provided asymmetric voltage waveform.

[0019]

[0024] The disclosures provided herein primarily describe the use of a processing system 100 for performing plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing techniques, but this configuration is not intended to limit the scope of the disclosures provided herein. It should be noted that the embodiments described herein may be used in conjunction with processing systems configured for use in plasma-enhanced deposition processes, such as plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD), plasma processing, or other plasma-based ion implantation processes, such as plasma doping (PLAD).

[0020]

[0025] FIG. 2 shows an etching method 200 including a plurality of steps for etching a high aspect ratio device structure. Step 210 is a breakthrough process. Step 220 is the main etching process. Step 230 is a passivation process. Step 240 is a passivation layer treatment process. Step 250 is a repetition of the main etching process of step 220. FIGS. 3A to 3H are representative diagrams of a device structure through various processes of method 200.

[0021]

[0026] In integrated circuit manufacturing, the use of a substrate 300 shown in FIG. 3A is employed as a basis for creating a film stack that can be etched later to create devices such as 3D DRAM devices. These substrates 300 can have various layers deposited thereon by a plurality of generally known processes utilized in the semiconductor industry. These processes can deposit a plurality of nanoscale layers on top of each other, as shown in FIG. 3A, to generate a film stack 310. The film stack 310 can be utilized to create electrical connections, electrical gates, etc. through an etching process. Further, the film stack 310 can include a plurality of materials in alternating layers. Therefore, the selection of materials used in the film stack 310 is carefully considered to achieve the desired results.

[0022]

[0027] Once a desired film stack 310 is formed on the substrate 300, the film stack 310 can be etched, for example, in a typical etching chamber to create a desired device within, on, or on the upper surface of the film stack 310. However, simply etching the film stack is likely to result in the slow removal of the entire upper surface of the film stack. Therefore, a mask layer 320 was developed to protect a portion of the film stack while leaving the exposed portion susceptible to etching. Furthermore, the mask layer 320 can be patterned to protect or expose specific portions, as indicated by patterned openings 325. For example, a mask layer 320 containing a circular pattern opening 325 cut out on the film stack 310 may leave the circular portion exposed to the etching process, thereby forming a cylindrical recess in the film stack 310. In some embodiments, the mask layer 320 is etching resistant. In other embodiments, the mask layer 320 is etching resistant, and the etching process slowly etches away the mask layer 320 while ideally etching away the exposed film stack 310 at a faster rate. Therefore, by having a patterned mask layer 320 on top of the film stack 310, regardless of whether it is etch-proof or etch-resistant, the desired structure can be created by etching the exposed areas.

[0023]

[0028] Figure 3A shows step 210 (the "breakthrough process") in which the membrane stack 310 is disposed on the substrate 300. The mask layer 320 is disposed on the membrane stack 310. In some embodiments, the mask layer 320 includes silicon oxide or a carbon-containing material. In other embodiments, the mask layer includes only silicon oxide having a thickness of 100 nanometers to 10,000 nanometers (for example, about 1,000 nanometers to about 10,000 nanometers, about 1,000 nanometers to about 2,000 nanometers). In some embodiments, the membrane stack 310 includes a plurality of layers of pure silicon. In other embodiments, the membrane stack 310 includes a plurality of alternating layers of silicon and silicon germanium. The number of layers may be from a few to hundreds, for example, 2 to 1000 layers such as a maximum of 10, 50, 100, 200, 300, 400, 500, 600, 700, 800, 900, or a maximum of 1000 layers, for example, a membrane stack of up to several micrometers to several tens of micrometers such as a maximum of 50, 10, 100 micrometers, 30, 40, 50, 60, 70, 80, 90, or a maximum of 100 micrometers is constructed.

[0024]

[0029] Once formed in the deposition chamber, the film stack 310 may be stored for future processing or transferred to an etching chamber, such as chamber 150 of the processing system 100, for processing. Typically, a thin silicon oxide layer 340 forms spontaneously on any reactive silicon surface as a result of exposure to air. The air oxidizes the silicon, producing a thin film (or layer) of silicon oxide. This thin silicon oxide layer 340 can be removed prior to etching of the film stack 310. As shown in Figure 3A, the film stack 310 includes reactive silicon-containing surfaces between patterned openings in a mask layer 320, thereby forming a thin silicon oxide layer 340. In this embodiment, the mask layer 320 is a silicon oxide mask with a thickness T1 of about 1,000 to 2,000 nanometers. The thin silicon oxide layer 340 can be removed by a breakthrough (or "pre-cleaning") process, which involves plasma etching with hydrogen radicals from an energized hydrogen gas. Alternatively, argon radicals may be used to etch the silicon oxide thin layer 340. The resulting substrate assembly is shown in Figure 3B after the breakthrough process of step 210 has been performed. In this breakthrough process, a mixed gas of nitrogen trifluoride (NF3), argon (Ar), and oxygen (O2) is excited at a low chamber pressure of about 40 millitorl to about 60 millitorl using low source and bias power to clean any spontaneous oxide layer formed from exposure to ambient air. Although Figure 3B shows a smooth silicon oxide mask layer 320, in practice, the removal of the silicon oxide thin layer 340 may etch the silicon oxide mask layer 320 to a minimum extent equal to the thickness of the silicon oxide thin layer 340.

[0025]

[0030] In step 220 of Figure 2, the etching process is performed to a first depth of the exposed region of the film stack 310. The etching process in step 220 may include plasma ion collisions through a bias-generating sheath located above an electrostatic chuck supporting the substrate 300. The etching process may include an etching power supply of about 1,000 watts to about 4,000 watts, e.g., about 1,000 watts to about 3,000 watts, e.g., about 1,300 watts to about 2,100 watts, with a frequency of about 13.56 megahertz, a bias power of about 2,000 watts to about 5,000 watts (2 megahertz), e.g., about 3,000 watts to about 5,000 watts, e.g., about 4,000 watts to about 4,500 watts, with a chamber pressure of about 10 millitorl to about 100 millitorl, and a temperature of about -50°C to about 200°C maintained by the electrostatic chuck. In one embodiment, a mixed gas containing chlorine gas (Cl2), hydrogen bromide (HBr), oxygen (O2), argon (Ar), or a combination thereof is excited for etching for a period of about 10 to about 200 seconds. Figure 3C shows that plasma ion particles 380 vertically etch recesses in the exposed region of the film stack 310 to a first depth D1. The first depth D1 is etched to about 2 nanometers to about 300 nanometers, for example, from about 100 nanometers to about 300 nanometers, for example, to about 200 nanometers. Although not bound by theory, the etching performed by the plasma ion particles 380 etches the silicon oxide of the mask layer 320 at a slower rate than the film stack 310 containing the silicon layer or silicon germanium layer, via vertical ion collisions. In one embodiment, the etching rate can be set to about 100 nanometers per minute to about 200 nanometers per minute, depending on the RF power and bias power levels used. However, the thickness of the silicon oxide mask can be reduced from about 10 nanometers to about 100 nanometers, while the silicon or silicon germanium layer of the film stack 310, for example, can be etched from about 70 nanometers to about 700 nanometers. Therefore, the silicon oxide mask layer 320 resists the etching process step 220, but its thickness is slightly reduced.Figure 3C shows the thickness of the silicon oxide mask layer 320 as T2. Thickness T2 is less than thickness T1 shown in Figure 3B (pre-etching process).

[0026]

[0031] The etching process in step 220 generates removal byproducts 350 containing etched and removed film stack 310 material. The byproduct 350 particles generally float upwards towards the plasma in the depressions and are discharged from chamber 150 through a chamber exhaust path connected to a vacuum pump 155. However, not all of the material is exhausted; rather, it deposits on the nearest surface where its volume expands beyond the limiting dimensions (or width) of the etched depressions. Though not bound by theory, the etched silicon (or silicon germanium) byproducts 350 adhere to the silicon oxide mask layer 320, causing narrowing (or pinch-off) of the patterned openings 325 in the mask layer 320. This narrowing of the patterned openings 325 creates an obstacle for subsequent etching processes, as ions cannot reach the entire horizontal bottom of the depressions, thereby preventing the generation of high aspect ratio features by iterative etching processes. Experimentally, as the byproduct 350 adheres to the inner wall of the mask layer 320, the vertical profile of the etched recess is altered during the etching process. Theoretically, a substantially vertical profile of the etched recess can be produced by controlling the etching process in step 220, as shown in Figure 2. Such control parameters include the depth etching of the recess before deformation, the etching time, and the saturation time of exposure to an oxygen-containing gas before etching, the etching mixed gas composition, and the chamber pressure. Figure 3D shows a diagram of the narrowing of the patterned opening 325. To counteract pinching narrowing of the mask layer 320, the inventors have achieved a method of aggressively clearing the mask layer 320, enabling a uniform profile while achieving deeper etching.

[0027]

[0032] One method for removing the narrowed removal byproduct 350 from the patterned opening 325 is to process the substrate assembly by forming a passivation layer 370 and then performing a passivation layer etching treatment, as shown in Figures 3E and 3F, and steps 230 and 240 in Figure 2. The passivation layer 370 involves silicon oxide deposition using an oxygen-containing gas. Oxygen in the oxygen-containing gas reacts with exposed silicon-reactive surfaces, such as the inner walls of the film stack recesses and the accumulation of byproduct 350 on the mask layer 320. Although not bound by theory, the oxygen oxidizing silicon is more reactive near the top of the recesses along the sidewalls of the film stack 310 and near the sidewalls of the mask layer 320, as oxygen particles react first to the parts closest to the openings. Furthermore, the oxidation of the exposed silicon is controlled by a source power of 2,500 watts with a bias power of approximately 50 to 100 watts (at approximately 13.56 megahertz), and by an oxygen flow rate of approximately 120 standard cubic centimeters (sccm) at time intervals of approximately 8 to 20 seconds, for example, approximately 10 to 20 seconds. Some oxidation occurs within the depressions, but the silicon oxide layer (or passivation layer) 370 formed from the passivation process 230 gradually thins as it approaches the deepest parts of the depressions.

[0028]

[0033] Step 240 in Figure 2 involves processing the passivation layer 370 using a controlled plasma etching process designed to target a depth equal to the thickness T2 of the mask layer. The passivation processing plasma involves using a 2,100-watt power supply and a bias power of approximately 50-100 watts (13.56 megahertz) to excite a mixed gas of nitrogen trifluoride (NF3), argon (Ar), and oxygen (O2) under a pressure of approximately 20-60 milliliters for a duration of 10-100 seconds. Thus, the by-products 350 accumulated along the inner wall of the mask layer 320 are effectively removed with minimal removal (or damage) of the silicon oxide passivation layer 370 located within the sidewall of the film stack 310 in recesses less than T3 in Figure 3F. Note that processing the passivation layer 370 reduces the thickness of the mask layer to a thickness T3, which is thinner than T2 in Figure 3E. This passivation method allows the mask layer 320 to be opened unobstructed for the subsequent etching process. The exposed sidewalls of the mask layer 320 and the remaining silicon oxide passivation layer 370 on the sidewalls of the recesses allow the next etching process to reach the deepest part of the recess with minimal lateral profile etching, thereby achieving deeper etching while maintaining the desired target limit dimensions (width). Figure 3F shows the remaining substrate assembly after the passivation process.

[0029]

[0034] As shown in step 250 of Figure 2 and in the diagram of Figure 3G, a subsequent etching process similar to step 220 is performed so that the vertical etching reaches a second depth D2. Note that the method described in Figure 2 (illustrated by the iterative path 260) can be repeated to achieve a desired depth or high aspect ratio structure on the substrate 300. The term "second depth" may refer to the desired final depth. For example, steps 220-240 can be repeated until the resulting structure reaches a high aspect ratio of 100:1 or higher. Since the thickness of the layer decreases in each etching step, the resulting thickness of the silicon oxide mask layer 320 may be a limiting factor.

[0030]

[0035] After the desired depth is achieved in the recess, the silicon oxide mask layer 320 can be removed by wet acid immersion, which dissolves the mask layer 320 and any remaining residual silicon oxide, including any remaining passivation layer material. Wet acid immersion involves immersing the substrate assembly in an acid, such as hydrofluoric acid. The resulting device structure is shown in Figure 3H, which shows the smooth top surface of the film stack 310 without the silicon oxide mask layer 320.

[0031]

[0036] Figure 4 shows an exemplary mask layer 400 having elliptical patterned openings 410. However, many shapes such as circles, squares, diamonds, ellipses, and triangles are envisioned as patterned openings 410, for example, but are not limited to these. The patterned openings 410 may be aligned in both equally spaced rows and columns, as shown in Figure 4, or they may be arranged in many other configurations to form a desired device structure.

[0032]

[0037] Figure 5 shows cross-sectional views of multiple film stack device structures, expanding to the single recess shown in Figure 3H. Film stack 310 shows the smooth top surface of film stack 310 without the silicon oxide mask layer. Each of the film stack structures corresponds to an active layer for a 3D DRAM device.

[0033]

[0038] Figure 6 shows a collection of critical dimension measurements reflecting multiple etching iterations of Method 200 as the recesses deepen with each etching. For a substantially vertical 100:1 high aspect ratio structure at an etching depth of approximately 8 micrometers, a recess (or hole) critical dimension (or width) of approximately 80 nanometers along the vertical profile of the film-layered recess is required. It should be noted that deviations of approximately 10 nanometers from the required critical dimension tolerance result in potential substrate warping, deformation, and premature failure. In other words, a tolerance of approximately 10 nanometers corresponds to a deviation of the center of the recess within 5 nanometers in any radial direction. Although Figure 6 shows only the results for an etching depth of 8 micrometers, the inventors achieved similar results using an etching depth of 10 micrometers while maintaining a critical dimension of approximately 100 nanometers along the vertical profile of the film-layered recess, while maintaining a critical dimension tolerance of approximately 10 nanometers. Therefore, the implementation of method 100 results in a substantially vertical recess that achieves a high aspect ratio device structure of 100:1 for depths up to 10 micrometers.

[0034]

[0039] All numerical values ​​are "approximate" or "about" the values ​​shown, taking into account experimental errors and variations that a person skilled in the art would expect.

[0035]

[0040] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims. All documents described herein, including any prior documents and / or test procedures, are incorporated herein by reference, insofar as they do not conflict with this text. While the forms of the present disclosure are illustrated and described as will be obvious from the above summary and specific embodiments, various modifications may be made without departing from the essence and scope of the present disclosure. Therefore, it is not intended to limit the present disclosure.

[0036]

[0041] Certain embodiments and features are described using sets of minimum and maximum numerical values. Unless otherwise indicated, it should be recognized that ranges are assumed to include any pair of values ​​(e.g., any pair of minimum and any maximum, any pair of minimums, and / or any pair of maximums). Some of the following claims describe certain minimums, maximums, and ranges.

Claims

1. A method for patterning a circuit board, (a) Etching the substrate to form a recess to a first depth, wherein a mask layer is placed on the substrate, (b) Depositing a passivation layer on the side wall of the recess, (c) To remove the blockage material formed from etching by-products on the mask layer, the passivation layer is treated, (d) Etching the recess to a second depth while maintaining the minimum variation in the width of the recess side wall, Methods that include...

2. The method according to claim 1, wherein the first depth is approximately 2 nanometers to approximately 300 nanometers.

3. The method according to claim 2, wherein the first depth is approximately 200 nanometers.

4. The method according to claim 1, wherein depositing the passivation layer includes exposing the substrate to a plasma formed from an oxygen-containing precursor gas.

5. The method according to claim 1, further comprising depositing the passivation layer to generate an oxygen plasma at approximately 13.56 MHz with an RF power of approximately 2,500 W and a bias power of approximately 100 W.

6. The method according to claim 1, wherein processing the passivation layer includes exposing the sidewalls of the mask layer.

7. The method according to claim 1, wherein the substrate includes a plurality of silicon layers, or alternating layers of silicon and silicon germanium.

8. The passivation layer is processed under a pressure of approximately 20 milliliters to approximately 60 milliliters, NF ３ , Ar, and O ２ The method according to claim 1, further comprising generating a plasma from a mixed gas.

9. The method according to claim 8, further comprising treating the passivation layer by exposing the substrate for a duration of about 10 seconds to about 100 seconds.

10. In etching the aforementioned substrate, Cl ２ , HBr, and O ２ The method according to claim 1, further comprising generating a plasma from a mixed gas containing the following:

11. The method according to claim 10, wherein generating plasma uses a bias power of 4,000 watts to about 4,500 watts.

12. In etching the recess, Cl ２ , HBr, and O ２ The method according to claim 1, further comprising generating a plasma from a mixed gas containing the following:

13. The method according to claim 12, wherein generating plasma uses a bias power of 4,000 watts to about 4,500 watts.

14. The method according to claim 1, wherein (a), (b), (c), and (d) are repeated until the recess has an aspect ratio of at least 100:

1.

15. The method according to claim 1, wherein maintaining a minimum variation in the width of the recess sidewall includes keeping the variation within about 10 nanometers.

16. A method for patterning a circuit board, (a) Etching the substrate in order to remove the oxide layer and expose the silicon-containing film laminate, (b) Etching the substrate to form a recess to a first depth within the film stack, wherein the substrate comprises a mask layer disposed on the film stack, the mask layer has an inner wall, the film stack is disposed on the substrate, and etching the substrate is Cl ２ HBr, O ２ , and generating plasma from a mixed gas of Ar, Etching the substrate to form recesses to a first depth, including exposing the substrate to the plasma for about 10 seconds to about 200 seconds, (c) Exposing the substrate to the generated oxygen plasma for about 10 to 20 seconds to oxidize the side walls of the recesses and the inner walls of the mask layer having silicon-containing etching byproducts, (d) Exposing the sidewalls of the mask layer by controlled etching, wherein the controlled etching is NF ３ Ar, and O ２ generating plasma from a mixed gas of The substrate is exposed to the plasma for approximately 10 to 200 seconds. (e) Repeat (b), (c), (d), (f) Etching the recess to a second depth while maintaining the vertical profile of the first depth within 5 nanometers from the center of the recess, Methods that include...

17. The method according to claim 16, wherein the final depth has a 100:1 aspect ratio structure.

18. A system for processing semiconductor substrates, A chamber comprising a lid, a main body, side walls, and a substrate support, The processing space defined by the lid, the body, and the side wall, A system controller connected to the aforementioned chamber, The system controller has a non-temporary computer-readable medium in which instructions are stored, and when an instruction is executed by the processor, it is sent to the process. (a) Etching the substrate in order to remove the thin layer of oxide and expose the silicon-containing film stack, (b) Etching the substrate to form a recess to a first depth, wherein a mask layer is placed on the substrate, (c) Depositing a passivation layer on the side wall of the recess, (d) To remove the blockage material formed from etching by-products on the mask layer, the passivation layer is treated, (e) Etching the recess to a second depth while maintaining the minimum variation in the width of the recess side wall, The process is to execute the following steps. system.

19. The system according to claim 18, further comprising a final depth having an aspect ratio of at least 100:

1.

20. The system according to claim 19, wherein the final depth includes a recess sidewall width profile of about 10 nanometers or less.

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