A substrate having electronic components mounted in the core cavity using hole-filling ink, and a method for fabricating the substrate.

Abstract

In one embodiment, an electronic device is disclosed, comprising a substrate, a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component at least partially surrounded within the cavity by cured hole-filling ink, the electronic component including an upper plane having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Description

Technical Field

[0001]

[0001] This disclosure generally relates to substrates, and more particularly to substrates having embedded electronic components implemented within the core of the substrate.

Background Art

[0002]

[0002] Integrated circuit (IC) technology has achieved great progress in improving computing power by miniaturizing electrical components. An IC can be realized in the form of an IC chip having a set of circuits integrated thereon. In some mounting forms, one or more IC chips can be physically carried and protected by an IC package, and various power and signal nodes of the one or more IC chips can be electrically coupled to respective conductive terminals of the IC package via electrical paths formed within the package substrate of the IC package. Various packaging technologies can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing techniques can be used to realize composite devices, such as multi-electronic component devices and system-on-a-chip (SOC) devices, which may include multiple functional blocks designed to perform specific functions, such as, for example, microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), and the like.

[0003]

[0003] In some implementations, embedded passive devices, such as deep trench capacitors, are incorporated into the IC packaging for improved performance and reduced package size. One factor driving the use of such embedded passive devices is the demand for small form factor products that have electrical performance equivalent to or better than their larger passive device counterparts. Depending on the size and / or thickness of the package substrate, and the size and / or process node of the IC chip supported thereon, a process for embedding a passive device in the package substrate in one packaging task may not be suitable for another packaging task.

[0004]

[0004] Therefore, there is a need for an improved method for embedding electrical components in a substrate such as a package substrate, which can be used for a wider variety of packaging tasks. [Overview of the project]

[0005]

[0005] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, the following overview should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope associated with any particular embodiment. Accordingly, the sole purpose of the following overview is to provide, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0006]

[0006] In one embodiment, the electronic device includes a substrate comprising: a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component being at least partially surrounded within the cavity by cured hole-filling ink, the electronic component including an upper plane having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0007]

[0007] In one embodiment, the substrate includes a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component at least partially surrounded within the cavity by cured hole-filling ink, the electronic component including an upper plane having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0008]

[0008] In one embodiment, a method for manufacturing a substrate includes: forming a cavity in a core having a first plane and a second plane, the cavity extending between the first plane and the second plane of the core; embedding an electronic component at least partially within the cavity, the electronic component being at least partially surrounded within the cavity by a cured filler ink, the electronic component including a plane having one or more electronic component terminals; and forming a metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the metallization structure.

[0009]

[0009] Other purposes and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. [Brief explanation of the drawing]

[0010]

[0010] A more complete understanding of many aspects of this disclosure and their associated advantages will be easier to obtain if they are examined together with the accompanying drawings, which are presented not to limit this disclosure but merely to illustrate it, by referring to the following detailed description. [Figure 1]

[0011] Figure 1 is a cross-sectional view of an exemplary substrate having embedded electronic components according to an aspect of the present disclosure. [Figure 2]

[0012] Figure 2 is a cross-sectional view of the exemplary substrate of Figure 1, showing void propagation and resulting defects in a dielectric material according to an aspect of this disclosure. [Figure 3]

[0013] This is a cross-sectional view of an exemplary deep trench capacitor according to an aspect of the present disclosure. [Figure 4]

[0014] This is a cross-sectional view of an exemplary substrate according to an aspect of the present disclosure. [Figure 5ABC]

[0015] Figures 5A to 5C illustrate exemplary steps taken when manufacturing an exemplary substrate according to an embodiment of the present disclosure. [Figure 5DEF] Figures 5D to 5F illustrate exemplary steps taken when manufacturing an exemplary substrate according to an embodiment of the present disclosure. [Figure 5GHI] Figures 5G to 5I illustrate exemplary steps taken when manufacturing an exemplary substrate according to an embodiment of the present disclosure. [Figure 6ABC]

[0016] Figures 6A to 6C illustrate exemplary steps taken when manufacturing an exemplary substrate according to an embodiment of the present disclosure. [Figure 6DEF] Figures 6D to 6F illustrate exemplary steps taken when manufacturing an exemplary substrate according to an embodiment of the present disclosure. [Figure 6GH] Figures 6G and 6H illustrate exemplary steps taken when manufacturing an exemplary substrate according to an embodiment of the present disclosure. [Figure 7]

[0017] This flowchart shows an exemplary method for manufacturing a substrate according to an aspect of the present disclosure. [Figure 8]

[0018] A side view of a package including a surface mount substrate, an integrated device, and an integrated passive device according to an aspect of this disclosure is shown. [Figure 9]

[0019] This diagram illustrates an exemplary flow chart of a method for manufacturing a package including a substrate, integrated devices, and integrated passive devices. [Figure 10]

[0020] This specification describes various electronic devices capable of integrating the electronic components, electronic circuits, integrated devices, integrated passive devices, passive components, packages, and / or device packages described herein.

[0011]

[0021] By convention, features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of depicted features may be enlarged or reduced as appropriate for clarity. By convention, some of the drawings are simplified for clarity. Therefore, the drawings may not depict all parts of a particular apparatus or method. Furthermore, similar reference numerals indicate similar features throughout this specification and the drawings. [Modes for carrying out the invention]

[0012]

[0022] Aspects of the Disclosure are shown in the following description and related drawings, which cover specific embodiments. Alternative embodiments or designs may be devised without departing from the scope of the teachings herein. In addition, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings herein.

[0013]

[0023] In some of the exemplary implementations described, cases are identified where some of the structure and operation of various components are incorporated from known conventional techniques and can then be configured according to one or more exemplary embodiments. In such cases, in order to help avoid obscuring the concepts illustrated in the exemplary embodiments disclosed herein, details internal to some of the structure and / or operation of known conventional components may be omitted.

[0014]

[0024] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. The singular forms "a", "an", and "the" used herein shall be construed to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0015]

[0025] FIG. 1 is a cross-sectional view of an exemplary substrate 100 having an embedded electronic component according to an aspect of the present disclosure. In this example, the substrate 100 includes a core 102 having a cavity 104 that extends completely through the core 102. An electronic component 106 is disposed within the cavity 104. The electronic component 106 has an upper plane 108 having one or more electronic component terminals 110 that provide electrical connection to a device (e.g., a deep trench capacitor) constituted by the electronic component 106.

[0016]

[0026] According to various aspects of the present disclosure, the substrates described herein (e.g., substrate 100) that include a core and embedded electronic components are targeted at package substrates. A package substrate is a part of an integrated circuit package that gives the board its mechanical strength and enables it to connect to external devices. Such a package substrate should be distinguished from other substrates, such as a substrate that may be included within the embedded electronic component itself, a die including a substrate (e.g., a silicon substrate or other similar electronic device).

[0017]

[0027] Substrate 100 further includes a plurality of dielectric layers 112 and patterned metallization layers 114 lying on the upper plane 116 of core 102 (in FIG. 1, only one such dielectric layer and the corresponding patterned metal layer lying on the upper plane 116 are shown). A patterned metallization layer 118 including via structures 120 is disposed on the upper plane 116 of core 102 to provide an electrical connection between one or more electronic component terminals 110 and the patterned metallization layer 114.

[0018]

[0028] In this example, one or more vias 122 extend through core 102 to connect the patterned metallization layer 118 on the upper plane 116 of core 102 to a further patterned metallization layer 124 on the lower surface 126 of core 102. A further plurality of dielectric layers 128 and patterned metallization layers 130 are formed on the lower surface 126 of core 102 (in FIG. 1, only one such dielectric layer and the corresponding patterned metal layer formed on the lower surface 126 are shown).

[0019]

[0029] In one embodiment, the same dielectric material used to form the dielectric layer 128 may be used to fill the cavity 104. Commonly used dielectric materials include Ajinomoto Build-Up Film (ABF), PPG (registered trademark) liquid resin, and similar materials. During the fabrication of the substrate 100, the electronic component 106 is inserted into the cavity 104 before the dielectric resin is injected to fill the region 132 between the cavity 104 and the electronic component 106. During insertion, the electronic component 106 is carefully aligned within the cavity 104 to ensure that one or more electronic component terminals 110 make proper contact with the corresponding portions of the patterned metallization layer 118 and electrically couple. In addition, the injection of the dielectric resin into the region 132 must be carried out carefully so as not to disturb the initial alignment of the electronic component 106 within the cavity 104. In one embodiment, once the dielectric resin is cured, it fixes the electronic component 106 in its appropriate location within the cavity 104.

[0020]

[0030] Current trends in PCB design are directed towards applications that present unique design and fabrication challenges (e.g., the need to reduce PCB warpage, the need for cavities to accommodate large electronic components, the need for larger keep-out zones, etc.). These challenges can be addressed, at least in part, by employing thicker cores in the design and fabrication of such PCBs. For example, warpage control is more easily achieved with thicker cores than with thinner cores. In addition, the need for larger cavity sizes and keep-out zones can be met by employing such thicker cores. In some scenarios, cores (e.g., both thick and thin cores) may be required to accommodate large embedded electronic components that occupy a considerable volume of the cavity in which they are embedded.

[0021]

[0031] However, substrates employing thick cores or requiring large embedded electronic components may be difficult to fabricate using the same packaging techniques used in the production of substrates with thin cores and / or smaller embedded electronic components. When using thick cores, a large gap exists between the electronic component and the cavity resulting from the increased cavity depth compared to the height of the electronic component (for example, a thick core has a thickness greater than the die height). In such thick core scenarios, it may be difficult or impossible to fill the cavity (e.g., particularly the area between the outside of the electronic component and the inner wall of the cavity) with commonly used dielectric resins (e.g., Ajinomoto Build-Up Film® (ABF), PPG® liquid resin, etc.) without creating voids in the resulting dielectric material into which the electronic component is finally embedded. Similarly, when the electronic component occupies a considerable volume of the cavity, it may be difficult to adequately fill the small area between the electronic component and the cavity with commonly used dielectric resins without creating voids in the resulting dielectric material into which the electronic component is finally embedded.

[0022]

[0032] Figure 1 shows a void 134 in the dielectric material filling the cavity 104, which occurs when the region between the inner surface of the cavity 104 and the outer surface of the electronic component 106 is not properly filled with the dielectric material. In Figure 1, the void 134 in the dielectric material does not present an immediate problem regarding the connection between one or more electronic component terminals 110 and the patterned metallization layer 118. However, the void 134 may propagate through the dielectric material as a result of thermal and / or mechanical stresses that occur during the use of the substrate for its intended purpose.

[0023]

[0033] Figure 2 is a cross-sectional view of an exemplary substrate 100 showing the propagation of voids 134 in a dielectric material and the resulting defects according to an aspect of this disclosure. For simplicity, the reference numerals used in Figure 1 are also used to indicate similar elements in Figure 2.

[0024]

[0034] In Figure 2, the propagation of the void 134 allows the electronic component 106 to shift its position within the cavity 104, resulting in the delamination of the electronic component 106 from the core 102. Such delamination can lead to performance degradation and / or complete failure of the electronic device on which the substrate 100 is incorporated.

[0025]

[0035] According to certain aspects of this disclosure, the electronic component may be a DTC. Figure 3 is a cross-sectional view of an exemplary DTC 300 according to an aspect of this disclosure. In Figure 3, a capacitor 310 is deposited in trenches 320 of an insulator 304 on a substrate 302. The capacitor 310 may include a metal layer 312, a dielectric layer 314, and a metal layer 316. The dielectric layer 314 separates the metal layer 312 from the metal layer 316. The metal layers 312, 316 form the electrodes of the capacitor 310 and may be connected to terminals on a surface, for example (see, for example, the top surface 108 having the electronic component terminals 110 of the electronic component 106 shown in Figure 1). In some scenarios, the capacitor is formed from an array of deep trenches in the substrate and filled with an electrical insulator (e.g., a dielectric) between the electrode layers. In some scenarios, the capacitor is mounted on the land side, under the shadow of the integrated circuit die (land-side capacitor, LSC), or on the die side, adjacent to the die (die-side capacitor, DSC).

[0026]

[0036] Some aspects of this disclosure are implemented with recognition of the problems associated with using existing processing techniques and materials to manufacture substrates having thick cores and / or cavities that house large embedded electronic components. According to some aspects of this disclosure, electronic components may be embedded in a cavity using a filler ink that is dispensed into the cavity and then cured to fix the electronic component in place within the cavity. Such filler inks are often used in existing manufacturing operations to fill hollow vias that extend through the core of a substrate. Some aspects of this disclosure are implemented with recognition of the fact that such filler inks have fluid and other material properties (e.g., low viscosity) that allow the filler ink to substantially fill the area between the inner surface of the cavity and the outer surface of the electronic component without creating voids, thereby resulting in a more rigid embedding of the electronic component into the core of the substrate. In one aspect, certain conventional processes dispense a fixed amount of filler material into the cavity, whereas the filler ink of this disclosure may be dispensed into the cavity until the cavity is filled. In some aspects of this disclosure, and without limitation, filler inks such as the THP-100DX1 series filler ink available from Taiyo America, Inc. and the PHP900 series filler ink available from Yamaei Chemical Co., Ltd. are suitable for securing electronic components within cavities.

[0027]

[0037] Figure 4 is a cross-sectional view of an exemplary substrate 400 according to an aspect of the present disclosure. In this example, the substrate 400 includes an electronic component 402 having a lower plane 404 and an upper plane 406. The upper plane 406 of the electronic component 402 includes one or more electronic component terminals 408 that provide electrical connections to the electronic component 402.

[0028]

[0038] The substrate 400 further includes a core 410 having a lower plane 412 and an upper plane 414. A cavity 416 extends through the core 410 between the upper plane 414 and the lower plane 412. In this example, the thickness H1 of the core 410 is substantially the same dimension as the height H2 of the electronic component 402 as measured between the upper plane 406 and the lower plane 404 of the electronic component 402. According to various aspects of this disclosure, the core 410 may be a thin core having a thickness H1 of 800 micrometers or less. Alternatively, the core may be a thick core having a thickness H1 greater than 700 micrometers (e.g., greater than 760 micrometers). In this example, the electronic component 402 occupies a considerable volume (e.g., 66%) of the cavity 416. According to various aspects of this disclosure, the electronic component 402 is fixed within the cavity 416 using cured hole-filling ink 418. In one embodiment, the cured filler ink 418 is initially deposited as a liquid filler ink that surrounds the electronic component 402 and fills the cavity 416 without the voids typically associated with fillers formed from commonly used dielectric resins. Once the liquid filler ink is deposited, it forms a cured filler ink 418 as a substantially void-free solid material (e.g., having no voids or having fewer and / or smaller voids than those typically found in conventional dielectric fillers used to embed electronic components under similar geometric filling constraints), thereby undergoing a curing process to provide a secure mounting of the electronic component 402 within the cavity 416. In this example, the filler ink 418 extends to cover portions of the lower plane 404 of the electronic component 402 and the lower plane 412 of the core 410. Because the filler ink 418 is substantially free of the type and number of voids typically associated with more common dielectric material fillings, the electronic component 402 is firmly fixed within the cavity 416 in such a manner that it reduces the opportunity for the electronic component 402 to detach from the core 410.

[0029]

[0039] In one embodiment, the substrate 400 may include an upper metallization structure 424 disposed on the upper plane 414 of the core 410. In the example shown in Figure 4, the upper metallization structure 424 includes one or more dielectric layers 426, one or more patterned metallization layers 428, and one or more vias 430. In one embodiment, the upper metallization structure 424 is configured to provide one or more conductive paths between one or more terminals 432 of the uppermost metallization layer 428a and one or more electronic component terminals 408. A lower metallization structure 434 may also be disposed on the lower plane 412 of the core 410.

[0030]

[0040] Although the dielectric layer 426 is shown as a separate layer in Figure 4, it will be understood that multiple dielectric layers can be fused during the fabrication process so that they appear and function as a single dielectric structure. Furthermore, it will be understood that different layers of dielectric layer 426 can be formed from different dielectric materials during the fabrication process. In one embodiment, different dielectric materials can be used for different dielectric layers when one or more of the dielectric layers 426 are to have a different dielectric constant than other dielectric layers 426.

[0031]

[0041] As described above, the cavity 416 may be filled with filler ink 418 to secure the electronic component 402 within the cavity 416. In one embodiment, the filler ink 418 may completely fill the cavity 416 such that the entire electronic component 402 is surrounded by the filler ink 418.

[0032]

[0042] Figures 5A to 5I illustrate exemplary operations that may be performed during the manufacturing of an exemplary substrate according to embodiments of the present disclosure. Figure 5A shows a first intermediate state 500 of the substrate during an exemplary manufacturing process according to embodiments of the present disclosure. In this example, the first intermediate state 500 of the substrate includes a core 502 having an upper plane 504 and a lower plane 506. A thin metal cladding layer 508 is disposed on the upper plane 504. A further thin metal cladding layer 510 is disposed on the lower plane 506. The first intermediate state 500 of the substrate also includes via structures 512 extending between the upper plane 504 and the lower plane 506 of the core 502. In one embodiment, the core 502 undergoes a drilling operation to form the via structures 512.

[0033]

[0043] Figure 5B shows a second intermediate state 514 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. In this example, a metallization layer 516 is formed on a thin metal cladding layer 508 in the upper plane 504 of the core 502, and a further metallization layer 518 is formed on a thin metal cladding layer 510 in the lower plane 506 of the core 502. Via structures 512 are at least partially filled to form vias 520 that electrically connect the metallization layers 516, 518. Depending on the thickness of the core 502, the vias may be fully filled (as shown in Figure 5B) or partially filled with metal, leaving a central hollow portion of the via 520 that is not filled with metal (not shown in Figure 5B). Regions 524 in the upper plane 504 of the core 502 and region 526 in the lower plane 506 of the core 502 are exposed and not covered by the metallization layers 516 and 518. To be understood, regions 524 and 526 may be formed in either an additive or subtractive metallization process.

[0034]

[0044] Figure 5C shows a third intermediate state 528 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, the second intermediate state 514 of the substrate is machined (e.g., laser-drilled) to form a cavity 530 within the core 502. In this example, the cavity 530 extends between the upper plane 504 and the lower plane 506 of the core 502.

[0035]

[0045] Figure 5D shows a fourth intermediate state 532 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, a layer of polyimide (PI) tape 534 is placed on top of the metallization layer 518 and above the lower opening of the cavity 530. An electronic component 536 is placed in the cavity 530 and mounted on the upper plane 538 of the PI tape 534, so that one or more electronic component terminals 540 on the lower plane 542 of the electronic component 536 are in contact with the upper plane 538 of the PI tape 534. In one aspect, one or more electronic component terminals 540 provide electrical connections by or to electrical components (e.g., deep trench capacitors) formed inside the electronic component 536.

[0036]

[0046] Figure 5E shows a fifth intermediate state 544 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, a vent 546 is formed through the PI tape 534 at the lower opening of the cavity 530.

[0037]

[0047] Figure 5F shows a sixth intermediate state 548 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, the filler ink 550 is dispensed in an uncured state into the upper opening 552 of the cavity 530 and drawn downward through the cavity 530 and through the vent 546. In one embodiment, the filler ink 550 is drawn into the cavity 530 by the pressure difference created between the upper opening 552 and the vent 546. In this example, the filler ink 550 completely fills the cavity 530, including the entire area between the sidewall of the electronic component 536 and the sidewall of the cavity 530. In one embodiment, the filler ink 550 also fills the area between the lower plane 542 of the electronic component 536 and the upper plane 538 of the PI tape 534. The remaining amount of filler ink 550 extends beyond the cavity 530, above the upper opening 552 of the cavity 530, and into the area on the PI tape 534 near the vent 546. In one embodiment, the filler ink 550 undergoes a pre-curing process while in a sixth intermediate state 548.

[0038]

[0048] Figure 5G shows a sixth intermediate state 554 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure, where a layer of PI tape 534 is removed. According to some aspects of the present disclosure, the void-filling ink 550 is then subjected to a curing process (e.g., a thermosetting process, an ultraviolet curing process, etc.). Once cured, the void-filling ink 550 forms a solid structure in which the electronic component 536 is embedded and fixed within the cavity 530. In one aspect, the cavity 530 is completely filled with uncured void-filling ink 550, thereby curing the void-filling ink 550 and forming a substantially void-free structure (e.g., void-free or having fewer and / or smaller voids than those typically found in conventional dielectric fillings used to embed electronic components under similar geometric filling constraints), thereby resulting in a robust mounting of the electronic component 536 within the cavity 530.

[0039]

[0049] The curing of the filler ink 550 and the removal of the PI tape 534 layer leave flushings 556, 558 to be removed (e.g., using a brushing process) to form a seventh intermediate state 560 of the substrate shown in Figure 5H. In the example shown in Figure 5H, flushing 556 is removed so that the cured filler ink 550 is level with the top surface of the metallization layer 516. Similarly, flushing 558 is removed so that the cured filler ink 550 is level with the bottom surface of the metallization layer 518.

[0040]

[0050] Figure 5I shows an eighth intermediate state 562 of a substrate in an exemplary manufacturing process according to an aspect of the present disclosure, where portions of the metallization layers 516 and 518 are selectively removed to form a first set of conductive traces 564 in the upper plane 504 of the core 502 and a second set of conductive traces 566 in the lower plane 506 of the core 502. In one embodiment, the eighth intermediate state 562 of the substrate manufacturing process may receive multiple build-upper layers of dielectric and metallic materials to ultimately form the upper metallization structure of the substrate (see, for example, Figure 4).

[0041]

[0051] Figures 6A–6H illustrate another set of exemplary operations performed during the manufacturing of an exemplary substrate according to embodiments of the present disclosure. Figure 6A shows a first intermediate state 600 of the substrate during an exemplary manufacturing process according to embodiments of the present disclosure. In this example, the first intermediate state 600 of the substrate includes a core 602 having an upper plane 604 and a lower plane 606. A thin metal cladding layer 608 is disposed on the upper plane 604. A further thin metal cladding layer 610 is disposed on the lower plane 606. The first intermediate state 600 of the substrate also includes a via structure 612 extending between the upper plane 604 and the lower plane 606 of the core 602. In one embodiment, the core 602 undergoes a drilling operation to form the via structure 612.

[0042]

[0052] Figure 6B shows a second intermediate state 614 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. In this example, a metallization layer 616 is formed on a thin metal cladding layer 608 in the upper plane 604 of the core 602, and a further metallization layer 618 is formed on a thin metal cladding layer 610 in the lower plane 606 of the core 602. Via structures 612 are partially filled to form hollow vias 620 that electrically connect the metallization layers 616, 618. The second intermediate state 614 of the substrate also includes a (e.g., laser-drilled) cavity 622 within the core 602. In this example, the cavity 622 extends between the upper plane 604 and the lower plane 606 of the core 602.

[0043]

[0053] Figure 6C shows a third intermediate state 624 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, a layer of PI tape 626 is placed on top of the metallization layer 618 and on the lower opening of the cavity 622. An electronic component 628 is placed in the cavity 622 and mounted on the upper plane 630 of the PI tape 626, so that one or more electronic component terminals 632 on the lower plane 634 of the electronic component 628 are in contact with the upper plane 630 of the PI tape 626. In one aspect, one or more electronic component terminals 632 provide electrical connections by or to electrical components (e.g., deep trench capacitors) formed inside the electronic component 628.

[0044]

[0054] Figure 6D shows a fourth intermediate state 636 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, a vent 638 is formed through the PI tape 626 at the lower opening of the cavity 622.

[0045]

[0055] Figure 6E shows a fifth intermediate state 640 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, the filler ink 642 is dispensed in an uncured state into the upper opening 644 of the cavity 622 and drawn downward through the cavity 622 and through the vent 638. In one embodiment, the filler ink 642 is drawn into the cavity 622 by a pressure difference created between the upper opening 644 of the cavity 622 and the vent 638. Unlike the process shown in Figure 6F, in this example, the uncured filler ink 642 only partially fills the cavity 622, including only the portion of the area between the sidewall of the electronic component 628 and the sidewall of the cavity 622. In one embodiment, the filler ink 642 also fills the area between the lower plane 634 of the electronic component 628 and the upper plane 630 of the PI tape 626. The remaining amount of filler ink 642 extends beyond the cavity 622 into an area on the PI tape 626 near the vent 638. According to certain aspects of the present disclosure, the filler ink 642 may undergo a pre-curing process at this point in the manufacturing process. In one embodiment, the filler ink 642 is not allowed to enter the hollow via 620 at all. To achieve this objective, the hollow via 620 may be temporarily protected with a covering barrier which is then removed after a partial amount of filler ink 642 has been deposited in the cavity 622.

[0046]

[0056] Figure 6F shows a sixth intermediate state 646 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure, where the PI tape 626 layer is removed. In one aspect, the remaining unfilled portion of the cavity 622 is then filled with an additional amount of uncured filler ink 642. In one aspect, the hollow via 620 is also filled with uncured filler ink 642. According to certain aspects of the present disclosure, the hollow via 620 may be filled with filler ink 642 at the same time that the remaining unfilled portion of the cavity 622 is filled with filler ink 642.

[0047]

[0057] The filler ink 642 in the hollow vias 620 and cavities 622 can then undergo a curing process. Once cured, the filler ink 642 forms a solid structure in which the electronic component 628 is embedded for fixation within the cavity 622. The curing of the filler ink 642 and the removal of the PI tape 626 layer leave flushing 648, 650 which are removed (e.g., using a brushing process) to form a seventh intermediate state 652 of the substrate shown in Figure 6G. In the example shown in Figure 6G, flushing 648 is removed so that the cured filler ink 642 is level with the top surface of the metallization layer 616. Similarly, flushing 650 is removed so that the cured filler ink 642 is level with the bottom surface of the metallization layer 618.

[0048]

[0058] Figure 6H shows an eighth intermediate state 654 of a substrate in an exemplary manufacturing process according to an aspect of the present disclosure, where portions of the metallization layers 616 and 618 are selectively removed to form a first set of conductive traces 656 in the upper plane 604 of the core 602 and a second set of conductive traces 658 in the lower plane 606 of the core 602. In one embodiment, the eighth intermediate state 654 of the substrate manufacturing process may receive multiple build-up layers of dielectric and metallic materials to form the upper metallization structure of the substrate (see, for example, Figure 4).

[0049]

[0059] Figure 7 is a flowchart illustrating an exemplary method 700 for manufacturing a substrate according to an aspect of the present disclosure. In operation 702, a cavity is formed in a core having a first plane and a second plane, the cavity extending between the first plane and the second plane of the core. In operation 704, an electronic component is at least partially embedded in the cavity, the electronic component being at least partially surrounded by cured filler ink, the electronic component including a plane having one or more electronic component terminals. In operation 706, a metallization structure is formed and configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the metallization structure.

[0050]

[0060] In some embodiments, embedding an electronic component at least partially within a cavity includes covering the lower opening of the cavity with polyimide (PI) tape and inserting the electronic component into the cavity such that one or more electronic component terminals on the plane of the electronic component are in contact with the upper surface of the PI tape.

[0051]

[0061] In some embodiments, embedding an electronic component at least partially within a cavity further includes forming a vent through a PI tape at a lower opening of the cavity, filling the cavity so as to surround the electronic component with uncured filler ink, precuring the uncured filler ink within the cavity to provide precured filler ink within the cavity, peeling off the PI tape, and curing the precured filler ink to provide cured filler ink for mounting the electronic component within the cavity.

[0052]

[0062] In some embodiments, filling a cavity to surround an electronic component with uncured filler ink includes dispensing the uncured filler ink through an upper opening of the cavity and providing a pressure difference between the upper opening of the cavity and a vent to draw the uncured filler ink into the cavity.

[0053]

[0063] In some embodiments, the method includes using a brushing motion to remove excess hardened filler ink material from the upper and lower portions of the cavity.

[0054]

[0064] In some embodiments, embedding an electronic component at least partially within a cavity further includes forming a vent through a PI tape at a lower opening of the cavity, filling the cavity with a first amount of uncured filler ink such that the first amount of uncured filler ink only partially surrounds the electronic component, pre-curing the first amount of uncured filler ink in the cavity, peeling off the PI tape, filling the cavity with a second amount of uncured filler ink such that the second amount of uncured filler ink completes the filling of the cavity to surround the electronic component, and curing the pre-cured and uncured filler inks to form cured filler ink that at least partially surrounds the electronic component in the cavity.

[0055]

[0065] In some embodiments, the method includes filling a hollow portion of at least one metal via structure extending through a core with uncured filler ink, wherein the hollow portion of the at least one metal via structure is filled with uncured filler ink in a cavity filling ink filling process that is simultaneous with filling the cavity with a second amount of uncured filler ink.

[0056]

[0066] In some embodiments, the electronic component includes a deep trench capacitor.

[0057]

[0067] The technical advantage of Method 700 is that it can be used to form a substrate having embedded electronic components (e.g., deep trench capacitors) in which the embedded electronic components are rigidly mounted within the cavity of the substrate. The rigidity of the mounting is less dependent on the size or core thickness of the electronic components than conventional electronic component embedding processes using cavity filling.

[0058]

[0068] Figure 8 shows a side view of a package 800 according to an aspect of the present disclosure, including a surface mount substrate 802, an integrated device 803, and an integrated passive device 805 (e.g., a substrate having embedded electronic components in a core). The package 800 may be coupled to a printed circuit board (PCB) 806 via a plurality of solder interconnects 810. The PCB 806 may include at least one board dielectric layer 860 and a plurality of board interconnects 862.

[0059]

[0069] The surface mount substrate 802 includes at least one dielectric layer 820 (e.g., a substrate dielectric layer), a plurality of interconnection parts 822 (e.g., substrate interconnection parts), a solder resist layer 840, and a solder resist layer 842. The integrated device 803 may be coupled to the surface mount substrate 802 via a plurality of solder interconnection parts 830. The integrated device 803 may be coupled to the surface mount substrate 802 via a plurality of pillar interconnection parts 832 and a plurality of solder interconnection parts 830. The integrated passive device 805 may be coupled to the surface mount substrate 802 via a plurality of solder interconnection parts 850. The integrated passive device 805 may be coupled to the surface mount substrate 802 via a plurality of pillar interconnection parts 852 and a plurality of solder interconnection parts 850.

[0060]

[0070] The package (e.g., 800) may be implemented within a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 800) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 800) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 800) may be configured to transmit and receive signals with different frequencies and / or different communication protocols.

[0061]

[0071] Figure 9 shows an exemplary method 900 for providing or manufacturing a package including an integrated device comprising a package substrate having an electronic component in the core, according to an aspect of the present disclosure. In some implementations, the method 900 of Figure 9 can be used to provide or manufacture the package 800 of Figure 8 as described in the present disclosure. However, the method 900 can also be used to provide or manufacture any of the packages described in the present disclosure.

[0062]

[0072] Note that the method in Figure 9 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package including an integrated device with a package substrate. In some implementation configurations, the order of the processes may be changed or modified.

[0063]

[0073] This method provides a substrate (e.g., 802) (in 905). The substrate 802 may be provided by a supplier or manufactured by the supplier. The substrate 802 includes at least one dielectric layer 820 and a plurality of interconnection portions 822. The substrate 802 may include an embedded trace substrate (ETS). In some mounting configurations, at least one dielectric layer 820 may include a prepreg layer.

[0064]

[0074] This method (in 910) bonds at least one integrated device (e.g., 803) to a first surface of a substrate (e.g., 802). For example, the integrated device 803 may be bonded to the substrate 802 via a plurality of pillar interconnects 832 and a plurality of solder interconnects 830. The plurality of pillar interconnects 832 can be optional. The plurality of solder interconnects 830 are bonded to a plurality of interconnects 822. A solder reflow process may be used to bond the integrated device 803 to the plurality of interconnects via the plurality of solder interconnects 830.

[0065]

[0075] The method also involves bonding at least one integrated passive device (e.g., 805) to a first surface of a substrate (e.g., 802) (in 910). For example, the integrated passive device 805 may be bonded to the substrate 802 via a plurality of pillar interconnects 852 and a plurality of solder interconnects 850. The plurality of pillar interconnects 852 can be optional. The plurality of solder interconnects 850 are bonded to a plurality of interconnects 822. A solder reflow process may be used to bond the integrated passive device 805 to the plurality of interconnects via the plurality of solder interconnects 850.

[0066]

[0076] This method bonds a plurality of solder interconnects (e.g., 810) (in 915) to a second surface of a substrate (e.g., 802). A solder reflow process may be used to bond the plurality of solder interconnects 810 to the substrate.

[0067]

[0077] Figure 10 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposer packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1002, a laptop computer device 1004, a stationary terminal device 1006, a wearable device 1008, or an automobile vehicle 1010 may include device 1000 as described herein. Device 1000 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1002, 1004, 1006, and 1008, and vehicle 1010 shown in Figure 10 are merely examples. Device 1000 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other devices that store or take in data or computer instructions, or any combination thereof.

[0068]

[0078] Implementation examples will be described in the following numbered embodiments.

[0069]

[0079] Embodiment 1. An electronic device comprising a substrate, the substrate comprising: a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component at least partially surrounded within the cavity by cured hole-filling ink, the electronic component including an upper plane having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0070]

[0080] Embodiment 2. The electronic device according to Embodiment 1, wherein the electronic components occupy at least 66% of the cavity.

[0071]

[0081] Embodiment 3. An electronic device according to Embodiment 1 or 2, wherein the core includes a plurality of inner side walls defining a cavity, the electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the cavity, and the cured hole-filling ink fills the area between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

[0072]

[0082] Embodiment 4. An electronic device according to any one of Embodiments 1 to 3, further comprising a lower dielectric layer disposed above the lower plane of the core and below the lower plane of an electronic component, wherein a cured hole-filling ink fills the region between the lower plane of the electronic component and the lower dielectric layer.

[0073]

[0083] Embodiment 5. An electronic device according to any one of Embodiments 1 to 4, further comprising one or more metal vias extending between the upper plane of the core and the lower plane of the core.

[0074]

[0084] Embodiment 6. The electronic device according to Embodiment 5, wherein the core has a thickness of 800 micrometers or less.

[0075]

[0085] Embodiment 7. The electronic device according to Embodiment 5 or 6, wherein at least one of the one or more metal vias comprises a metal via structure having a hollow cavity, and the hollow cavity of the metal via structure is filled with a cured hole-filling ink.

[0076]

[0086] Embodiment 8. The electronic device according to Embodiment 7, wherein the core has a thickness exceeding 800 micrometers.

[0077]

[0087] Embodiment 9. An electronic device according to any one of Embodiments 1 to 8, further comprising an electronic circuit package mounted on one or more upper metal terminals of an upper metallization structure.

[0078]

[0088] Embodiment 10. An electronic device according to any one of Embodiments 1 to 9, wherein the electronic component includes a deep trench capacitor.

[0079]

[0089] Embodiment 11. An electronic device according to any one of Embodiments 1 to 10, wherein the electronic device includes at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in a motor vehicle.

[0080]

[0090] Embodiment 12. A substrate comprising: a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component at least partially surrounded within the cavity by cured hole-filling ink, the electronic component including an upper plane having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0081]

[0091] Embodiment 13. The substrate according to Embodiment 12, wherein electronic components occupy at least 66% of the cavity.

[0082]

[0092] Embodiment 14. The substrate according to Embodiment 12 or 13, wherein the core includes a plurality of inner side walls defining a cavity, the electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the cavity, and the cured hole-filling ink fills the area between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

[0083]

[0093] Embodiment 15. A substrate according to any one of Embodiments 12 to 14, further comprising a lower dielectric layer disposed above the lower plane of the core and below the lower plane of an electronic component, wherein a cured hole-filling ink fills the region between the lower plane of the electronic component and the lower dielectric layer.

[0084]

[0094] Embodiment 16. A substrate according to any one of Embodiments 12 to 15, comprising one or more metal vias extending between the upper plane of the core and the lower plane of the core.

[0085]

[0095] Embodiment 17. The substrate according to Embodiment 16, wherein at least one of the metal vias comprises a metal via structure having a hollow cavity, and the hollow cavity of the metal via structure is filled with a cured hole-filling ink.

[0086]

[0096] Embodiment 18. The substrate according to Embodiment 17, wherein the core has a thickness exceeding 700 micrometers.

[0087]

[0097] Embodiment 19. A substrate according to any one of embodiments 12 to 18, further comprising an electronic circuit package mounted on one or more upper metal terminals of the upper metallization structure.

[0088]

[0098] Embodiment 20. A substrate according to any one of Embodiments 12 to 19, wherein the electronic component includes a deep trench capacitor.

[0089]

[0099] Embodiment 21. A method for manufacturing a substrate, comprising: forming a cavity in a core having a first plane and a second plane, the cavity extending between the first plane and the second plane of the core; embedding an electronic component at least partially within the cavity, the electronic component being at least partially surrounded within the cavity by a cured filler ink, the electronic component including a plane having one or more electronic component terminals; and forming a metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the metallization structure.

[0090]

[0100] Embodiment 22. The method according to Embodiment 21, wherein embedding an electronic component at least partially within a cavity includes covering the lower opening of the cavity with polyimide (PI) tape, and inserting the electronic component into the cavity such that one or more electronic component terminals on the plane of the electronic component are in contact with the upper surface of the PI tape.

[0091]

[0101] Embodiment 23. The method according to Embodiment 22, further comprising: embedding an electronic component in the cavity to form a vent through the PI tape at the lower opening of the cavity; filling the cavity so as to surround the electronic component with uncured filler ink; precuring the uncured filler ink in the cavity to provide precured filler ink in the cavity; peeling off the PI tape; and curing the precured filler ink to provide cured filler ink for mounting the electronic component in the cavity.

[0092]

[0102] Embodiment 24. The method according to Embodiment 23, wherein filling the cavity to surround an electronic component with uncured filler ink includes dispensing uncured filler ink through an upper opening of the cavity and providing a pressure difference between the upper opening of the cavity and a vent to draw the uncured filler ink into the cavity.

[0093]

[0103] Embodiment 25. The method according to Embodiment 23 or 24, further comprising using a brushing motion to remove excess hardened filler ink material from the upper and lower portions of the cavity.

[0094]

[0104] Embodiment 26. The method according to any one of Embodiments 22 to 25, further comprising: at least partially embedding an electronic component in a cavity to form a vent through the PI tape at the lower opening of the cavity; filling the cavity with a first amount of uncured filler ink such that the first amount of uncured filler ink only partially surrounds the electronic component; pre-curing the first amount of uncured filler ink in the cavity; peeling off the PI tape; filling the cavity with a second amount of uncured filler ink such that the second amount of uncured filler ink completes the filling of the cavity to surround the electronic component; and curing the pre-cured filler ink and the uncured filler ink to form cured filler ink that at least partially surrounds the electronic component in the cavity.

[0095]

[0105] Embodiment 27. The method according to Embodiment 26, further comprising filling a hollow portion of at least one metal via structure extending through a core with uncured filler ink, wherein the hollow portion of the at least one metal via structure is filled with uncured filler ink in a filler ink filling process that is simultaneous with filling the cavity with a second amount of uncured filler ink.

[0096]

[0106] Embodiment 28. The method according to any one of Embodiments 21 to 27, wherein the electronic component includes a deep trench capacitor.

[0097]

[0107] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0098]

[0108] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be illustrative. In some implementations, various components and / or parts in the figures may be optional.

[0099]

[0109] The term “exemplary” is used herein to mean “to serve as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation described herein. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even if they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can propagate between them. Two electrically coupled objects may or may not propagate an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any number above fourth) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may also be the first, second, third, or fourth component. The term “encapsulating” means that an object can partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located on top of a component located at the bottom. A top component may be considered a bottom component, and vice versa.As described in this disclosure, a first component positioned "over" a second component may mean that the first component is positioned above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be positioned on (e.g., above) a first surface of the second component, and the third component may be positioned on (e.g., below) a second surface of the second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being positioned on another, the term “on” as used in this application may be used to mean a component that is on and / or inside another component (e.g., on the surface of the component or embedded within the component). Therefore, for example, a first component on a second component may mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A first component located "in" a second component may be partially located within the second component or completely located within the second component. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean a range of 10 percent of "value X". For example, a value of "about 1" or "approximately 1" means a value in the range of 0.9 to 1.1.

[0100]

[0110] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes can be used to form interconnects.

[0101]

[0111] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0102]

[0112] In the detailed description above, it will be seen that in the examples, different features are grouped together. This manner of disclosure should not be understood as an intention that exemplary embodiments have more features than are explicitly stated within each embodiment. Rather, the various embodiments of this disclosure may contain fewer features than all the features of the individual exemplary embodiments disclosed. Accordingly, the following embodiments should be considered incorporated into the description, and each embodiment may be valid on its own as a distinct example. Each dependent embodiment may refer within the embodiment to a specific combination with one of the other embodiments, but the embodiments (singular or plural) of that dependent embodiment are not limited to that specific combination. It will be understood that other exemplary embodiments may also include combinations of dependent embodiments (singular or plural) with the subject matter of any other dependent embodiment or independent embodiment, or any combination of features with other dependent embodiments and independent embodiments. The various embodiments disclosed herein explicitly include certain combinations (e.g., contradictory embodiments such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if an aspect is not directly dependent on an independent aspect, it is intended that aspects of that aspect may be included in any other independent aspect.

[0103]

[0113] While the above disclosures represent exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made to this Specified without departing from the scope of the Disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, elements of the Disclosure may be described or claimed in the singular, but the plural is intended unless a limitation to the singular is explicitly stated.

Claims

1. It is an electronic device, It is a substrate, A core having an upper plane and a lower plane, wherein the core includes a cavity extending between the upper plane and the lower plane of the core, An electronic component at least partially disposed within the cavity, wherein the electronic component is at least partially surrounded within the cavity by cured filler ink, and the electronic component includes an upper plane having one or more electronic component terminals. The upper metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure, An electronic device comprising a substrate.

2. The electronic device according to claim 1, wherein the electronic component occupies at least 66% of the cavity.

3. The core includes a plurality of inner side walls that define the cavity, The electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the cavity, The electronic device according to claim 1, wherein the cured hole-filling ink fills the region between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

4. The electronic device according to claim 1, further comprising a lower dielectric layer disposed above the lower plane of the core and below the lower plane of the electronic component, wherein the cured hole-filling ink fills the region between the lower plane of the electronic component and the lower dielectric layer.

5. The electronic device according to claim 1, further comprising one or more metal vias extending between the upper plane of the core and the lower plane of the core.

6. The electronic device according to claim 5, wherein the core has a thickness of 800 micrometers or less.

7. The electronic device according to claim 5, wherein at least one of the one or more metal vias includes a metal via structure having a hollow cavity, and the hollow cavity of the metal via structure is filled with the cured hole-filling ink.

8. The electronic device according to claim 7, wherein the core has a thickness exceeding 800 micrometers.

9. The electronic device according to claim 1, further comprising an electronic circuit package mounted on one or more upper metal terminals of the upper metallization structure.

10. The electronic device according to claim 1, wherein the electronic component includes a deep trench capacitor.

11. The aforementioned electronic device The electronic device according to claim 1, comprising at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in an automobile vehicle.

12. It is a substrate, A core having an upper plane and a lower plane, wherein the core includes a cavity extending between the upper plane and the lower plane of the core, An electronic component at least partially disposed within the cavity, wherein the electronic component is at least partially surrounded within the cavity by cured filler ink, and the electronic component includes an upper plane having one or more electronic component terminals. The upper metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure, A substrate comprising the above.

13. The substrate according to claim 12, wherein the electronic component occupies at least 66% of the cavity.

14. The core includes a plurality of inner side walls that define the cavity, The electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the cavity, The substrate according to claim 12, wherein the cured hole-filling ink fills the region between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

15. The substrate according to claim 12, further comprising a lower dielectric layer disposed above the lower plane of the core and below the lower plane of the electronic component, wherein the cured hole-filling ink fills the region between the lower plane of the electronic component and the lower dielectric layer.

16. The aforementioned upper metallization structure The substrate according to claim 12, comprising one or more metal vias.

17. The substrate according to claim 16, wherein at least one of the one or more metal vias includes a metal via structure having a hollow cavity, and the hollow cavity of the metal via structure is filled with the cured hole-filling ink.

18. The substrate according to claim 17, wherein the core has a thickness exceeding 700 micrometers.

19. The substrate according to claim 12, further comprising an electronic circuit package mounted on one or more upper metal terminals of the upper metallization structure.

20. The substrate according to claim 12, wherein the electronic component includes a deep trench capacitor.

21. A method for manufacturing a circuit board, A cavity is formed within a core having a first plane and a second plane, the cavity extending between the first plane and the second plane of the core. An electronic component wherein the electronic component is at least partially surrounded within the cavity by a cured hole-filling ink, and the electronic component includes a plane having one or more electronic component terminals, thereby at least partially embedding the electronic component within the cavity. The metallization structure is formed to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the metallization structure, Methods that include...

22. Embedding the aforementioned electronic component at least partially within the cavity is The lower opening of the cavity is covered with polyimide (PI) tape, and Insert the electronic component into the cavity such that one or more of the electronic component terminals on the plane of the electronic component are in contact with the upper surface of the PI tape. The method according to claim 21, including the method described in claim 21.

23. Embedding the aforementioned electronic component at least partially within the cavity is To form a vent that penetrates the PI tape in the lower opening of the cavity, The cavity is filled with uncured filler ink so as to surround the electronic component. To provide pre-cured filler ink in the cavity, the uncured filler ink in the cavity is to be pre-cured. Removing the aforementioned PI tape, and To provide the cured filler ink for mounting the electronic components in the cavity, the pre-cured filler ink is cured. The method according to claim 22, further comprising:

24. The cavity is filled with the uncured filler ink so as to surround the electronic component. Dispensing the uncured filler ink through the upper opening of the cavity, and To draw the uncured filler ink into the cavity, a pressure difference is provided between the upper opening of the cavity and the vent. The method according to claim 23, including the method described in claim 23.

25. The method according to claim 23, further comprising using a brushing motion to remove excess hardened filler ink material from the upper and lower portions of the cavity.

26. Embedding the aforementioned electronic component at least partially within the cavity is To form a vent that penetrates the PI tape in the lower opening of the cavity, The cavity is filled with a first amount of uncured filler ink such that the first amount of uncured filler ink only partially surrounds the electronic component. Pre-curing the first amount of the uncured filler ink in the cavity, Remove the aforementioned PI tape. The cavity is filled with a second amount of the uncured filler ink, the second amount of the uncured filler ink completing the filling of the cavity to surround the electronic component, and To form the cured filler ink that at least partially surrounds the electronic component in the cavity, the pre-cured filler ink and the uncured filler ink are cured. The method according to claim 22, further comprising:

27. The method according to claim 26, further comprising filling the hollow portion of at least one metal via structure extending through the core with the uncured filler ink, wherein the hollow portion of the at least one metal via structure is filled with the uncured filler ink in a filler ink filling process that is simultaneous with the filling of the cavity with a second amount of the uncured filler ink.

28. The method according to claim 28, wherein the electronic component includes a deep trench capacitor.

Images