Thick-film single-layer capacitor

Abstract

A single-layer capacitor and a circuit board having such a capacitor are provided. The circuit board may include a circuit board substrate having a mounting surface and a single-layer capacitor at least partially embedded therein. The single-layer capacitor includes a first conductive layer formed on at least a portion of a first surface of the substrate and a second conductive layer formed on at least a portion of a second surface of the substrate. At least one of the first or second conductive layers has a thickness of at least about 5 microns. A method for forming a single-layer capacitor includes the steps of depositing a first conductive layer on at least a portion of a first surface of the substrate and depositing a second conductive layer on at least a portion of a second surface of the substrate. At least one of the first or second conductive layers has a thickness of at least about 5 microns.

Description

[Technical Field]

[0001] Related applications This application claims priority pursuant to U.S. Provisional Patent Application No. 63 / 501,159, filed on 10 May 2023, which is incorporated herein by reference. [Background technology]

[0002] Single-layer capacitors (SLCs) offer various advantages, such as temperature stability, generally high breakdown voltage, and low leakage current. However, SLCs are generally relatively thin, which can impair their usefulness in embedded applications, as embedded capacitors may require a thicker layer of metal to allow the formation of one or more vias for connection without touching or damaging the capacitor's substrate layer. Thus, there is a need for improved SLCs, such as those for embedded applications. [Overview of the project] [Means for solving the problem]

[0003] According to one embodiment of the present disclosure, the circuit board includes a circuit board substrate having a mounting surface and a single-layer capacitor at least partially embedded within the circuit board substrate. The single-layer capacitor includes a substrate having a first surface opposite to a second surface, a first conductive layer formed on at least a portion of the first surface, and a second conductive layer formed on at least a portion of the second surface. At least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

[0004] According to another embodiment of the present disclosure, a single-layer capacitor includes a substrate having a first surface and a second surface opposite to the first surface, a first conductive layer formed on at least a portion of the first surface of the substrate, and a second conductive layer formed on at least a portion of the second surface of the substrate. At least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

[0005] According to yet another embodiment of the present disclosure, a method for forming a single-layer capacitor includes the steps of depositing a first conductive layer on at least a portion of a first surface of a substrate, and depositing a second conductive layer on at least a portion of a second surface of the substrate, the second surface being opposite to the first surface. At least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

[0006] A complete and effective disclosure of the present invention, including its best mode, is directed to those skilled in the art and is more specifically provided in the remainder of the specification with reference to the accompanying drawings. [Brief explanation of the drawing]

[0007] [Figure 1] This is a side view of a capacitor according to an aspect of the present disclosure. [Figure 2A] This disclosure shows a circuit board including a fully embedded capacitor according to an aspect of this disclosure. [Figure 2B] Another circuit board including a fully embedded capacitor according to an aspect of this disclosure is shown. [Figure 2C] This disclosure shows a circuit board including a partially embedded capacitor according to an aspect of this disclosure. [Figure 3A] This is a perspective view of a capacitor according to the embodiments of this disclosure. [Figure 3B] Figure 3A is a side view of the capacitor. [Figure 4] This disclosure shows a circuit board including a fully embedded capacitor according to an aspect of this disclosure. [Figure 5]A flowchart of a method for forming a capacitor according to an aspect of the present disclosure. [Figure 6] A flowchart of another method for forming a capacitor according to an aspect of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0008] The repeated use of reference characters in this specification and drawings is intended to represent the same or similar features or elements of the present invention.

[0009] This discussion is merely an illustration of exemplary embodiments and is not intended to limit the broader aspects of the present invention, which should be understood by those skilled in the art to be embodied in exemplary configurations.

[0010] Generally speaking, the present invention relates to a single-layer capacitor having a relatively thick conductive layer or electrode. For example, a single-layer capacitor (referred to herein as SLC or "capacitor") can include a substrate, a first conductive layer formed on at least a portion of a first surface of the substrate, and a second conductive layer formed on at least a portion of a second surface of the substrate on the opposite side of the first surface of the substrate. At least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

[0011] Many embedded capacitor applications require a relatively thick conductive layer that allows for via drilling for connections without touching or damaging the substrate. A thick conductive layer can achieve the required thickness and protect the substrate. In some embodiments, one or more additional metal layers can be plated on top of the thick conductive layer or electrodes, which may make the single-layer capacitor a solderable component. A typical single-layer capacitor does not have a plated conductive layer or electrodes and is only wire-bondable or epoxy-connectable. A single-layer capacitor with a plated conductive layer or electrodes can be soldered to, for example, a circuit board, which may expand the possible applications of the single-layer capacitor.

[0012] In some embodiments, the conductive layer can be formed to be relatively thick. For example, such a conductive layer can be formed by adding a thick film strip of metal to a substrate. Such a metal may be present in a glass matrix and may include silver or copper. For example, such a strip can be printed and fired onto the capacitor, or deposited by immersing the capacitor in a liquid conductive material. Adding a thick film conductive layer in this manner may involve any method commonly known in the art (e.g., by a printing wheel for transferring a metal-containing paste onto a substrate).

[0013] The thick conductive layer may have an average thickness of at least about 5 μm or microns, for example, about 10 microns or more, about 20 microns or more, about 25 microns or more, about 35 microns or more, about 50 microns or more, or about 75 microns or more. The thick conductive layer may have an average thickness of about 500 microns or less, for example, about 300 microns or less, for example, about 200 microns or less, for example, about 150 microns or less, for example, about 100 microns or less, for example, about 80 microns or less. For example, the thick conductive layer may have an average thickness in the range of about 5 microns to about 150 microns, for example, in the range of about 10 microns to about 100 microns, for example, in the range of about 25 microns to about 75 microns. In one embodiment, the aforementioned thicknesses refer to the average thickness of the entire conductive portion or electrode of the capacitor added or deposited on one surface of the capacitor, which may include, for example, adding multiple layers of conductive material to achieve a first conductive layer or electrode on a first surface of a substrate and / or a second conductive layer or electrode on a second surface of a substrate. In another embodiment, the aforementioned thickness refers to the average thickness of a single layer of the conductive layer or electrode of the capacitor.

[0014] In some embodiments, a passivation layer can be deposited between the substrate and each conductive layer, thereby facilitating the plating of the conductive layer. More specifically, as mentioned above, many embedded capacitor applications require a relatively thick conductive layer that allows via drilling for connections without touching or damaging the substrate. With a dielectric protective layer (i.e., a passivation layer), it becomes possible to plate the wafer to obtain a conductive layer of the required thickness to protect the substrate. It may be possible to form a passivation layer on each of a pair of opposing surfaces of the substrate or wafer and then plate the conductive layer on each of the pair of opposing surfaces.

[0015] In addition, or instead, a plated conductive layer or electrodes can make a single-layer capacitor a solderable component. A typical single-layer capacitor does not have a plated conductive layer or electrodes and is only wire-bondable or epoxy-connectable. A single-layer capacitor with a plated conductive layer or electrodes can be soldered to, for example, a circuit board, which can expand the possible applications of single-layer capacitors.

[0016] In some embodiments, the substrate may be formed from a material having a dielectric constant (K) less than about 30, less than about 25 in some embodiments, less than about 20 in some embodiments, and less than about 15 in some embodiments, as determined according to ASTM D2520-13 at an operating temperature of 25°C and a frequency of 500 MHz. However, in other embodiments, higher frequencies and / or smaller parts can be achieved using a material having a dielectric constant higher than 30. For example, in such embodiments, the dielectric constant may range from about 30 to about 120 or more, from about 50 to about 100 in some embodiments, and from about 70 to about 90 in some embodiments, as determined according to ASTM D2520-13 at an operating temperature of 25°C and a frequency of 500 MHz.

[0017] In yet another embodiment, the substrate may be formed from a material having a relatively high dielectric constant (K), for example, from about 10 to about 40,000, from about 50 to about 30,000 in some embodiments, and from about 100 to about 20,000 in some embodiments.

[0018] The substrate can generally have a low thermal conductivity, for example, less than about 10 W / (m·K), less than about 5 W / (m·K) in some embodiments, less than about 3 W / (m·K) in some embodiments, less than about 2 W / (m·K) in some embodiments, less than about 1 W / (m·K) in some embodiments, and greater than about 0.1 W / (m·K) in some embodiments. However, in other embodiments, the substrate can have a thermal conductivity greater than 10 W / (m·K).

[0019] The substrate may include one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate may include sapphire, ruby, alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), aluminum oxide (Al2O3), boron nitride (BN), silicon (Si), silicon carbide (SiC), silica (SiO2), silicon nitride (Si3N4), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO2), mixtures thereof, oxides and / or nitrides of such materials, or any other suitable ceramic material. Additional examples of ceramic materials include barium titanate (BaTiO3), calcium titanate (CaTiO3), zinc oxide (ZnO), ceramics containing low-temperature fired glass, or other glass-bonding materials. Dielectric materials such as diamond and cubic boron arsenide may also be used.

[0020] Specific examples of types of high dielectric constant materials include, for example, NPO (COG) (up to about 100 maximally), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. The materials described above are explained by industry-recognized definitions, and some of these are standard classifications established by the Electronic Industries Alliance (EIA), and it should be understood that they should be recognized by those skilled in the art. For example, such materials can include ceramics. Such materials can include perovskites such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), bismuth sodium titanate, etc. In a specific embodiment, for example, barium strontium titanate (「BSTO」) of the formula Ba x Sr 1-x TiO3 can be used, where x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites are, for example, Ba x Ca 1-x TiO3 where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6, Pb x Zr 1-x TiO3 (「PZT」), lead lanthanum zirconate titanate (「PLZT」), lead titanate (PbTiO3), barium calcium zirconate titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3) and NaBa2(NbO3)5KHb2PO4 can be included. Further additional complex perovskites can include A[B1 1 / 3 B2 2 / 3 O3 materials, where A is Ba x Sr 1-x(x can be a value between 0 and 1), B1 is Mg y Zn 1-y (y can be a value between 0 and 1), B2 is Ta z Nb 1-z (z can be a value from 0 to 1). In a particular embodiment, the dielectric material may include a titanate.

[0021] As used herein, "formed on top of" may refer to a layer being in direct contact with another layer. However, an intermediate layer can also be formed between them. In addition, when used in reference to the bottom surface, "formed on top of" can be applied to the outer surface of the part. Therefore, a layer "formed on top of" the bottom surface may be closer to the outside of the part than the layer on which it is formed.

[0022] The passivation layer of the capacitor can be formed on at least a portion of the surface of the substrate. The passivation layer can cover and protect the substrate from deposition processes (e.g., electroplating) used to form a conductive layer on the substrate surface. The passivation layer can be formed from a variety of suitable materials, including polymer materials. For example, in some embodiments, the passivation layer is or can include polyimide. In some embodiments, the passivation layer can include at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, or glass. The substrate and / or passivation layer can be formed from a variety of inorganic materials, such as glass, ceramic, or glass-ceramic mixtures. As described above, the substrate can include silicon oxynitride, silicon oxide, silicon, alumina, sapphire, and / or other suitable materials.

[0023] In some embodiments, the passivation layer can be formed by depositing a paste (e.g., glass paste, glass ceramic paste, etc.) followed by a firing step. However, the passivation layer can be formed using any suitable process.

[0024] The first conductive layer of the capacitor can be formed on at least a portion of the passivation layer. The first conductive layer does not need to be in direct contact with the substrate and / or directly electrically connected. In one exemplary configuration, the conductive material forming the first conductive layer can be electroplated onto the passivation layer. Other methods for depositing the conductive material can also be used, as will be recognized by those skilled in the art.

[0025] The capacitor may also include an additional, or second, conductive layer. In some embodiments, the second conductive layer may be formed on a second surface of the substrate, opposite to the first surface of the substrate (on which the passivation layer and the first conductive layer are formed). Furthermore, in some embodiments, the second passivation layer may be formed on at least a portion of the second surface of the substrate, and the second conductive layer may be formed on the second passivation layer so that the second passivation layer is positioned between the second conductive layer and the substrate. As described above with respect to the passivation layer formed between the first conductive layer and the substrate, the second passivation layer may be formed by depositing a paste (e.g., glass paste, glass ceramic paste, etc.) followed by a firing step, but the second passivation layer can be formed using any suitable process. The second passivation layer may also be formed from a variety of suitable materials, including polymer materials. For example, in some embodiments, the second passivation layer may be or include polyimide and / or at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, glass, ceramic, or glass-ceramic mixture.

[0026] The conductive layer can be formed from any of the various different metals known in the art. The conductive or electrode layer can be made from a metal such as a conductive metal. Conductive materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. The conductive layer or electrode can also be made from low-resistance materials such as silver, copper, gold, aluminum, palladium, etc. In a particular embodiment, the conductive layer may include nickel or an alloy thereof.

[0027] One or more protective layers can be formed on the substrate and / or passivation layer. For example, one or more protective layers can be formed on the first surface and / or second surface of the substrate. As another example, one or more protective layers can be formed on a first passivation layer (formed on the first surface of the substrate) such that the first conductive layer is formed on one or more protective layers. In some embodiments, similarly, one or more protective layers can be formed on a second passivation layer, for example, between the second passivation layer and the second conductive layer. Example materials for the protective layers include benzocyclobutene (BCB), polyimide, silicon oxynitride, alumina (Al2O3), silica (SiO2), silicon nitride (Si3N4), epoxy, glass, or other suitable materials.

[0028] Thin film layers of a capacitor can be formed using various thin-film techniques. For example, one or more of a first conductive layer, a second conductive layer, a first passivation layer, and a second passivation layer can be the thin film layers of a capacitor. Examples of such techniques that can be used include chemical deposition (e.g., chemical deposition), PECVD (plasma-excited chemical deposition) processing, physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin-film elements. Additional examples include any suitable patterning technique (e.g., photolithography), etching, and any other suitable subtractive technique for forming thin-film elements.

[0029] The thin film layer can have a variety of thicknesses. For example, the thin film layer can have a thickness ranging from about 0.001 micrometers (microns) to about 100 microns in some embodiments, from about 0.0375 microns to about 40 microns in some embodiments, from about 0.1 microns to about 30 microns in some embodiments, from about 0.2 microns to about 20 microns in some embodiments, and from about 0.4 microns to about 10 microns in some embodiments. For example, in some embodiments, the resistive layer can have a thickness of less than about 10 microns, less than about 8 microns in some embodiments, less than about 6 microns in some embodiments, and less than about 4 microns in some embodiments.

[0030] The conductive layer can be plated on each passivation layer. For example, if a first passivation layer is formed on a first surface of the substrate, the first conductive layer can be plated on the first passivation layer. In embodiments that also include a second passivation layer formed on a second surface of the substrate, the second conductive layer can be plated on the second passivation layer.

[0031] Conductive layers can be formed such that each conductive layer is a thin-film plating of a metal. Such thin-film plating can be formed by depositing a conductive material, such as a conductive metal, onto a passivation layer. Plated conductive layers or electrodes can be formed by techniques known in the art, such as electroless plating, electroplating, or a combination thereof. When forming electrodes using multiple layers, the electrodes may include electroplated layers and electroless plating layers. For example, electroless plating can be used first to deposit the initial layers of material. The plating technique can then be switched to an electrochemical plating system, which allows for faster accumulation of the material. When forming plated conductive layers or electrodes by any of the plating methods, at least a portion of the capacitor is exposed to the plating solution. By exposure, in one embodiment, the capacitor can be immersed in the plating solution.

[0032] The plating solution used in the plating process may contain conductive materials such as conductive metals. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution so that the plating layer and external terminals contain nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution so that the plating layer and external terminals contain copper. In addition, it should be understood that the plating solution may contain other additives as are commonly known in the art. For example, the additives may include other organic additives and media that can assist the plating process. In addition, additives may be used to use the plating solution at a desired pH level. In one embodiment, an additive that reduces resistance may be used in the solution to aid in complete plating coating and adhesion between the plating material and the capacitor. The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined amount of time. The exposure time is not necessarily limited, but can be a sufficient amount of time so that enough plating material can be deposited to form a plating layer. In this regard, the time should be sufficient to form a continuous layer on each surface of the substrate.

[0033] The difference between electroplating and electroless plating is that electroplating uses an electrical bias, for example, by using an external power supply. Electroplating solutions can typically be exposed to high current densities, such as 10–15 amperes / square foot (rated at 9.4 volts). Connections can be formed by a negative connection to a capacitor where the plating terminals are to be formed, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to the opposite polarity to the plating solution. Using this method, the conductive material in the plating solution is attracted to the metal already present on the substrate. For example, as mentioned above, an initial amount of metal can be deposited on the substrate using an electroless process, and the remaining amount of metal for the conductive layer can be deposited using electroplating.

[0034] Various pretreatment steps can be used before immersing or exposing the capacitor to the plating solution. Such steps can be carried out for a variety of purposes, including catalyzing, accelerating, and / or improving the adhesion between the plating material and the initial metal deposit. In addition, an initial cleaning step can be used before plating or any other pretreatment step. This step can be used to remove any oxide buildup that forms on the substrate and / or the initial metal deposit. Cleaning of the component can be performed by complete immersion in a pre-cleaning tank, such as one containing an acidic cleaning agent. In one embodiment, the exposure can be for a predetermined time, for example, on the order of about 10 minutes. Alternatively, cleaning can be performed by chemical polishing or a harperizing step.

[0035] In addition, a step to activate the metal can be performed to promote the deposition of conductive materials. Activation can be achieved by immersion in a palladium salt, photopatterned palladium organometallic precursors (via a mask or laser), screen printing or inkjet deposition of palladium compounds, or electrophoretic palladium deposition. It should be understood that palladium-based activation is disclosed here only as an example of an activating solution that often works well for activating exposed areas formed of nickel or its alloys. However, it should be understood that other activating solutions may be available and are therefore not necessarily limited. Also, an activating dopant can be introduced into the conductive material instead of, or in addition to, the aforementioned activation step. For example, when the conductive layer contains nickel and the activating dopant contains palladium, a palladium dopant can be introduced into the nickel ink or composition forming the conductive layer. Doing so eliminates the palladium activation step. It should be further understood that some of the above activation methods, such as organometallic precursors, are also suitable for co-deposition of glass-forming agents to increase the adhesion of capacitors to the generally ceramic body. When the activation step is taken as described above, traces of the activating material may often remain on the exposed conductive areas before and after plating.

[0036] In addition, post-plating treatment steps can be used as desired or as needed. Such steps can be carried out for a variety of purposes, including improving and / or enhancing the adhesion of materials. For example, a heating (or annealing) step can be used after the plating step. Such heating can be carried out by baking, laser irradiation, UV exposure, microwave exposure, arc welding, etc.

[0037] Therefore, as described above, the conductive layer used in a capacitor may contain at least one plating layer. In one embodiment, the conductive layer may contain only one plating layer. However, it should be understood that the conductive layer may contain multiple plating layers. For example, the conductive layer or electrode may contain a first plating layer and a second plating layer. In addition, the conductive layer or electrode may also contain a third plating layer. Furthermore, the materials of these plating layers may be any of the aforementioned and those commonly known in the art. For example, one plating layer, such as the first plating layer, may contain copper or an alloy thereof. Another plating layer, such as the second plating layer, may contain nickel or an alloy thereof. Alternatively, another plating layer, such as the second plating layer, may contain copper or an alloy thereof. Another plating layer, such as the third plating layer, may contain tin, lead, gold, or a combination of alloys. Alternatively, the first plating layer may contain nickel, followed by a tin or gold plating layer. In another embodiment, a first copper plating layer may be formed, followed by a nickel layer.

[0038] In one embodiment, the first or initial plating layer may be a conductive metal (e.g., copper). This region can then be covered with a second layer containing a resistant polymer material for sealing. This region can then be polished to selectively remove the resistant polymer material, and then re-plated with a third layer containing a conductive metal material (e.g., copper). The aforementioned second layer above the initial plating layer may correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel or copper) on top of the initial electroless or electroplated layer (e.g., plated copper). Other exemplary materials for the aforementioned solder barrier layer include nickel-phosphorus, gold, and silver. The aforementioned third layer on the solder barrier layer corresponds in some embodiments to a conductive layer such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder. In addition, a layer of metal plating can be formed, followed by an electroplating step to provide a resistance alloy or a higher resistance metal alloy coating, such as an electroless Ni-P alloy, on such metal plating. However, it should be understood that any metal coating is possible, as those skilled in the art will understand from the full disclosure herein. It should be understood that any of the aforementioned steps can be carried out as a bulk process, such as barrel plating, fluidized bed plating, and / or flow-through plating finishing processes, all of which are commonly known in the art. Such bulk processes allow for the processing of multiple parts at once and provide an efficient and rapid electrode deposition process. This is particularly advantageous compared to conventional electrode deposition methods, such as printing of thick conductive or electrode layers, which require processing of individual parts.

[0039] In some embodiments, the capacitor can be at least partially embedded in a circuit board, such as a printed circuit board (PCB). For example, the capacitor can be positioned in an opening or cavity in the circuit board such that at least a portion of the capacitor is enclosed by the circuit board. A portion of the capacitor may protrude from or extend upward from the mounting surface of the circuit board, or at most, the outermost surface of the capacitor may be coplanar with the mounting surface of the circuit board, while the rest of the capacitor is within the opening or cavity and enclosed by the circuit board. In at least some embodiments, the capacitor can be electrically connected to the circuit board, for example, through vias or other conductive paths extending from the capacitor to a conductive area of ​​the circuit board (e.g., a conductive layer, termination, or port) on the circuit board.

[0040] Figure 1 is a side view of a single-layer capacitor 100 according to an aspect of the present disclosure. The single-layer capacitor 100 may also be referred to herein as SLC100 or capacitor 100. As shown in Figure 1, the capacitor 100 may include a substrate 102 having a first surface 104 and a second surface 106 opposite the first surface 104 along the height or thickness direction Z. The substrate 102 may be formed from a dielectric material. In some embodiments, the dielectric material may have a relatively low dielectric constant (K), while in other embodiments, the dielectric material may have a relatively high dielectric constant.

[0041] The capacitor 100 may include a first conductive layer 108 formed on at least a portion of a first surface 104 of the substrate 102, and a second conductive layer 110 formed on at least a portion of a second surface 106 of the substrate 102. In some embodiments, the first conductive layer 108 is a thick conductive layer and has a first thickness t1 of at least about 5 microns. For example, the first conductive layer 108 may have a first thickness t1 of at least about 10 microns, a first thickness t1 of at least about 12 microns, a first thickness t1 of at least about 20 microns, a first thickness t1 of at least about 40 microns, a first thickness t1 of at least about 80 microns, a first thickness t1 of at least about 100 microns, a first thickness t1 of at least about 250 microns, or a first thickness t1 of at least about 500 microns. In some embodiments, the first thickness t1 can be in the range of about 5 microns to about 150 microns, about 10 microns to about 100 microns, or about 25 microns to about 75 microns. The first conductive layer 108 may also have other thicknesses.

[0042] Similarly, in at least some embodiments, the second conductive layer 110 is a thick conductive layer having a second thickness t2 of at least about 5 microns. For example, the second conductive layer 110 may have a second thickness t2 of at least about 10 microns, at least about 12 microns, at least about 20 microns, at least about 40 microns, at least about 80 microns, at least about 100 microns, at least about 250 microns, or at least about 500 microns. In some embodiments, the second thickness t2 may be in the range of about 5 to about 150 microns, about 10 to about 100 microns, or about 25 to about 75 microns. The second conductive layer 110 may also have other thicknesses.

[0043] Furthermore, in at least some embodiments, the substrate thickness tsub It can be at least about 50 microns. For example, substrate thickness t sub This can be at least about 75 microns, at least about 100 microns, at least about 150 microns, at least about 250 microns, at least about 500 microns, or at least about 1000 microns. In some embodiments, the substrate thickness t sub The ratio of to the first thickness t1 can be at least 2, for example, at least 2, at least 2.5, at least 3, or at least 4. Similarly, in some embodiments, the substrate thickness t sub The ratio of the second thickness t2 can be at least 2, for example, at least 2, at least 2.5, at least 3, or at least 4.

[0044] Furthermore, referring to Figure 1, the substrate thickness t is along the height or thickness direction Z. sub It can have a substrate thickness t. In some embodiments, the substrate thickness t sub The substrate thickness t can be greater than at least one thickness t1, t2 of the first conductive layer 108 or the second conductive layer 110. In other embodiments, the substrate thickness t sub The substrate thickness t can be greater than the sum of the thicknesses t1 and t2 of the first conductive layer 108 and the second conductive layer 110. In yet another embodiment, the substrate thickness t sub The thickness of at least one of the first conductive layer 108 or the second conductive layer 110 can be less than t1, t2.

[0045] It will be understood that the first conductive layer 108 and the second conductive layer 110 can be formed from any suitable conductive material as described elsewhere in this specification, and the substrate 102 can be formed from any suitable dielectric material as described elsewhere in this specification.

[0046] In some embodiments, the first conductive layer 108 and / or the second conductive layer 110 can extend across the entire respective surfaces 104, 106 on which each layer 108, 110 is formed. For example, the first conductive layer 108 can extend to each edge defining the first surface 104 of the substrate 102, and / or the second conductive layer 110 can extend to each edge defining the second surface 106 of the substrate 102. Alternatively, as shown in Figure 1, for example, the first conductive layer 108 and / or the second conductive layer 110 may be offset from one or more edges of the respective surfaces 104, 106.

[0047] Next, referring to Figures 2A to 2C, side views of a circuit board 250 in which a single-layer capacitor 100 according to an embodiment of the present disclosure is at least partially embedded are shown. The circuit board 250 may include a circuit board substrate 252 having a mounting surface 254. In the embodiments shown in Figures 2A and 2B, the capacitor 100 is fully embedded in the circuit board substrate 252. More specifically, in the embodiment of Figure 2A, the capacitor 100 is fully embedded in the circuit board substrate 252 such that the substrate 102, the first conductive layer 108, and the second conductive layer 110 of the capacitor 100 are each positioned below the mounting surface 254 of the circuit board 250 along the height or thickness direction Z. In the embodiment of Figure 2B, the capacitor 100 is fully embedded in the circuit board substrate 252 such that the first conductive layer 108 of the capacitor 100 is coplanar with the mounting surface 254 of the circuit board 250. For example, the outermost surface of the first conductive layer 108 (i.e., the surface of the first conductive layer 108 opposite the first surface 104 of the substrate 102) can be coplanar with the mounting surface 254 of the circuit board 250, and since no portion of the capacitor 100 extends above, beyond, or outside the circuit board 250, the capacitor 100 is still considered to be fully embedded in the circuit board 250. In other embodiments, a portion of the capacitor 100 is located within the circuit board 250, and the capacitor 100 can be partially embedded within the circuit board substrate 252 such that the rest of the capacitor 100, such as the first conductive layer 108 and / or at least a portion of the substrate 102 of the capacitor 100, protrudes from or outside the circuit board 250, for example, along the height or thickness direction Z. For example, in the embodiment shown in Figure 2C, the capacitor 100 is partially embedded in the circuit board substrate 252 such that the first conductive layer 108 extends above the mounting surface 254 of the circuit board 250.

[0048] As further shown in Figures 2A to 2C, the capacitor 100 can be electrically connected to the conductive layer 256 of the circuit board 250. For example, as shown in Figure 2A, a via 258 can extend from the first conductive layer 108 of the capacitor 100 toward the mounting surface 254 of the circuit board 250 and connect to the conductive layer 256 formed on the mounting surface 254. In this way, the via 258 of the circuit board 250 can electrically connect the capacitor 100 to the conductive layer 256 of the circuit board 250.

[0049] Referring to Figures 2B and 2C, in another embodiment, the conductive path 260 can electrically connect the capacitor 100 and the conductive layer 256 of the circuit board 250. As shown in Figures 2B and 2C, the conductive path 260 extends from the first conductive layer 108 of the capacitor 100 to the conductive layer 256 of the circuit board 250. In this way, the conductive path 260 of the circuit board 250 can electrically connect the capacitor 100 and the conductive layer 256 of the circuit board 250.

[0050] Next, we will move on to Figures 3A, 3B, and 4 to describe other embodiments of the embeddable single-layer capacitor. Figures 3A and 3B show a perspective view and a side view of the single-layer capacitor 300, respectively. Similar to the capacitor 100 described above, the capacitor 300 includes a substrate 302 having a first surface 304 and a second surface 306 located opposite the first surface 304 along the height or thickness direction Z. The capacitor 300 also includes a first conductive layer 308 formed on at least a portion of the first surface 304 of the substrate 302 and a second conductive layer 310 formed on at least a portion of the second surface 306 of the substrate 302.

[0051] However, unlike capacitor 100, capacitor 300 shown in Figures 3A and 3B also includes a first passivation layer 312 and a second passivation layer 314. The first passivation layer 312 is formed on at least a portion of the first surface 304 of the substrate 302, so that the first passivation layer 312 is positioned between the substrate 302 and the first conductive layer 308. The second passivation layer 314 is formed on at least a portion of the second surface 306 of the substrate 302, so that the second passivation layer 314 is positioned between the substrate 302 and the second conductive layer 310. The passivation layers 312 and 314 facilitate the formation of the conductive layers 308 and 310 using plating methods (such as electroless plating and electrolytic plating), thereby increasing the usefulness or functionality of the single-layer capacitor.

[0052] In some embodiments, the first passivation layer 312 and / or the second passivation layer 314 can extend over the entire respective surfaces 304, 306 on which the respective passivation layers 312, 314 are formed. For example, the first passivation layer 312 can extend to each edge defining the first surface 304 of the substrate 302, and / or the second passivation layer 314 can extend to each edge defining the second surface 306 of the substrate 302. Alternatively, the first passivation layer 312 and / or the second passivation layer 314 may be offset from one or more edges of the respective surfaces 304, 306, as shown, for example, in Figures 3A and 3B.

[0053] Similarly, the first conductive layer 308 may extend over the entire first passivation layer 312, for example, to each edge of the first passivation layer 312, and / or the second conductive layer 310 may extend over the entire second passivation layer 314, for example, to each edge of the second passivation layer 314. In other embodiments, the first conductive layer 308 and / or the second conductive layer 310 may be offset from one or more edges of the respective passivation layers 312, 314 on which the respective conductive layers 308, 310 are formed.

[0054] As shown in Figure 3B, the first conductive layer 308 may have a first thickness t1 along the height or thickness direction Z, and the second conductive layer 310 may have a second thickness t2 along the height or thickness direction Z. The first passivation layer 312 may have a first passivation thickness t along the height or thickness direction Z. p1 The second passivation layer 314 may have a second passivation thickness t along the height or thickness direction Z. p2 It can have the following characteristics. Similarly, the substrate 302 has a substrate thickness t along the height or thickness direction Z. sub It can have.

[0055] In some embodiments, the first conductive layer 308 and the second conductive layer 310 may have approximately equal thicknesses t1 and t2, while in other embodiments, the first thickness t1 of the first conductive layer 308 or the second thickness t2 of the second conductive layer 310 may be greater than the other thickness t1 and t2. Similarly, in various embodiments, the first passivation layer 312 and the second passivation layer 314 may have approximately equal passivation thickness t p1 , t p2 It can have, or different passivation thickness t p1 , t p2It may have the following: In some embodiments, the first thickness t1 of the first conductive layer 308 and / or the second thickness t2 of the second conductive layer 310 is the first passivation thickness t p1 and the second passivation thickness t p2 It can be made larger than that. In other embodiments, the first passivation thickness t p1 or second passivation thickness t p2 At least one of these can be greater than at least one of the first thickness t1 or the second thickness t2.

[0056] Furthermore, substrate thickness t sub The substrate thickness t can be greater than the respective thickness of each individual layer 308, 310, 312, and 314, and in some embodiments, the substrate thickness t sub This can be greater than or equal to the sum of the thicknesses of each individual layer 308, 310, 312, and 314. However, in other embodiments, at least one of the first conductive layer 308, the second conductive layer 310, the first passivation layer 312, or the second passivation layer 314 is greater than or equal to the substrate thickness t sub It can have a thickness greater than that, and in yet another embodiment, the substrate thickness t sub This can be less than the sum of the thicknesses of each individual layer 308, 310, 312, and 314. For example, in some embodiments, the substrate thickness t sub The ratio of the substrate thickness t to the sum of the thicknesses of each individual layer 308, 310, 312, and 314 can be at least about 1, for example, at least about 1.5, at least about 2, at least about 2.5, at least about 3, or at least about 4. However, in other embodiments, the substrate thickness t sub The ratio of the thickness of each individual layer 308, 310, 312, and 314 to the sum of their respective thicknesses can be approximately 1 or less, for example, approximately 0.9 or less, approximately 0.8 or less, approximately 0.75 or less, or approximately 0.7 or less.

[0057] In some embodiments, the first passivation thickness t p1and / or second passivation thickness t p2 This can be at least about 50 angstroms, for example, at least about 75 angstroms, at least about 100 angstroms, or at least about 150 angstroms. Furthermore, the substrate thickness t sub This can be at least about 50 microns, for example, at least about 75 microns, at least about 100 microns, at least about 150 microns, at least about 250 microns, at least about 500 microns, or at least about 1000 microns.

[0058] Referring next to Figure 4, a side view is provided of a circuit board 450 in which a single-layer capacitor 300 according to an embodiment of the present invention is at least partially embedded. The circuit board 450 may include a circuit board substrate 452 having a mounting surface 454. In the embodiment shown in Figure 4, the capacitor 300 is fully embedded in the circuit board substrate 452. More specifically, in the embodiment of Figure 4, the capacitor 300 is fully embedded in the circuit board 452 such that the substrate 302 of the capacitor 300, the first conductive layer 308, the first passivation layer 312, the second passivation layer 314, and the second conductive layer 310 are each positioned below the mounting surface 454 of the circuit board 450 along the height or thickness direction Z. Although not shown herein, it will be understood that in other embodiments, the capacitor 300 can be fully embedded in the circuit board 452 such that the first conductive layer 308 of the capacitor 300 is coplanar with the mounting surface 454 of the circuit board 450, similar to the example shown with respect to the capacitor 100 in Figure 2B. In yet another embodiment, the capacitor 300 can be partially embedded in the circuit board substrate 452 such that the first conductive layer 308 of the capacitor 300, the first passivation layer 312, at least a portion of the substrate 302, the second passivation layer 314, and / or a portion of the second conductive layer 310 extend above the mounting surface 454 of the circuit board 450 along the height or thickness direction Z, as shown with respect to the capacitor 100 in Figure 2C.

[0059] As further shown in Figure 4, the capacitor 300 can be electrically connected to the conductive layer 456 of the circuit board 450. For example, as shown in Figure 4, a via 458 can extend from the first conductive layer 308 of the capacitor 300 toward the mounting surface 454 of the circuit board 450 and connect to the conductive layer 456 formed on the mounting surface 454. In this way, the via 458 of the circuit board 450 can electrically connect the capacitor 300 to the conductive layer 456 of the circuit board 450. In other embodiments, a conductive path, for example, a conductive path formed on the mounting surface 454, similar to the conductive path 260 of the circuit board 250 shown in Figures 2B and 2C, can electrically connect the capacitor 300 to the conductive layer 456 of the circuit board 450.

[0060] Referring to Figure 5, aspects of this subject matter are directed toward a method 500 for forming a single-layer capacitor as described herein. Generally, the method 500 is described herein with reference to the capacitor 100 in Figures 1, 2A, 2B, and 2C. However, it should be understood that the disclosed method 500 can be implemented with any suitable capacitor. In addition, although Figure 5 shows the steps performed in a particular order for illustrative and illustrative purposes, the method discussed herein is not limited to any particular order or arrangement. Those skilled in the art will understand that, using the disclosures provided herein, various steps of the method disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of this subject matter.

[0061] Method 500 may include the step (502) of depositing a first conductive layer 108 on at least a portion of the first surface 104 of the substrate 102 of the capacitor 100. The first conductive layer 108 may have a thickness of at least about 10 microns, for example, at least about 20 microns, at least about 40 microns, or at least about 80 microns. The first conductive layer 108 may cover the entire first surface 104 of the substrate 102, or it may be offset from one or more edges defining the periphery of the first surface 104. The first conductive layer 108 may be formed from any suitable conductive material as described herein.

[0062] Method 500 may also include the step (504) of depositing a second conductive layer 110 on at least a portion of the second surface 106 of the substrate 102 of the capacitor 100. The second conductive layer 110 may have a thickness of at least about 10 microns, for example, at least about 20 microns, at least about 40 microns, or at least about 80 microns. The second conductive layer 110 may cover the entire second surface 106 of the substrate 102, or it may be offset from one or more edges defining the periphery of the second surface 106. The second conductive layer 110 may be formed from any suitable conductive material as described herein.

[0063] It will be understood that the steps of depositing the first conductive layer 108 (502) and depositing the second conductive layer 110 (504) may include finishing the capacitor 100 (substrate 102 having the first conductive layer 108 and the second conductive layer 110 on both sides) using any suitable method such as firing to ensure adhesion between the components of the capacitor 100 and to prepare the capacitor 100 for use in a circuit board 250, for example, as described herein.

[0064] In some embodiments, the step of depositing the first conductive layer 108 may include printing the first conductive layer 108 onto at least a portion of the first surface 104 of the substrate 102, for example, by screen printing. Similarly, in some embodiments, the step of depositing the second conductive layer 110 may include printing the second conductive layer 110 onto at least a portion of the second surface 106 of the substrate 102, for example, by screen printing. It will be understood that screen printing the first conductive layer 108 and / or the second conductive layer 110 may include utilizing screen printing techniques as known within the art. However, the conductive layers 108, 110 may be added to the substrate 102 by any known process such as spin coating, impregnation, casting, drop coating, spray coating, deposition, sputtering, sublimation, knife coating, painting, or printing (e.g., inkjet, screen, or pad printing).

[0065] In some embodiments, one or more additional layers of conductive material can be plated on top of the first printed layer of conductive material to form a first conductive layer 108 and / or a second conductive layer 110 having a thickness of at least about 5 microns, for example, about 10 microns or more. For example, the step of depositing the first conductive layer 108 may include printing a first layer of conductive material on a first surface 104 of the substrate 102, and then plating at least one additional layer of conductive material on top of the first layer of conductive material. Similarly, the step of depositing the second conductive layer 110 may include printing a second layer of conductive material on a second surface 106 of the substrate 102, and then plating at least one additional layer of conductive material on top of the second layer of conductive material.

[0066] Moving on to Figure 6, an aspect of this subject matter is directed toward a method 600 for forming a single-layer capacitor as described herein. Generally, the method 600 is described herein with reference to the capacitor 300 in Figures 3A, 3B, and 4. However, it should be understood that the disclosed method 600 can be implemented with any suitable capacitor. In addition, although Figure 6 shows the steps performed in a particular order for illustrative and illustrative purposes, the method discussed herein is not limited to any particular order or arrangement. Those skilled in the art will understand that, using the disclosures provided herein, various steps of the method disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of this subject matter.

[0067] Method 600 may include the step (602) of depositing a first passivation layer 312 on at least a portion of the first surface 304 of the substrate 302 of the single-layer capacitor 300. The passivation layer 312 may be formed from a variety of suitable materials, including polymer materials and / or inorganic materials, such as glass or ceramic. For example, in some embodiments, the first passivation layer 312 may be or include polyimide. In some embodiments, the passivation layer may include at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, or glass.

[0068] Method 600 may include the step (604) of depositing a first conductive layer 308 on at least a portion of the first passivation layer 312 such that the first passivation layer 312 is positioned between the first surface 304 of the substrate 302 and the first conductive layer 308. The first conductive layer 308 may be contained within the periphery of the first passivation layer 312, for example, extending to the edge of the first passivation layer 312 and / or offset from one or more edges of the first passivation layer 312. The first conductive layer 308 does not have to be in direct contact with the substrate 302 and / or directly electrically connected to it.

[0069] Furthermore, the method 600 may include the step (606) of depositing a second passivation layer 314 on at least a portion of a second surface 306 of the substrate 302, the second surface 306 being opposite to the first surface 304 on which the first passivation layer 312 is formed. Similar to the first passivation layer 312, the second passivation layer 314 can be formed from a variety of suitable materials, including polymer materials and / or inorganic materials, such as at least one of glass, ceramic, polyimide, silicon oxynitride, Al2O3, SiO2, Si3N4, or benzocyclobutene.

[0070] The method 600 may also include the step (608) of depositing a second conductive layer 310 on at least a portion of the second passivation layer 314 such that the second passivation layer 314 is positioned between the second surface 306 of the substrate 302 and the second conductive layer 310. The second conductive layer 310 may be contained within the periphery of the second passivation layer 314, for example, extending to the edge of the second passivation layer 314 and / or offset from one or more edges of the second passivation layer 314. The second conductive layer 310 does not have to be in direct contact with the substrate 302 and / or directly electrically connected to it.

[0071] As described elsewhere in this specification, depositing the first and / or second passivation layers 312, 314 may include depositing a paste (e.g., glass paste, glass ceramic paste, etc.) onto the substrate 302, and then firing the substrate and paste to form the passivation layers on the substrate 302. However, the passivation layers can be formed using any suitable process. For example, it would be understood that the passivation layers may be deposited on the substrate 302 by depositing a paste as described above and firing the paste and substrate 302, and then the respective conductive layers 308, 310 may be deposited on the respective passivation layers 312, 314.

[0072] Furthermore, depositing the first and / or second conductive layers 308, 310 may include plating the first conductive layer 308 onto the first passivation layer 312 and / or plating the second conductive layer 310 onto the second passivation layer 314. The first and / or second conductive layers 308, 310 can be plated using electroplating and / or electroless plating methods as described above.

[0073] In any case, it will be understood that the steps of depositing the first passivation layer 312 (602), depositing the first conductive layer 308 (604), depositing the second passivation layer 314 (606), and depositing the second conductive layer 310 (608) may include finishing the capacitor 300 (the substrate 302 having the first conductive layer 308 and the first passivation layer 312 on the surface opposite to the second conductive layer 310 and the second passivation layer 314) using any suitable method such as firing to ensure adhesion between the components of the capacitor 300 and prepare the capacitor 300 for use in a circuit board 450, for example, as described herein.

[0074] Purpose The capacitors described herein are useful for a variety of applications, such as hybrid package components and filtering internal package semiconductors. Furthermore, because these capacitors exhibit excellent performance at high frequencies, such as 20 GHz and above, they may be useful in devices that process broadband radio frequency signals. Example devices include mobile devices (e.g., cell phones, tablets), cell phone base stations, receiving optical subassemblies (ROSAs), transmitting optical subassemblies (TOSAs), and other RF communication devices. Such RF devices may be particularly useful in military and space applications.

[0075] Those skilled in the art can practice these and other modifications and variations of the invention without departing from the spirit and scope of the invention. In addition, it should be understood that the aspects of the various embodiments can be replaced in whole or in part. Furthermore, those skilled in the art will understand that the foregoing description is merely illustrative and is not intended to limit the invention as further described in such appended claims. [Explanation of Symbols]

[0076] 100 Capacitors 102 circuit boards 104 First surface 106 Second surface 108 First conductive layer 110 Second conductive layer 250 Circuit Board 252 Circuit boards 254 Implementation aspects 256 Conductive layer 258 Beer 260 Conductive Path 300 Capacitors 302 circuit board 304 First surface 306 Second surface 308 First conductive layer 310 Second conductive layer 312 First Passivation Layer 314 Second Passivation Layer 450 Circuit Board 452 Circuit board PCB 454 Implementation aspects 456 Conductive layer 458 Beer

Claims

1. A circuit board substrate having a mounting surface, A single-layer capacitor is at least partially embedded in the circuit board substrate, The single-layer capacitor includes, A substrate having a first surface on the opposite side of a second surface, A first conductive layer formed on at least a portion of the first surface, A second conductive layer formed on at least a portion of the second surface, Includes, A circuit board in which at least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

2. The circuit board according to claim 1, wherein both the first conductive layer and the second conductive layer have a thickness of at least about 10 microns.

3. At least one via connected to the first conductive layer, the at least one via extending toward the mounting surface of the circuit board substrate. The circuit board according to claim 1, further comprising:

4. The circuit board according to claim 3, wherein a circuit board conductive layer is formed on the mounting surface, and at least one via electrically connects the circuit board conductive layer and the first conductive layer of the single-layer capacitor.

5. The circuit board according to claim 1, wherein the single-layer capacitor is completely embedded in the circuit board substrate such that the substrate, the first conductive layer, and the second conductive layer are each positioned below the mounting surface along the height direction.

6. The circuit board according to claim 1, wherein the single-layer capacitor is completely embedded in the circuit board substrate such that the first conductive layer is coplanar with the mounting surface.

7. The circuit board according to claim 1, wherein the single-layer capacitor is partially embedded in the circuit board substrate such that one or more of the substrate, the first conductive layer, or the second conductive layer extend upward along the height direction toward the mounting surface.

8. A substrate having a first surface and a second surface on the opposite side of the first surface, A first conductive layer formed on at least a portion of the first surface of the substrate, A second conductive layer formed on at least a portion of the second surface of the substrate, Includes, A single-layer capacitor in which at least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

9. The single-layer capacitor according to claim 8, wherein both the first conductive layer and the second conductive layer have a thickness of at least about 10 microns.

10. A method for forming a single-layer capacitor, The steps include depositing a first conductive layer on at least a portion of the first surface of a substrate, A step of depositing a second conductive layer on at least a portion of the second surface of the substrate, wherein the second surface is on the opposite side of the first surface, Includes, A method wherein at least one of the first conductive layer or the second conductive layer has a thickness of at least about 5 microns.

11. The method according to claim 10, wherein both the first conductive layer and the second conductive layer have a thickness of at least about 10 microns.

12. The method according to claim 10, wherein the step of depositing the first conductive layer includes screen printing the first conductive layer onto at least the portion of the first surface of the substrate such that the first conductive layer has a thickness of at least about 5 microns.

13. The method according to claim 10, wherein the step of depositing the second conductive layer includes screen printing the second conductive layer onto at least the portion of the second surface of the substrate such that the second conductive layer has a thickness of at least about 5 microns.

14. The method according to claim 10, wherein the step of depositing the first conductive layer includes printing a first layer of conductive material on at least a portion of the first surface of the substrate, and plating at least one additional layer of conductive material on the first layer of conductive material.

15. The method according to claim 14, wherein the step of depositing the second conductive layer includes printing a second layer of conductive material on at least a portion of the second surface of the substrate, and plating at least one additional layer of conductive material on the second layer of conductive material.

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