A system and method for determining the optimal data relocation in individual read failure events using multiple write streams.

Abstract

An indirectly addressable memory system and method for a storage device, comprising memory and processing circuitry, including processing circuitry for receiving read requests from a host. The processing circuitry determines to use one of a plurality of write streams to rearrange data at the memory address associated with the read request. The processing circuitry then ensures that the data is rearranged using the write streamry. The plurality of write streams include a hot write stream, a warm write stream, and a cold write stream. To ensure that the data is rearranged using the write streamry, the processing circuitry determines the write stream based on the age of the data or the amount of invalid data within the data.

Description

Technical Field

[0001] The present disclosure relates to a system and method for relocating data associated with an address to one of a plurality of write streams for an indirect addressing memory system.

Summary of the Invention

[0002] According to the present disclosure, a system and method for read interference data relocation by using a plurality of write streams of an indirect addressing memory system, such as a solid state drive (SSD) device, are provided. The read interference data relocation system and method discussed herein reduce the possibility of fragmentation of hot and cold data in the memory of the system. Hot and cold data are distinguished by their respective frequencies of being accessed or transferred by the read interference data relocation system, and as a result, hot data is accessed more frequently than cold data. When managing, storing, or accessing data from the memory of the read interference data relocation system (e.g., an indirect addressing memory), data fragmentation of hot and cold data can cause inefficiencies in processing. To better manage data, the systems and methods disclosed herein use a plurality of write streams to split hot data, warm data, and cold data when relocating data based at least on the age of each data within the read interference data relocation system.

[0003] In some embodiments, a read-interrupted data relocation system (e.g., a solid-state drive device) includes memory and processing circuits that are communicatively coupled to each other. The read-interrupted data relocation system may include any suitable hardware, software, or any combination thereof that implements the features described herein. In some embodiments, the read-interrupted data relocation system receives a read request from a host and decides to relocate the data at the memory address associated with the read request using one of a hot data write stream, a warm data write stream, and a cold data write stream. The read-interrupted data relocation system then ensures that the data is relocated using the determined write stream. In some embodiments, the memory includes one of solid-state drive (SSD) memory, flash memory, or universal serial bus (USB) drive memory. [Brief explanation of the drawing]

[0004] The following description includes discussion of the drawings, which have examples given as implementations of embodiments of the embodiments of this disclosure. The drawings should be understood as examples, not limitations. Where used herein, references to one or more “embodiments” should be understood as describing specific features, structures, and / or characteristics contained in at least one implementation. Thus, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations, and not all necessarily refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0005] [Figure 1] The diagrams below illustrate exemplary systems of storage devices having processing circuits and memory according to some embodiments of the present disclosure.

[0006] [Figure 2]The diagrams illustrate the storage device, according to some embodiments of the present disclosure, which rearranges data associated with a physical memory address accessed by an received read request.

[0007] [Figure 3] The flowcharts shown illustrate the process for rearranging data in memory of a read-interference data rearrangement system according to some embodiments of the present disclosure. [Figure 4] The flowcharts shown illustrate the process for rearranging data in memory of a read-interference data rearrangement system according to some embodiments of the present disclosure.

[0008] [Figure 5] The flowcharts shown illustrate the process for selecting a write stream from multiple write streams in a read-interference data relocation system, according to some embodiments of the present disclosure. [Figure 6] The flowcharts shown illustrate the process for selecting a write stream from multiple write streams in a read-interference data relocation system, according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0009] This disclosure provides a system and method for read-deaf data relocation using multiple write streams for an indirectly addressable memory system (e.g., an SSD device). Specifically, this disclosure provides a system and method for read-deaf data relocation using multiple write streams in a storage device to improve the quality of operation of the read-deaf data relocation system (e.g., to improve processing efficiency when multiple reads are received for hot data or cold data). In some embodiments, the multiple write streams include a hot data write stream, a warm data write stream, and a cold data write stream. Each write stream resides in the memory of the storage device and is used during read-deaf data relocation to partition the data based on how often it is accessed by the read-deaf data relocation system. Each write stream is a contiguous stream of stored data, and each write stream has a head (i.e., the first physical memory address) holding the first data of the write stream, and a tail which is the next available physical memory address of the write stream for the data to be relocated.

[0010] A read-off data relocation system (e.g., a storage device) may include processing circuitry and memory. In some embodiments, read requests are executed on a network bus or interface communicatively coupled to the host and the storage device. In some embodiments, the processing circuitry of the read-off data relocation system may include processing units (e.g., processors) capable of operating on received read requests. In some embodiments, read-off data relocation may be completed by multiple processors, so that, for example, each processor is responsible for processing its own received read request.

[0011] In some embodiments, the processor of the processing circuit may be a highly parallelized processor capable of rapidly handling high bandwidth read requests or data relocations (for example, by initiating simultaneous processing of a new read request or data relocation before the previous read request or data relocation is completed).

[0012] In memory such as indirectly addressed memory (e.g., SSDs), read interference can occur after a large number of read operations have been performed on the same physical memory address within the same memory block. Read interference can alter the data value stored at a physical memory address or the data value at a nearby physical memory address, which can lead to undesirable results or errors.

[0013] To avoid errors associated with read failures, a read failure data relocation system may relocate data associated with physical memory addresses that are susceptible to read failures. The read failure data relocation system may determine, by processing circuitry, that each physical memory address is more susceptible to read failures than a predetermined number of read operations, before the system can anticipate a read failure. Once a physical memory address is determined to be susceptible to read failures, the data associated with that physical memory address is relocated to the end of a write stream of other relocated data. In some implementations, the beginning of the write stream is determined to be within a memory block of available physical memory in the read failure data relocation system's memory. However, read failure relocation using a single write stream can cause data fragmentation of hot and cold data if both hot and cold data are relocated to the same write stream. In such an embodiment, this type of data fragmentation can lead to processing inefficiencies when accessing data from memory.

[0014] Data relocation can improve the reliability of indirectly addressed memory systems. However, it can lead to data fragmentation of both hot and cold data, and as a result, a read-hindered data relocation system may relocate both hot and cold data to the same write stream. Data fragmentation, in which cold data is intermittently stored across multiple memory blocks of hot data, can cause performance problems in read-hindered data relocation systems and memory reliability problems in indirectly addressed memory systems.

[0015] Data fragmentation can also occur when processing circuits write to and overwrite multiple memory addresses in indirectly addressed memory. This typically results from the use of multiple logical memory addresses that do not directly correspond to physical memory addresses with the same value. This type of logical memory addressing requires logical-to-physical memory address mapping in an indirect table to maintain a comprehensive mapping from logical memory addresses to physical memory addresses that store valid data.

[0016] When a host sends a write request along with data and a logical memory address for storing that data in indirectly addressable memory (e.g., an SSD), the read-deprived data relocation system finds the next available first physical memory address in memory for writing the data. The first physical memory address determined by the read-deprived data relocation system does not necessarily correspond to the logical memory address sent by the host. An indirect table may be used to track the physical memory addresses mapped to each logical memory address. In some implementations, the indirect table may contain valid bits indicating that the logical-physical memory address mapping is valid. Once data is written to memory, the indirect table is updated with the valid logical-physical memory address mapping. When the read-deprived data relocation system receives a read request to access data at the same logical memory address, it decides to access the data from the first physical memory address based on the indirect table.

[0017] However, if a second write request for the same logical memory address to which data has been previously written is received by the read-interrupted data relocation system, the read-interrupted data relocation system determines the next available second physical memory address to write the data associated with the second write request. Thus, the previously written logical memory address is mapped to the second physical memory address. Once the logical-physical mapping is updated, the data stored in the first physical memory address remains there until it is overwritten or erased during garbage collection. In some implementations, the first physical memory address is marked as invalid or dirty by using the valid bits associated with the first physical memory address.

[0018] The storage device uses processing circuitry to determine whether the data at the physical memory address associated with a read request should be relocated using one of the write streams from at least one hot data write stream, at least one warm data write stream, and at least one cold data write stream. The read-interference data relocation system may decide to relocate the data at the physical memory address associated with a read request based on whether that physical memory address is susceptible to read interference. The read-interference data relocation system may determine, before it can anticipate read interference, that each physical memory address is more susceptible to read interference than a predetermined number of read operations, based on the number of read operations on that physical memory address. If the read-interference data relocation system determines that the data at the address associated with a read request should be relocated, it ensures that the data is relocated using the determined write stream.

[0019] In some embodiments, a read-destroyed data relocation system ensures that data is relocated using a determined write stream. In some implementations, the read-destroyed data relocation system determines which write stream should relocate the data based on the age of the data at a physical memory address. The age of the data at each physical memory address can be defined by the period over which the data at that physical memory address has been accessed, written to, or transferred. The read-destroyed data relocation system determines, based on the age of the data at a physical memory address, that the data at that physical memory address should be relocated to one of the hot data write streams, warm data write streams, and cold data write streams in the order in which the data age increases. In some implementations, once a physical memory address is determined to be susceptible to read destructive activity, the data associated with that physical memory address is relocated to the end of one of these write streams (e.g., warm data write stream, hot data write stream, or cold data write stream).

[0020] In some embodiments, the read-interference data relocation systems and methods of the present disclosure may refer to a storage device system (e.g., an SSD storage system) that includes a storage device, such as a solid-state drive device, that is coupled to a host via a network bus or interface.

[0021] An SSD is a data storage device that uses an integrated circuit assembly as memory for permanently storing data. The SSD has no moving mechanical components, and because of this feature, the SSD is distinguished from conventional electromechanical magnetic disks, such as hard disk drives (HDDs) or floppy disks, which include spinning disks and movable read / write heads. Compared with electromechanical disks, SSDs are typically more resistant to physical shock, operate quietly, have shorter access times, and less latency. The SSD uses indirect memory addressing to store data at the next available physical memory address and map the next available physical memory address to a logical memory address in an indirect table.

[0022] Many types of SSDs use NAND-based flash memory that retains data without power and include some type of non-volatile storage technology. The quality of service (QoS) of an SSD may be related to the predictability of low latency and the consistency of high input / output operations per second (IOPS) while processing read / write input / output (I / O) workloads. This means that the latency or completion time of an I / O command needs to be within a specified range without having unexpected outliers. Also, the throughput or I / O speed may need to be tightly controlled without causing a sudden drop in the performance level.

[0023] The subject matter of the present disclosure may be better understood by referring to FIGS. 1 through 6.

[0024] FIG. 1 shows an exemplary diagram of a read interference data rearrangement system 100 of a storage device 102 having a processing circuit 104 and a memory 106, according to some embodiments of the present disclosure. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., a solid-state drive device). In some embodiments, the processing circuit 104 may include a processor or any suitable processing unit. In some embodiments, the memory 106 may be a non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the storage device 102 may include any suitable memory device having an indirect addressing memory system in addition to, or instead of, an SSD.

[0025] In some embodiments, the read interference data rearrangement system 100 is configured to receive a read request 110 transmitted on a network bus or interface from an external source (e.g., host 108). In some embodiments, the read interference data rearrangement system 100 receives read requests (e.g., read request 110) from both inside and outside the storage device 102. There may also be a temporary memory (e.g., a cache or a queue) disposed within the processing circuit 104, such that the temporary memory is configured to store any unprocessed read requests to be processed by the read interference data rearrangement system 100.

[0026] Additionally, the storage device 102 includes a memory 106. In some embodiments, the memory 106 includes one or more non-volatile memories, such as flash memory, Universal Serial Bus (USB) drive memory, phase-change memory (PCM), PCM and switch (PCM), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), spin-transfer torque random access memory (STT-RAM), resistive random access memory (RRAM®), memristor, magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, the processing circuit 104 is communicably coupled to the memory 106 to store data at memory addresses within the memory 106 and to access such data. The memory 106 is a memory that uses indirect memory addressing. A memory that uses indirect memory addressing typically includes an indirect table that maps logical memory addresses (i.e., virtual memory addresses) from read or write requests to physical memory addresses from the memory (e.g., memory 106). In some implementations, the indirect table may contain valid bits indicating that the logical-to-physical memory address mapping is valid. Once data is written to memory, the indirect table is updated with the valid logical-to-physical memory address mapping. When the read-interference data relocation system 100 receives a read request 110 to access data at a logical memory address, the read-interference data relocation system 100 determines the physical memory address to access the data from there based on the indirect table.

[0027] In some embodiments, a data bus interface is used to transport data associated with physical memory addresses from memory 106. The data bus between memory 106 and processing circuit 104 provides a network bus for reading or writing data through memory 106. In some embodiments, the processor or processing unit of processing circuit 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to herein as processing circuit 104, may include any suitable software, hardware, or both for controlling memory 106 and processing circuit 104. In some embodiments, the storage device 102 may further include a multicore processor. Memory 106 may also include hardware elements for the non-temporary storage of instructions, commands, or requests.

[0028] A storage device (e.g., an SSD device) may comprise one or more packages of non-volatile memory dies, each die comprising a storage cell. In some embodiments, the storage cells are organized into pages, and the pages are organized into blocks. Each storage cell may store one or more bits of information.

[0029] While the read-deafened data relocation system 100 illustrates one embodiment in which the storage device 102 is configured to relocate data associated with a physical memory address to one of a plurality of write streams provided herein, it will be understood that if the read-deafened data relocation system 100 similarly determines that a physical memory address is susceptible to read deafening, any other suitable device may relocate the data associated with the physical memory address to one of a plurality of write streams to avoid fragmentation of hot, warm, and cold data.

[0030] For clarity and brevity, and not as an limitation, this disclosure is provided in the context of read-interrupted data relocation to one of a plurality of write streams to avoid fragmentation of hot, warm, and cold data when a read interruption is expected at each physical memory address, providing the features and functions disclosed herein. The read-interrupted data relocation process may consist of any suitable software, hardware, or both to implement such features and functions. The read-interrupted data relocation process may be implemented at least in part, for example, within a storage device 102 (e.g., as part of a read-interrupted data relocation system 100 or any other suitable device in which efficiency can be improved by read-interrupted data relocation). For example, for a solid-state storage device (i.e., storage device 102), the relocation of data from a physical memory address to one of a plurality of write streams based on a read interruption event may be implemented within a processing circuit 104.

[0031] Figure 2 shows an exemplary diagram of a read-off data relocation system 200 having a storage device 102 that relocates data 210 associated with a physical memory address 207 accessed by an received read request 110, according to some embodiments of the present disclosure. While a specific configuration of data blocks in memory 106 is shown in Figure 2, the number of data blocks per data line and the size of each data block are not limited by the read-off data relocation system 200 shown, and memory 106 may contain any appropriate number of data blocks per data line and each data block of any appropriate size. In some embodiments, the physical memory address 207 is determined by the read-off data relocation system 200 based on the corresponding mapped logical memory address 205 using an indirection table 203. In some embodiments, the indirection table 203 may be stored in a processing circuit 104 in memory 106, or in another additional memory in the storage device 102. In some embodiments, there may be more than one storage device, each storage device being directed by a storage controller that stores and manages an indirection table for each storage device. In such embodiments, the processing circuit of each storage device may be communicatively coupled to a storage controller to access an indirect table in order to perform read-interrupted data relocation, or the storage controller may include multiple processors for performing read-interrupted data relocation in parallel for each storage device. The processing circuit 104 is communicatively coupled to the memory 106, and as a result, the processing circuit 104 can access the data stored in each data block of the memory 106.

[0032] In some embodiments, the storage device 102 receives read requests 110 that include a logical memory address 202 for reading and accessing data from there. In some embodiments, the source of the read requests 110 is another device located outside the storage device 102 (e.g., a host). In some embodiments, the source of the requests 110 may be located within the storage device 102, for example, an application programming interface (API). In some embodiments, the storage device 102 can receive and process multiple read requests (e.g., requests 110) by using temporary memory, such as a cache, to store multiple read requests before they are processed by the read-interrupted data relocation system 200.

[0033] In some embodiments, the read-destroyed data relocation system 200 determines the physical memory address 207 in conjunction with the indirect table 203 in order to access the data 210 stored at the physical memory address 207. Once the read-destroyed data relocation system 200 receives a read request 110, it searches the indirect table 203 for a valid matching logical memory address (e.g., a mapped logical memory address 205). Once the read-destroyed data relocation system 200 determines a mapped logical memory address 205 that matches the received logical memory address 202 of the read request 110, it can access the corresponding physical memory address 207 from the indirect table 203.

[0034] Memory 106 includes stored data 210 at physical memory address 207, as well as at least three write streams, including a hot data write stream 204, a warm data write stream 206, and a cold data write stream 208. Each write stream includes a contiguous stream of data blocks of stored data, initialized at the first data block and extending to the end of the write stream, which is the next available physical memory address for the data to be relocated. When new data is relocated to the end of each write stream, the end is updated to the next available physical memory address following the previous end of each write stream. Each of the write streams is located in a different area of ​​memory 106. Hot data, warm data, and cold data are distinguished by the frequency with which they are accessed or transferred by the read-interference data relocation system 200, with hot data being accessed more frequently than cold data. Warm data may be used as an intermediate classification of data between hot data and cold data to increase the granularity of data organization.

[0035] In some embodiments, data 210 is located at physical memory address 207, and when the read-interference data relocation system 200 accesses data 210, the read-interference data relocation system 200 determines that the number of read operations performed on physical memory address 207 exceeds a preset number of read operations corresponding to the likelihood of read interference. To avoid read interference in memory 106, the read-interference data relocation system 200 performs read-interference data relocation 212 using multiple write streams by relocating data 210 to the end of a hot data write stream 204. The read-interference data relocation system 200 may determine the type of data (e.g., hot data, warm data, or cold data) based at least on the age of the data. In some embodiments, the read-interference data relocation system 200 determines that data 210 is frequently accessed and is classified as hot data. In some embodiments, the type of data in each data block (e.g., hot data, warm data, or cold data) may also be determined by the amount of invalid data in each data block. In such an embodiment, the read-interference data relocation system 200 may determine that data in a data block having many invalid memory addresses is hot data, while data in a data block with few invalid memory addresses is cold data.

[0036] Figure 3 shows a flowchart illustrating a process 300 for rearranging data in the memory of a read-interference data relocation system according to several embodiments of the present disclosure. In some embodiments, the read-interference data relocation system, storage device, processing circuit, memory, host, and read request mentioned may be implemented or represented as read-interference data relocation system 100, storage device 102, processing circuit 104, memory 106, host 108, and read request 110, respectively. In some embodiments, the process 300 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0037] In step 302, the read-deprived data relocation system receives a read request from the host. In some embodiments, the data is received by a processing circuit, a network bus, or an interface. The read request includes at least a logical memory address from which the read-deprived data relocation system accesses the data. In some implementations, the read-deprived data relocation system determines the physical memory address corresponding to the received logical memory address by using an indirect table. In some embodiments, the read-deprived data relocation system receives more than one read request. At least one of the received read requests may be stored in memory, such as a cache or queue or any form of volatile memory. In some embodiments, the processing circuit may include a multicore processor capable of performing read-deprived data relocations triggered by one or more read requests. Once the read-deprived data relocation system receives a read request from the host, in step 304, the read-deprived data relocation system determines whether the data at the memory address associated with the read request should be relocated using one of several write streams.

[0038] In step 304, the read-deprived data relocation system determines whether the data at the address associated with the read request should be relocated using one of several write streams. The read-deprived data relocation system may decide whether to relocate the data at the physical memory address associated with the read request based on whether the memory at that address (i.e., the physical memory address) is susceptible to read interference. In some implementations, the read-deprived data relocation system determines, based on the number of read operations on the physical memory address, that each physical memory address is susceptible to read interference compared to a predetermined number of read operations, before the read-deprived data relocation system can anticipate a read interference at that physical memory address. If the read-deprived data relocation system determines that the data at the address associated with the read request should be relocated, in step 306, the read-deprived data relocation system ensures that the data is relocated using one of several write streams. If the read-deprived data relocation system determines that the data at the memory address associated with the read request should not be relocated, process 300 is completed.

[0039] In step 306, the read-destroyed data relocation system ensures that the data is relocated using a write stream. In some implementations, the read-destroyed data relocation system determines which write stream should relocate the data based on the age of the data at the physical memory address. The age of the data can be defined by the period over which the data at the physical memory address has been accessed, written to, or transferred. Depending on the age of the data at the physical memory address, the read-destroyed data relocation system determines that the data should be relocated to one of the hot data write streams, warm data write streams, and cold data write streams, in the order of increasing data age. In some embodiments, there is a data age range associated with the warm data write stream, including a minimum warm data age and a maximum warm data age. Therefore, any data with a data age less than the minimum warm data age is determined by the processing circuit to be hot data, and any data with a data age greater than the maximum warm data age is determined by the processing circuit to be cold data. In some implementations, once a physical memory address is determined to be susceptible to read-destroyed data, the data associated with the physical memory address is relocated to the end of the determined write stream. In some embodiments, a read-interference data relocation system determines the write stream to which data at a physical memory address is relocated based on the amount of invalid data within a data block. In such implementations, data blocks with more invalid data are determined to be relocated to a hot data write stream. Conversely, data blocks with little to no invalid data may be determined to be relocated to a cold data write stream.

[0040] Figure 4 shows a flowchart illustrating a process 400 for rearranging data in the memory of a read-interrupted data relocation system according to several embodiments of the present disclosure. In some embodiments, the read-interrupted data relocation system, storage device, processing circuit, memory, host, and read request mentioned may be implemented or represented as read-interrupted data relocation system 100, storage device 102, processing circuit 104, memory 106, host 108, and read request 110, respectively. In some embodiments, the process 400 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0041] In step 402, the read-deprived data relocation system receives a read request from the host. In some embodiments, the data is received via a network bus or interface. The read request includes at least a logical memory address from which the read-deprived data relocation system accesses the data. In some implementations, the read-deprived data relocation system determines the physical memory address corresponding to the received logical memory address by using an indirect table. In some embodiments, the read-deprived data relocation system receives more than one read request. At least one of the received read requests may be stored in memory, such as a cache or queue or any form of volatile memory. In some embodiments, the processing circuitry may include a multicore processor capable of performing read-deprived data relocations triggered by one or more read requests. Once the read-deprived data relocation system receives a read request from the host, in step 404, the read-deprived data relocation system determines whether the data at the memory address associated with the read request is susceptible to read deprivation.

[0042] In step 404, the read-deprived data relocation system determines whether the data at the address associated with the read request is susceptible to read deprivation. In some implementations, the read-deprived data relocation system determines, based on the number of read operations on the physical memory address, that each physical memory address is susceptible to read deprivation compared to a predetermined number of read operations, before the read-deprived data relocation system can foresee read deprivation at that physical memory address. If the number of read operations on the physical memory address, including the read request received from step 402, exceeds the predetermined number of read operations, in step 406, the read-deprived data relocation system determines that the data at the physical memory address should be relocated using one of the write streams from at least one hot data write stream, at least one warm data write stream, and at least one cold data write stream. If the read-deprived data relocation system determines that the data at the memory address associated with the read request should not be relocated, process 400 is completed.

[0043] In step 406, the read-deprived data relocation system selects one write stream from a plurality of write streams. The plurality of write streams may include at least one hot data write stream, at least one warm data write stream, and at least one cold data write stream. In some embodiments, the write stream may be selected based on the age of the data at the memory address associated with the read request. The age of the data may be defined by the period over which the data has been accessed, written to, or transferred at the physical memory address. Depending on the age of the data at the physical memory address, the read-deprived data relocation system determines that the data should be relocated to one of the hot data write streams, warm data write streams, and cold data write streams in the order of increasing data age. In some embodiments, the write stream may be selected based on the amount of invalid data in the data at the memory address associated with the read request. Once a write stream has been selected by the read-deprived data relocation system, the read-deprived data relocation system ensures that the data at the memory address associated with the read request is relocated to the selected write stream.

[0044] In step 408, the read-destroyed data relocation system ensures that data is relocated using a write stream. In some embodiments, there is a data age range associated with a warm data write stream, including a minimum warm data age and a maximum warm data age. Thus, any data with a data age less than the minimum warm data age is determined by the processing circuit to be hot data, and any data with a data age greater than the maximum warm data age is determined by the processing circuit to be cold data. In some implementations, once a physical memory address is determined to be susceptible to read-destroyed data, the data associated with the physical memory address is relocated to the end of the determined write stream. In some embodiments, the read-destroyed data relocation system determines the write stream to which the data at the physical memory address is relocated based on the amount of invalid data in the data block. In such implementations, data blocks with more invalid data are determined to be relocated to the hot data write stream. Thus, data blocks with little to no invalid data may be determined to be relocated to the cold data write stream.

[0045] Figure 5 shows a flowchart illustrating a process 500 for selecting a write stream from multiple write streams in a read-interference data relocation system, according to some embodiments of the present disclosure. In some embodiments, step 406 in Figure 4 may be implemented by the steps shown in process 500. In some embodiments, the read-interference data relocation system, storage device, processing circuit, memory, host, and read request mentioned may be implemented or represented as read-interference data relocation system 100, storage device 102, processing circuit 104, memory 106, host 108, and read request 110, respectively. In some embodiments, process 500 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0046] In step 502, the read-interference data relocation system determines whether the age of the data at the memory address associated with the read request is less than the minimum warm data age. In some implementations, the minimum warm data age is determined by the minimum age of any data in a warm data write stream. In some implementations, the minimum warm data age is comprised of a preset warm data age value. If the age of the data associated with the read request is less than the minimum warm data age, in step 504, the read-interference data relocation system selects a hot data write stream. If the age of the data at the memory address associated with the read request is greater than the minimum warm data age, in step 506, the read-interference data relocation system determines whether the age of the data at the memory address associated with the read request is greater than the maximum warm data age.

[0047] In stage 504, the read-interrupted data relocation system selects the hot data write stream. In some implementations, when the read-interrupted data relocation system determines the physical memory address at the end of the hot data write stream, it determines the physical memory address to relocate the data at the memory address associated with the read request.

[0048] In step 506, the read-interference data relocation system determines whether the age of the data at the memory address associated with the read request is greater than the maximum warm data age. In some implementations, the maximum warm data age is determined by the maximum age of any data in a warm data write stream. In some implementations, the maximum warm data age is comprised of a preset warm data age value. If the age of the data associated with the read request is greater than the maximum warm data age, in step 508, the read-interference data relocation system selects a cold data write stream. If the age of the data at the memory address associated with the read request is less than the maximum warm data age, in step 510, the read-interference data relocation system selects a warm data write stream.

[0049] In stage 508, the read-interrupted data relocation system selects a cold data write stream. In some implementations, when the read-interrupted data relocation system determines the physical memory address at the end of the cold data write stream, it determines the physical memory location for relocating the data at the memory address associated with the read request.

[0050] In stage 510, the read-interrupted data relocation system selects a warm data write stream. In some implementations, when the read-interrupted data relocation system determines the physical memory address at the end of the warm data write stream, it determines the physical memory address to relocate the data at the memory address associated with the read request.

[0051] Figure 6 shows a flowchart illustrating a process 600 for selecting a write stream from multiple write streams in a read-interference data relocation system, according to some embodiments of the present disclosure. In some embodiments, step 406 in Figure 4 may be implemented by the steps shown in process 600. In some embodiments, the read-interference data relocation system, storage device, processing circuit, memory, host, and read request mentioned may be implemented or represented as read-interference data relocation system 100, storage device 102, processing circuit 104, memory 106, host 108, and read request 110, respectively. In some embodiments, process 600 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0052] In step 602, the read-interference data relocation system determines whether the amount of invalid data in the data at the memory address associated with the read request is greater than the maximum amount of invalid data in the warm data. In some implementations, the maximum amount of invalid data in the warm data is comprised of a preset maximum amount of invalid data in the warm data. If the amount of invalid data in the data associated with the read request is greater than the maximum amount of invalid data in the warm data, in step 604, the read-interference data relocation system selects a hot data write stream. If the amount of invalid data in the data at the memory address associated with the read request is less than the maximum amount of invalid data in the warm data, in step 606, the read-interference data relocation system determines whether the amount of invalid data in the data at the memory address associated with the read request is less than the minimum amount of invalid data in the warm data.

[0053] In stage 604, the read-interrupted data relocation system selects the hot data write stream. In some implementations, when the read-interrupted data relocation system determines the physical memory address at the end of the hot data write stream, it determines the physical memory address to relocate the data at the memory address associated with the read request.

[0054] In step 606, the read-interference data relocation system determines whether the amount of invalid data in the data at the memory address associated with the read request is less than the minimum amount of warm data. In some implementations, the minimum amount of invalid data in warm data is comprised of a preset minimum amount of invalid data in warm data. If the amount of invalid data in the data associated with the read request is less than the minimum amount of invalid data in warm data, in step 608, the read-interference data relocation system selects a cold data write stream. If the amount of invalid data in the data at the memory address associated with the read request is greater than the minimum amount of invalid data in warm data, in step 610, the read-interference data relocation system selects a warm data write stream.

[0055] In stage 608, the read-interrupted data relocation system selects a cold data write stream. In some implementations, when the read-interrupted data relocation system determines the physical memory address at the end of the cold data write stream, it determines the physical memory location for relocating the data at the memory address associated with the read request.

[0056] In step 610, the read-interrupted data relocation system selects a warm data write stream. In some implementations, when the read-interrupted data relocation system determines the physical memory address at the end of the warm data write stream, it determines the physical memory address to relocate the data at the memory address associated with the read request.

[0057] Unless otherwise explicitly stated, the terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments.”

[0058] Unless otherwise explicitly stated, the terms “including,” “comprising,” and “having,” and their variations, mean “including, but not limited to.”

[0059] Unless otherwise explicitly stated, the listed items do not imply that any or all of them are mutually exclusive.

[0060] Unless otherwise explicitly stated, the terms “a,” “an,” and “the” mean “one or more.”

[0061] Unless otherwise explicitly stated, multiple devices communicating with each other do not need to communicate with each other continuously. In addition, multiple devices communicating with each other may communicate directly or indirectly through one or more intermediate media.

[0062] A description of one embodiment having several components communicating with one another does not imply that all such components are required. On the contrary, various optional components are described to illustrate a wide variety of possible embodiments. Furthermore, while processing steps, method steps, algorithms, or the like may be described in a sequential order, such processing, methods, and algorithms may be configured to function in an alternative order. In other words, any order or sequence of steps that may be described does not necessarily imply that these steps must be performed in that order. The processing steps described herein may be performed in any practical order. Furthermore, several steps may be performed simultaneously.

[0063] Where a single device or article is described herein, it will be readily apparent that more than one device or article (whether they cooperate or not) may be used instead of a single device or article. Similarly, where more than one device or article (whether they cooperate or not) is described herein, it will be readily apparent that a single device or article may be used instead of more than one device or article, or that a different number of devices or articles may be used instead of the number of devices or programs indicated. The functions and / or features of a device may be embodied by one or more other devices not expressly described as having such functions / features. Therefore, other embodiments do not necessarily have to include the device itself.

[0064] At least some specific operations, which may be shown in the figures, indicate that certain events occur in a specific order. In alternative embodiments, some specific operations may be performed, modified, or omitted in a different order. Furthermore, steps may be added to the logic described above, and still conform to the embodiments described. Moreover, the operations described herein may be performed sequentially, or some specific operations may be processed in parallel. Furthermore, multiple operations may be performed by a single processing unit or by distributed processing units.

[0065] The above description of various embodiments is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit to the exact forms disclosed. Many modifications and variations are possible in light of the above teachings.

Claims

1. memory; and Receiving a read request from the host, Deciding to rearrange the data at the memory address associated with the read request using a write stream selected from a plurality of write streams based on the characteristics of the data, and The data is rearranged using the aforementioned write stream. Processing circuit for performing this task A system equipped with these features.

2. The system according to claim 1, wherein the memory has indirect addressing memory.

3. The system according to claim 2, wherein the memory has a solid-state drive memory.

4. The system according to claim 2, wherein the memory has flash memory.

5. The system according to claim 2, wherein the memory has a universal serial bus drive memory.

6. The system according to any one of claims 1 to 5, wherein the write stream is selected based on the age of the data.

7. The system according to any one of claims 1 to 5, wherein the write stream is selected based on the amount of invalid data among the data.

8. The system according to any one of claims 1 to 5, wherein the plurality of write streams include a hot data write stream, a warm data write stream, and a cold data write stream.

9. A method for rearranging data in memory of an indirectly addressed memory system, The stage in which a read request is received from the host by the processing circuit, The processing circuit determines whether to rearrange the data at the memory address associated with the read request using a write stream selected from a plurality of write streams based on the characteristics of the data, and The processing circuit causes the data to be rearranged using the write stream. A method that includes [a certain feature].

10. The method according to claim 9, wherein the step of deciding to rearrange the data at the address of the memory associated with the read request using one of a plurality of write streams is further comprising the step of deciding to rearrange the data at the address of the solid-state drive memory associated with the read request using one of a plurality of write streams.

11. The method according to claim 9, wherein the step of deciding to rearrange the data at the memory address associated with the read request using one of a plurality of write streams is further comprising the step of deciding to rearrange the data at the flash memory address associated with the read request using one of a plurality of write streams.

12. The method according to claim 9, wherein the step of deciding to rearrange the data at the address of the memory associated with the read request using one of a plurality of write streams is further comprising the step of deciding to rearrange the data at the address of the universal serial bus drive memory associated with the read request using one of a plurality of write streams.

13. The method according to any one of claims 9 to 12, wherein the step of rearranging the data using the write stream comprises the step of selecting the write stream based on the age of the data.

14. The method according to any one of claims 9 to 12, wherein the step of rearranging the data using the write stream includes the step of selecting the write stream based on the amount of invalid data among the data.

15. The method according to any one of claims 9 to 12, the step of deciding to rearrange the data at the address of the memory associated with the read request using one of a plurality of write streams, wherein the plurality of write streams include a hot data write stream, a warm data write stream, and a cold data write stream.

16. When executed by the processing circuit, Procedure for receiving read requests from the host, A procedure for determining whether to rearrange the data at the memory address associated with the read request using a write stream selected from a plurality of write streams based on the characteristics of the data, and Procedure for causing the data to be rearranged using the aforementioned write stream A computer program comprising non-temporary computer-readable instructions that cause the processing circuit to perform the above-mentioned action.

17. The computer program according to claim 16, wherein the memory includes indirectly addressable memory.

18. The computer program according to claim 17, wherein the memory includes a solid-state drive memory.

19. The computer program according to claim 17, wherein the memory includes flash memory.

20. The computer program according to claim 17, wherein the memory includes a universal serial bus drive memory.

21. The computer program according to any one of claims 16 to 20, wherein the write stream is selected based on the age of the data.

22. The computer program according to any one of claims 16 to 20, wherein the write stream is selected based on the amount of invalid data among the data.

23. The computer program according to any one of claims 16 to 20, wherein the plurality of write streams include a hot data write stream, a warm data write stream, and a cold data write stream.

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