How to extend NoC interconnects across multiple dies in 3D

Abstract

Embodiments of this specification describe techniques for extending a network-on-chip (NoC) across multiple IC dies in 3D. An integrated circuit (IC) device includes a first vertically stacked IC die and a second vertically stacked IC die, and an inter-die bus interface between the second die and the NoC packet switch (NFS) of the first die. The inter-die bus may include one or more driver circuits coupled to the inter-die links of the inter-die bus. Communication over the inter-die links may be synchronous (e.g., packet-based) or asynchronous (e.g., based on a point-to-point protocol such as the AXI protocol) with respect to the NFS. The inter-die bus may interface with circuit blocks of the second IC device via a point-to-point (e.g., AXI) protocol or via the NFS of the second IC die. The IC device may include multiple inter-die buses that can extend inter-die and intra-die routing options.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to methods for extending NoC interconnects across multiple dies in 3D.

Background Art

[0002] A network-on-chip (NoC) provides an efficient way to communicate between circuit blocks or between subsystems of an IC die. As Moore's Law reaches the limits of physics, integrated circuit (IC) designers face challenges in further shrinking the size of IC devices. To address these challenges and improve performance, the semiconductor industry is looking at stacked or three-dimensional (3D) IC devices. Extending the NoC across multiple stacked IC dies presents timing and signal strength issues.

Summary of the Invention

[0003] Techniques for extending NoC interconnects across multiple IC dies in 3D are described.

[0004] One example described herein is a first vertically stacked IC die and a second vertically stacked IC die, the first IC die comprising a network-on-chip (NoC) circuit, the first vertically stacked IC die and the second vertically stacked IC die, and an inter-die bus configured to interface between a packet-switched NoC and the second IC die, the inter-die bus including a driver circuit coupled to an inter-die link of the inter-die bus, an integrated circuit (IC) device including the inter-die bus.

[0005] Another example described herein is an IC device comprising a first vertically stacked IC die and a second vertically stacked IC die, each having a first network-on-chip packet switch and a second network-on-chip (NoC) packet switch (NPS) for a three-dimensional (3D) packet-switching NoC, and an inter-die bus interfacing the first and second NPS asynchronously with the 3D packet-switching NoC, wherein the inter-die bus includes driver circuits coupled to the inter-die links of the inter-die bus.

[0006] Another example described herein is an IC device comprising a first vertically stacked IC die and a second vertically stacked IC die, the first IC die including a network-on-chip (NoC) packet switch (NPS) of a packet-switched NoC, and a dedicated inter-die bus that interfaces between the NPS and a circuit block of the second IC die asynchronously with respect to a point-to-point protocol, the inter-die bus including driver circuits coupled to the inter-die links of the inter-die bus. [Brief explanation of the drawing]

[0007] More detailed explanations of the features listed above, which are briefly summarized above, can be provided by referring to exemplary implementations, some of which are illustrated in the attached drawings. However, it should be noted that the attached drawings illustrate only typical exemplary implementations and should therefore not be considered limiting in scope. [Figure 1] An example is illustrated of a multilayer integrated circuit (IC) device comprising a first vertically stacked IC die and a second vertically stacked IC die, each containing a circuit block, wherein the first IC die includes a NoC circuit configured to provide a packet-switched network on-chip (NoC). [Figure 2]This is a block diagram of the interface circuit of a first IC die including a NoC master unit (NMU) according to one embodiment. [Figure 3] This is a block diagram of the interface circuit of a first IC die including a NoC slave unit (NSU) according to one embodiment. [Figure 4] A communication path passing through a packet-switched NoC according to one embodiment will be illustrated as an example. [Figure 5] An example is illustrated of an IC device in which a second IC die includes a NoC circuit, and the IC device further includes an inter-die bus for providing a three-dimensional (3D) packet-switched NoC. [Figure 6A] One embodiment illustrates an IC device 100 that includes a driver circuit in which an inter-die bus drives packets from a first IC die to a second IC die in synchronization with a 3D packet switching NoC. [Figure 6B] One embodiment illustrates an IC device in which an inter-die bus includes a driver circuit that drives packets from a second IC die to a first IC in synchronization with a 3D packet switching NoC. [Figure 6C] An example of an IC device 100, according to one embodiment, in which the inter-die bus includes the features shown in Figures 6A and 6B, is illustrated. [Figure 7A] This example illustrates an IC device in which an inter-die bus depackages packets received from a first IC die and drives the depackaged packets to a second IC die asynchronously using a point-to-point protocol with a 3D packet switching NoC. [Figure 7B] This example illustrates an IC device in which an inter-die bus depackages packets received from a second IC die and drives the depackaged packets to a first IC die asynchronously with a 3D packet switching NoC using a point-to-point protocol. [Figure 7C] An example of an IC device in which the inter-die bus has the features shown in Figures 7A and 7B is illustrated. [Figure 8]In one embodiment, an IC device 100 is illustrated that further includes an inter-die bus providing a dedicated asynchronous communication path between the circuit block of the second IC die and the packet-switched NoC of the first IC die, such that the circuit block of the second IC die functions as an endpoint of the packet-switched NoC. [Figure 9A] One embodiment illustrates an IC die in which a dedicated inter-die bus provides a unidirectional asynchronous path from the circuit block of the second IC die to the packet switching NoC of the first IC die. [Figure 9B] One embodiment illustrates an IC die in which a dedicated inter-die bus provides a unidirectional asynchronous path from the packet switching No.C of the first IC die to the circuit block of the second IC die. [Figure 10] This is a block diagram of a programmable logic or configurable circuit including an array of configurable or programmable circuit blocks or tiles according to one embodiment.

[0008] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements of one embodiment are intended to be usefully incorporated into other embodiments. [Modes for carrying out the invention]

[0009] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of the features. They are not intended as an exhaustive description of the features or as a limitation on the scope of the claims. In addition, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not illustrated or explicitly described in that way.

[0010] Embodiments of this specification describe methods for extending NoC interconnects across multiple IC dies in 3D. Embodiments of this specification may provide relatively low-latency, deterministic, and efficient NoC communication between stacked IC dies. Embodiments of this specification may be useful for providing relatively large bandwidth between IC dies. Embodiments of this specification may be useful for extending routing options and / or reducing load in conventional 2D NoC. For example, a compiler may route intra-die NoC traffic (i.e., 2D NoC traffic) from a first die to a second die and back to the first die to reduce routing congestion on the first die. Extended routing options may improve efficiency (e.g., in artificial intelligence (AI) based IC designs) and / or provide more efficient access to memory resources.

[0011] Figure 1 illustrates a multilayer integrated circuit (IC) device 100 according to one embodiment, which includes a first vertically stacked IC die 102 and a second vertically stacked IC die 104. The IC device 100 may include one or more additional IC dies above, below, and / or between the IC dies 102 and 104.

[0012] IC dies 102 and 104 may contain one or more blocks of circuitry that may represent subsystems of a system-on-chip (SoC). In the example in Figure 1, IC die 102 contains circuit blocks 108 and 110, and IC die 104 contains circuit blocks 116 and 118.

[0013] The IC die 102 further includes a NoC circuit 106 that provides a packet-switched network on chip (NoC). The NoC circuit 106 includes NoC packet switches (NPS) 120-1 to 120-n (collectively, NPS 120) that route packets within the packet-switched NoC and function as access points to the packet-switched NoC. In Figure 1, circuit blocks 108 and 110 may communicate with each other and / or external devices through the packet-switched NoC via their respective interface circuits 112 and 114, and their respective NPS 120-1 and 120-6. Circuit blocks 108 and 110 may be referred to as endpoints of the packet-switched NoC.

[0014] Interface circuits 112 and 114 packetize and / or depacketize communication between the packet-switched NoC and the respective circuit blocks 108 and 110. Interface circuits 112 and 114 may convert between the NoC packet protocol (NPP) of the packet-switched NoC and the point-to-point protocol of the circuit blocks 108 and 110. The point-to-point protocol may be asynchronous with the NPP. The point-to-point protocol may include multiple channels, which may include, but are not limited to, a write address channel (AW), a write data channel (W), a read address channel (AR), and a read data channel (R). If the channels are unidirectional, the channels may further include a write response channel (B) for returning responses to the requester. Read responses may be returned to the requester via the read data channel (R). Separate, independent read and write channels can support simultaneous read and write operations and may be useful in maximizing interface bandwidth. Separate address and data channels for read and write transfers may further improve bandwidth.

[0015] Interface circuits 112 and 114 may include master and / or slave interface circuits. For example, interface circuit 112 may include a master interface circuit that enables circuit block 108 to initiate communication (e.g., a memory access request) with other endpoints (e.g., circuit block 110), and interface circuit 114 may include a slave interface circuit that enables circuit block 110 to service requests from other endpoints (e.g., circuit block 108). Interface circuit 112 may further include a slave interface circuit that enables circuit block 108 to service requests from other endpoints. Exemplary master and slave interface circuits are provided below with reference to FIGS. 2-4. However, interface circuits 112 and 114 are not limited to master and / or slave circuits.

[0016] Interface circuits 112 and 114 may comply with a point-to-point protocol, such as, but not limited to, the Advanced eXtensible Interface (AXI) on-chip communication bus protocol developed by ARM of Cambridge, UK.

[0017] FIG. 2 is a block diagram of an interface circuit 112 including a NoC master unit (NMU) 200 according to an embodiment. The output path of the NMU 200 includes a master interface circuit 202 that interfaces with the circuit block 108. The master interface circuit 202 may include an AXI master interface. The output path further includes a packetization circuit 204, an address map 206, a read re-tag buffer 208, a quality-of-service (QoS) ordering control circuit 210, a VC mapping circuit 212, and a rate matching and asynchronous data boundary crossing circuit 214. The response path of the NMU 200 includes a rate matching and asynchronous data boundary crossing circuit 214, a rearrangement circuit 216, a de-packetization circuit 218, an address map 206, and a master interface circuit 202. The operation of the NMU 200 is further described below with reference to FIG. 4. The interface circuit 112 may further include a NoC slave unit (NSU) as described below with reference to FIG. 3.

[0018] FIG. 3 is a block diagram of an interface circuit 114 including a NoC slave unit (NSU) 300 according to an embodiment. The input path of the NSU 300 includes a de-packetization circuit 302, a rate matching and asynchronous data boundary crossing circuit 304, and a slave interface circuit 306 that interfaces with the circuit block 110. The slave interface circuit 306 may conform to the AXI protocol. The slave interface circuit 306 may include an AXI slave interface. The response path of the NSU 300 includes a slave interface circuit 306, a rate matching and asynchronous data boundary crossing circuit 304, a packetization circuit 308, and a QoS circuit 310. The operation of the NSU 300 is further described below with reference to FIG. 4. The interface circuit 114 may further include an NMU.

[0019] Figure 4 illustrates a communication path through a packet-switched NoC between circuit block 108 and circuit block 110 according to one embodiment. In the example in Figure 4, interface circuit 112 includes an NMU 200, and interface circuit 114 includes an NSU 300. In this example, circuit block 108 functions as the master, and circuit block 110 functions as the slave. Figure 4 describes below the read and write operations initiated by circuit block 108 and directed to circuit block 110.

[0020] When NMU 200 receives a read request from circuit block 108, it packets the read request and forwards the packetized read request to destination NSU 300 via NPS 120-1. NMU 200 may perform one or more of the following functions: The NSU 300 may perform asynchronous crossing and rate matching (e.g., from the AXI master clock domain to the packet-switched NoC clock domain), destination lookup to the destination NSU 300, address remapping (in the virtual case), AXI translation of read requests from the AxSizeMaster protocol to the AxSizeNoC protocol (AxAddr, AxSize, AxLen, AxBurst, AxCache), read chopping, read tagging and inserting read reorder buffer entries to track out-of-order read data returns, packetizing read requests to NPP, rate limiting and error correction code (ECC) generation, VC mapping, VC arbitration, and / or data bus inversion (DBI) generation.

[0021] In the example in Figure 4, the packetized read request passes through NPS 120-1 to 120-6. NPS 120-1 may perform a destination table lookup for its target output port. NPS 120-1 may also perform Least Recently Used (LRU) arbitration on the output port.

[0022] Upon receiving a packetized read request, the NSU 300 depacketizes the read request packet and provides the depacketized read request to the circuit block 110 based on a point-to-point protocol. The NSU 300 may perform one or more of the following functions: ECC checking and correction, AXI-ID compression and AXI exclusive access monitoring, read chopping for downsizing, read tracker entry insertion to track read data interleaving, AXI conversion of requests from NPP to the NSU 300 protocol (e.g., from AxSizeNoC protocol to AxSizeSlave protocol), asynchronous crossing and rate matching from the packet-switched NoC clock domain to the AXI slave clock domain, and conversion of read requests to the circuit block 110 protocol.

[0023] When the NSU 300 receives a read response from circuit block 110, it packets the response and forwards the packetized response to circuit block 108 via NPS 120-6. The NSU 300 may perform one or more of the following functions: asynchronous crossing and rate matching from the AXI slave clock domain to the clock domain of the packet-switched NoC; AXI conversion of the read response from AxSizeSlave to AxSizeNoC; reassembly of the read data in the read tracker to match AxSizeNoC; packetization of the read response to the NPP of the packet-switched NoC; ECC generation; and VC mapping and VC arbitration.

[0024] Upon receiving a read response packet, the NMU 200 depackets the read response packet and provides the depacketized read response to circuit block 108 based on a point-to-point protocol. The NMU 200 may perform one or more of the following functions: data DBI and ECC check, ECC correction, and depacketization of the read response packet; reassembly and sorting of the read data to the requested order and AxSizeMaster boundary; AXI conversion of the read response data from AxSizeNoC to AxSizeMaster; asynchronous crossing and rate matching from the clock region of the packet-switching NoC to the clock region of the NMU 202.

[0025] When NMU 200 receives a write request from circuit block 108, NMU packets the write request and forwards the packetized write request to destination NSU 300 via NPS 120-1. NMU 200 may perform one or more of the following functions: The NMU 200 may perform asynchronous crossing and rate matching from the NMU 200's clock domain to the packet-switched NoC's clock domain, destination lookup to the destination NSU 300, address remapping (if virtual), AXI conversion of write requests (AxAddr, AxSize, AxLen, AxBurst, AxCache, writestrobe, and writedata) from the AxSizeMaster protocol to the AxSizeNoC protocol, write chopping, single-slave-per-id (SSID) checks for pending write transactions having the same AXI-ID but different NoC destination IDs (DST, abbreviation for destination ID), write tracker entry insertion, packetization of write requests to the NPP, rate limiting, ECC generation, VC mapping, VC arbitration, and DBI generation.

[0026] Upon receiving an NPP-formatted write request packet, the NSU 300 depacketizes the write request packet and provides the depacketized write request to circuit block 110 based on a point-to-point protocol. The NSU 300 may perform one or more of the following functions: depacketization of the write request packet, ECC checking and correction, write chopping for downsizing, write tracker entry insertion, AXI conversion of requests from the AxSizeNoC protocol to the AxSizeSlave protocol, and asynchronous crossing and rate matching from the clock domain of the packet-switched NoC to the clock domain of the NSU 300.

[0027] Upon receiving a write response (e.g., an acknowledgment) from circuit block 110, NSU 300 packets the write acknowledgment and forwards the write packet to NMU 200 via NPS 120-6. NSU 300 may perform one or more of the following functions: asynchronous crossing and rate matching from NSU 300's clock domain to the clock domain of packet-switched NoC; (in the case of write chopping) merging write responses in the write tracker; packetizing write responses according to NPP; generating ECC; and performing VC mapping and VC arbitration.

[0028] Upon receiving a write response packet in NPP format, the NMU 200 depacketizes the write response packet and provides the depacketized write response to circuit block 108 based on the point-to-point protocol. The NMU 200 may perform one or more of the following functions: checking DBI and ECC, correcting and depacketizing ECC, merging write responses (if write chopping is performed during the write request), and asynchronous crossing and rate matching from the clock region of the packet-switched NoC to the clock region of the NMU 200.

[0029] In Figure 1, the IC device 100 may include one or more inter-die buses that provide a communication path between the packet-switched NoCs of IC die 102 and IC die 104. The inter-die buses may be useful to enable one or more circuit blocks of IC die 104 to communicate with one or more endpoints of the packet-switched NoC, examples of which are further provided below.

[0030] The inter-die bus may be synchronized with the packet-switched NoC (e.g., packet-based) or asynchronous with the packet-switched NoC (e.g., point-to-point or AXI-based). The inter-die bus may include master and / or slave circuits. The inter-die bus may be unidirectional or bidirectional (a unidirectional master and / or slave-based inter-die bus may include a unique return path as described with reference to Figures 1-4).

[0031] In one embodiment, the IC die 104 includes a NoC circuit fully integrated with a NoC circuit 106 via one or more inter-die buses to provide a 3D packet-switched NoC. In this example, the circuit block of the IC die 104 is treated as the endpoint of the 3D packet-switched NoC. An example is provided below with reference to Figures 5, 6A-6C, and 7A-7C.

[0032] In another embodiment, the die-to-die bus provides a dedicated communication path between the circuit block of IC die 104 and the packet-switched NoC of IC die 102, thereby treating the circuit block of IC die 104 as an endpoint of the packet-switched NoC. The dedicated communication path may be unidirectional. A unidirectional dedicated die-to-die bus may be useful when the circuit block of an IC die communicates only as a master device (e.g., to access a memory device) or only as a slave device (e.g., a memory device accessed by a master device). A unidirectional dedicated die-to-die bus may save resources (e.g., design resources, power consumption, and / or area of ​​IC die 104) compared to embodiments in which IC die 104 has NoC circuitry. 3D connectivity resources can be particularly costly to implement. Therefore, saving 3D connectivity resources can be particularly useful, and examples of unidirectional buses are further provided below.

[0033] Figure 5 illustrates an IC device 100 according to one embodiment, in which the IC die 104 includes a NoC circuit 502, and the IC device 100 further includes an inter-die bus 504 for providing a three-dimensional (3D) packet-switched NoC. The NoC circuit 502 is fully integrated with the NoC circuit 106, and the NoC circuit 502 is essentially an extension of the NoC circuit 106 and operates synchronously with the NoC circuit 106. The 3D packet-switched NoC may be useful to enable inter-die communication between the circuit blocks of the IC die 102 and the circuit blocks of the IC die 104, and / or to extend routing options for the NoC compiler.

[0034] An IC die may include multiple inter-die buses, which can be useful for further extending routing options for the NoC compiler. For example, the NoC compiler may route NoC communication between circuit blocks 108 and 110 via inter-die bus 504 and one or more additional inter-die buses (for example, based on congestion considerations and / or efficiency). The NoC compiler treats the NPS of IC dies 102 and 104 as being in a common address space.

[0035] In Figure 5, circuit blocks 116 and 118 access the 3D packet-switched NoC via their respective NoC interface circuits 506 and 508 and NPS 120-8 and 120-10, as further described above with reference to Figures 1 to 4. In Figure 5, circuit blocks 108, 110, 116, and 118 may be referred to as endpoints of the 3D packet-switched NoC.

[0036] Furthermore, in Figure 5, the inter-die bus 504 interfaces between NPS 120-12 of IC die 102 and NPS 120-14 of IC die 104. Alternatively, the inter-die bus 504 may interface between another NPS of IC die 102 (e.g., any of NPS 120-1 to 120-6 and 120-n in Figure 2) and / or another NPS of IC die 104 (e.g., NPS 120-8 or 120-10).

[0037] The inter-die bus 504 includes a link 514 (e.g., a metal-filled via) extending between IC dies 102 and 104. The inter-die bus 504 further includes an interface circuit 516 that interfaces link 514 with NPS 120-12, and an interface circuit 520 that interfaces link 514 with NPS 120-14. Communication over link 514 may be synchronous or asynchronous with the clock domain of the 3D packet-switched NoC. Exemplary embodiments of the inter-die bus 504 are provided below with reference to Figures 6A-6C and 7A-7C.

[0038] Figure 6A illustrates an IC device 100 in which an inter-die bus 504 forwards packets from NPS 120-14 to NPS 120-12 in synchronization with a 3D packet switching NoC, according to one embodiment. The example in Figure 6A may be useful when the inter-die bus 504 is used for one-way communication from IC die 104 to IC die 102.

[0039] In Figure 6A, interface circuit 520 includes a driver circuit 602 that drives packets received from NPS 120-14 via link 514, and interface circuit 516 includes a driver circuit 604 that boosts signals received via link 514. Driver circuits 602 and 604 may include high-impedance current driver circuits. Driver circuits 602 and 604 may be useful in overcoming losses associated with link 514.

[0040] Figure 6B illustrates an IC device 100 in which an inter-die bus 504 forwards packets from NPS 120-12 to NPS 120-14 in synchronization with a 3D packet switching NoC, according to one embodiment. The example in Figure 6B may be useful when the inter-die bus 504 is used for one-way communication from IC die 102 to IC die 104.

[0041] In Figure 6B, interface circuit 516 includes a driver circuit 606 that drives packets received from NPS 120-12 via link 514, and interface circuit 520 includes a driver circuit 608 that boosts signals received via link 514. Driver circuits 606 and 608 may include high-impedance current driver circuits.

[0042] Figure 6C illustrates an IC device 100 according to one embodiment, in which the inter-die bus 504 includes the features described above with respect to Figures 6A and 6B. The example in Figure 6C may be useful when the inter-die bus 504 is used for bidirectional communication between IC die 102 and IC die 104.

[0043] In the examples in Figures 6A to 4C, the inter-die bus 504 transmits packets via link 514 in synchronization with the clock domain of the 3D packet-switched NoC. In the examples presented below with reference to Figures 7A to 7C, the inter-die bus 504 transmits depacketized data via link 514 asynchronously with the clock domain of the 3D packet-switched NoC (e.g., via a point-to-point protocol). The synchronous examples in Figures 6A to 6C may utilize fewer links 514 than the asynchronous examples in Figures 7A to 7C, but the asynchronous examples in Figures 7A to 7C may avoid or reduce timing issues between the clock domain of the 3D packet-switched NoC and the clock domain of the inter-die bus 504.

[0044] Figure 7A illustrates an IC device 100 in which, according to one embodiment, the interdie bus 504 depacketizes packets received from NPS 120-12 (for example, converts packets from the NPP of the 3D packet switching NoC to a point-to-point protocol) and asynchronously transmits the point-to-point protocol formatted communication to the clock domain of the 3D packet switching NoC via link 514.

[0045] In the example of Figure 7A, interface circuit 520 includes a master interface circuit 702 that depacketizes packets received from NPS 120-14 (i.e., converts packets from the NPP of the 3D packet-switched NoC to a point-to-point (e.g., AXI) protocol, effectively decoupling the depacketized data from the clock domain of the 3D packet-switched NoC). The master interface circuit 702 may include an NMU as further described above with reference to Figures 2 and 4. Interface circuit 520 further includes a driver circuit 704 that drives the output of the master interface circuit 702 via link 514. The driver circuit 704 may include a high-impedance current driver circuit. Interface circuit 520 may include another driver circuit for the return path (e.g., for read response data and / or write confirmation). In one embodiment, the forward and return paths may use the same 3D connection / wire and may include driver circuits for each direction. Alternatively, the forward and return paths may use their respective dedicated 3D connections / wires of link 514.

[0046] Furthermore, in the example of Figure 7A, the interface circuit 516 includes a driver circuit 706 that boosts the signal received via link 514. The driver circuit 706 may include a high-impedance current driver circuit. The driver circuit 706 may be omitted in some embodiments. The interface circuit 516 further includes a slave interface circuit 708 that packetizes the output of the driver circuit 706 (for example, converting the output of the driver circuit 706 from NPP to point-to-point protocol in 3D switch packet No.C). The slave interface circuit 708 may include an NSU as further described above with reference to Figures 3 and 4.

[0047] Figure 7B illustrates an IC device 100 according to one embodiment, in which the interdie bus 504 depacketizes packets received from NPS 120-12 (for example, converts NPP packets of 3D packet switching NoC to point-to-point protocol) and asynchronously transmits point-to-point protocol format signals to the clock domain of 3D packet switching NoC via link 514.

[0048] In the example of Figure 7B, interface circuit 516 includes a master interface circuit 710 that depacketizes packets received from NPS 120-12. The master interface circuit 710 may include an NMU as further described above with reference to Figures 2 and 4. Interface circuit 516 further includes a driver circuit 712 that drives the output of the master interface circuit 710 via link 314. The driver circuit 712 may include a high-impedance driver circuit.

[0049] Furthermore, in the example of Figure 7B, the interface circuit 520 includes a driver circuit 714 that boosts the signal received via link 514. The driver circuit 714 may include a high-impedance driver circuit. The driver circuit 714 may be omitted in some embodiments. The interface circuit 520 further includes a slave interface circuit 716 that packetizes the output of the driver circuit 714 (for example, converting from point-to-point protocol to 3D switched packet No.C NPP). The slave interface circuit 716 may include an NSU as further described above with reference to Figures 3 and 4.

[0050] Figure 7C illustrates an IC device 100 according to one embodiment, in which the inter-die bus 504 includes the features described above with respect to Figures 7A and 7B. In the example of Figure 7C, the inter-die bus 504 transmits depacketized data between NPS 120-12 and NPS 120-14 bidirectionally and asynchronously to the clock domain of the 3D packet switching NoC.

[0051] In Figures 7A, 7B, and / or 7C, the bandwidth of the inter-die bus 504 may be configurable (for example, to utilize a selectable number of links 514). Configuration parameters may be provided to interface circuits 516 and / or 520. Bandwidth configurability may be useful to match the bandwidth of the inter-die bus 504 to the bandwidth of the 3D packet-switched No-C, for example, when the transmission rate of the inter-die bus 504 differs from that of the 3D packet-switched No-C. For example, but not limited to, the inter-die bus 504 may be configurable to a transmission rate of 128 bits per cycle or 256 bits per cycle. If the 3D packet-switched No-C operates at 1 GHz with a transmission rate of 128 bits per cycle and the inter-die bus transmits at 500 MHz over link 514, the inter-die bus 504 may be configured for a transmission rate of 256 bits per cycle.

[0052] Figure 8 illustrates an IC device 100 according to one embodiment, further including an inter-die bus 802 that provides a dedicated asynchronous communication path between circuit block 116 on IC die 104 and the packet-switched NoC on IC die 102, such that circuit block 116 functions as the endpoint of the packet-switched NoC. The IC device 100 may include one or more additional inter-die buses, such as an inter-die bus 810 that provides a dedicated asynchronous communication path between circuit block 118 on IC die 104 and the packet-switched NoC on IC die 102.

[0053] In the example of Figure 8, the inter-die bus 802 includes a link 804 (e.g., a metal-filled via) extending between IC die 102 and IC die 104. The inter-die bus 802 further includes an interface circuit 806 that interfaces link 804 with the NPS 120-16 of NoC circuit 106. The inter-die bus 802 further includes an interface circuit 808 that interfaces link 804 with circuit block 116. The inter-die bus 802 is further described below with reference to Figure 9A.

[0054] Furthermore, in the example of Figure 8, the inter-die bus 810 includes a link 824 (e.g., a metal-filled via) extending between IC die 102 and IC die 104. The inter-die bus 810 further includes an interface circuit 820 that interfaces link 824 with NPS 120-18 of NoC circuit 106. The inter-die bus 810 further includes an interface circuit 822 that interfaces link 824 with circuit block 115. The inter-die bus 810 is further described below with reference to Figure 9B.

[0055] Figure 9A illustrates an IC device 100 in one embodiment in which an inter-die bus 802 provides a unidirectional asynchronous path from circuit block 116 to packet switching NoC of IC die 102. The example in Figure 9A may represent a situation in which circuit block 116 acts as a master device.

[0056] In the example in Figure 9A, circuit block 116 includes an interface circuit 903 that translates the output of circuit block 116 from the protocol of circuit block 116 to the point-to-point (e.g., AXI) protocol of output 916, which is asynchronous with the NPP of the packet-switched NoC of IC die 102. Interface circuit 903 may include an AXI master interface. (In Figures 1, 5, and / or 8, one or more other circuit blocks of IC device 100 may include interface circuits similar to interface circuit 903).

[0057] Furthermore, in the example of Figure 9A, the interface circuit 808 includes a driver circuit 904 that drives the output 902 via link 804. The driver circuit 904 may include a high-impedance current driver circuit.

[0058] Furthermore, in the example of Figure 9A, the interface circuit 806 includes a driver circuit 906 that boosts the signal received via link 804. The driver circuit 906 may include a high-impedance current driver circuit. The driver circuit 906 may be omitted in some embodiments. The interface circuit 806 further includes a slave interface circuit 908 that packetizes the output of the driver circuit 906. The slave interface circuit 908 may include an NSU with an AXI slave interface, as further described above with respect to the NSU 300 in Figure 3.

[0059] Figure 9B illustrates an IC device 100 in one embodiment in which an inter-die bus 810 provides a unidirectional asynchronous path from packet switching No.C on IC die 102 to circuit block 118 on IC die 104. The example in Figure 9B may represent a situation in which circuit block 118 functions as a slave device.

[0060] In the example of Figure 9B, interface circuit 820 includes a master interface circuit 910 that depacketizes packets received from NPS 120-18 (for example, into a point-to-point protocol). The master interface circuit 910 may include an NMU with an AXI master interface as further described above with respect to the NMU 200 in Figure 2. Interface circuit 820 further includes a driver circuit 912 that drives the output of the master interface circuit 910 via link 824. The driver circuit 912 may include a high-impedance current driver circuit.

[0061] Furthermore, in the example of Figure 9B, the interface circuit 822 includes a driver circuit 914 that boosts the signal received via link 824. The driver circuit 914 may include a high-impedance current driver circuit. The driver circuit 914 may be omitted in some embodiments.

[0062] Furthermore, in the example of Figure 9B, circuit block 118 includes an interface circuit 915 that converts the output 916 of the driver circuit 914 from a point-to-point protocol to the protocol of circuit block 118. Interface circuit 903 may include an AXI master interface.

[0063] In Figure 1, the IC device 100 may include a combination of die buses disclosed herein.

[0064] IC die 102 and / or IC die 104, or a portion thereof, may include one or more of various types of configurable circuit blocks, as described below with reference to Figure 10. Figure 10 is a block diagram of a configurable circuit 1000, including an array of configurable or programmable circuit blocks or tiles, according to one embodiment. An example in Figure 10 may represent other IC devices that utilize configurable interconnection structures for selectively combining circuit / logic elements, such as field programmable gate arrays (FPGAs) and / or complex programmable logic devices (CPLDs).

[0065] For example, in the example in Figure 10, the tile includes a multi-gigabit transceiver (MGT) 1001, a configurable logic block (CLB) 1002, a block random access memory (BRAM) 1003, an input / output block (IOB) 1004, configuration and clocking logic (Config / Clocks) 1005, a digital signal processing (DSP) block 1006, a specialized input / output block (I / O) 1007 (e.g., a configuration port and a clock port), and other programmable logic 1008 (which may include, but is not limited to, a digital clock manager, an analog-to-digital converter, and / or system monitoring logic). The tile further includes a dedicated processor 1010.

[0066] One or more tiles may include a programmable interconnect element (INT) 1011 having connections to input and output terminals 1020 of programmable logic elements within the same tile, and / or to one or more other tiles. A programmable INT 1011 may include connections to interconnect segments 1022 of other programmable INTs 1011 within the same tile and / or other tiles. A programmable INT 1011 may include connections to interconnect segments 1024 of general-purpose routing resources between logic blocks (not shown). A general-purpose routing resource may include routing channels between logic blocks (not shown) containing tracks of interconnect segments (e.g., interconnect segment 1024) and switch blocks (not shown) for connecting interconnect segments. An interconnect segment of a general-purpose routing resource (e.g., interconnect segment 1024) may span one or more logic blocks. A programmable INT 1011, in combination with a general routing resource, may represent a programmable interconnect structure.

[0067] CLB1002 may include a configurable logic element (CLE) 1012 that can be programmed to implement a user logic circuit. CLB 1002 may also include a programmable INT 1011.

[0068] BRAM 1003 may include BRAM logic elements (BRL) 1013 and one or more programmable INTs 1011. The number of interconnected elements included in a tile may vary depending on the height of the tile. BRAM 1003 may have a height of, for example, five CLBs 1002. Other numbers (e.g., four) may also be used.

[0069] The DSP block 1006 may include one or more programmable INTs 1011 in addition to DSP logic elements (DSPLs) 1014. The IOB 1004 may include, for example, one or more instances of programmable INTs 1011 in addition to two instances of input / output logic elements (IOLs) 1015. For example, the I / O pads connected to the I / O logic element 1015 are not necessarily limited to the area of ​​the I / O logic element 1015.

[0070] In the example in Figure 10, the configuration / clock 1005 may be used for configuration, clock, and / or other control logic. The vertical column 1009 may be used to distribute the clock and / or configuration signals.

[0071] Logical blocks (e.g., programmable with fixed functions) may disrupt the linear structure of the configurable circuit 1000. For example, processor 1010 spans several columns of CLB 1002 and BRAM 1003. Processor 1010 may include one or more of various components, but is not limited to a single microprocessor, or a complete programmable processing system of a microprocessor, memory controller, and / or peripherals.

[0072] In Figure 10, the configurable circuit 1000 further includes an analog circuit 1050, which may include, but is not limited to, one or more analog switches 107, a multiplexer, and / or a demultiplexer. The analog switch 107 may be useful for reducing leakage current.

[0073] Figure 10 is provided for illustrative purposes only. The configurable circuit 1000 is not limited to the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the type of logic blocks contained in the rows, the relative size of the logic blocks, the illustrated interconnection / logic implementation, or other exemplary features of Figure 10.

[0074] The embodiments presented in this disclosure are referenced above. However, the scope of this disclosure is not limited to the specific embodiments described. Rather, any combination of the features and elements described is intended to implement and practice the intended embodiments, whether or not they relate to different embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aforementioned aspects, features, embodiments, and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims.

[0075] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, which may all be collectively referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0076] Any combination of one or more computer-readable media may be used. A computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any preferred combination thereof. More specific examples (non-exclusive list) of computer-readable storage media include an electrical connection with one or more wires, a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any preferred combination thereof. In the context of this specification, a computer-readable storage medium is any tangible medium that contains or can store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0077] A computer-readable signal medium may include, for example, a propagating data signal in which computer-readable program code is embodied, either in the baseband or as part of a carrier wave. Such a propagating signal may take any of various forms, including but not limited to electromagnetic, optical, or any preferred combination thereof. A computer-readable signal medium may be any computer-readable medium, rather than a computer-readable storage medium, that can communicate, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device.

[0078] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, or any preferred combination thereof.

[0079] Computer program code for performing the operations of the embodiments of this disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The program code may run entirely on the user's computer, partially as a standalone software package on the user's computer, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet Service Provider).

[0080] Aspects of the present disclosure are described below with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments presented herein. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device such that instructions executed via the processor of the computer or other programmable data processing device result in a machine that creates means for implementing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0081] These computer program instructions may also be stored in computer-readable storage media, and the instructions may also instruct computers, programmable data processing devices, and / or other devices to function in a particular manner, such as to produce products containing instructions that implement functions / actions specified in blocks of flowcharts and / or block diagrams.

[0082] Computer program instructions can also be loaded into a computer, other programmable data processing device, or other device to perform a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process. Thus, instructions executed on a computer or other programmable device provide a process for implementing the functions / actions specified in the blocks of a flowchart and / or block diagram.

[0083] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in a different order than shown in the figure. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs a specified function or action or a combination of dedicated hardware and computer instructions.

[0084] The technology disclosed above can be illustrated in the following non-limiting examples.

[0085] Example 1. An integrated circuit (IC) device comprising: a first vertically stacked IC die and a second vertically stacked IC die, the first IC die comprising a network-on-chip (NoC) circuit; and an inter-die bus configured to interface between the packet-switching NoC and the second IC die, the inter-die bus comprising a first driver circuit coupled to the inter-die link of the inter-die bus.

[0086] Example 2. The IC device according to Example 1, wherein the first driver circuit is further configured to drive packets via an inter-die link in synchronization with the NoC circuit.

[0087] Embodiment 3. The IC device according to Embodiment 1, wherein the inter-die bus is further configured to depacketize requests, and the first driver circuit is further configured to drive the depacketized requests via an asynchronous inter-die link with the NoC circuit.

[0088] Embodiment 4. The IC device according to Embodiment 3, wherein the inter-die bus is further configured to depacketize requests based on a point-to-point protocol, and the first driver circuit is further configured to drive the depacketized requests over the inter-die link based on a point-to-point protocol.

[0089] Example 5. The IC device according to Example 4, wherein the interdie bus further includes a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel.

[0090] Example 6. The IC device described in Example 1, wherein the die bus is configured as a one-way die bus.

[0091] Example 7. The IC device described in Example 1, wherein the die bus is configured as a bidirectional die bus.

[0092] Example 8. The IC device according to Example 1, further comprising one or more additional inter-die buses configured to interface between a packet-switching No.C and a second IC die.

[0093] Embodiment 9. The IC device according to Embodiment 1, wherein the first IC die further comprises a first interface circuit for an inter-die bus and a first NoC packet switch (NPS), the first interface circuit comprising a first master interface circuit configured to receive a first request from the first NPS and depacketize the first request based on a point-to-point protocol, and the first interface circuit further comprises a first driver circuit, the first driver circuit further configured to drive the depacketized first request via the inter-bus link asynchronously with the NoC circuit.

[0094] Example 10. The IC device according to Example 9, wherein the second IC die comprises a second interface circuit for an inter-die bus and a second NPS, the second interface circuit comprising a first slave interface circuit configured to receive a depacketized first request over the inter-die link, repacket the depacketized first request, and forward the repacketized first request to the second NPS.

[0095] Example 11. The IC device according to Example 10, further comprising a second driver circuit coupled between the die-to-die link and the slave interface circuit as the second interface circuit.

[0096] Example 12. The IC device according to Example 10, wherein the second interface circuit further comprises a second master interface circuit configured to receive a second request from a second NPS and depacketize the second request based on a point-to-point protocol, and the second interface circuit further comprises a second driver circuit, the second driver circuit configured to drive the depacketized second request via the inter-bus link asynchronously with the packet-switched NoC.

[0097] Example 13. The IC device according to Example 12, further comprising a second slave interface circuit configured to receive a second request that has been depacked via an interdie link, repacket the depacked second request, and forward the repacked request to the first NPS.

[0098] Example 14. The IC device according to Example 13, wherein the first interface circuit further comprises a third driver circuit coupled between the die-to-die link and the slave interface circuit.

[0099] Example 15. The IC device according to Example 1, wherein the first IC die further comprises a first interface circuit for an inter-die bus and a NoC packet switch (NPS), and the second IC die further comprises a circuit block configured to output requests based on a point-to-point protocol and a second interface circuit for an inter-die bus, the second interface comprising a first driver circuit, the first driver circuit further configured to drive requests via an asynchronous inter-die link with a packet-switched NoC, and the first interface circuit comprising a NoC slave unit (NSU) configured to receive requests via the inter-die link, packetize the requests, and forward the packetized requests to the NPS.

[0100] Example 16. The IC device according to Example 1, wherein the first IC die further comprises a first interface circuit of an inter-die bus configured to receive packetized requests from a NoC packet switch (NPS) of a NoC circuit, the first interface circuit comprising a NoC master unit (NMU) configured to depacketize requests based on a point-to-point protocol, the first interface circuit further comprising a first driver circuit configured to drive the depacketized requests over an inter-die link, and the second IC die further comprises a second interface circuit of the inter-die bus, the second interface configured to provide the depacketized requests to a circuit block of the second IC die.

[0101] Example 17. The IC device according to Example 16, further comprising a second IC die, a second driver circuit configured to boost depacked requests.

[0102] Example 18. An integrated circuit (IC) device comprising a first vertically stacked IC die and a second vertically stacked IC die, each having a first network-on-chip packet switch and a second network-on-chip (NoC) packet switch (NPS) for a three-dimensional (3D) packet-switching NoC, and an inter-die bus configured to interface between the 3D packet-switching NoC and the asynchronous first and second NPS, wherein the inter-die bus comprises driver circuits coupled to the inter-die links of the inter-die bus.

[0103] Example 19. The IC device according to Example 18, wherein the first IC die and the second IC die further comprise a first interface circuit and a second interface circuit of an inter-die bus, respectively, and the first interface circuit and the second interface circuit are configured to communicate over an inter-die link based on a point-to-point protocol.

[0104] Example 20. An integrated circuit (IC) device comprising a first vertically stacked IC die and a second vertically stacked IC die, wherein the first IC die includes a network-on-chip (NoC) packet switch (NPS) for packet switching NoC, and a dedicated inter-die bus configured to interface between the NPS and a circuit block of the second IC die asynchronously with respect to a point-to-point protocol, wherein the inter-die bus includes a driver circuit coupled to the inter-die link of the inter-die bus.

[0105] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. Integrated circuit (IC) device, A first vertically stacked IC die and a second vertically stacked IC die, wherein the first IC die includes a network-on-chip (NoC) circuit, An integrated circuit (IC) device comprising: an inter-die bus configured to interface between a packet-switched No.C and the second IC die, wherein the inter-die bus comprises a first driver circuit coupled to an inter-die link of the inter-die bus.

2. The IC device according to claim 1, wherein the first driver circuit is further configured to drive packets via the die link in synchronization with the NoC circuit.

3. The IC device according to claim 1, wherein the inter-die bus is further configured to depacketize requests, and the first driver circuit is further configured to drive the depacketized requests via the inter-die link asynchronous with the NoC circuit.

4. The IC device according to claim 3, wherein the inter-die bus is further configured to depacketize the requests based on a point-to-point protocol, and the first driver circuit is further configured to drive the depacketized requests via the inter-die link based on the point-to-point protocol.

5. The IC device according to claim 1, wherein the inter-die bus is configured as a one-way inter-die bus.

6. The IC device according to claim 1, wherein the inter-die bus is configured as a bidirectional inter-die bus.

7. The IC device according to claim 1, further comprising one or more additional inter-die buses configured to interface between the packet switching No.C and the second IC die.

8. The first IC die further comprises a first interface circuit for the inter-die bus and a first NoC packet switch (NPS), The first interface circuit comprises a first master interface circuit configured to receive a first request from the first NPS and depacketize the first request based on a point-to-point protocol. The IC device according to claim 1, wherein the first interface circuit further comprises the first driver circuit, the first driver circuit further configured to drive the depacked first request via the inter-bus link asynchronously with the NoC circuit.

9. The second IC die comprises a second interface circuit for the inter-die bus and a second NPS, The IC device according to claim 8, wherein the second interface circuit comprises a first slave interface circuit configured to receive the depacked first request via the die link, repackage the depacked first request, and forward the repackaged first request to the second NPS.

10. The first IC die further comprises a first interface circuit for the inter-die bus and a NoC packet switch (NPS), The second IC die further comprises a circuit block configured to output requests based on a point-to-point protocol, and a second interface circuit for the inter-die bus, the second interface comprising the first driver circuit, the first driver circuit further configured to drive the requests via the inter-die link asynchronous with the packet-switched NoC. The IC device according to claim 1, wherein the first interface circuit comprises a NoC slave unit (NSU) configured to receive the request via the die link, packetize the request, and forward the packetized request to the NPS.

11. The first IC die further comprises a first interface circuit of the inter-die bus configured to receive packetized requests from the NoC packet switch (NPS) of the NoC circuit, the first interface circuit comprising a NoC master unit (NMU) configured to depacketize the requests based on a point-to-point protocol, and the first interface circuit further comprising a first driver circuit configured to drive the depacketized requests via the inter-die link. The IC device according to claim 1, wherein the second IC die further comprises a second interface circuit of the inter-die bus, the second interface configured to provide the depacked requests to the circuit block of the second IC die.

12. The IC device according to claim 11, wherein the second IC die further comprises a second driver circuit configured to boost the depacked requests.

13. Integrated circuit (IC) device, A first vertically stacked IC die and a second vertically stacked IC die each comprising a first network-on-chip packet switch and a second network-on-chip (NoC) packet switch (NPS) for three-dimensional (3D) packet switching NoC, An integrated circuit (IC) device comprising: an inter-die bus configured to interface between the 3D packet switching NoC and the asynchronous first NPS and second NPS, wherein the inter-die bus comprises driver circuits coupled to the inter-die links of the inter-die bus.

14. The IC device according to claim 13, wherein the first IC die and the second IC die further comprise the first interface circuit and the second interface circuit of the inter-die bus, respectively, and the first interface circuit and the second interface circuit are configured to communicate over the inter-die link based on a point-to-point protocol.

15. Integrated circuit (IC) device, The first vertically stacked IC die and the second vertically stacked IC die, wherein the first IC die includes a packet-switched network-on-chip (NoC) NoC packet switch (NPS), An integrated circuit (IC) device comprising: a dedicated die bus configured to interface between the NPS and a second IC die circuit block asynchronous with the packet-switched NoC, based on a point-to-point protocol, wherein the die bus includes a driver circuit coupled to the die link of the die bus.

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