Power amplifier

Abstract

To provide an improved power amplifier that can prevent an excessive bias current from flowing through a circuit structure and protect it from damage. [Solution] A power amplifier 100 includes an input terminal RFIN, an output terminal RFOUT, a first amplifier circuit PA1, a second amplifier circuit PA3, a bias circuit, a current detection circuit 110, and a first protection circuit 120. The first amplifier circuit includes a first signal input terminal IN1 and a first signal output terminal OUT1 coupled to the input terminal. The first amplifier circuit amplifies a radio frequency signal received from the input terminal. The second amplifier circuit amplifies a radio frequency signal received from the first signal output terminal. The bias circuit outputs a bias current to the second amplifier circuit. The current detection circuit generates a digital control signal VOCP according to the bias current. The first protection circuit selectively reduces the radio frequency signal input to the first signal input terminal according to the digital control signal.

Description

[Technical Field]

[0001] The present disclosure relates to a power amplifier and a circuit protection method. [Background technology]

[0002] Power amplifiers are applied in many circuit-related technical fields, such as wireless communication technology. Radio frequency transmission circuits in wireless communication technology include power amplifiers to amplify radio signals transmitted to a back-end transmitting antenna. Power amplifiers are an important component of radio frequency transmission circuits, but they consume very high power and can be easily damaged by many factors (e.g., unstable input voltages and load mismatches, which can cause radio frequency signals to bounce back and form reflected standing waves, resulting in a power amplifier failing to reach the transmitting antenna). Therefore, how to protect power amplifiers to ensure normal operation and prevent damage has become a major research area. Summary of the Invention

[0003] The present disclosure provides a power amplifier and a circuit protection method that protects the entire power amplifier by preventing circuit damage in the power amplifier using a current detection circuit and a protection circuit.

[0004] A power amplifier according to an embodiment of the present disclosure includes an input terminal, an output terminal, a first amplifier circuit, a second amplifier circuit, a bias circuit, a current detection circuit, and a first protection circuit. The input terminal is used to input a radio frequency signal. The output terminal is used to output an amplified radio frequency signal. The first amplifier circuit includes a first signal input terminal coupled to the input terminal and a first signal output terminal. The first amplifier circuit is used to amplify the radio frequency signal received from the input terminal. The second amplifier circuit includes a second signal input terminal coupled to the first signal output terminal and a second signal output terminal. The second amplifier circuit is used to amplify the radio frequency signal received from the first signal output terminal. The bias circuit is used to output a bias current to the second amplifier circuit. The current detection circuit is coupled to the bias circuit and the second amplifier circuit. The current detection circuit is used to generate a digital control signal according to the bias current. The first protection circuit is coupled between the input terminal of the power amplifier and the first signal input terminal of the first amplifier circuit. The first protection circuit selectively reduces the radio frequency signal input to the first signal input terminal in accordance with the digital control signal.

[0005] A circuit protection method according to an embodiment of the present disclosure includes the following steps: providing a power amplifier; the power amplifier including a first amplifier circuit, a second amplifier circuit, and a bias circuit; the first amplifier circuit and the second amplifier circuit connected in series to amplify a radio frequency signal received from an input terminal; and the bias circuit outputting a bias current to the second amplifier circuit; a current detection circuit generating a digital control signal according to the bias current; and a first protection circuit selectively reducing the radio frequency signal input to the first signal input terminal of the power amplifier according to the digital control signal. The first protection circuit is coupled between the input terminal of the power amplifier and the first signal input terminal of the first amplifier circuit.

[0006] A power amplifier according to an embodiment of the present disclosure includes an input terminal, an output terminal, an amplifier circuit, a bias circuit, a current detection circuit, and a first protection circuit. The input terminal is used to input a radio frequency signal. The output terminal is used to output an amplified radio frequency signal. The amplifier circuit includes a first signal input terminal coupled to the input terminal and a first signal output terminal. The amplifier circuit is used to amplify the radio frequency signal received from the input terminal. The bias circuit is used to output a bias current to the amplifier circuit. The current detection circuit is coupled to the signal input terminal. The current detection circuit is used to generate a digital control signal according to the bias current. The first protection circuit is coupled between the input terminal of the power amplifier and the signal input terminal of the amplifier circuit. The first protection circuit is used to selectively reduce the radio frequency signal input to the signal input terminal according to the digital control signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit block diagram of a power amplifier according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit schematic diagram of an amplifier circuit PA3, a bias circuit BIAS3, and a current detection circuit according to the first embodiment of the present disclosure. [Figure 3A] FIG. 3A is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 3C] FIG. 3C is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 3D] FIG. 3D is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 3E] FIG. 3E is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 3F] FIG. 3F is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 4A] FIG. 4A is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to one embodiment of the present disclosure. [Figure 4B] FIG. 4B is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 4C] FIG. 4C is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a first protection circuit according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a circuit block diagram of a power amplifier according to the second embodiment of the present disclosure. [Figure 6] FIG. 6 is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a second protection circuit according to a first sub-embodiment of the second embodiment of the present disclosure. [Figure 7] FIG. 7 is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, a second protection circuit, and a third protection circuit according to a second subembodiment of the second embodiment of the present disclosure. [Figure 8] FIG. 8 is a circuit block diagram of a power amplifier according to the third embodiment of the present disclosure. [Figure 9] FIG. 9 is a circuit block diagram of a power amplifier according to a fourth embodiment of the present disclosure. [Figure 10] FIG. 10 is a flowchart of a circuit protection method according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] To protect the power amplifier from damage caused by sudden large current or large power, one embodiment of the present disclosure adds a current detection circuit to a bias circuit of a final stage amplifier circuit of the power amplifier to determine whether the bias current provided by the bias circuit of the final stage amplifier circuit is too large. Furthermore, if it is determined that the bias current is larger than a threshold, a control signal (e.g., a digital control signal VOCP) can be used to activate one or more protection circuits of a first stage amplifier circuit disposed in the power amplifier, thereby reducing the amplification gain of the first stage amplifier circuit or reducing the bias current of the first stage amplifier circuit, thereby preventing excessive bias current from flowing through the circuit structure of the power amplifier and protecting the power amplifier from damage.

[0009] Power amplifiers adapted for various applications according to embodiments of the present disclosure may have one or more amplifier circuit stages. For convenience of explanation, the power amplifier 100 of FIG. 1 is based on a three-stage amplifier circuit as an example. Other embodiments of the present disclosure also include a power amplifier with a two-stage amplifier circuit (e.g., FIG. 8) or a power amplifier with a one-stage amplifier circuit (e.g., FIG. 9). Those applying the present embodiment may apply it to power amplifiers with different numbers of amplifier circuits as needed.

[0010] 1 is a circuit block diagram of a power amplifier 100 according to a first embodiment of the present disclosure. The power amplifier 100 mainly includes an input terminal RFIN, an output terminal RFOUT, a three-stage amplifier circuit (for example, amplifier circuits PA1, PA2, and PA3 in FIG. 1), bias circuits BIAS1 to BIAS3 corresponding to each stage of the amplifier circuit, a current detection circuit 110, and a first protection circuit 120.

[0011] The input terminal RFIN is used to input a radio frequency signal RF. The output terminal RFOUT is used to output the radio frequency signal amplified by the amplifier circuits PA1 to PA3. The amplifier circuit PA1 includes a signal input terminal IN1 coupled to the input terminal RFIN, a bias terminal NB1, and a signal output terminal OUT1. The amplifier circuit PA1 is used to amplify the radio frequency signal RF received from the input terminal RFIN and provide the amplified signal to the signal output terminal OUT1.

[0012] The amplifier circuit PA2 includes a signal input terminal IN2 coupled to the signal output terminal OUT1, a bias terminal NB2, and a signal output terminal OUT2, and is used to amplify the radio frequency signal received from the signal input terminal IN2 and provide it to the signal output terminal OUT2.

[0013] The amplifier circuit PA3 includes a signal input terminal IN3 coupled to the signal output terminal OUT2 by the amplifier circuit PA2. The amplifier circuit PA3 also includes a bias terminal NB3 and a signal output terminal OUT3. The amplifier circuit PA3 is used to amplify the radio frequency signal received from the signal output terminal OUT2 and provide it to the signal output terminal OUT3.

[0014] The bias circuits BIAS1 to BIAS3 are used to output bias currents IBIAS1 to IBIAS3 to the corresponding amplifier circuits PA1 to PA3 via the corresponding output terminals VBOUT1 to VBOUT3, respectively.

[0015] The current detection circuit 110 is coupled to the bias circuit BIAS3 and the amplifier circuit PA3. The current detection circuit 110 generates a digital control signal VOCP according to the bias current IBIAS3. In this embodiment, the current detection circuit 110 is disposed in the bias circuit BIAS3. However, those who apply this embodiment may dispose the current detection circuit 110 in other locations as needed, as long as the current detection circuit 110 can detect the bias circuit BIAS3.

[0016] The first protection circuit 120 is coupled between the input terminal RFIN of the power amplifier 100 and the signal input terminal IN1 of the amplifier circuit PA. The first protection circuit 120 selectively reduces the radio frequency signal input to the signal input terminal IN1 in accordance with a digital control signal VOCP. That is, the first protection circuit can attenuate the input power of the power amplifier 100 at the input terminal RFIN based on the digital control signal VOCP. The first protection circuit 120 includes a termination N120-1 coupled to the signal input terminal IN1 and a termination N120-2 coupled to a reference voltage terminal (e.g., ground terminal).

[0017] The power amplifier 100 also includes a voltage generator 130, an input matching circuit 140, inter-stage matching circuits 150 and 152, and an output matching circuit 155. The voltage generator 130 generates reference voltages VREF and VREFP from a first voltage (e.g., a system voltage VCCB) in accordance with a power amplifier enable signal PAEN. The bias circuits BIAS1 to BIAS3 generate bias currents IBIAS1 to IBIAS3 based on the reference voltages VREF and VREFP, respectively. Each matching circuit (i.e., the input matching circuit 140, the inter-stage matching circuits 150 and 152, and the output matching circuit 155) has a circuit structure configured based on a stable signal and may be implemented by one or a combination of passive elements (e.g., resistors, capacitors, and inductors) and active elements (e.g., transistors).

[0018] 2 is a circuit schematic diagram of an amplifier circuit PA, a bias circuit BIAS, and a current detection circuit 110 according to a first embodiment of the present disclosure. FIG. 2 shows a detailed circuit structure of the current detection circuit 110. The current detection circuit 110 mainly includes a current detector 210. The current detector 210 is coupled to the bias circuit BIAS and the amplifier circuit PA3. The output terminal RFOUT of FIG. 2 is coupled to an antenna ANTA. The antenna ANTA is, for example, a transmitting antenna.

[0019] The amplifier circuit PA3 mainly includes a transistor Qrf3 and corresponding passive elements (e.g., a resistor RB3, RE3, a capacitor CBE3, and an inductor Lrf3). The input terminal RFIN3 of the amplifier circuit PA3 functions as the signal input terminal IN3 in FIG. 1, amplifies the radio frequency signal received from the signal output terminal OUT2, and provides it to the signal output terminal of the amplifier circuit PA3. The amplifier circuit PA3 receives a bias current IBIAS3 via the resistor RB3.

[0020] The bias circuit BIAS3 mainly includes a bias transistor Q4, transistors Q5 and Q6, resistors R5 to R8, and a capacitor C2. The bias transistor Q4 generates a bias current IBIAS3 at a node VB3 according to the system voltage VCCB.

[0021] The current detector 210 includes a detection transistor Q1. The current detector 210 also includes a resistor R1. A bias transistor Q4 is coupled to the detection transistor Q1, forming a current mirror architecture. The detection transistor Q1 provides a detection current Isense through the current mirror architecture, and the detection current Isense is related to the bias current IBIAS3. For example, in this embodiment, the size ratio of the bias transistor Q4 to the detection transistor Q1 is equal to the ratio of the current value of the current flowing through a resistor R5 (coupled between the bias transistor Q4 and the node providing the system voltage VCCB) to the current value of the detection current Isense, and the sum of the current value of the current flowing through the resistor R5 and the current value of the detection current Isense is the current value of the bias current IBIAS3. When the bias current IBIAS3 increases (for example, due to a load mismatch in the power amplifier 100, the radio frequency signal is not transmitted to the antenna ANTA, but is reflected back to the amplifier circuit PA, forming a reflected standing wave. The reflected standing wave is, for example, a reflected standing wave SW that may appear in the form of a voltage on the node RF IN B3 in FIG. 2), the voltage value of the base-emitter voltage VBEQ4 of the bias transistor Q4 decreases, and the current value of the current flowing through the resistor R5 increases. The current value of the current flowing through the resistor R5 also reflects the change (increase) in the current value of the detection current Isense according to the size ratio between the bias transistor Q4 and the detection transistor Q1. That is, when the bias current IBIAS3 increases, the current value of the detection current Isense also increases. The resistor R1 has a voltage drop ΔV based on the detection current Isense.

[0022] The current detection circuit 110 further includes a logic circuit 220. The logic circuit 220 includes an input terminal IN220 and an output terminal OUT220. The input terminal IN220 of the logic circuit 220 is coupled to the detection transistor Q1. The logic circuit 220 generates a digital control signal VOCP at the output terminal OUT220 according to the detection current Isense. In addition, the current detector 210 of the current detection circuit 110 further includes a choke inductor L1. The choke inductor L1 is coupled between the input terminal IN220 of the logic circuit 220 and the detection transistor Q1 of the current detector 210. The choke inductor L1 provides high impedance to prevent the radio frequency signal RF from leaking to the outside (such as leakage to the bias circuit BIAS3), thereby preventing the bias voltage generated by the bias circuit BIAS3 from being affected by the logic circuit 220 and stabilizing the function of the amplifier circuit PA3.

[0023] The logic circuit 220 may include a level conversion circuit 230 and a comparison circuit 240. The level conversion circuit 230 is coupled between the detection transistor Q1 and the comparison circuit 240. In this embodiment, the level conversion circuit 230 includes resistors R2 and R3 and a transistor Q2. The level conversion circuit 230 performs level conversion using the detection current Isense and converts a voltage drop ΔV based on the detection current Isense into a voltage at a terminal VF3. The terminal VF3 serves as an output terminal of the level conversion circuit 230. For example, the voltage at the terminal VF3 may be a voltage value obtained by subtracting the voltage drop ΔV and the base-emitter voltage VBEQ2 of the transistor Q2 from the reference voltage VREFP.

[0024] The comparison circuit 240 mainly includes a comparison transistor Q3. Furthermore, the "detection current Isense is greater than the threshold" state can be used to indicate that the bias current IBIAS3 is too large. When the detection current Isense is greater than the threshold, the voltage at the output terminal (terminal VF3) of the level conversion circuit 230 decreases due to an increase in the value of the voltage drop ΔV. This causes the voltage at the output terminal (terminal VF3) of the level conversion circuit 230 to become smaller than the base-emitter voltage VBEQ3 of the transistor Q3. This causes the comparison transistor Q3 to enter an open state, and the logic circuit 220 enables the digital control signal VOCP based on the open state of the comparison transistor Q3. That is, the digital control signal VOCP at this time is, for example, at a high potential. Specifically, when the comparison transistor Q3 is in an open state, both ends of the depletion-mode transistor DFET are conductive, and the reference voltage VREF is introduced to the output terminal OUT220 of the logic circuit 220, thereby enabling the digital control signal VOCP. Thus, if the bias current IBIAS3 is too large, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP. Conversely, if the detection current Isense is less than the threshold, the comparison transistor Q3 is in a conductive state, and the logic circuit 220 disables the digital control signal VOCP based on the conductive state of the comparison transistor Q3. That is, the digital control signal VOCP at this time is, for example, at a low potential. Therefore, if the bias current IBIAS3 is not too large, the output terminal OUT220 of the logic circuit 220 outputs an disabled digital control signal VOCP.

[0025] The comparison circuit 240 also includes a series-connected depletion-mode transistor DFET1 and a resistor R4. The control terminal of the comparison transistor Q is coupled to the output terminal (termination VF3) of the level conversion circuit 230. The control terminal of the depletion-mode transistor DFET1 is coupled to the output terminal OUT220, one terminal of the depletion-mode transistor DFET1 is coupled to a reference voltage VREF, and the other terminal of the depletion-mode transistor DFET1 is coupled to one terminal of a resistor R4. The other terminal of the resistor R4 is coupled to the output terminal OUT220. The depletion-mode transistor DFET1 and the resistor R4 are connected in series to form a circuit structure with high impedance, thereby increasing the detection sensitivity of the detection current Isense in the logic circuit 220. For example, the resistance collectively formed by the depletion-mode transistor DFET1 and the resistor R4 is greater than approximately 1 MΩ. To further explain, when the sense current Isense is below the threshold, i.e., in the normal state where the bias current IBIAS3 is not too large, the voltage between the gate and source of the depletion-mode transistor DFET1 is smaller than the conduction voltage of the depletion-mode transistor DFET1, so the depletion-mode transistor DFET1 remains open. In this case, the resistance formed by the depletion-mode transistor DFET1 and resistor R4 is equal to the resistance between the drain and source of the depletion-mode transistor DFET1 plus the resistance of resistor R4. That is, when the sense current Isense is below the threshold, the depletion-mode transistor DFET1 and resistor R4 collectively form a circuit structure with a high impedance (e.g., greater than 1 MΩ), and the sense-state digital control signal VOCP becomes clearer, thereby increasing the sensitivity of the logic circuit 220 to detect the sense current Isense. On the other hand, if the current value of the sense current Isense increases and becomes greater than the threshold value, the voltage between the gate and source of the depletion-mode transistor DFET1 becomes greater than the conduction voltage of the depletion-mode transistor DFET1, so that the depletion-mode transistor DFET1 remains in the conductive state.In this case, the resistance formed by the depletion-mode transistor DFET1 and the resistor R4 together is equal to the resistance of the resistor R4 alone. Thus, when the sense current Isense is below the threshold, the resistance formed by the depletion-mode transistor DFET1 and the resistor R4 together is greater than the resistance formed by the depletion-mode transistor DFET1 and the resistor R4 together when the sense current Isense is above the threshold.

[0026] The first protection circuit 120 in FIG. 1 reduces the radio frequency signal input to the signal input terminal IN1 according to an enabled digital control signal VOCP. FIGS. 3A-3F and 4A-4C illustrate the function of the first protection circuit 120. FIGS. 3A-3F are circuit schematic diagrams of an amplifier circuit PA1, a bias circuit BIAS1, and first protection circuits 120-1, 120-11, 120-12, 120-13, 120-14, 120-15, according to an embodiment of the present disclosure. In FIGS. 3A-3F, one end (node ​​N120-1) of each of the first protection circuits 120-1, 120-11, 120-12, 120-15 is coupled to the input matching circuit 140 and the input terminal of the amplifier circuit PA1. The other end (node ​​N120-2) of each of the first protection circuits 120-1, 120-11, 120-12, 120-15 is coupled to a reference voltage terminal (e.g., ground terminal).

[0027] The amplifier circuit PA1 mainly includes a transistor Qrf1 and corresponding passive elements (e.g., a resistor RB1, a capacitor CBE1, and an inductor Lrf1). The input terminal of the amplifier circuit PA1 receives a radio frequency signal RF at an input terminal RFIN through an input matching circuit 140, amplifies the radio frequency signal RF, and provides the radio frequency signal RF to a signal output terminal of the amplifier circuit PA1. The amplifier circuit PA1 receives a bias current IBIAS1 through a resistor RB1.

[0028] The terminal N120-1 of the first protection circuit 120-1 is coupled between the input terminal RFIN of the power amplifier and the signal input terminal IN1 of the amplifier circuit PA1 (shown in FIG. 1). The terminal N120-2 of the first protection circuit 120-1 is coupled to a reference voltage terminal (e.g., ground terminal). The first protection circuit 120-1 is used to selectively provide a low-impedance path for the radio frequency signal to the reference voltage terminal in accordance with a digital control signal VOCP so that the radio frequency signal at the terminal N120-1 is guided to the reference voltage terminal (e.g., ground terminal) by the first protection circuit 120, thereby reducing transmission of the radio frequency signal into the structure of the amplifier circuit PA1. The first protection circuit 120-1 of FIG. 3A can be implemented as various circuit structures, such as the first protection circuits 120-11 to 120-15 of FIGS. 3B to 3F.

[0029] 3B, the first protection circuit 120-11 includes a protection transistor SW3, a resistor RA1, and a capacitor CA1. A first end (e.g., an emitter end) of the protection transistor SW3 is coupled to a reference voltage end (e.g., a ground end). A second end (e.g., a collector end) of the protection transistor SW3 is coupled to a node N120-1 of the first protection circuit 120 by a capacitor CA1. A control end (e.g., a base end) of the protection transistor SW3 receives a digital control signal VOCP via a resistor RA1. Furthermore, when the bias current IBIAS3 is too large and the detection current Isense is greater than a threshold, the output end OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and the protection transistor SW3 receives the enabled digital control signal VOCP to make the first and second ends of the protection transistor SW3 conductive, so that the radio frequency signal at the node N120-1 is partially diverted to the reference voltage end (e.g., ground end). On the other hand, when the bias current IBIAS3 is not too large and the detection current Isense is not greater than the threshold, the output terminal OUT220 of the logic circuit 220 receives the disabled digital control signal VOCP, which is used to disconnect the first and second terminals of the protection transistor SW3, so as to prevent the radio frequency signal at the terminal N120-1 from being directed to the reference voltage terminal. In addition, the protection transistor SW3 in this embodiment may be, for example, a bipolar transistor.

[0030] 3C, compared with FIG. 3B, the first protection circuit 120-12 also includes resistors RA2 and RA3. One end of the resistor RA2 and one end of the resistor RA3 are coupled to a reference voltage terminal (e.g., ground terminal). The other end of the resistor RA2 is coupled to a second end (collector terminal) of the protection transistor SW3. The other end of the resistor RA3 is coupled to a first end (emitter terminal) of the protection transistor SW3. Therefore, further, when the bias current IBIAS3 is too large and the detection current Isense is greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and the protection transistor SW3 receives the enabled digital control signal VOCP and is used to make the first and second ends of the protection transistor SW3 conductive (as indicated by arrow AR2) so that the radio frequency signal at the terminal N120-1 is partially diverted to the reference voltage terminal (e.g., ground terminal). Conversely, when the bias current IBIAS3 is not too large and the detection current Isense is not greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs a disabled digital control signal VOCP, and the protection transistor SW3 receives the disabled digital control signal VOCP and disconnects both ends of the protection transistor SW3, so that the radio frequency signal at the node N120-1 is not directed to the reference voltage terminal. In the embodiment of Figure 3C, both ends of the protection transistor SW3 are respectively coupled to the resistor RA2 and the resistor RA3. Therefore, when both ends of the protection transistor SW3 are turned on, the conductive resistance value of the protection transistor SW3 in the embodiment of Figure 3C is smaller than the conductive resistance value of the protection transistor SW3 in the embodiment of Figure 3B, and more radio frequency signals can be directed to the reference voltage terminal, thereby more effectively reducing the transmission of radio frequency signals into the structure of the amplifier circuit PA1.

[0031] 3D, the first protection circuit 120-13 includes a protection transistor QD1, a capacitor C1, and a resistor RA1. A first end (e.g., an emitter end) of the protection transistor QD1 is coupled to a reference voltage end (e.g., a ground end). A second end (e.g., a collector end) and a control end (e.g., a base end) of the protection transistor QD1 both receive a digital control signal VOCP via the resistor RA1. The second end (collector end) and the control end (base end) of the protection transistor QD1 are coupled to a node N120-1 of the first protection circuit 120 by the capacitor C1. Therefore, further, when the bias current IBIAS is too large and the detection current Isense is greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and the first end (emitter end) and the second end (collector end) of the protection transistor QD1 are made conductive based on the enabled digital control signal VOCP (as indicated by the arrow AR3) so that the radio frequency signal at the terminal N120-1 is partially diverted to the reference voltage terminal. Conversely, when the bias current IBIAS is not too large and the detection current Isense is not greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs a disabled digital control signal VOCP, and the protection transistor QD1 receives the disabled digital control signal VOCP and is used to disconnect both ends of the protection transistor QD1 so that the radio frequency signal at the terminal N120-1 is not diverted to the reference voltage terminal. In addition, in this embodiment, the protection transistor QD1 uses, for example, a bipolar transistor as a diode, so that the protection transistor QD1 has a simpler configuration.

[0032] 3E, the first protection circuit 120-14 includes a protection transistor QD1, a capacitor C1, and a resistor RA1. A first end (emitter end) of the protection transistor QD1 is coupled to a node N120-1 of the first protection circuit 120. A second end (collector end) and a control end (base end) of the protection transistor QD1 both receive a digital control signal VOCP. The second end (collector end) and the control end (base end) of the protection transistor QD1 are coupled to a reference voltage end (e.g., ground end) by a capacitor CA1. Therefore, further, when the bias current IBIAS3 is too large and the detection current Isense is greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and the first end (emitter end) and the second end (collector end) of the protection transistor QD1 can be made conductive based on the enabled digital control signal VOCP so that the radio frequency signal at the terminal N120-1 is partially diverted to the reference voltage terminal (e.g., ground terminal) (as shown by the arrow AR4). Conversely, when the bias current IBIAS3 is not too large and the detection current Isense is not greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs a disabled digital control signal VOCP, and the protection transistor QD1 receives the disabled digital control signal VOCP and is used to disconnect both ends of the protection transistor QD1 so that the radio frequency signal at the terminal N120-1 is not diverted to the reference voltage terminal.

[0033] In this embodiment, the input matching circuit 140-14 of FIG. 3E is coupled between the input terminal RFIN and a first end (terminal N120-1) of the first protection circuit 120-14. The input matching circuit 140-14 includes a shunt inductor Lin1 and a capacitor Cin1. One end of the shunt inductor Lin1 is coupled to a reference voltage terminal (e.g., a ground terminal). The other end of the shunt inductor Lin1 is coupled to the first end (terminal N120-1) of the first protection circuit 120 and one end of the capacitor Cin1. The other end of the capacitor Cin1 is coupled to the input terminal RFIN.

[0034] 3F, the first protection circuit 120-15 includes a protection diode DA1, a capacitor CA1, and a resistor RA1. The anode terminal of the protection diode DA1 is coupled to the node N120-1. The cathode terminal of the protection diode DA1 receives a digital control signal VOCP. The cathode terminal of the protection diode DA1 is coupled to a reference voltage terminal (e.g., ground terminal) by the capacitor CA1. Therefore, further, when the bias current IBIAS3 is too large and the detection current Isense is greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and the anode terminal and the cathode terminal of the protection diode DA1 can be made conductive based on the enabled digital control signal VOCP, so that the radio frequency signal at the node N120-1 is partially guided to the reference voltage terminal (e.g., ground terminal). Conversely, if the bias current IBIAS3 is not too large and the detection current Isense is not greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs the disabled digital control signal VOCP, and the protection diode DA1 receives the disabled digital control signal VOCP and disconnects both ends of the protection diode DA1 so as to prevent the radio frequency signal at the terminal N120-1 from being directed to the reference voltage terminal. In this embodiment, the input matching circuit 140-15 of FIG. 3F may have the same circuit structure as the input matching circuit 140-14 of FIG. 3E.

[0035] 4A-4F are circuit schematic diagrams of an amplifier circuit PA1, a bias circuit BIAS1, and first protection circuits 120-2, 120-21, and 120-22 according to an embodiment of the present disclosure. First ends (termination N120-1) of the first protection circuits 120-2, 120-21, and 120-22 in FIGS. 4A-4C are coupled to the input terminal RFIN. Second ends (termination N120-4) of the first protection circuits 120-2, 120-21, and 120-22 in FIGS. 4A-4C are coupled to the signal input terminal of the amplifier circuit PA1. The first protection circuit 120-2 selectively provides a high-impedance path for radio frequency signals in accordance with a digital control signal VOCP, and is used to reduce transmission of radio frequency signals into the structure of the amplifier circuit PA1. The first protection circuit 120-2 of FIG. 4A can be implemented as various circuit structures, such as the first protection circuits 120-21 and 120-22 of FIGS. 4B and 4C.

[0036] Referring to FIG. 4B, the first protection circuit 120-21 includes a protection transistor SW3, resistors RA2 and RA3, and an inverter IN1. A first end (e.g., an emitter end) of the protection transistor SW3 is coupled to a node N120-4 of the first protection circuit 120-21. A second end (e.g., a collector end) of the protection transistor SW3 is coupled to an input terminal RFIN. One ends of the resistors RA2 and RA3 are coupled to a reference voltage terminal (e.g., a ground terminal). The other end of the resistor RA3 is coupled to a first end (emitter terminal) of the protection transistor SW3. The other end of the resistor RA2 is coupled to a second end (collector terminal) of the protection transistor SW3, and the other end of the resistor RA2 is coupled to the input terminal RFIN by a capacitor CA1. The input terminal of the inverter IN1 receives a digital control signal VOCP. The output terminal of the inverter IN1 is coupled to a control terminal (base terminal) of the protection transistor SW3 by a resistor RA1.

[0037] Therefore, furthermore, when the bias current IBIAS is too large and the detection current Isense is greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, the first protection circuit 120-21 is used to receive the enabled digital control signal VOCP by the inverter IN1, and the inverter IN1 is used to convert the enabled digital control signal VOCP into a disabled signal, and the first end (emitter end) and the second end (collector end) of the protection transistor SW3 are cut off. That is, when the logic circuit 220 outputs the enabled digital control signal VOCP to reduce the transmission of radio frequency signals into the structure of the amplifier circuit PA1, the protection transistor SW3 is in a cut-off state. On the other hand, if the bias current IBIAS is not too large and the detection current Isense is not greater than the threshold value, the output terminal OUT220 of the logic circuit 220 outputs the disabled digital control signal VOCP, and the inverter IN1 is used to convert the disabled digital control signal VOCP into an enable signal, so that the first end and the second end of the protection transistor SW3 are conductive and the radio frequency signal is more completely transmitted inside the structure of the amplifier circuit PA1.

[0038] Referring to FIG. 4C, the first protection circuit 120-22 includes a protection transistor QD1, a resistor RA1, and an inverter IN1. A first end (emitter end) of the protection transistor QD1 is coupled to the input terminal RFIN. A second end (collector end) and a control end (base end) of the protection transistor QD1 are both coupled to the signal input terminal of the amplifier circuit PA1. An input end of the inverter IN1 receives a digital control signal VOCP. An output end of the inverter IN1 is coupled to the second end (collector end) and the control end (base end) of the protection transistor QD1. In this embodiment, the input matching circuit 140-22 of FIG. 4C may have the same circuit structure as the input matching circuits 140-14 and 140-15 of FIGS. 3E and 3F.

[0039] Therefore, further, when the bias current IBIAS is too large and the detection current Isense is larger than the threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and the first end (emitter terminal) and the second end (collector terminal) of the protection transistor QD1 are disconnected, so that the first protection circuit 120-22 is used to receive the enabled digital control signal VOCP by the inverter IN1, and the inverter IN1 is used to convert the enabled digital control signal VOCP into a disabled signal. That is, when the logic circuit 220 outputs the enabled digital control signal VOCP to reduce the transmission of radio frequency signals into the structure of the amplifier circuit PA1, the protection transistor QD1 is in a disconnected state. On the other hand, when the bias current IBIAS is not too large and the detection current Isense is not greater than the threshold value, the output terminal OUT220 of the logic circuit 220 outputs a disabled digital control signal VOCP, and the inverter IN1 is used to convert the disabled digital control signal VOCP into an enabled signal, so that the first end and the second end of the protection transistor QD1 are made conductive, and the radio frequency signal is more completely transmitted into the structure of the amplifier circuit PA1.

[0040] Fig. 5 is a circuit block diagram of a power amplifier 500 according to a second embodiment of the present disclosure. The power amplifier 500 in Fig. 5 differs from the power amplifier 100 in Fig. 1 in that the power amplifier 500 in Fig. 5 includes a second protection circuit 560 and a third protection circuit 570 in addition to the first protection circuit 120.

[0041] The second protection circuit 560 may reduce the bias current IBIAS1 and the gain of the amplifier circuit PA1 based on the enabled digital control signal VOCP. Conversely, the bias current IBIAS1 and the gain of the amplifier circuit PA1 may be maintained (or not reduced) based on the disabled digital control signal VOCP. The third protection circuit 570 further reduces the bias current IBIAS1 and the gain of the amplifier circuit PA1 by providing an additional shunt path for the radio frequency signal based on the enabled digital control signal VOCP and the second protection circuit 560. Conversely, the bias current IBIAS1 and the gain of the amplifier circuit PA1 may be maintained (or not reduced) based on the disabled digital control signal VOCP and the second protection circuit 560. That is, although the power amplifier 500 of FIG. 5 includes both the second protection circuit 560 and the third protection circuit 570, only the second protection circuit 560 is required to "reduce the bias current IBIAS1 and the gain of the amplifier circuit PA1." See FIG. 6.

[0042] 6 is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, and a second protection circuit 560 according to a first sub-embodiment of the second embodiment of the present disclosure. The bias circuit BIAS1 mainly includes a bias transistor Q41. The bias circuit BIAS1 also includes transistors Q51 and Q61, resistors R51 to R81, and a capacitor C21. The bias transistor Q41 generates a bias current IBIAS1 at a node VB1 according to a system voltage VCCB.

[0043] A first end N410-1 of the second protection circuit 560 is coupled to the control end (base end) of the bias transistor Q41. A second end of the second protection circuit 560 is coupled to the reference voltage end VREFN (e.g., ground end). The second protection circuit 560 mainly includes a protection transistor SW1. The protection transistor SW1 is used to selectively provide a low impedance path to the reference voltage end (i.e., a current path from the first end N410-1 to the reference voltage end VREFN) for the bias current IBIAS in accordance with a digital control signal VOCP.

[0044] Specifically, the second protection circuit 560 also includes a transistor Q71 and resistors R91 and R101. The base and collector terminals of the transistor Q71 are coupled to each other, and the transistor Q71 is coupled to a first terminal N410-1 of the second protection circuit 560 by the resistor R91. The control terminal (base terminal) of the protection transistor SW1 receives a digital control signal VOCP through the resistor R91. Therefore, further, when the bias current IBIAS is too large and the detection current Isense is greater than a threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and both ends (i.e., the emitter terminal and the collector terminal) of the protection transistor SW1 can be made conductive based on the enabled digital control signal VOCP, such that the current at the first terminal N410-1 of the second protection circuit 560 is guided to a reference voltage terminal VREFN (e.g., ground terminal) through a low-impedance path formed by the resistor R101, the transistor Q71, and the protection transistor SW1. In this way, not only does the voltage at the first end N410-1 of the second protection circuit 560 decrease, but also the current value of the bias current IBIAS generated by the bias transistor Q decreases. Conversely, if the bias current IBIAS is not too large and the detection current Isense is not greater than the threshold, the output end OUT220 of the logic circuit 220 outputs a disabled digital control signal VOCP, and both ends of the protection transistor SW1 are disconnected based on the disabled digital control signal VOCP, so that the current at the first end N410-1 of the second protection circuit 560 is not directed to the reference voltage end VREFN.

[0045] 7 is a circuit schematic diagram of an amplifier circuit PA1, a bias circuit BIAS1, a second protection circuit 560, and a third protection circuit 570 according to a second subembodiment of the second embodiment of the present disclosure. The architecture of the second protection circuit 560 is the same in FIGS. 6 and 7. The difference between the second subembodiment in FIG. 7 and FIG. 6 is that the bias circuit BIAS1 in FIG. 7 includes a third protection circuit 570 in addition to the second protection circuit 560.

[0046] The first end N510-1 of the third protection circuit 570 is coupled between the first end (emitter end) of the bias transistor Q41 and the bias output end of the bias circuit BIAS. The second end N510-2 of the third protection circuit 570 is coupled to a reference voltage end (e.g., ground end). The third protection circuit 570 mainly includes a protection transistor SW2. The protection transistor SW2 is used to selectively provide a low-impedance path (i.e., a current path from the first end N510-1 to the reference voltage end) for the radio frequency signal based on a digital control signal VOCP.

[0047] Specifically, the third protection circuit 570 also includes a transistor Q81 and a resistor R111. The base and collector terminals of the transistor Q81 are coupled to each other, and the transistor Q81 is coupled to a first end N510-1 of the third protection circuit 570. The control terminal (base terminal) of the protection transistor SW2 receives a digital control signal VOCP through the resistor R111. Therefore, further, when the bias current IBIAS3 is too large and the detection current Isense is greater than a threshold, the output terminal OUT220 of the logic circuit 220 outputs an enabled digital control signal VOCP, and both ends (i.e., the emitter terminal and the collector terminal) of the protection transistor SW2 can be made conductive based on the enabled digital control signal VOCP so that the radio frequency signal at the first end N510-1 of the third protection circuit 570 is guided to a reference voltage terminal (e.g., ground terminal) (as indicated by arrow AR7) through a low impedance path formed by the transistor Q81 and the protection transistor SW2. In this way, the radio frequency signal received through the amplifier circuit PA1 is partially guided to the reference voltage terminal through a low impedance path, so that the transmission of the radio frequency signal to the amplifier circuit PA1 is reduced, and the third protection circuit 570 may reduce the gain of the amplifier circuit PA1. Conversely, if the bias current IBIAS3 is not too large and the detection current Isense is not greater than the threshold, the output terminal OUT220 of the logic circuit 220 outputs a disabled digital control signal VOCP, and both ends of the protection transistor SW2 may be disconnected based on the disabled digital control signal VOCP to prevent the radio frequency signal at the first terminal N510-1 of the third protection circuit 570 from being guided to the reference voltage terminal.

[0048] FIG. 8 is a circuit block diagram of a power amplifier 800 according to a third embodiment of the present disclosure. The power amplifier 800 of FIG. 8 is implemented by employing a two-stage amplifier circuit. Specifically, the power amplifier 800 mainly includes an input terminal RFIN, an output terminal RFOUT, a two-stage amplifier circuit (e.g., amplifier circuits PA1 and PA2), bias circuits BIAS1 to BIAS2 corresponding to each stage of the amplifier circuit, a current detection circuit 110, and a first protection circuit 120. The power amplifier 800 also includes a voltage generation circuit 830, an input matching circuit 840, an inter-stage matching circuit 850, and an output matching circuit 855. The power amplifier 800 may also include a second protection circuit 560 and a third protection circuit 570.

[0049] 1 may be applied to the bias circuit BIAS2 of the power amplifier 800 of FIG. 8 to generate a digital control signal VOCP according to a bias current IBIAS2 of a final-stage amplifier circuit (e.g., amplifier circuit PA2). The first protection circuit 120, the second protection circuit 560, and the third protection circuit 570 are arranged in a first-stage amplifier circuit (e.g., amplifier circuit PA1). When it is determined that the bias current IBIAS2 is greater than a threshold, one or a combination of the first protection circuit 120, the second protection circuit 560, and the third protection circuit 570 in the first-stage amplifier circuit of the power amplifier 800 is activated using the digital control signal VOCP to reduce the amplification gain of the amplifier circuit PA1 or reduce the bias current of the amplifier circuit PA1, thereby preventing an excessive bias current from flowing through the circuit structure of the power amplifier 800 and damaging the circuit structure of the power amplifier 800. For the circuit structures and corresponding element structures of the first protection circuit 120, the second protection circuit 560 and the third protection circuit 570, please refer to the above embodiments.

[0050] 9 is a circuit block diagram of a power amplifier 900 according to a fourth embodiment of the present disclosure. The power amplifier 900 in FIG. 9 is implemented by employing a single-stage amplifier circuit (i.e., an amplifier circuit PA1). Specifically, the power amplifier 900 mainly includes an input terminal RFIN, an output terminal RFOUT, an amplifier circuit PA1, a bias circuit BIAS1, a current detection circuit 110, and a first protection circuit 120. The power amplifier 900 also includes a voltage generation circuit 930, an input matching circuit 940, and an output matching circuit 955.

[0051] 1 is applied to the bias circuit BIAS1 of FIG. 9 and generates a digital control signal VOCP according to the bias current IBIAS1 of the final-stage amplifier circuit (amplifier circuit PA1). The first protection circuit 120, the second protection circuit 560, and the third protection circuit 570 are arranged in the initial-stage amplifier circuit (amplifier circuit PA1). If it is determined that the bias current IBIAS1 is greater than a threshold, the digital control signal VOCP is used to activate one or a combination of the first protection circuit 120, the second protection circuit 560, and the third protection circuit 570 arranged in the power amplifier 900, thereby reducing the amplification gain of the amplifier circuit PA1 or reducing the bias current of the amplifier circuit PA1, thereby preventing excessive bias current from flowing through the circuit structure of the power amplifier 900 and damaging the circuit structure of the power amplifier 900. If it is determined that the bias current IBIAS1 is not greater than the threshold, the first protection circuit 120, the second protection circuit 560, and the third protection circuit 570 arranged in the power amplifier 900 can be turned off by a digital control signal VOCP. For the circuit structures and corresponding element structures of the first protection circuit 120, the second protection circuit 560, and the third protection circuit 570, please refer to the above embodiments.

[0052] Fig. 10 is a flowchart of a circuit protection method according to an embodiment of the present disclosure. The circuit protection method of Fig. 10 can be applied to each of the power amplifiers 100, 800, and 900 of Figs. 1 to 9. Here, the power amplifier 100 of Fig. 1 is taken as an example to explain each step of the circuit protection method of Fig. 10.

[0053] In step S1010, the power amplifier 100 of Fig. 1 is provided. The power amplifier 100 includes at least an amplifier circuit PA1, an amplifier circuit PA3, and a bias circuit BIAS3. The amplifier circuit PA1 and the amplifier circuit PA3 are connected in series to amplify a radio frequency signal RF received from an input terminal RFIN, and the bias circuit BIAS3 outputs a bias current IBIAS3 to the amplifier circuit PA3.

[0054] In step S1020, the current detection circuit 110 generates a digital control signal VOCP according to the bias current IBIAS3. Specifically, the bias transistor Q4 and the detection transistor Q1 in FIG. 2 form a current mirror architecture to provide a detection current Isense, which is related to the bias current IBIAS3. It is determined whether the detection current Isense is greater than a threshold. If the detection current Isense is greater than the threshold, the digital control signal VOCP is enabled. Additionally, if the detection current Isense is equal to or less than the threshold, the digital control signal VOCP is disabled.

[0055] In step S1030, the radio frequency signal input to the signal input terminal IN1 of the power amplifier 100 is selectively reduced by the first protection circuit 120 in accordance with the digital control signal VOCP. The first protection circuit 120 may perform step S1030. The first protection circuit 120 is coupled between the input terminal RFIN of the power amplifier 100 and the signal input terminal IN1 of the amplifier circuit PA. For example, the first protection circuit 120 selectively provides a first low impedance path to the reference voltage terminal of the first protection circuit 120 for the radio frequency signal from the signal input terminal IN1 of the power amplifier 100 in accordance with the digital control signal VOCP.

[0056] On the other hand, a second protection circuit 560 may be provided to perform step S1030. The second protection circuit 560 selectively provides a second low-impedance path to the reference voltage terminal for the bias current IBIAS in accordance with the digital control signal VOCP. Also, a third protection circuit 570 may be provided to perform step S1030. The third protection circuit 570 selectively provides a third low-impedance path to the reference voltage terminal for the radio frequency signal in accordance with the digital control signal VOCP. For details of steps S1010 to S1030, please refer to the above embodiments.

[0057] In summary, the power amplifier and circuit protection method of the present disclosure add a current detection circuit to a bias circuit of a final stage amplifier circuit of the power amplifier to determine whether the bias current provided by the bias circuit of the final stage amplifier circuit is too large. Furthermore, if it is determined that the bias current is larger than a threshold, a control signal (e.g., a digital control signal VOCP) is used to activate one or more protection circuits of a first stage amplifier circuit disposed in the power amplifier, thereby reducing the amplification gain of the first stage amplifier circuit or reducing the bias current of the first stage amplifier circuit to prevent excessive bias current from flowing through the circuit structure of the power amplifier and protecting the power amplifier from damage.

Claims

1. 1. A power amplifier comprising: an input terminal used for inputting a radio frequency signal; an output terminal used for outputting the amplified radio frequency signal; a first amplifier circuit including a first signal input coupled to the input and a first signal output, the first amplifier circuit being used to amplify the radio frequency signal received from the input; a second amplifier circuit including a second signal input coupled to the first signal output and a second signal output, the second amplifier circuit being used to amplify the radio frequency signal received from the first signal output; a bias circuit used to output a bias current to the second amplifier circuit; a current detection circuit coupled to the bias circuit and the second amplifier circuit, the current detection circuit being used to generate a digital control signal according to the bias current; a first protection circuit coupled between an input terminal of the power amplifier and a first signal input terminal of the first amplifier circuit, the first protection circuit selectively reducing the radio frequency signal input to the first signal input terminal in accordance with the digital control signal; a power amplifier including:

2. the current detection circuit includes a current detector coupled to the bias circuit and the second amplifier circuit; the current detector includes a detection transistor; the bias circuit includes a bias transistor; 2. The power amplifier of claim 1, wherein the bias transistor is coupled to the sense transistor to form a current mirror architecture, the sense transistor providing a sense current through the current mirror architecture, the sense current being related to the bias current.

3. the current detection circuit further includes a logic circuit having an input terminal and an output terminal; 3. The power amplifier of claim 2, wherein the input of the logic circuit is coupled to the sense transistor, and the logic circuit generates the digital control signal at the output according to the sensed current.

4. the logic circuit further includes a comparison transistor; When the detection current is greater than a threshold, the comparison transistor is in a cut-off state, and the logic circuit enables the digital control signal based on the cut-off state of the comparison transistor; 4. The power amplifier of claim 3, wherein the first protection circuit reduces the radio frequency signal input to the first signal input according to the enabled digital control signal.

5. 5. The power amplifier of claim 4, wherein the logic circuit further comprises a series-connected depletion-mode transistor and a resistor, a first end of the resistor coupled to the depletion-mode transistor and a second end of the resistor coupled to the comparison transistor.

6. 4. The power amplifier of claim 3, wherein the current detector further includes a choke inductor, the choke inductor coupled between an input of the logic circuit and the detection transistor.

7. 2. The power amplifier of claim 1, wherein the first protection circuit includes a first end and a second end, the first end being coupled between an input end of the power amplifier and a first signal input end of the first amplification circuit, and the second end being coupled to a reference voltage end, and the first protection circuit is used to selectively provide a low impedance path for the radio frequency signal in accordance with the digital control signal.

8. 8. The power amplifier of claim 7, wherein the first protection circuit includes a first protection transistor, a first end of the first protection transistor coupled to the reference voltage terminal, a second end of the first protection transistor coupled to the first end of the first protection circuit, and the first protection transistor is used to receive the enabled digital control signal to make the first end and the second end of the first protection transistor conductive.

9. the first protection circuit further includes a first resistor and a second resistor; 9. The power amplifier of claim 8, wherein a first end of the first resistor and a first end of the second resistor are coupled to the reference voltage terminal, a second end of the first resistor is coupled to a second end of the first protection transistor, and a second end of the second resistor is coupled to a first end of the first protection transistor.

10. The first protection circuit includes: a first protection transistor, a first end of the first protection transistor being coupled to the reference voltage end, and a second end and a control end of the first protection transistor both receiving the digital control signal; a first capacitor, the second end and the control end of the first protection transistor being coupled to the first end of the first protection circuit by the first capacitor; Including, 8. The power amplifier of claim 7, wherein the first end and the second end of the first protection transistor are made conductive based on the digital control signal being enabled.

11. The first protection circuit includes: a first protection transistor, a first end of the first protection transistor coupled to a first end of the first protection circuit, and a second end and a control end of the first protection transistor both receiving the digital control signal; a first capacitor, the second end and the control end of the first protection transistor being coupled to the reference voltage end by the first capacitor; Including, 8. The power amplifier of claim 7, wherein the first end and the second end of the first protection transistor are made conductive based on the digital control signal being enabled.

12. The first protection circuit includes: a first protection diode, an anode terminal of the first protection diode being coupled to a first end of the first protection circuit and a cathode terminal of the first protection diode receiving the digital control signal; a first capacitor, the cathode terminal of the first protection diode being coupled to the reference voltage terminal by the first capacitor; Including, 8. The power amplifier of claim 7, wherein the anode and cathode terminals of the first protection diode are made conductive based on the digital control signal being enabled.

13. further comprising an input matching circuit coupled between the input end and a first end of the first protection circuit; 12. The power amplifier of claim 11, wherein the input matching circuit includes a shunt inductor, a first end of the shunt inductor coupled to the reference voltage terminal, and a second end of the shunt inductor coupled to the first end of the first protection circuit.

14. further comprising an input matching circuit coupled between the input end and a first end of the first protection circuit; 13. The power amplifier of claim 12, wherein the input matching circuit includes a shunt inductor, a first end of the shunt inductor coupled to the reference voltage terminal, and a second end of the shunt inductor coupled to a first end of the first protection circuit.

15. 2. The power amplifier of claim 1, wherein the first protection circuit includes a first end and a second end, the first end coupled to an input end of the power amplifier and the second end coupled to a first signal input end of the first amplification circuit, and the first protection circuit is used to selectively provide a high impedance path for the radio frequency signal in accordance with the digital control signal.

16. The first protection circuit includes: a first protection transistor, a first end of the first protection transistor coupled to a second end of the first protection circuit and a second end of the first protection transistor coupled to the input; a first resistor, a first end of the first resistor being coupled to a reference voltage terminal and a second end of the first resistor being coupled to a first end of the first protection transistor; a second resistor, a first end of the second resistor being coupled to the reference voltage terminal and a second end of the second resistor being coupled to the input terminal; an inverter, an input terminal of which receives the digital control signal and an output terminal of which is coupled to the control terminal of the first protection transistor; Including, 16. The power amplifier of claim 15, wherein the first protection circuit is adapted to receive the enabled digital control signal by the inverter to disconnect the first end and the second end of the first protection transistor.

17. The first protection circuit includes: a first protection transistor, a first end of the first protection transistor being coupled to the input end, and a second end and a control end of the first protection transistor being both coupled to a first signal input end of the first amplifier circuit; an inverter, an input terminal of which receives the digital control signal and an output terminal of which is coupled to the second end and a control terminal of the first protection transistor; Including, 16. The power amplifier of claim 15, wherein the first protection circuit is adapted to receive the enabled digital control signal by the inverter to disconnect the first end and the second end of the first protection transistor.

18. the bias circuit is a second bias circuit used to output a second bias current; the power amplifier further includes a first bias circuit used to output a first bias current to the first amplification circuit; the first bias circuit includes a first bias transistor; the power amplifier further includes a second protection circuit, a first end of the second protection circuit coupled to the control end of the first bias transistor, and a second end of the second protection circuit coupled to a reference voltage end; 2. The power amplifier of claim 1, wherein the second protection circuit includes a second protection transistor, the second protection transistor being used to selectively provide a low impedance path for the first bias current in accordance with the digital control signal.

19. a third protection circuit, a first end of the third protection circuit being coupled between a first end of the first bias transistor and a first bias output terminal of the first bias circuit, and a second end of the third protection circuit being coupled to the reference voltage terminal; further comprising 20. The power amplifier of claim 18, wherein the third protection circuit includes a third protection transistor, the third protection transistor being used to selectively provide a low impedance path for the radio frequency signal according to the digital control signal.

20. a third amplifier circuit coupled between the first amplifier circuit and the second amplifier circuit, the third amplifier circuit being used to amplify the radio frequency signal; a third bias circuit used to output a third bias current to the third amplifier circuit; further comprising The third amplifier circuit includes: a third signal input coupled to the first signal output of the first amplifier circuit; a third signal output coupled to the first signal input of the second amplifier circuit; 10. The power amplifier of claim 1, comprising:

21. 1. A power amplifier comprising: an input terminal used for inputting a radio frequency signal; an output terminal used for outputting the amplified radio frequency signal; an amplifier circuit including a first signal input coupled to the input and a first signal output, the amplifier circuit being used to amplify the radio frequency signal received from the input; a bias circuit used to output a bias current to the amplifier circuit; a current detection circuit coupled to the input terminal, the current detection circuit being used to generate a digital control signal according to the bias current; a first protection circuit coupled between an input terminal of the power amplifier and a signal input terminal of the amplifier circuit, the first protection circuit being used to selectively reduce the radio frequency signal input to the input terminal in accordance with the digital control signal; a power amplifier including:

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