Semiconductor wafer, piezoelectric element, and method for manufacturing semiconductor wafer

Abstract

To provide a semiconductor wafer, a piezoelectric element and a manufacturing method of the semiconductor wafer which can make stress uniform while suppressing an increase in manufacturing cost.SOLUTION: A piezoelectric film 15 comprises: a first piezoelectric film 151; and a second piezoelectric film 152 which is arranged on one surface or the other surface of the first piezoelectric film 151. The second piezoelectric film 152 has the in-plane stress distribution different from the first piezoelectric film 151. The stress over the entire piezoelectric film 15 can be made to be uniform by constituting the piezoelectric film 15 with the first piezoelectric film 151 and the second piezoelectric film 152 having the mutually-different in-plane stress distributions. Since the in-plane stress distribution can be adjusted according to a deposition condition, the first piezoelectric film 151 and the second piezoelectric film 152 can be formed by the same device and an increase in manufacturing cost can be suppressed.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor wafer, a piezoelectric element, and a method for manufacturing a semiconductor wafer. [Background technology]

[0002] Conventionally, microphones have been proposed that have a cantilevered piezoelectric element, in which the piezoelectric film bends and deforms in response to an applied voltage, and output a voltage corresponding to the capacitance between the electrodes. In such microphones, the piezoelectric element warps due to stress, resulting in a decrease in low-frequency sensitivity.

[0003] In response to this, for example, Patent Document 1 proposes a technique for adjusting heat dissipation by the stage structure of a film formation apparatus, thereby making stress uniform within the wafer surface. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2017 / 0294294 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when using, for example, scandium aluminum nitride (ScAlN) for the piezoelectric film, the stress distribution shape changes depending on the Sc concentration of the piezoelectric film. Therefore, when manufacturing piezoelectric elements with various Sc concentrations depending on the application, the method described in Patent Document 1 requires preparing stages according to the Sc concentration, which increases the manufacturing cost.

[0006] In view of the above, an object of the present invention is to provide a semiconductor wafer, a piezoelectric element, and a method for manufacturing a semiconductor wafer, which are capable of making stress uniform while suppressing an increase in manufacturing costs. [Means for solving the problem]

[0007] In order to achieve the above object, the invention described in claim 1 provides a semiconductor wafer having a structure in which a piezoelectric film (15, 17) is formed on a substrate (11), the piezoelectric film includes a first piezoelectric film (151) and a second piezoelectric film (152) disposed on one or the other surface of the first piezoelectric film, the second piezoelectric film having an in-plane stress distribution different from that of the first piezoelectric film. The stress in the first piezoelectric film changes in the opposite direction to that in the first piezoelectric film depending on the in-plane position. do.

[0008] In this way, by constructing a piezoelectric film from a first piezoelectric film and a second piezoelectric film having different in-plane stress distributions, the stress is made uniform throughout the piezoelectric film. In addition, since the in-plane stress distribution can be adjusted by the film formation conditions, it is possible to form the first piezoelectric film and the second piezoelectric film using the same device, which makes it possible to suppress increases in manufacturing costs.

[0009] In addition, in the invention described in claim 7, a piezoelectric element having a configuration in which a piezoelectric film (15, 17) is formed on a substrate (11), the piezoelectric film includes a first piezoelectric film (151) and a second piezoelectric film (152) disposed on one or the other surface of the first piezoelectric film, and the second piezoelectric film has an in-plane stress distribution different from that of the first piezoelectric film. The stress in the first piezoelectric film changes in the opposite direction to that in the first piezoelectric film depending on the in-plane position. do.

[0010] In this way, by constructing a piezoelectric film from a first piezoelectric film and a second piezoelectric film having different in-plane stress distributions, the stress is made uniform throughout the piezoelectric film. In addition, since the in-plane stress distribution can be adjusted by the film formation conditions, it is possible to form the first piezoelectric film and the second piezoelectric film using the same device, which makes it possible to suppress increases in manufacturing costs.

[0011] In addition, in the invention described in claim 13, there is provided a method for manufacturing a semiconductor wafer having a configuration in which a piezoelectric film (15, 17) is formed on a substrate (11), the method comprising the steps of depositing a first piezoelectric film (151) constituting the piezoelectric film, and depositing a second piezoelectric film (152) arranged on one or the other surface of the first piezoelectric film and constituting the piezoelectric film, wherein in depositing the second piezoelectric film, the second piezoelectric film is deposited under deposition conditions different from those for depositing the first piezoelectric film, so that the first piezoelectric film and the second piezoelectric film have different in-plane stress distributions. Then, the second piezoelectric film is formed so that the stress of the second piezoelectric film changes in the opposite direction to that of the first piezoelectric film depending on the in-plane position. do.

[0012] In this way, by constructing a piezoelectric film with a first piezoelectric film and a second piezoelectric film having different in-plane stress distributions, the stress in the entire piezoelectric film is made uniform. In addition, by adjusting the in-plane stress distribution through film formation conditions, it becomes possible to form the first piezoelectric film and the second piezoelectric film using the same device, which makes it possible to suppress increases in manufacturing costs.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view of a semiconductor wafer according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a piezoelectric film. [Diagram 3] FIG. 2 is a top view of a semiconductor wafer. [Figure 4] 4A and 4B are diagrams illustrating in-plane stress distributions of a first piezoelectric film and a second piezoelectric film that form the piezoelectric film. [Diagram 5] FIG. 13 is a diagram showing the in-plane stress distribution of the entire piezoelectric film. [Figure 6] FIG. 1 is a diagram showing a configuration of a semiconductor wafer manufacturing apparatus. [Figure 7] FIG. 4 is a diagram showing an in-plane stress distribution of the first piezoelectric film. [Figure 8] FIG. 4 is a diagram showing an in-plane stress distribution of a second piezoelectric film. [Figure 9]11 is a diagram showing changes in in-plane stress distribution depending on combinations of film thicknesses of a first piezoelectric film and a second piezoelectric film. FIG. [Figure 10] 6 is a diagram showing the relationship between the film thickness of the first piezoelectric film and the second piezoelectric film and the estimated yield. [Figure 11] FIG. 11 is a cross-sectional view of a piezoelectric film in a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) A semiconductor wafer 1 shown in Fig. 1 has a piezoelectric film formed on a substrate, and includes a substrate 11, an insulating film 12, an undercoat film 13, a lower electrode film 14, a lower piezoelectric film 15, an intermediate electrode film 16, an upper piezoelectric film 17, and an upper electrode film 18.

[0017] Substrate 11 is made of, for example, silicon. An insulating film 12 made of silicon oxide or the like is formed on the surface of substrate 11. An undercoat film 13 is formed on the surface of insulating film 12. Undercoat film 13 is intended to facilitate crystal growth when forming lower-layer electrode film 14 and the like, and is made of aluminum nitride or the like.

[0018] A lower-layer electrode film 14 to an upper-layer electrode film 18 are laminated in this order on the surface of the base film 13. That is, the piezoelectric elements obtained by dividing the semiconductor wafer 1 into chip units have a bimorph structure in which the lower-layer piezoelectric film 15 is sandwiched between the lower-layer electrode film 14 and the intermediate electrode film 16, and the upper-layer piezoelectric film 17 is sandwiched between the lower-layer piezoelectric film 15 and the upper electrode film 18.

[0019] The piezoelectric element is configured so that the lower piezoelectric film 15 and the upper piezoelectric film 17 bend and deform in response to the voltage between the lower electrode film 14 and the intermediate electrode film 16, and the voltage between the intermediate electrode film 16 and the upper electrode film 18.

[0020] Furthermore, the piezoelectric element outputs a voltage according to the capacitance between the lower electrode film 14 and the intermediate electrode film 16 and the capacitance between the intermediate electrode film 16 and the upper electrode film 18. The lower electrode film 14, the intermediate electrode film 16 and the upper electrode film 18 are made of, for example, molybdenum, and the lower piezoelectric film 15 and the upper piezoelectric film 17 are made of ScAlN in this embodiment.

[0021] The detailed configurations of the lower piezoelectric film 15 and the upper piezoelectric film 17 will be described. As shown in Fig. 2, the lower piezoelectric film 15 has two types of films each made of a piezoelectric material. These two types of films are referred to as a first piezoelectric film 151 and a second piezoelectric film 152. The second piezoelectric film 152 is disposed on one surface or the other surface of the first piezoelectric film 151.

[0022] In this embodiment, a plurality of first piezoelectric films 151 and a plurality of second piezoelectric films 152 are provided, and the lower piezoelectric film 15 is configured by alternately stacking the first piezoelectric films 151 and the second piezoelectric films 152. In this embodiment, the same number of first piezoelectric films 151 and second piezoelectric films 152 are provided, such that the bottom layer of the lower piezoelectric film 15 is composed of the first piezoelectric film 151 and the top layer is composed of the second piezoelectric film 152.

[0023] Both the first piezoelectric film 151 and the second piezoelectric film 152 are made of ScAlN, but they have different in-plane stress distributions. Specifically, as shown in Fig. 3, the position along the axis that passes through the center of the substrate 11 and is parallel to the surface of the substrate 11 is taken as the in-plane position, and the stresses of the first piezoelectric film 151 and the second piezoelectric film 152 corresponding to the in-plane positions are illustrated as shown in Fig. 4. In Fig. 4, the solid line and the dashed line indicate the stresses of the first piezoelectric film 151 and the second piezoelectric film 152, respectively.

[0024] 4, the stress of the first piezoelectric film 151 is graphed as an upward convex curve. That is, the stress of the first piezoelectric film 151 is greatest at the center, and the stress decreases toward the outer edge. On the other hand, the stress of the second piezoelectric film 152 is graphed as a downward convex curve. That is, the stress of the second piezoelectric film 152 is least at the center, and the stress increases toward the outer edge.

[0025] In this way, the first piezoelectric film 151 and the second piezoelectric film 152 have an in-plane stress distribution in which the stress changes in opposite directions depending on the in-plane position. By stacking the first piezoelectric film 151 and the second piezoelectric film 152 having such an in-plane stress distribution, the stress of the first piezoelectric film 151 and the stress of the second piezoelectric film 152 cancel each other out, and the in-plane stress is made uniform throughout the lower piezoelectric film 15 as shown in FIG.

[0026] 2, the first piezoelectric film 151 is formed to be thicker than the second piezoelectric film 152, but the first piezoelectric film 151 and the second piezoelectric film 152 may have the same thickness, or the first piezoelectric film 151 may be formed to be thinner than the second piezoelectric film 152. The total thickness of one first piezoelectric film 151 and one second piezoelectric film 152 is, for example, 100 nm.

[0027] The upper-layer piezoelectric film 17 has a similar configuration to the lower-layer piezoelectric film 15. That is, the upper-layer piezoelectric film 17 includes two types of films having in-plane stress distributions in opposite directions, and the in-plane stress in the entire upper-layer piezoelectric film 17 is made uniform by stacking these two types of films.

[0028] The following describes a method for manufacturing the semiconductor wafer 1. A manufacturing apparatus 2 shown in Fig. 6 forms a thin film made of ScAlN by magnetron sputtering, and is used when forming the lower-layer piezoelectric film 15 or the upper-layer piezoelectric film 17 on the substrate 11.

[0029] 6, the manufacturing apparatus 2 includes a stage 21, an RF bias power supply 22, a target 23, a backing plate 24, a DC power supply 25, a magnet 26, and a gas supply unit 27. The stage 21 to the magnet 26 are disposed in a chamber (not shown).

[0030] The stage 21 is disposed at the bottom of the chamber. The stage 21 holds the substrate 11 during film formation. The stage 21 is provided with a heater 211, and the substrate 11 is heated by the heater 211 during film formation. An RF bias power supply 22 is connected to the stage 21. The RF bias power supply 22 is for supplying RF power to the stage 21.

[0031] The target 23 is disposed at the upper part of the chamber, separated from the stage 21 and the substrate 11. The target 23 is made of an ScAl alloy. A backing plate 24 is disposed above the target 23. The backing plate 24 cools the target 23 during film formation, and also functions as an electrode for connecting the target 23 to a DC power supply 25.

[0032] A DC power supply 25 is connected between the target 23 and the stage 21. The DC power supply 25 is for supplying pulsed DC power to the target 23. A magnet 26 is disposed above the target 23 and the backing plate 24, separated from the target 23 and the backing plate 24. The magnet 26 is for generating plasma around the target 23 during film formation.

[0033] The gas supply unit 27 supplies a sputtering gas into the chamber. In this embodiment, the sputtering gas is a mixed gas of N2 and Ar. The gas supply unit 27 is configured to adjust the gas flow rate ratio of N2 and Ar and the pressure inside the chamber.

[0034] In the manufacturing apparatus 2 configured as above, a layer made of ScAlN is formed on the substrate 11 by magnetron sputtering by supplying DC pulse power to the target 23 by the DC power supply 25, supplying RF power to the stage 21 by the RF bias power supply 22, and supplying sputtering gas into the chamber by the gas supply unit 27. Then, the substrate 11 having the insulating film 12 to the upper electrode film 18 formed thereon is divided into chip units by dicing, thereby obtaining semiconductor chips on which piezoelectric elements are formed.

[0035] A method for adjusting the in-plane stress distribution of the first piezoelectric film 151 and the second piezoelectric film 152 when forming the lower piezoelectric film 15 by the manufacturing apparatus 2 will be described. In the manufacturing apparatus 2, the lower piezoelectric film 15 is formed by alternately forming the first piezoelectric film 151 and the second piezoelectric film 152. At this time, by forming the second piezoelectric film 152 under different film forming conditions than those for the first piezoelectric film 151, the first piezoelectric film 151 and the second piezoelectric film 152 come to have mutually different in-plane stress distributions.

[0036] The in-plane stress distribution of the first piezoelectric film 151 and the second piezoelectric film 152 can be adjusted by the film formation conditions, such as the distance L1 between the target 23 and the surface of the substrate 11, the distance L2 between the target 23 and the magnet 26, the RF bias power, the DC power, the pressure in the chamber, the gas flow rate ratio, and the film formation temperature.

[0037] It is not necessary to change all of the deposition conditions when depositing the first piezoelectric film 151 and the second piezoelectric film 152, and the in-plane stress distribution can be adjusted by changing only some of the deposition conditions. According to the inventors' intensive studies, it was found that, for example, by increasing the RF bias power and decreasing the DC power, the graph of the in-plane stress distribution tends to change from an upwardly convex shape to a downwardly convex shape.

[0038] Fig. 7 shows the in-plane stress distribution of the first piezoelectric film 151 with an Sc concentration of 24% formed under the conditions of distance L1 of 60 mm, distance L2 of 40 mm, RF bias power of 15 W, DC power of 8 kW, pressure in the chamber of 1.18 Pa, and gas flow ratio of Ar of 30%. Fig. 8 shows the in-plane stress distribution of the first piezoelectric film 151 with an Sc concentration of 24% formed under the conditions of distance L1 of 80 mm, distance L2 of 40 mm, RF bias power of 30 W, DC power of 6 kW, pressure in the chamber of 1.18 Pa, and gas flow ratio of Ar of 15%.

[0039] As shown in Figures 7 and 8, two in-plane stress distributions in opposite directions could be obtained depending on the film formation conditions. By forming the lower-layer piezoelectric film 15 by stacking the first piezoelectric film 151 and the second piezoelectric film 152 having such in-plane stress distributions, the stress distribution in the entire lower-layer piezoelectric film 15 is made uniform. The XRD half-widths of the first piezoelectric film 151 and the second piezoelectric film 152 were 1.53 deg and 1.64 deg, respectively, and a sufficiently high crystallinity was obtained for use as a piezoelectric element.

[0040] Furthermore, by adjusting the film thickness ratio between the first piezoelectric film 151 and the second piezoelectric film 152 so that the stress of the first piezoelectric film 151 and the stress of the second piezoelectric film 152 cancel each other out, the stress distribution in the entire lower piezoelectric film 15 can be made more uniform. Specifically, one of the first piezoelectric film 151 and the second piezoelectric film 152 is formed thicker than the other in accordance with the stress of the first piezoelectric film 151 and the stress of the second piezoelectric film 152. This makes it possible to make the stress distribution in the entire lower piezoelectric film 15 more uniform, compared to when the first piezoelectric film 151 and the second piezoelectric film 152 have the same film thickness.

[0041] 9 shows the change in average stress in the entire lower piezoelectric film 15 when changing the ratio of the thickness of the first piezoelectric film 151 to the thickness of the second piezoelectric film 152. The eleven graphs show, from bottom to top, the stress in the lower piezoelectric film 15 when the thickness ratio of the first piezoelectric film 151 to the second piezoelectric film 152 is 0:10, 1:9, 2:8, 3:7, 4:6, 5:5, 6:4, 7:3, 8:2, 9:1, and 10:0.

[0042] 10 shows the relationship between the estimated yield and the ratio of the thickness of the first piezoelectric film 151 to the total thickness of the first piezoelectric film 151 and the second piezoelectric film 152. Here, the estimated yield is the ratio of the area of ​​the region where the stress at the center of the semiconductor wafer 1 is ±50 MPa to the area of ​​the measurement range.

[0043] In the experimental results shown in Figs. 9 and 10, when the thickness ratio of the first piezoelectric film 151 to the second piezoelectric film 152 was 8:2, the stress in the lower piezoelectric film 15 was well uniformed and the estimated yield was maximized. In this way, by adjusting the thickness ratio of the first piezoelectric film 151 to the second piezoelectric film 152, the variation in the stress distribution in the lower piezoelectric film 15 can be further reduced. In addition, when the first piezoelectric film 151 and the second piezoelectric film 152 were combined, the estimated yield was approximately six times higher at maximum than when the thickness ratio was 0:10 or 10:0, that is, when the lower piezoelectric film 15 was composed of only one of the first piezoelectric film 151 and the second piezoelectric film 152.

[0044] As described above, in this embodiment, the lower piezoelectric film 15 and the upper piezoelectric film 17 include two types of layers having different in-plane stress distributions. This makes the stress uniform throughout the lower piezoelectric film 15 and the upper piezoelectric film 17, thereby reducing the decrease in low-frequency sensitivity caused by warping of the lower piezoelectric film 15 and the upper piezoelectric film 17. In addition, the characteristics of the piezoelectric elements can be made uniform.

[0045] In this embodiment, the second piezoelectric film 152 is formed under different film formation conditions than the first piezoelectric film 151 so that the first piezoelectric film 151 and the second piezoelectric film 152 have different in-plane stress distributions. This makes the stress uniform throughout the lower piezoelectric film 15 and the upper piezoelectric film 17, thereby reducing the decrease in low-frequency sensitivity due to warping of the lower piezoelectric film 15 and the upper piezoelectric film 17.

[0046] In addition, since the in-plane stress distribution can be adjusted simply by changing the film formation conditions, for example, when forming a first piezoelectric film 151 and a second piezoelectric film 152 having different Sc concentrations, there is no need to change the device structure, and the increase in the manufacturing cost of the semiconductor wafer 1 can be suppressed.

[0047] Furthermore, according to the above embodiment, the following effects can be obtained.

[0048] (1) The second piezoelectric film 152 has an in-plane stress distribution in which the stress changes depending on the in-plane position in the opposite direction to that of the first piezoelectric film 151. This makes it possible to make the stress in the entire lower piezoelectric film 15 more uniform.

[0049] (2) The film thicknesses of the first piezoelectric film 151 and the second piezoelectric film 152 are adjusted so that the stress of the first piezoelectric film 151 and the stress of the second piezoelectric film 152 cancel each other out. This makes it possible to make the stress in the entire lower piezoelectric film 15 more uniform.

[0050] (3) The piezoelectric film 15 includes a plurality of first piezoelectric films 151 and a plurality of second piezoelectric films 152, and the first piezoelectric films 151 and the second piezoelectric films 152 are alternately stacked. This can make the stress in the entire lower piezoelectric film 15 more uniform.

[0051] (4) The first piezoelectric film 151 and the second piezoelectric film 152 are formed by sputtering. The deposition conditions of the second piezoelectric film 152 are different from those of the first piezoelectric film 151 in at least some of the distance L1, distance L2, RF bias power, DC power, pressure in the chamber, gas flow rate ratio, and deposition temperature. For example, when the second piezoelectric film 152 is formed, the RF bias power is increased and the DC power is decreased compared to when the first piezoelectric film 151 is formed. This makes it possible to form the second piezoelectric film 152 having an in-plane stress distribution different from that of the first piezoelectric film 151.

[0052] (5) The second piezoelectric film 152 is formed so that the stress of the second piezoelectric film 152 changes in the opposite direction to that of the first piezoelectric film 151 depending on the in-plane position. This makes it possible to make the stress in the entire lower piezoelectric film 15 more uniform.

[0053] Second embodiment The second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the lower piezoelectric film 15 is changed, and other aspects are the same as those of the first embodiment, so only the differences from the first embodiment will be described.

[0054] In this embodiment, the laminated structure of the first piezoelectric film 151 and the second piezoelectric film 152 is symmetrical with respect to a plane that passes through the center in the thickness direction of the lower piezoelectric film 15 and is perpendicular to the thickness direction. For example, as shown in Fig. 11, the lower piezoelectric film 15 is configured such that the first piezoelectric film 151 and the second piezoelectric film 152 are laminated alternately such that the bottom layer and the top layer are composed of the first piezoelectric film 151. The dashed line in Fig. 11 indicates a plane that passes through the center in the thickness direction of the lower piezoelectric film 15 and is perpendicular to the thickness direction.

[0055] 11, the central layer of the lower piezoelectric film 15 is the first piezoelectric film 151, but the central layer may be the second piezoelectric film 152. Furthermore, the lower piezoelectric film 15 may be configured such that the first piezoelectric film 151 and the second piezoelectric film 152 are alternately laminated such that the bottom and top layers are composed of the second piezoelectric film 152.

[0056] This embodiment has the same configuration and operation as the first embodiment, and therefore can obtain the same effects as the first embodiment.

[0057] Furthermore, according to the above embodiment, the following effects can be obtained.

[0058] (1) The laminated structure of the first piezoelectric film 151 and the second piezoelectric film 152 is symmetrical with respect to a plane that passes through the center in the thickness direction of the lower piezoelectric film 15 and is perpendicular to the thickness direction. Specifically, the lower piezoelectric film 15 is configured such that the first piezoelectric film 151 and the second piezoelectric film 152 are alternately laminated such that the bottom and top layers are composed of the first piezoelectric film 151, or the bottom and top layers are composed of the second piezoelectric film 152. This makes it possible to reduce warping of the piezoelectric element due to the stress of the lower piezoelectric film 15.

[0059] (Other embodiments) The present invention is not limited to the above-mentioned embodiments, and can be modified as appropriate within the scope of the claims. In addition, in each of the above-mentioned embodiments, it goes without saying that the elements constituting the embodiments are not necessarily essential, except when they are specifically stated as essential or when they are clearly considered essential in principle. In addition, in each of the above-mentioned embodiments, when the numbers, values, amounts, ranges, etc. of the components of the embodiments are mentioned, they are not limited to the specific numbers, except when they are specifically stated as essential or when they are clearly limited to a specific number in principle.

[0060] In each of the above embodiments, the lower piezoelectric film 15 is made up of two types of films, but the lower piezoelectric film 15 may be made up of three or more types of films.

[0061] In each of the above embodiments, the graphs of the stress of the first piezoelectric film 151 and the second piezoelectric film 152 are convex upward and convex downward, respectively, but as long as the stress of the second piezoelectric film 152 changes in the opposite direction to that of the first piezoelectric film 151 depending on the in-plane position, the graphs of the stress may have other shapes. For example, the graph of the stress of the first piezoelectric film 151 may be M-shaped with two convex upward graphs connected together, and the graph of the stress of the second piezoelectric film 152 may be W-shaped with two convex downward graphs connected together. Furthermore, the graph of the stress of the first piezoelectric film 151 may be shaped as three or more convex upward graphs connected together, and the graph of the stress of the second piezoelectric film 152 may be shaped as three or more convex downward graphs connected together. [Explanation of symbols]

[0062] 11 Substrate 15 Piezoelectric film 151 First Piezoelectric Film 152 Second Piezoelectric Film 17 Piezoelectric film

Claims

1. A semiconductor wafer having a structure in which a piezoelectric film (15, 17) is formed on a substrate (11), The piezoelectric film includes a first piezoelectric film (151) and a second piezoelectric film (152) disposed on one surface or the other surface of the first piezoelectric film, The second piezoelectric film has an in-plane stress distribution different from that of the first piezoelectric film, and has an in-plane stress distribution in which the stress changes in an opposite direction to that of the first piezoelectric film depending on the in-plane position.

2. 2. The semiconductor wafer according to claim 1, wherein the thicknesses of the first and second piezoelectric films are adjusted so that the stress of the first and second piezoelectric films cancel each other out.

3. 3. The semiconductor wafer according to claim 1, wherein the piezoelectric film comprises a plurality of the first piezoelectric films and a plurality of the second piezoelectric films, the first piezoelectric films and the second piezoelectric films being alternately stacked.

4. 4. The semiconductor wafer according to claim 3, wherein the piezoelectric film has a laminated structure of the first piezoelectric film and the second piezoelectric film that is symmetrical with respect to a plane that passes through a center in the thickness direction and is perpendicular to the thickness direction.

5. The semiconductor wafer of claim 4, wherein the piezoelectric film is configured such that the first piezoelectric film and the second piezoelectric film are alternately stacked, with the bottom layer and the top layer being composed of the first piezoelectric film, or the bottom layer and the top layer being composed of the second piezoelectric film.

6. A semiconductor wafer described in any one of claims 1 to 5, wherein the first piezoelectric film has a greater stress than the second piezoelectric film in some in-plane positions and a lesser stress than the second piezoelectric film in other positions.

7. A piezoelectric element having a structure in which a piezoelectric film (15, 17) is formed on a substrate (11), The piezoelectric film includes a first piezoelectric film (151) and a second piezoelectric film (152) disposed on one surface or the other surface of the first piezoelectric film, The second piezoelectric film has an in-plane stress distribution different from that of the first piezoelectric film, and the second piezoelectric film has an in-plane stress distribution in which the stress changes in an opposite direction to that of the first piezoelectric film depending on the in-plane position.

8. 8. The piezoelectric element according to claim 7, wherein the thicknesses of the first piezoelectric film and the second piezoelectric film are adjusted so that stresses in the first piezoelectric film and the second piezoelectric film cancel each other out.

9. The piezoelectric element according to claim 7 or 8, wherein the piezoelectric film comprises a plurality of the first piezoelectric films and a plurality of the second piezoelectric films, the first piezoelectric films and the second piezoelectric films being alternately stacked.

10. The piezoelectric element according to claim 9 , wherein the piezoelectric film has a laminated structure of the first piezoelectric film and the second piezoelectric film that is symmetrical with respect to a plane that passes through a center in the thickness direction and is perpendicular to the thickness direction.

11. The piezoelectric element of claim 10, wherein the piezoelectric film is configured such that the first piezoelectric film and the second piezoelectric film are alternately stacked, with the bottom layer and the top layer being composed of the first piezoelectric film, or the bottom layer and the top layer being composed of the second piezoelectric film.

12. A piezoelectric element described in any one of claims 7 to 11, wherein the first piezoelectric film has a greater stress than the second piezoelectric film in some in-plane positions and a lesser stress than the second piezoelectric film in other positions.

13. A method for manufacturing a semiconductor wafer having a structure in which a piezoelectric film (15, 17) is formed on a substrate (11), comprising the steps of: forming a first piezoelectric film (151) constituting the piezoelectric film; and depositing a second piezoelectric film (152) disposed on one or the other surface of the first piezoelectric film and constituting the piezoelectric film; A method for manufacturing a semiconductor wafer, in which the second piezoelectric film is formed under different film formation conditions than those for forming the first piezoelectric film so that the first piezoelectric film and the second piezoelectric film have different in-plane stress distributions, and the second piezoelectric film is formed so that the stress of the second piezoelectric film changes in the opposite direction to that of the first piezoelectric film depending on the in-plane position.

14. The steps of forming the first piezoelectric film and forming the second piezoelectric film include forming the first piezoelectric film and the second piezoelectric film by sputtering, respectively; 14. The method for manufacturing a semiconductor wafer according to claim 13, wherein the deposition conditions for depositing the second piezoelectric film are different from the deposition conditions for depositing the first piezoelectric film in at least some of the following: pressure in a chamber, distance between a target and a surface of the substrate, distance between a target and a magnet, RF bias power, DC power, gas flow ratio, and deposition temperature.

15. The method for manufacturing a semiconductor wafer according to claim 14 , wherein, in forming the second piezoelectric film, RF bias power is increased and DC power is decreased as compared to forming the first piezoelectric film.

16. A method for manufacturing a semiconductor wafer having a structure in which a piezoelectric film (15, 17) is formed on a substrate (11), comprising the steps of: forming a first piezoelectric film (151) constituting the piezoelectric film; and depositing a second piezoelectric film (152) disposed on one or the other surface of the first piezoelectric film and constituting the piezoelectric film; In forming the second piezoelectric film, the second piezoelectric film is formed under different film formation conditions from those for forming the first piezoelectric film so that the first piezoelectric film and the second piezoelectric film have different in-plane stress distributions. The steps of forming the first piezoelectric film and forming the second piezoelectric film include forming the first piezoelectric film and the second piezoelectric film by sputtering, respectively; the second piezoelectric film is formed under at least some of the following conditions: a pressure in a chamber, a distance between a target and a surface of the substrate, a distance between a target and a magnet, an RF bias power, a DC power, a gas flow rate ratio, and a film formation temperature; and A method for manufacturing a semiconductor wafer, wherein, in forming the second piezoelectric film, RF bias power is increased and DC power is decreased compared to forming the first piezoelectric film.

17. A method for manufacturing a semiconductor wafer as described in any one of claims 13 to 16, wherein the first piezoelectric film and the second piezoelectric film are formed such that the first piezoelectric film has a greater stress than the second piezoelectric film in some in-plane positions and a lesser stress than the second piezoelectric film in other positions.

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