Display devices and electronic devices

Abstract

A display device comprises: a drive substrate having a first face and a second face; and a plurality of light-emitting elements provided on the first face. The drive substrate includes: a plurality of drive transistors that drive each of the plurality of light-emitting elements and are provided on the second face; a plurality of through electrodes penetrating between the first and second faces; and a plurality of connection parts that connect the diffusion layer of each drive transistor and each through electrode and are provided on the second face. The connection part includes a semiconductor layer or a semiconductor compound layer.

Description

[Technical field]

[0001] The present disclosure relates to a display device and an electronic device including the same. [Background technology]

[0002] A display device in which a plurality of light-emitting elements such as organic light-emitting diode (hereinafter referred to as "OLED") elements are arranged on a substrate is self-luminous and has the characteristic of low power consumption, and therefore is expected to be applied to various electrical devices.

[0003] In the above display device, a technology has been proposed that achieves both miniaturization and high definition by forming a plurality of pixel circuits, which respectively drive a plurality of light-emitting elements, and their peripheral circuits on the same single crystal silicon substrate using a silicon semiconductor microprocess (see, for example, Patent Documents 1 and 2). Small display devices manufactured using such technology are expected to be applied to electronic viewfinders and the like.

[0004] Patent document 3 proposes a display device using a silicon semiconductor microprocessing process, which has a structure in which a plurality of light-emitting sections (light-emitting elements) 20 are provided on a first surface of a Si layer (silicon substrate) 13A, and a plurality of driving transistors Tr2 for driving each of the plurality of light-emitting sections (light-emitting elements) 20 are provided on a second surface of the Si layer 13A. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5870546 [Patent Document 2] Patent No. 6031954 [Patent Document 3] JP 2014-194517 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the technology described in Patent Document 3, the connection between the through electrode 13V and the source / drain region (diffusion layer) 132A of the driving transistor Tr2 is made by wiring 121 (see Figure 1 of Patent Document 3, etc.), which reduces the freedom of routing of wiring other than wiring 121.

[0007] An object of the present disclosure is to provide a display device capable of suppressing a decrease in the degree of freedom in routing wiring, and an electronic device including the same. [Means for solving the problem]

[0008] In order to solve the above problems, the first disclosure is: a drive substrate having a first surface and a second surface; A plurality of light emitting elements provided on a first surface; Equipped with The drive board is a plurality of driving transistors provided on the second surface and configured to drive the plurality of light-emitting elements, respectively; a plurality of through electrodes penetrating between the first surface and the second surface; a plurality of connection portions provided on the second surface, the connection portions connecting the diffusion layers of the drive transistors and the through electrodes; Equipped with The connection is a display device comprising a semiconductor layer or a semiconductor compound layer.

[0009] A second disclosure relates to an electronic device including the display device of the first disclosure. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating an example of an overall configuration of a display device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a configuration of a pixel circuit. [Diagram 3] 1 is a cross-sectional view showing an example of a configuration of a display device according to a first embodiment of the present disclosure. [Figure 4]FIG. 4 is an enlarged cross-sectional view of a portion of FIG. [Figure 5A] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5B] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5C] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5D] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5E] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5F] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5G] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5H] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5I] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5J] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 5K] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 6] FIG. 1 is a cross-sectional view showing a configuration of a display device according to a reference example. [Figure 7] FIG. 11 is a cross-sectional view showing an example of a configuration of a display device according to a second embodiment of the present disclosure. [Figure 8A] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 8B] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 8C] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 8D] 1A to 1C are process diagrams illustrating an example of a manufacturing method for a display device. [Figure 9] FIG. 2 is a plan view illustrating an example of a schematic configuration of a module. [Figure 10A]FIG. 1 is a front view showing an example of the appearance of a digital still camera. [Figure 10B] FIG. 2 is a rear view showing an example of the appearance of a digital still camera. [Figure 11] FIG. 1 is a perspective view showing an example of the appearance of a head mounted display. [Figure 12] FIG. 1 is a perspective view showing an example of the appearance of a television device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will be described in the following order. In all drawings of the following embodiments, the same or corresponding parts are denoted by the same reference numerals. 1. First embodiment 1-1 Display device configuration 1-2 Display device manufacturing method 1-3 Effects 2. Second embodiment 2-1 Display device configuration 2-2 Display device manufacturing method 2-3 Effects 3. Variations 4. Application Examples

[0012] <1 First embodiment> [1-1 Display device configuration] 1 is a schematic diagram showing an example of the overall configuration of a display device 10 according to a first embodiment of the present disclosure. The display device 10 is a so-called organic EL (Electro Luminescence) display device. The display device 10 is suitable for use in various electronic devices, and has a display area 110A and a peripheral area 110B provided on the periphery of the display area 110A.

[0013] A plurality of sub-pixels 100R, 100G, and 100B are arranged in a matrix in the display region 110A. The sub-pixel 100R displays red, the sub-pixel 100G displays green, and the sub-pixel 100B displays blue.

[0014] In the following description, when there is no particular distinction between the sub-pixels 100R, 100G, and 100B, they are referred to as sub-pixel 100. In the following description, the row direction means the row direction of the matrix array, and the column direction means the column direction of the matrix array.

[0015] Columns of sub-pixels 100R, 100G, and 100B that display the same color are repeatedly arranged in the row direction. A combination of three sub-pixels 100R, 100G, and 100B aligned in the row direction constitutes one pixel.

[0016] In addition, the display region 110A is provided with a plurality of signal lines 111A extending in the column direction and a plurality of scanning lines 112A extending in the row direction. Sub-pixels 100 are provided at intersections between the signal lines 111A and the scanning lines 112A. Each signal line 111A is connected to a signal line driving circuit 111, and each scanning line 112A is connected to a scanning line driving circuit 112.

[0017] The peripheral region 110B is provided with a signal line driving circuit 111 and a scanning line driving circuit 112, which are drivers for displaying images. The signal line driving circuit 111 supplies a signal voltage of a video signal corresponding to luminance information supplied from a signal supply source (not shown) to a selected sub-pixel 100 via a signal line 111A. The scanning line driving circuit 112 is composed of a shift register that sequentially shifts (transfers) a start pulse in synchronization with an input clock pulse, and the like. When writing a video signal to each sub-pixel 100, the scanning line driving circuit 112 scans them row by row, and sequentially supplies a scanning signal to each scanning line 112A.

[0018] 2 is a circuit diagram showing an example of the configuration of a pixel circuit 120 that drives the sub-pixel 100. A plurality of pixel circuits 120 are provided in the display area 110A, each corresponding to a respective one of the sub-pixels 100. The pixel circuit 120 is an active-type pixel circuit. The pixel circuit 120 is configured to drive a threshold voltage V thand control the light emission of the light-emitting element 12. th As a method for correcting the above and controlling the light emission of the light emitting element 12, for example, the method described in Japanese Patent No. 5141192 can be used.

[0019] The pixel circuit 120 includes a drive transistor Tr1, a write transistor Tr2, and a capacitance element (capacitor) Cs. One of the source / drain regions (diffusion layer) of the drive transistor Tr1 is connected to a power supply line 113 and is set to a specified potential by a power supply line drive circuit (not shown). The other of the source / drain regions (diffusion layer) of the drive transistor Tr1 is connected to a first electrode of the light emitting element 12 and is connected to one of the electrodes of the capacitance element Cs. The gate electrode of the drive transistor Tr1 is connected to one of the source / drain regions of the write transistor Tr2 and is connected to the other electrode of the capacitance element Cs.

[0020] The other source / drain region of the write transistor Tr2 is connected to a signal line 111A and is supplied with a video signal from the signal line driving circuit 111. The gate electrode of the write transistor Tr2 is connected to a scanning line 112A and is supplied with a scanning signal from the scanning line driving circuit 112.

[0021] The display device 10 is, for example, a microdisplay in which self-luminous elements such as OLED elements or Micro-OLED elements are formed in an array. The display device 10 is suitable for use in a display device for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), an electronic view finder (EVF), a small projector, or the like.

[0022] FIG. 3 is a cross-sectional view showing an example of the configuration of the display device 10 according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing an enlarged portion of FIG. 3. The display device 10 is a top-emission type display device, and includes a drive substrate (first substrate) 11 having a first surface S1 and a second surface S2, an insulating layer 13 and a plurality of light-emitting elements 12 provided on the first surface S1 of the drive substrate 11, a protective layer 14 provided on the plurality of light-emitting elements 12, a color filter 15 provided on the protective layer 14, a filling resin layer 16 provided on the color filter 15, and a counter substrate (second substrate) 17 provided on the filling resin layer 16. Furthermore, the display device 10 includes an insulating layer 18 provided on the second surface S2 of the drive substrate 11, a multilayer wiring layer 19 provided on the insulating layer 18, and a support substrate 11A provided on the multilayer wiring layer 19. The counter substrate 17 side is the top side, and the drive substrate 11 side is the bottom side.

[0023] (Drive board) The driving substrate 11 is a so-called backplane. The driving substrate 11 is a semiconductor substrate 20 that is the main body of the driving substrate 11, and has a pixel circuit 120 formed on a second surface S2 of the semiconductor substrate 20. The pixel circuit 120 further includes a through electrode 24 and a connection portion 25 in addition to the driving transistor Tr1, the writing transistor Tr2, and the capacitance element Cs described above. Note that the writing transistor Tr2 and the capacitance element Cs are not shown in FIGS. 3 and 4.

[0024] The semiconductor substrate 20, which is the main body of the driving substrate 11, is preferably a silicon substrate. This silicon substrate is made of, for example, single crystal silicon or polysilicon (polycrystalline silicon).

[0025] (Drive transistor) The driving transistor Tr1 drives the light emitting element 12. A plurality of driving transistors Tr1 are provided on the second surface S2 of the driving substrate 11. The driving transistor Tr1 is, for example, a P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The driving transistor Tr1 includes a gate electrode 21, a source / drain region 22 which is a first diffusion layer, and a source / drain region 23 which is a second diffusion layer. The channel of the driving transistor Tr1 is made of, for example, single crystal silicon or polysilicon.

[0026] The gate electrode 21 is provided on a region between a source / drain region 22 and a source / drain region 23 provided at a distance from each other. The gate electrode 21 includes, for example, a gate insulating layer 21A provided on the second surface S2 of the drive substrate 11, a polysilicon layer 21B provided on the gate insulating layer 21A, and a silicide layer 21C provided on the polysilicon layer 21B. The gate electrode 21 may further include sidewalls 21D and 21E on both sides.

[0027] The gate insulating layer 21A is made of, for example, a silicon oxide layer. The polysilicon layer 21B is made of, for example, P + is a polysilicon layer of the type. Here, P + A P-type polysilicon layer is a layer that contains P-type impurities. - This refers to a polysilicon layer that is highly doped compared to the type diffusion region 22A.

[0028] The silicide layer 21C includes a compound of silicon and a metal. The metal includes at least one selected from the group consisting of molybdenum (Mo), tungsten (W), titanium (Ti), cobalt (Co) and nickel (Ni). The sidewalls 21D and 21E are formed of a silicon oxide layer.

[0029] The semiconductor substrate 20 has an N-type semiconductor well region (hereinafter referred to as an "N-type well region") 20A on the second surface S2 side. The source / drain regions 22, 23 are P-type semiconductor regions provided in the N-type well region 20A. The source / drain region 22 and the source / drain region 23 are provided separately on the second surface S2 side of the semiconductor substrate 20.

[0030] The source / drain region 22 is P - A diffusion region (first diffusion region) 22A of the P + and a diffusion region (second diffusion region) 22B of the P - The P-type diffusion region 22B is a region in which a P-type impurity is introduced. + The P type diffusion region 22A is a low concentration impurity region that is doped at a lower concentration than the P type diffusion region 22A. + The P-type diffusion region 22B is a region in which a P-type impurity is introduced. - This refers to a high-concentration impurity diffusion region that is doped at a higher concentration than the type diffusion region 22A.

[0031] P + The diffusion region 22B of the P - The diffusion region 22A of the mold is provided. + The diffusion region 22B of the P - The P-type diffusion region 22A is located on the front surface side (the second surface S2 side of the semiconductor substrate 20). + At least a portion of the mold diffusion region 22B is located in the region between the gate electrode 21 and the connection portion 25.

[0032] P + The diffusion region 23B of the P - The diffusion region 23A of the mold is provided. + The diffusion region 23B of the P - The mold is located on the front surface side of the diffusion region 23A (the second surface S2 side of the semiconductor substrate 20).

[0033] The source / drain region 22 is formed by forming a silicide layer 22C by P +The silicide layer 22C is provided on the surface of the diffusion region 22B of the gate electrode 21. The silicide layer 22C is provided on a portion of the second surface S2 of the drive substrate 11 between the gate electrode 21 and the connection portion 25. The material of the silicide layer 22C can be, for example, the same material as the silicide layer 21C of the gate electrode 21. The silicide layer 22C may be made of the same material as the silicide layer 21C of the gate electrode 21, or may be made of a material different from that of the silicide layer 21C of the gate electrode 21.

[0034] The source / drain region 23 is formed by forming a silicide layer 23C by P + The silicide layer 23C is provided on the surface of the diffusion region 23B of the gate electrode 21. An example of a material for the silicide layer 23C is the same as the material for the silicide layer 21C of the gate electrode 21. The silicide layer 23C may be made of the same material as the silicide layer 21C of the gate electrode 21, or may be made of a material different from that of the silicide layer 21C of the gate electrode 21.

[0035] (Through electrode) The through electrode 24 connects the light emitting element 12 and the connection portion 25. The through electrode 24 penetrates between the first surface S1 and the second surface S2 of the driving substrate 11. The through electrode 24 has, for example, a pillar shape. The through electrode 24 includes, for example, a conductive material such as polysilicon, single crystal silicon, or a metal. In order to suppress leakage current between the through electrode 24 and the driving substrate 11, it is preferable that the through electrode 24 includes polysilicon or single crystal silicon. As the metal, tungsten (W) is preferable.

[0036] (separation area) The drive substrate 11 may include an isolation region 26, and the through electrode 24 may be provided in this isolation region 26. Specifically, the isolation region 26 may have a contact hole 24H, and the through electrode 24 may be provided in this contact hole 24H. The isolation region 26 separates the through electrode 24 from the semiconductor substrate 20. This makes it possible to suppress leakage current from flowing between the through electrode 24 and the drive substrate 11. The isolation region 26 is formed of, for example, an oxide layer such as a silicon oxide layer.

[0037] The isolation region 26 includes a first isolation region 26A and a second isolation region 26B. The first isolation region 26A suppresses leakage current flowing between the through electrode 24 and the source / drain region 22. The first isolation region 26A is provided adjacent to the source / drain region 22 on the second surface S2 side of the drive substrate 11. The first isolation region 26A may be an inter-element isolation (Shallow Trench Isolation) region that separates the drive transistor Tr1 from other elements provided on the second surface S2 of the drive substrate 11. The width of the first isolation region 26A may be wider than the width of the second isolation region 26B.

[0038] The second isolation region 26B suppresses leakage current flowing between a portion of the semiconductor substrate 20 deeper than the source / drain region 22 and the through electrode 24. The second isolation region 26B has, for example, a pillar shape. The second isolation region 26B extends from the first surface S1 of the semiconductor substrate 20 to the first isolation region 26A and is coupled to the first isolation region 26A.

[0039] (Connection) A plurality of connection parts 25 are provided on the second surface S2 of the drive substrate 11. The connection parts 25 connect the source / drain region (diffusion layer) 22 of the drive transistor Tr1 and the through electrode 24. In addition, the connection parts 25 function as an etching stopper layer when the contact hole 24H is formed by etching.

[0040] The connection portion 25 includes, for example, a polysilicon layer 25A provided on the second surface S2 of the drive substrate 11, and a silicide layer 25B provided on the polysilicon layer 25A. The connection portion 25 includes the silicide layer 25B, so that the parasitic resistance between the drive transistor Tr1 and the through electrode 24 can be reduced. However, the silicide layer 25B is provided as necessary, and does not necessarily have to be provided. The connection portion 25 may further include sidewalls 25C and 25D on both sides.

[0041] The polysilicon layer 25A is an example of a semiconductor layer. + The polysilicon layer 25A is a polysilicon layer of a type. An example of the material of the polysilicon layer 25A is the same material as the polysilicon layer 21B of the gate electrode 21. The polysilicon layer 25A may be made of the same material as the polysilicon layer 21B of the gate electrode 21, or may be made of a material different from that of the polysilicon layer 21B of the gate electrode 21.

[0042] The silicide layer 25B is an example of a semiconductor compound layer. An example of the material of the silicide layer 25B is the same material as the silicide layer 21C of the gate electrode 21. The silicide layer 25B may be made of the same material as the silicide layer 21C of the gate electrode 21, or may be made of a material different from that of the silicide layer 21C of the gate electrode 21. The sidewalls 25C and 25D are made of, for example, a silicon oxide layer.

[0043] In order to suppress leakage current flowing between the connection portion 25 and the semiconductor substrate 20, the connection portion 25 is preferably provided within a region consisting of the source / drain region 22 and the first isolation region 26A. That is, the connection portion 25 is preferably in contact with only the source / drain region 22 and the first isolation region 26A on the first surface S1 of the semiconductor substrate 20.

[0044] (insulating layer) The insulating layer 18 is provided on the second surface S2 of the drive substrate 11. The insulating layer 18 is provided with a conductive plug 18A, a conductive plug 18B, and the like. The conductive plug 18A connects the wiring 19A of the multi-layer wiring layer 19 and the silicide layer 21C of the gate electrode 21. The conductive plug 18B connects a power supply line (not shown) and the source / drain region 23.

[0045] (Multilayer wiring layer) The multi-layer wiring layer 19 is provided on the insulating layer 18. The multi-layer wiring layer 19 includes a plurality of wiring layers such as the wiring 19A.

[0046] (Support substrate) The support substrate 11A is provided on the multi-layer wiring layer 19. The support substrate 11A supports the drive substrate 11. The support substrate 11A is made of, for example, silicon.

[0047] (Light emitting element) A plurality of light-emitting elements 12 are arranged in a matrix on one main surface of the driving substrate 11. The light-emitting elements 12 are white OLED elements or white Micro-OLED (MOLED) elements. In the first embodiment, a method of using white OLED elements and color filters 15 is used as a colorization method in the display device 10. Note that the colorization method is not limited to this, and a method of coloring RGB or the like may also be used. Also, a single-color filter may be used.

[0048] The light emitting element 12 has a first electrode (eg, an anode) 12A, an organic layer 12B, and a second electrode (eg, a cathode) 12C stacked on a first surface S1 of a driving substrate 11 in this order.

[0049] (First electrode) The first electrode 12A is provided for each sub-pixel 100, electrically separated from the other. The first electrode 12A also functions as a reflective layer, and is preferably made of a metal layer having as high a reflectance and a large work function as possible in terms of improving light emission efficiency. As a material for the metal layer, for example, at least one of a simple substance or an alloy of a metal element such as chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), magnesium (Mg), iron (Fe), tungsten (W), or silver (Ag) can be used. As a specific example of the alloy, it may be made of a laminated film of a plurality of metal layers.

[0050] (Second electrode) The second electrode 12C is provided as a common electrode for all the sub-pixels 100 in the display region 110A. The second electrode 12C is a transparent electrode that is transparent to the light generated in the organic layer 12B. Here, the transparent electrode also includes a semi-transparent reflective layer. The second electrode 12C is made of, for example, a metal or a metal oxide. As the metal, at least one of a simple substance and an alloy of a metal element such as aluminum (Al), magnesium (Mg), calcium (Ca), or sodium (Na) can be used. As the alloy, for example, an alloy of magnesium (Mg) and silver (Ag) (MgAg alloy) or an alloy of aluminum (Al) and lithium (Li) (AlLi alloy) is suitable. As the metal oxide, for example, a mixture of indium oxide and tin oxide (ITO), a mixture of indium oxide and zinc oxide (IZO), or a metal oxide such as zinc oxide (ZnO) can be used.

[0051] (insulating layer) The insulating layer 13 serves to electrically separate the first electrodes 12A for each subpixel 100. The insulating layer 13 is provided between the first electrodes 12A and covers the periphery of the first electrodes 12A. More specifically, the insulating layer 13 has openings in portions corresponding to the first electrodes 12A, and covers from the periphery of the upper surface of the first electrodes 12A (the surface facing the second electrode 12C) to the side surfaces (end surfaces) of the first electrodes 12A.

[0052] The insulating layer 13 is made of, for example, an organic material or an inorganic material. Examples of the organic material include polyimide and acrylic resin. Examples of the inorganic material that can be used include silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0053] (organic layer) The organic layer 12B is provided between the first electrode 12A and the second electrode 12C. The organic layer 12B is provided as an organic layer common to all the sub-pixels 100 in the display region 110A. The organic layer 12B has a configuration in which, for example, a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are laminated in this order from the first electrode 12A side. Note that the configuration of the organic layer is not limited to this, and layers other than the light-emitting layer are provided as necessary.

[0054] The hole injection layer is for increasing the efficiency of hole injection into the light emitting layer and is a buffer layer for suppressing leakage. The hole transport layer is for increasing the efficiency of hole transport into the light emitting layer. The light emitting layer generates light by recombining electrons and holes when an electric field is applied. The electron transport layer is for increasing the efficiency of electron transport into the light emitting layer. An electron injection layer may be provided between the electron transport layer and the second electrode 12C. This electron injection layer is for increasing the efficiency of electron injection.

[0055] (protective layer) The protective layer 14 is intended to insulate the light emitting element 12 from the outside air and to prevent moisture from entering the light emitting element 12 from the external environment. In addition, when the second electrode 12C is made of a metal layer, the protective layer 14 may also have a function of preventing oxidation of the metal layer.

[0056] The protective layer 14 is made of, for example, an inorganic material with low hygroscopicity. The inorganic material includes, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), titanium oxide (TiO), and aluminum oxide (AlO). The protective layer 14 may have a single-layer structure, but may have a multi-layer structure when the thickness is increased. This is to relieve internal stress in the protective layer 14. The protective layer 14 may be made of a polymer resin. The polymer resin includes at least one of a thermosetting resin and an ultraviolet-curing resin.

[0057] (Color filter) The color filter 15 is, for example, an on-chip color filter (OCCF). The color filter 15 includes, for example, a red filter, a green filter, and a blue filter. The red filter, the green filter, and the blue filter are provided facing the light emitting element 12 of the sub-pixel 100R, the light emitting element 12 of the sub-pixel 100G, and the light emitting element 12 of the sub-pixel 100B, respectively. As a result, the white light emitted from each light emitting element 12 in the sub-pixel 100R, the sub-pixel 100G, and the sub-pixel 100B passes through the above-mentioned red filter, green filter, and blue filter, respectively, and red light, green light, and blue light are respectively emitted from the display surface. In addition, a light shielding layer (not shown) may be provided between the color filters of each color, i.e., in the region between the sub-pixels 100. Note that the color filter 15 is not limited to an on-chip color filter, and may be provided on one main surface of the counter substrate 17.

[0058] (Filled resin layer) The filled resin layer 16 functions as an adhesive layer that bonds the color filter 15 and the counter substrate 17. The filled resin layer 16 contains, for example, at least one of a thermosetting resin and an ultraviolet-curing resin.

[0059] (opposing substrate) The counter substrate 17 is provided so that one surface of the counter substrate 17 faces a first surface S1 of the drive substrate 11 on which a plurality of light emitting elements 12 are provided. The counter substrate 17, together with the filled resin layer 16, seals the light emitting elements 12, the color filter 15, etc. The counter substrate 17 is made of a material such as glass that is transparent to the colored light emitted from the color filter 15.

[0060] [1-2 Display device manufacturing method] Hereinafter, an example of a manufacturing method for the display device 10 according to the first embodiment of the present disclosure will be described with reference to FIGS. 5A to 5K.

[0061] First, a plurality of second isolation regions 26B penetrating from the first surface S1 to the second surface S2 of the semiconductor substrate 20 are formed in the semiconductor substrate 20 (see FIG. 5A). Next, a first isolation region 26A is formed in the upper portion of each second isolation region 26B (the end portion on the second surface S2 side of the semiconductor substrate 20), and then a plurality of N-type well regions 20A are formed by implanting ions into the second surface S2 of the semiconductor substrate 20. After the N-type well region 20A is formed, for example, the second surface S2 of the semiconductor substrate 20 is oxidized to form a gate insulating layer 21A on the second surface S2 of the semiconductor substrate 20 (see FIG. 5B).

[0062] Next, a P-type impurity such as boron is ion-implanted into each N-type well region 20A to form a P - A plurality of diffusion regions 22B, 23B of the mold are formed. Next, the gate insulating layer 21A is partially removed, and a surface exposed portion 22D in which the surface of each diffusion region 22A is exposed is formed in a portion of the surface of each diffusion region 22A adjacent to the first isolation region 26A (see FIG. 5C).

[0063] Next, a polysilicon layer 25E is formed on the second surface S2 of the semiconductor substrate 20 by, for example, a CVD (Chemical Vapor Deposition) method (see FIG. 5D). Next, the polysilicon layer 25E is patterned by, for example, photolithography and etching to form a plurality of gate electrodes 21 and a polysilicon layer 25A on the second surface S2 of the semiconductor substrate 20 (see FIG. 5E).

[0064] Next, an oxide layer is formed on the semiconductor substrate 20 by, for example, a CVD method, and then the oxide layer is etched back to form sidewalls 21D and 21E on each gate electrode 21 and to form sidewalls 25C and 25D on the polysilicon layer 25A. The sidewalls 25C and 25D and the polysilicon layer 25A constitute a connection portion 25.

[0065] Thereafter, a P-type impurity such as boron is doped into the polysilicon layer 21B of each gate electrode 21, the polysilicon layer 25A of each connection portion 25, and each P - The diffusion region 22B and each P- As a result, the polysilicon layer 21B of each gate electrode 21 and the polysilicon layer 25A of each connection portion 25 are implanted into the P + The polysilicon layer is a molded layer. - The diffusion region 22A of the mold, each P - The diffusion regions 23A are each + Diffusion region 22B, P + In this case, the P-type impurity is doped with the P-type impurity. - The ions are implanted at a higher concentration than in the process of forming the mold diffusion regions 22A and 23A.

[0066] Next, the upper portions of the gate electrodes 21 and the connecting portions 25 are silicided, and the P + The diffusion region 22B and each P + The surface of the diffusion region 23B of the P-type is silicided. As a result, a silicide layer 21C and a silicide layer 25B are formed on the upper portions of the gate electrodes 21 and the connecting portions 25, respectively. + The diffusion region 22B of the mold, each P + A silicide layer 22C and a silicide layer 23C are formed on the surfaces of the diffusion regions 23B of the mold, respectively (see FIG. 5G). In this manner, the drive substrate 11 is obtained.

[0067] Next, an insulating layer 18 is formed on the second surface S2 of the semiconductor substrate 20 by, for example, a CVD method, and then the surface of the insulating layer 18 is polished and flattened by, for example, CMP (Chemical Mechanical Polishing). Next, a contact hole 18AH is formed in the insulating layer 18 by, for example, photolithography and etching, and then a tungsten layer is formed on the insulating layer 18 by, for example, a CVD method, and the contact hole 18AH is filled with the tungsten layer. Next, the tungsten layer is polished by, for example, CMP, and the tungsten layer other than in the contact hole 18AH is removed. As a result, a conductive plug 18A is formed in the contact hole 18AH (see FIG. 5H). Next, a multilayer wiring layer 19 including wiring 19A is formed on the insulating layer 18 (see FIG. 5I). The configuration of this multilayer wiring layer 19 is selected according to the specifications of the circuit to be used.

[0068] Next, the support substrate 11A is bonded to the multi-layer wiring layer 19, and the drive substrate 11 and the like are inverted together with the support substrate 11A, and then the first surface S1 of the drive substrate 11 is polished by, for example, CMP, to adjust the semiconductor substrate 20 to a desired thickness. Next, a contact hole 24H penetrating the semiconductor substrate 20 is formed in the separation region 26 by, for example, dry etching. At this time, the connection portion 25 functions as an etching stopper layer. Thereafter, a conductive material is embedded in the contact hole 24H, and the first surface S1 of the semiconductor substrate 20 is polished and flattened by, for example, CMP. As a result, a conductive plug 18A is formed in the contact hole 24H (see FIG. 5J).

[0069] Next, a metal layer is formed on the first surface S1 of the driving substrate 11, for example by a sputtering method, and then the metal layer is patterned, for example by photolithography and etching, to form a plurality of first electrodes 12A separated for each light-emitting element 12 (i.e., for each sub-pixel 100) (see Figure 5K).

[0070] Next, the insulating layer 13 is formed by, for example, a CVD method. Next, the insulating layer 13 is patterned by photolithography and etching. Next, a hole injection layer, a hole transport layer, a light emitting layer, and an electron transport layer are laminated in this order on the multiple first electrodes 12A and on the insulating layer 13 by, for example, a vapor deposition method, to form the organic layer 12B. Next, a second electrode 12C is formed on the organic layer 12B by, for example, a sputtering method. As a result, multiple light emitting elements 12 are formed on the first surface S1 of the driving substrate 11.

[0071] Next, the protective layer 14 is formed on the second electrode 12C by, for example, a vapor deposition method or a CVD method, and then the color filter 15 is formed on the protective layer 14 by, for example, photolithography. In order to flatten the step of the protective layer 14 or the step due to the film thickness difference of the color filter 15 itself, a flattening layer may be formed above, below, or both above and below the color filter 15. Next, the color filter 15 is covered with the filled resin layer 16 by, for example, an ODF (One Drop Fill) method, and then the counter substrate 17 is placed on the filled resin layer 16. Next, for example, the filled resin layer 16 is heated or irradiated with ultraviolet light to harden the filled resin layer 16, thereby bonding the driving substrate 11 and the counter substrate 17 via the filled resin layer 16. This seals the display device 10. In addition, when the filled resin layer 16 contains both a thermosetting resin and an ultraviolet-curing resin, the filled resin layer 16 may be temporarily hardened by irradiating it with ultraviolet light, and then the filled resin layer 16 may be fully hardened by applying heat thereto. In this manner, the display device 10 shown in FIG. 3 is obtained.

[0072] [1-3 Effects] 6 is a cross-sectional view showing a configuration of a display device 410 according to a reference example. In a driving substrate 411 of the display device 410, a source / drain region (diffusion layer) 22 of a driving transistor Tr1 and a through electrode 24 are connected by conductive plugs 418A, 418B of an insulating layer 418 and a wiring 419A of a multi-layer wiring layer 419. Therefore, the degree of freedom of routing of wiring 419B and the like other than the wiring 419A included in the multi-layer wiring layer 419 is reduced. Furthermore, minimum processing dimensions that are disadvantageous in terms of manufacturing yield are often used, which is likely to lead to a decrease in yield. Furthermore, when a voltage higher than that used in typical LSIs (e.g., 1.2 V or 3.3 V) is applied to the first electrode 12A that drives the light-emitting element 12 (as is often required for liquid crystal elements and OLED elements), from the standpoint of reliability, the wiring 419A connected to the through electrode 24 needs to be spaced farther from the adjacent wiring 419B, etc. than the others, which reduces the freedom of routing of the wiring 419B, etc.

[0073] In contrast, as described above, in the drive substrate 11 of the display device 10 according to the first embodiment, the source / drain region (diffusion layer) 22 of the drive transistor Tr1 and the through electrode 24 are connected by the connection portion 25. This makes it possible to reduce the wiring 419A and the like in the reference example. Therefore, in the display device 10 according to the first embodiment, it is possible to improve the degree of freedom in routing the wiring 19A and the like included in the multilayer wiring layer 19. In addition, the area obtained by reducing the wiring 419A can be effectively utilized. For example, the manufacturing yield of the display device 10 can be improved by thickening the wiring 19A and the like included in the multi-wiring layer 19 and widening the space between the wirings. Furthermore, in the first embodiment, when the through electrode 24 is superimposed (i.e., aligned) on the connection portion 25, the degree of freedom in the size, shape, and the like of the pattern (i.e., the connection portion 25) on which the through electrode 24 is superimposed can be improved compared to the case in the reference example in which the through electrode 24 is superimposed on the conductive plug 418A. This improves the manufacturing yield of the display device 10, and also suppresses the variation in resistance between the source / drain region (diffusion layer) 22 and the through electrode 24.

[0074] Furthermore, the use of minimum processing dimensions that are disadvantageous in terms of manufacturing yield can be reduced, so that a decrease in yield can be suppressed. In addition, since the reduction in wiring 419A provides space in the multilayer wiring layer 19, even if it is necessary to increase the spacing between the wirings in the multilayer wiring layer 19 from the standpoint of reliability, as described above, it is possible to suppress a decrease in the freedom of wiring layout.

[0075] The drive substrate 11 includes the through electrodes 24 in the isolation regions 26 (that is, the first isolation region 26A and the second isolation region 26B). This makes it possible to suppress leakage current flowing between the semiconductor substrate 20 and the through electrodes 24.

[0076] The through electrode 24 is provided in the first isolation region 26A on the second surface S2 side of the semiconductor substrate 20. This makes it possible to reduce the area where the polysilicon layer 25A of the connection portion 25 contacts the semiconductor substrate 20. Therefore, the leakage current flowing between the semiconductor substrates 20 can be suppressed.

[0077] <2. Second embodiment> [2-1 Display device configuration] 7 is a schematic diagram showing an example of an overall configuration of a display device 10A according to a second embodiment of the present disclosure. The display device 10A according to the second embodiment differs from the display device 10 according to the first embodiment in that the display device 10A includes a connection portion 27 instead of the connection portion 25 (see FIG. 3).

[0078] The connection portion 27, like the connection portion 25, connects the source / drain region (diffusion layer) 22 of the driving transistor Tr1 to the through electrode 24. The connection portion 25 is made of, for example, a silicide layer. The silicide layer is an example of a semiconductor compound layer. An example of a material for the silicide layer constituting the connection portion 25 is a material similar to that of the silicide layer 21C of the gate electrode 21. The silicide layer constituting the connection portion 27 may be made of a material similar to that of the silicide layer 21C of the gate electrode 21, or may be made of a material different from that of the silicide layer 21C of the gate electrode 21.

[0079] [2-2 Display device manufacturing method] Hereinafter, an example of a manufacturing method for the display device 10A according to the second embodiment of the present disclosure will be described with reference to FIGS. 5A, 5B, and 8A to 8D.

[0080] First, the steps from forming the second isolation region 26B (see FIG. 5A) to forming the gate insulating layer 21A (see FIG. 5B) are performed in the same manner as in the manufacturing method of the display device 10 according to the first embodiment. Next, P-type impurities such as boron are ion-implanted into each N-type well region 20A to form P - A plurality of mold diffusion regions 22B and 23B are formed.

[0081] Next, a polysilicon layer 25E is formed on the second surface S2 of the semiconductor substrate 20 by, for example, a CVD method (see FIG. 8A). Next, the polysilicon layer 25E is patterned by, for example, photolithography and etching to form a plurality of gate electrodes 21 on the second surface S2 of the semiconductor substrate 20 (see FIG. 8B).

[0082] Next, an oxide layer is formed on the semiconductor substrate 20 by, for example, a CVD method, and then the oxide layer is etched back to form sidewalls 21D, 21E on each gate electrode 21 (see FIG. 8C). Next, a polysilicon layer 27A is formed on the second surface S2 of the semiconductor substrate 20 by, for example, a CVD method, and then the polysilicon layer 27A is patterned by, for example, photolithography and etching, so that the polysilicon layer 27A remains on each isolation region 26.

[0083] Next, a P-type impurity such as boron is doped into each of the polysilicon layers 21B, 27A, and - The diffusion region 22A and each P - The dopant is implanted into the diffusion region 23A of the type 21B. This causes each of the polysilicon layers 21B and each of the polysilicon layers 27A to have a P + The polysilicon layer is a molded layer. - The diffusion region 22A of the mold, each P - The diffusion regions 23A are each + Diffusion region 22B, P + A mold diffusion region 23B is formed.

[0084] Next, the upper portion of each gate electrode 21, each P + The surface of the diffusion region 23B of the mold, each P + The surface of the mold diffusion region 22B and the entirety of each polysilicon layer 27A are silicided to form the silicide layer 21C, the silicide layer 23C, and the connection portion (silicide layer) 27 (see FIG. 8D). In this manner, the drive substrate 11 is obtained. Next, the steps after the step of forming the insulating layer 18 are performed in the same manner as in the manufacturing method of the display device 10 according to the first embodiment. In this manner, the display device 10A shown in FIG.

[0085] [2-3 Effects] As described above, in the drive substrate 11 of the display device 10A according to the second embodiment, the source / drain region (diffusion layer) 22 of the drive transistor Tr1 and the through electrode 24 are connected by a connection portion 27 made of a silicide layer. Therefore, compared to the display device 10 according to the first embodiment, the parasitic resistance between the drive transistor Tr1 and the through electrode 24 can be reduced.

[0086] <3 Variation> (Variation 1) In the above-described first and second embodiments, examples have been described in which the semiconductor substrate 20 includes the first isolation region 26A and the second isolation region 26B. However, the semiconductor substrate 20 may not include the second isolation region 26B, or may not include the first isolation region 26A and the second isolation region 26B.

[0087] (Variation 2) In the above-described first embodiment, the impurity concentration of the polysilicon layer 25A of the connection portion 25 is substantially the same as that of the polysilicon layer 21B of the driving transistor Tr1. However, the impurity concentration of the polysilicon layer 25A of the connection portion 25 may be different from that of the polysilicon layer 21B of the driving transistor Tr1. For example, the impurity concentration of the polysilicon layer 25A of the connection portion 25 may be higher than that of the polysilicon layer 21B of the driving transistor Tr1. In this case, the contact resistance between the polysilicon layer 25A of the connection portion 25 and the source / drain region 22, and the contact resistance between the polysilicon layer 25A of the connection portion 25 and the through electrode 24 can be reduced. Also, the parasitic resistance between the driving transistor Tr1 and the through electrode 24 can be reduced.

[0088] (Variation 3) In the above-described first embodiment, an example in which the connection portion 25 includes the polysilicon layer 25A and the silicide layer 25B has been described, but the entire connection portion 25 may be made of a silicide layer. In this case, the parasitic resistance between the drive transistor Tr1 and the through electrode 24 can be reduced.

[0089] (Variation 4) In the above-described first and second embodiments, the gate electrode 21 includes the gate insulating layer 21A, the polysilicon layer 21B, and the silicide layer 21C. However, the gate electrode 21 may include the gate insulating layer 21A and the silicide layer 21C. In this case, the parasitic resistance between the drive transistor Tr1 and the through electrode 24 can be reduced.

[0090] (Variation 5) In the above-described first and second embodiments, an example was described in which the driving substrate 11 has a configuration in which the pixel circuits 120 are formed on the semiconductor substrate 20, but the driving substrate 11 may have a configuration in which the pixel circuits 120 are formed on a glass substrate.

[0091] (Variation 6) In the above-described first and second embodiments, the driving transistor Tr1 is a P-type MOSFET, but the driving transistor Tr1 may be an N-type MOSFET. Note that in the above-described first and second embodiments, the writing transistor Tr2 may be a P-type MOSFET or an N-type MOSFET.

[0092] (Variation 7) In the above-described first and second embodiments, examples have been described in which the light-emitting element 12 is an OLED element or the like, but the light-emitting element 12 may also be a self-luminous light-emitting element such as an inorganic electroluminescence (IEL) element or a semiconductor laser element.

[0093] (Variation 8) In the above-described first embodiment, an example has been described in which the silicide layer 22C is provided on the surface of the source / drain region (diffusion layer) 22, but the silicide layer 22C may not be provided on the surface of the source / drain region 22. That is, the surface of the source / drain region 22 may be non-silicide. In this case, it is possible to suppress leakage current between the connection portion 25 and the N-type well region 20A.

[0094] (Variation 9) In the above-mentioned first embodiment, an example in which the connection portion 25 includes the polysilicon layer 25A and the silicide layer 25B has been described, but the connection portion 25 may include a metal layer instead of the polysilicon layer 25A and the silicide layer 25B. In the above-mentioned second embodiment, an example in which the connection portion 27 is configured with a silicide layer has been described, but the connection portion 25 may be configured with a metal layer. The metal layer may be configured with, for example, Ta, TaN, or Nb, or may be configured with two metal layers of a WN layer and a RuO2 layer.

[0095] The gate electrode 21 may be a metal gate electrode. Specifically, the gate electrode 21 may include a metal layer instead of the polysilicon layer 21B. When the gate electrode 21 is a metal gate electrode, the metal layer of the gate electrode 21 and the metal layers of the connection parts 25 and 27 may be made of the same metal material or different metal materials. When the driving transistor Tr1 is a P-type MOSFET, the metal layer of the gate electrode 21 is made of, for example, Ta, TaN, or Nb. When the driving transistor Tr1 is an N-type MOSFET, the metal layer of the gate electrode 21 is made of, for example, two metal layers, a WN layer and a RuO2 layer.

[0096] <4 Application Examples> (electronic equipment) The display device 10, 10A according to any of the above-mentioned first and second embodiments and their modified examples is incorporated into various electronic devices as a module as shown in FIG. 9. In particular, the display device 10, 10A is suitable for electronic viewfinders of video cameras and single-lens reflex cameras, head-mounted displays, and other devices that require high resolution and are used in a magnified manner near the eyes. This module has an exposed area 210 on one short side of the drive substrate 11 that is not covered by an opposing substrate or the like, and an external connection terminal (not shown) is formed in this area 210 by extending the wiring of the signal line drive circuit 111 and the scanning line drive circuit 112. A flexible printed circuit (FPC) 220 for inputting and outputting signals may be connected to this external connection terminal.

[0097] (Example 1) 10A and 10B show an example of the external appearance of a digital still camera 310. This digital still camera 310 is a lens-interchangeable single-lens reflex type, and has an interchangeable photographing lens unit (interchangeable lens) 312 approximately in the center of the front of a camera main body (camera body) 311, and a grip part 313 for the photographer to hold on the left side of the front.

[0098] A monitor 314 is provided at a position shifted leftward from the center on the back of the camera body 311. An electronic viewfinder (eyepiece window) 315 is provided above the monitor 314. By looking into the electronic viewfinder 315, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 312 and determine the composition. As the electronic viewfinder 315, the display device 10 or 10A according to any of the above-mentioned first and second embodiments and their modified examples can be used.

[0099] (Example 2) 11 shows an example of the appearance of a head mounted display 320. The head mounted display 320 has, for example, ear hooks 322 for wearing on the user's head on both sides of a glasses-shaped display unit 321. As the display unit 321, the display device 10 or 10A according to any of the above-mentioned first and second embodiments and their modified examples can be used.

[0100] (Example 3) 12 shows an example of the appearance of a television device 330. This television device 330 has an image display screen unit 331 including, for example, a front panel 332 and a filter glass 333, and this image display screen unit 331 is configured by the display device 10, 10A according to any one of the above-mentioned first and second embodiments and their modified examples.

[0101] The above describes the first and second embodiments and modified examples of the present disclosure in detail. However, the present disclosure is not limited to the above-described first and second embodiments and modified examples, and various modifications based on the technical ideas of the present disclosure are possible.

[0102] For example, the configurations, methods, steps, shapes, materials, and values, etc., described in the first and second embodiments and the modified examples described above are merely examples, and different configurations, methods, steps, shapes, materials, and values, etc., may be used as necessary.

[0103] The configurations, methods, steps, shapes, materials, numerical values, and the like of the first and second embodiments and the modifications described above can be combined with each other without departing from the spirit of the present disclosure.

[0104] Unless otherwise specified, the materials exemplified in the above-mentioned first and second embodiments and modified examples can be used alone or in combination of two or more.

[0105] The present disclosure may also employ the following configuration. (1) a drive substrate having a first surface and a second surface; A plurality of light emitting elements provided on the first surface; Equipped with The drive substrate is a plurality of driving transistors provided on the second surface and configured to drive the plurality of light emitting elements, respectively; a plurality of through electrodes penetrating between the first surface and the second surface; a plurality of connection portions provided on the second surface, the connection portions connecting the diffusion layers of the driving transistors and the through electrodes; Equipped with The connection portion is a display device including a semiconductor layer or a semiconductor compound layer. (2) the semiconductor layer is a polysilicon layer, The display device according to (1), wherein the semiconductor compound layer is a silicide layer. (3) The display device according to (1) or (2), wherein the connection portion further comprises a semiconductor compound layer provided on the semiconductor layer. (4) the semiconductor layer is a polysilicon layer, The display device according to (3), wherein the semiconductor compound layer is a silicide layer. (5) The display device according to any one of (1) to (4), wherein the surface of the diffusion layer is non-silicide. (6) the connection portion comprises a first polysilicon layer; a gate electrode of the driving transistor comprising a second polysilicon layer; The display device according to any one of (1) to (5), wherein the first polysilicon layer and the second polysilicon layer are made of the same material. (7) the connection portion comprises a first polysilicon layer; a gate electrode of the driving transistor comprising a second polysilicon layer; The display device according to any one of (1) to (5), wherein the first polysilicon layer and the second polysilicon layer are made of different materials. (8) The display device according to any one of (1) to (7), wherein the drive substrate includes a separation region that separates the through electrode from a semiconductor substrate that is a main body of the drive substrate. (9) The display device according to any one of (1) to (8), wherein the through electrode contains tungsten. (10) The display device according to any one of (1) to (8), wherein the through electrode includes polysilicon. (11) The display device according to any one of (1) to (8), wherein the through electrode contains single crystal silicon. (12) The display device according to any one of (1) to (9), wherein the light-emitting element is an organic light-emitting diode element. (13) The driving substrate is a threshold voltage V th and a pixel circuit for controlling the emission of the light emitting element, The display device according to any one of (1) to (12), wherein the pixel circuit includes the drive transistor, a signal writing transistor, and a capacitive element. (14) The display device according to any one of (1) to (13), wherein the channel of the driving transistor is made of single crystal silicon. (15) An electronic device comprising the display device according to any one of (1) to (14). [Explanation of symbols]

[0106] 10, 10A, 410 display device 11, 411 Drive board 11A support board 12 Light emitting element 12A First electrode 12B Organic layer 12C Second electrode 13 Insulating layer 14 Protective layer 15 Color Filters 16 Filled resin layer 17 Opposing substrate 18, 418 Insulating layer 18A, 18B, 418A, 418B Conductive plug 19, 419 Multilayer wiring layer 19A, 419A, 419B Wiring 20 Semiconductor substrate 20A N-type semiconductor well area 21 Gate electrode 21A Gate insulation layer 21B Polysilicon layer 21C silicide layer 21D, 21E Sidewall 22, 23 Source / drain region (diffusion layer) 22A, 23A P - Mold diffusion area 22B, 23B P + Mold diffusion area 22C, 23C Polysilicon layer 24 Through electrode 25, 27 Connection 25A Polysilicon layer (semiconductor layer) 25B Silicide layer (semiconductor compound layer) 25C, 25D sidewall 26 Separation area 26A First Separation Region 26B Second Separation Region 100R, 100G, 100B subpixels 110A display area 110B Surrounding Area 111 Signal line driver circuit 111A signal line 112 Scanning line driving circuit 112A Scan Line 310 Digital still cameras (electronic devices) 320 Head-mounted display (electronic device) 330 Television equipment (electronic devices) Cs capacitive element S1 First Side S2 Second Side Tr1 Drive transistor Tr2 Write transistor

Claims

1. a drive substrate having a first surface and a second surface; A plurality of light emitting elements provided on the first surface; Equipped with The drive substrate is a plurality of driving transistors provided on the second surface and configured to drive the plurality of light-emitting elements, respectively; a plurality of through electrodes penetrating between the first surface and the second surface; a plurality of connection portions provided on the second surface, the connection portions connecting the diffusion layers of the driving transistors and the through electrodes; Equipped with The connection portion is a display device including a semiconductor layer or a semiconductor compound layer.

2. the semiconductor layer is a polysilicon layer, 2. The display device according to claim 1, wherein the semiconductor compound layer is a silicide layer.

3. The display device according to claim 1 , wherein the connection portion further comprises a semiconductor compound layer provided on the semiconductor layer.

4. the semiconductor layer is a polysilicon layer, 4. The display device according to claim 3, wherein the semiconductor compound layer is a silicide layer.

5. 2. The display device according to claim 1, wherein the surface of the diffusion layer is non-silicide.

6. the connection portion comprises a first polysilicon layer; a gate electrode of the driving transistor comprising a second polysilicon layer; 2. The display device according to claim 1, wherein the first polysilicon layer and the second polysilicon layer are made of the same material.

7. the connection portion comprises a first polysilicon layer; a gate electrode of the driving transistor comprising a second polysilicon layer; 2. The display device according to claim 1, wherein the first polysilicon layer and the second polysilicon layer are made of different materials.

8. The display device according to claim 1 , wherein the drive substrate includes a separation region that separates the through-electrode from a semiconductor substrate that is a main body of the drive substrate.

9. The display device according to claim 1 , wherein the through electrode includes tungsten.

10. The display device according to claim 1 , wherein the through electrode includes polysilicon.

11. The display device according to claim 1 , wherein the through electrode includes single crystal silicon.

12. The display device according to claim 1 , wherein the light-emitting element is an organic light-emitting diode element.

13. The driving substrate is a threshold voltage V th and a pixel circuit for controlling the emission of the light emitting element, The display device according to claim 1 , wherein the pixel circuit comprises the drive transistor, a signal writing transistor, and a capacitance element.

14. 2. The display device according to claim 1, wherein the channel of the driving transistor is made of single crystal silicon.

15. An electronic device comprising the display device according to claim 1 .

Images