Method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device with good electrical characteristics, To provide a semiconductor device with stable electrical characteristics, To provide a highly reliable semiconductor device. [Solution] The semiconductor device has a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer has an island-shaped top surface. The first insulating layer is provided in contact with the top surface and side surfaces of the semiconductor layer. The first conductive layer is located on the first insulating layer and has a portion overlapping with the semiconductor layer. The semiconductor layer contains a metal oxide, and the first insulating layer contains an oxide. The semiconductor layer has a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer. The first insulating layer has a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer. The second region and the fourth region contain phosphorus or boron.

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device. 2. Description of the Related Art One embodiment of the present invention relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have been attracting attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like, and therefore can be used for the semiconductor layer of transistors that constitute large display devices. In addition, since it is possible to use a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon by improving it, capital investment can be reduced. In addition, transistors using metal oxides have higher field-effect mobility than those using amorphous silicon, and therefore a high-performance display device provided with a driver circuit can be realized.

[0005] Furthermore, Patent Document 2 discloses a thin-film transistor in which an oxide semiconductor film having a low-resistance region containing at least one element selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, and lead as a dopant is applied to a source region and a drain region. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2011-228622 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics, a semiconductor device with stable electrical characteristics, or a semiconductor device with high reliability.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer has an island-shaped top surface. The first insulating layer is provided in contact with an upper surface and a side surface of the semiconductor layer. The first conductive layer is located on the first insulating layer and has a portion overlapping with the semiconductor layer. The semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer. The first insulating layer includes a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer. The second region and the fourth region include a first element. The first element is preferably phosphorus, boron, magnesium, aluminum, or silicon. The first element is preferably present in a state bonded to oxygen.

[0010] In the above, it is preferable that a peak due to the oxidation state of the first element is observed in the second region or the fourth region in X-ray photoelectron spectroscopy analysis.

[0011] In the above, the second region preferably has a region in which the concentration of the first element is higher than that of the fourth region.

[0012] In the above, it is preferable that in the second region, the first element has a concentration gradient such that the concentration becomes higher closer to the first insulating layer.

[0013] In the above, it is preferable that in the fourth region, the first element has a concentration gradient such that the concentration becomes higher closer to the semiconductor layer.

[0014] In the above, the semiconductor layer has a first element concentration of 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferred to have a region where:

[0015] In the above, it is preferable to have a second insulating layer. In this case, it is preferable that the semiconductor layer is provided on and in contact with the second insulating layer. It is preferable that the first insulating layer has a portion in contact with the second insulating layer in a region not overlapping with the semiconductor layer. It is preferable that the second insulating layer has a fifth region not overlapping with the semiconductor layer and containing the first element.

[0016] In the above, it is preferable to have a second conductive layer. In this case, it is preferable that the second conductive layer is located below the second insulating layer and has a region overlapping with the semiconductor layer and the first conductive layer.

[0017] In the above, a metal oxide layer is preferably provided between the first insulating layer and the first conductive layer. In this case, the metal oxide layer preferably contains one or more of the same elements as the semiconductor layer.

[0018] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: a first step of forming an island-shaped semiconductor layer containing a metal oxide; a second step of forming a first insulating layer containing an oxide on the island-shaped semiconductor layer; a third step of forming a first conductive layer on the first insulating layer so as to overlap with a part of the semiconductor layer; and a fourth step of supplying a first element into the first insulating layer and the semiconductor layer in a region not covered with the first conductive layer. The first element is preferably phosphorus, boron, magnesium, aluminum, or silicon.

[0019] In the fourth step, the first element is preferably supplied so that the concentration in the semiconductor layer has a distribution in which the concentration is higher closer to the first insulating layer.

[0020] In the fourth step, the first element is preferably supplied by using a plasma ion doping method or an ion implantation method.

[0021] In the above, it is preferable to have a fifth step of performing a heat treatment after the fourth step, in which the heat treatment is preferably performed at a temperature in the range of 200° C. or more and 400° C. or less. Effect of the Invention

[0022] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, a semiconductor device with stable electrical characteristics, or a display device with high reliability can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0024] [Figure 1] An example of a transistor configuration. [Diagram 2] An example of a transistor configuration. [Diagram 3] An example of a transistor configuration. [Figure 4] An example of a transistor configuration. [Diagram 5] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 6] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] 1A and 1B are a block diagram and a circuit diagram of a display device. [Figure 12] FIG. [Figure 13] 1 shows an example of a display module configuration. [Figure 14] Example of electronic device configuration. [Figure 15]Example of electronic device configuration. [Figure 16] Example of electronic device configuration. [Figure 17] Calculation results of impurity concentration. [Figure 18] Sheet resistance measurement results. [Figure 19] Sheet resistance measurement results. [Figure 20] Sheet resistance measurement results. [Figure 21] Impurity concentration measurement results. [Figure 22] Electrical characteristics of a transistor. [Diagram 23] Electrical characteristics of a transistor. [Figure 24] Transistor electrical characteristics and reliability evaluation results. [Diagram 25] TDS analysis results. [Figure 26] TDS analysis results. [Figure 27] XPS analysis results. [Figure 28] XPS analysis results. [Figure 29] Electrical characteristics of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0026] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component may be exaggerated for clarity.

[0027] In addition, the ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and do not limit the numbers.

[0028] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0029] In this specification and the like, the functions of a source and a drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow is changed during circuit operation, etc. For this reason, the terms source and drain can be used interchangeably.

[0030] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of a current flowing through a semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined to be one.

[0031] In addition, in this specification, "electrical connection" includes a case where a connection is made via "something having some electrical action." Here, "something having some electrical action" is not particularly limited as long as it enables transmission and reception of an electrical signal between the connection objects. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0032] In addition, in this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchangeable with the terms "conductive film" and "insulating film".

[0033] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source of an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0034] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0035] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or a substrate having an IC mounted thereon using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0036] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0037] The touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. The touch panel can have a display panel and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display panel.

[0038] In addition, in this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0039] (Embodiment 1) In this embodiment, a semiconductor device and a display device according to one embodiment of the present invention, and a manufacturing method thereof will be described.

[0040] One embodiment of the present invention is a transistor including a semiconductor layer in which a channel is formed on a formation surface, a gate insulating layer (also referred to as a first insulating layer) on the semiconductor layer, and a conductive layer (also referred to as a first conductive layer) functioning as a gate electrode on the gate insulating layer. The semiconductor layer preferably contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0041] The gate insulating layer is preferably provided in contact with the top and side surfaces of the semiconductor layer processed into an island shape. In particular, when a metal oxide is used for the semiconductor layer, the gate insulating layer preferably contains an oxide.

[0042] The semiconductor layer has a channel formation region where a channel can be formed and a pair of low-resistance regions that function as a source region and a drain region. The channel formation region overlaps with a gate electrode in the semiconductor layer. The pair of low-resistance regions are provided on either side of the channel formation region and have a lower resistance than the channel formation region.

[0043] The pair of low resistance regions preferably contains an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and a rare gas. Representative examples of the rare gas include helium, neon, argon, krypton, and xenon. In particular, it is preferable that the pair of low resistance regions contains boron or phosphorus.

[0044] In particular, the pair of low resistance regions preferably contains an impurity element that easily bonds with oxygen, such as boron, phosphorus, aluminum, magnesium, or silicon.

[0045] The impurity element contained in the pair of low-resistance regions preferably has a concentration gradient such that the concentration increases toward the gate insulating layer.

[0046] In addition, some of the impurity elements contained in the low-resistance region may diffuse into the channel formation region due to the influence of heat during the manufacturing process, etc. In such a case, the concentration of the impurity element in the channel formation region is preferably 1 / 10 or less, more preferably 1 / 100 or less, of the concentration in the low-resistance region.

[0047] In addition, the gate insulating layer preferably contains the above-mentioned impurity element in a portion in contact with the pair of low-resistance regions, i.e., a portion not overlapping with the gate electrode, and the gate insulating layer preferably does not contain the above-mentioned impurity in a portion in contact with the channel formation region, i.e., a portion overlapping with the gate electrode.

[0048] By performing heat treatment in a state where a gate insulating layer containing oxide is provided in contact with the top surface of a semiconductor layer, oxygen released from the gate insulating layer can be supplied to the semiconductor layer, thereby compensating for oxygen vacancies in the semiconductor layer and realizing a highly reliable transistor.

[0049] On the other hand, when oxygen is supplied to the low-resistance region, the carrier density is reduced, and the electrical resistance may increase. However, in one embodiment of the present invention, the above-mentioned impurity element is added to a portion of the gate insulating layer that is in contact with the low-resistance region. By adding the above-mentioned impurity element to an oxide film that can release oxygen by heating, the amount of oxygen released can be reduced. As a result, the supply of oxygen from the gate insulating layer to the low-resistance region is suppressed, and the low-resistance region can maintain a low electrical resistance.

[0050] With this structure, oxygen vacancies are sufficiently reduced, and a semiconductor device having excellent electrical characteristics and high reliability can be realized, which combines a channel formation region with extremely low carrier density and source and drain regions with extremely low electrical resistance.

[0051] Such a transistor can be manufactured, for example, by performing treatment for supplying the above-described impurity element to a gate insulating layer and a semiconductor layer using a gate electrode as a mask, and then performing heat treatment.

[0052] In this case, it is more preferable to supply the impurity element by a plasma ion doping method or an ion implantation method, since these methods make it easy to adjust the depth to which ions are added, and therefore it becomes easy to add ions to a region including the gate insulating layer and the semiconductor layer.

[0053] In addition, when the impurity element is added, it is preferable to set the ion supply conditions so that the impurity concentration is highest in the region on the gate insulating layer side of the semiconductor layer or in the vicinity of the interface between the semiconductor layer and the gate insulating layer. This allows the impurity element to be added to both the semiconductor layer and the gate insulating layer at an appropriate concentration in one process. Furthermore, by adding the impurity element at a high concentration to the upper part of the low resistance region to reduce the resistance, it is possible to further reduce the contact resistance between the low resistance region and the source electrode or the drain electrode. In addition, by forming a region with a high concentration of the impurity element in a portion close to the low resistance region of the gate insulating layer, the diffusibility of oxygen in this portion is effectively reduced, and the diffusion of oxygen in the gate insulating layer to the low resistance region side can be more effectively suppressed.

[0054] For example, the low resistance region of the semiconductor layer has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3It is preferable that the low resistance region of the semiconductor layer includes a region having a higher impurity concentration than a region in contact with the low resistance region of the gate insulating layer. This makes it possible to form a low resistance region with extremely low resistance.

[0055] In addition, a region of the gate insulating layer not overlapping with the gate electrode preferably includes a region having an impurity concentration lower than that of the low resistance region and higher than that of the portion overlapping with the gate electrode.

[0056] In addition, when an element that easily bonds with oxygen is used as an impurity element, the impurity element exists in a state of being bonded to oxygen in the semiconductor. That is, the impurity element takes away oxygen in the semiconductor layer, causing oxygen vacancies in the semiconductor layer, and the oxygen vacancies bond with hydrogen in the film to generate carriers. Furthermore, since the impurity element in the semiconductor layer exists stably in an oxidized state, it is possible to realize a stable low-resistance region without being desorbed by heat or the like applied during the process. For example, even if temperatures of 400°C or higher, 600°C or higher, or 800°C or higher are applied during the process, it is possible to maintain a stable low-resistance region.

[0057] In general, when a silicon film is used as a semiconductor layer, a donor that supplies electrons to the semiconductor or an acceptor that supplies holes (positive holes) is used as an impurity, and the donor or acceptor is substituted for a silicon atom to impart n-type or p-type conductivity to the semiconductor layer. Meanwhile, as described above, in one embodiment of the present invention, it is only necessary for the impurity element contained in the oxide semiconductor to have a function of removing oxygen from the oxide semiconductor and causing oxygen vacancies in the semiconductor layer, and the impurity element itself does not need to have a function of generating carriers. In this respect, it can be said that the mechanism by which the resistance of the semiconductor layer is reduced in one embodiment of the present invention is completely different from that in the case of silicon or the like.

[0058] In addition, it is preferable to use an insulating film containing an oxide as the gate insulating layer. Furthermore, it is preferable that the gate insulating layer contains oxygen (also referred to as excess oxygen) that is released by heating. In this case, the impurity element in the gate insulating layer exists in a state of being combined with the excess oxygen in the gate insulating layer. When the excess oxygen and the impurity element are combined and stabilized, the region to which the impurity element is added is in a state in which almost no oxygen is released even when heated. In addition, the region is in a state in which oxygen is difficult to diffuse. As a result, it is possible to prevent the resistance from increasing due to the supply of oxygen from the gate insulating layer to the low resistance region, while oxygen is supplied to the channel formation region, thereby reducing oxygen vacancies. As a result, a transistor with good electrical characteristics and high reliability can be realized.

[0059] The impurity element is preferably an element that bonds with oxygen in the semiconductor layer and the gate insulating layer to stabilize it. For example, it is preferable to use an element whose oxide can exist as a solid under standard conditions. Particularly preferred elements can be selected from rare gases, typical nonmetallic elements other than hydrogen, typical metal elements, and transition metal elements. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, silicon, etc.

[0060] A more specific example will be described below with reference to the drawings.

[0061] [Configuration example 1] FIG. 1A is a top view of a transistor 100, FIG. 1B corresponds to a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A, and FIG. 1C corresponds to a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 1A. Note that FIG. 1A omits some of the components of the transistor 100 (such as a gate insulating layer). The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Note that, as with FIG. 1A, the top views of the transistors in the following drawings are also illustrated with some of the components omitted.

[0062] The transistor 100 is provided over a substrate 102 and includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, and the like. The island-shaped semiconductor layer 108 is provided over the insulating layer 103. The insulating layer 110 is provided in contact with an upper surface of the insulating layer 103 and an upper surface and side surface of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are stacked in this order over the insulating layer 110 and have a portion overlapping with the semiconductor layer 108. The insulating layer 116 is provided to cover an upper surface of the insulating layer 110, a side surface of the metal oxide layer 114, and an upper surface of the conductive layer 112. The insulating layer 118 is provided to cover the insulating layer 116.

[0063] A part of the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer .

[0064] 1A and 1B, the transistor 100 may have a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to a region 108n described later through an opening 141a or an opening 141b provided in the insulating layer 118, the insulating layer 116, and the insulating layer 110, respectively.

[0065] The semiconductor layer 108 preferably comprises a metal oxide.

[0066] For example, the semiconductor layer 108 preferably contains indium, M (wherein M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0067] In particular, it is preferable to use an oxide containing indium, gallium, and zinc for the semiconductor layer 108.

[0068] The semiconductor layer 108 may have a stacked structure in which layers with different compositions, layers with different crystallinity, or layers with different impurity concentrations are stacked.

[0069] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes roughly match each other.

[0070] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, and in this case, it is also called "top surface shapes roughly match."

[0071] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. The metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110. The metal oxide layer 114 can be made of a material that is less permeable to oxygen and hydrogen than the insulating layer 110, for example.

[0072] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0073] An insulating material or a conductive material can be used for the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, it functions as a part of the gate electrode.

[0074] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0075] A conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used as the metal oxide layer 114. In particular, a conductive oxide containing indium is preferable because of its high conductivity.

[0076] In addition, it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108 for the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 for the metal oxide layer 114, because this allows the use of a common device.

[0077] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, it is preferable to use a material with a higher gallium composition (content) than the semiconductor layer 108 because the blocking property against oxygen can be further improved. In this case, by using a material with a higher indium composition than the metal oxide layer 114 for the semiconductor layer 108, the field-effect mobility of the transistor 100 can be increased.

[0078] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0079] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108n sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the region 108n functions as a source region or drain region of the transistor 100.

[0080] The region 108n can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a high density of oxygen defects, a region having a high impurity concentration, or an n-type region.

[0081] The region 108n of the semiconductor layer 108 is a region containing an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable that the region 108n contains boron or phosphorus. Two or more of these elements may be contained.

[0082] The insulating layer 110 has a region in contact with a channel formation region of the semiconductor layer 108, that is, a region overlapping with the conductive layer 112. The insulating layer 110 also has a region in contact with a low-resistance region 108n of the semiconductor layer 108 and not overlapping with the conductive layer 112.

[0083] It is preferable to use an oxide film for the insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108. For example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. In this way, oxygen desorbed from the insulating layer 103 or the insulating layer 110 during heat treatment or the like in the manufacturing process of the transistor 100 can be supplied to the channel formation region of the semiconductor layer 108, thereby reducing oxygen vacancies in the semiconductor layer 108.

[0084] FIG. 2 shows an enlarged cross-sectional view of a region P surrounded by a dashed line in FIG.

[0085] The insulating layer 110 has a region 110d containing the above-described impurity element. The region 110d is located near the interface with at least the region 108n. The region 110d is also located near at least the interface with the insulating layer 103 in a region where the semiconductor layer 108 is not provided and does not overlap with the conductive layer 112. As shown in FIGS. 1B, 1C, and 2, the region 110d is preferably not provided in a portion in contact with a channel formation region of the semiconductor layer 108.

[0086] 2, the insulating layer 103 has a region 103d containing the above-mentioned impurity element near the interface in contact with the insulating layer 110. The region 103d may also be provided near the interface in contact with the region 108n. In this case, the impurity concentration in the portion overlapping with the region 108n is lower than that in the portion in contact with the insulating layer 110.

[0087] Here, it is preferable that the impurity concentration in the region 108n has a concentration gradient such that the concentration is higher closer to the insulating layer 110. This results in a lower resistance toward the upper part of the region 108n, so that the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced. In addition, since the total amount of impurity elements in the region 108n can be reduced compared to a case where the concentration is uniform throughout the region 108n, the amount of impurities that may diffuse into the channel formation region due to the influence of heat during the manufacturing process can be kept low.

[0088] In addition, it is preferable that the impurity concentration in the region 110d has a concentration gradient such that the concentration becomes higher closer to the semiconductor layer 108. In the insulating layer 110 using an oxide film capable of releasing oxygen by heating, the region 110d to which the above-mentioned impurity element is added can suppress the release of oxygen compared to other regions. Therefore, the region 110d located near the interface with the region 108n of the insulating layer 110 functions as a blocking layer against oxygen, and can effectively reduce the amount of oxygen supplied to the region 108n.

[0089] As will be described later, the treatment of adding an impurity element to the region 108n and the region 110d can be performed using the conductive layer 112 as a mask. In this way, the region 110d can be formed in a self-aligned manner at the same time as the formation of the region 108n.

[0090] In Figure 2 and other figures, in order to exaggerate the fact that the portion of the insulating layer 110 with a high impurity concentration is located near the interface with the semiconductor layer 108, region 110d is illustrated with a hatched pattern only near the semiconductor layer 108 in the insulating layer 110; however, in reality, the above-mentioned impurity elements may be contained throughout the entire thickness of the insulating layer 110.

[0091] The regions 108n and 110d each have an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferable that the region 108n includes a region in which the impurity concentration is higher than that of the region 110d of the insulating layer 110. It is also preferable that the region 108n has a portion having a higher impurity concentration than the region 110d of the insulating layer 110, because this makes it possible to more effectively reduce the electrical resistance of the region 108n.

[0092] The concentration of impurities contained in the regions 108n and 110d can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or rear side with XPS analysis.

[0093] In addition, in the region 108n, the impurity element is preferably present in an oxidized state. For example, it is preferable to use an element that is easily oxidized, such as boron, phosphorus, magnesium, aluminum, or silicon, as the impurity element. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the semiconductor layer 108, even if a high temperature (for example, 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process, desorption is suppressed. Furthermore, the impurity element removes oxygen from the semiconductor layer 108, and many oxygen vacancies are generated in the region 108n. The oxygen vacancies are bonded with hydrogen in the film to become a carrier supply source, and the region 108n becomes in an extremely low resistance state.

[0094] In addition, when a high-temperature process is performed in a later step, if a large amount of oxygen is supplied to the region 108n from the outside or a film in the vicinity of the region 108n, the resistance may increase. Therefore, when performing a high-temperature process, it is preferable to perform the process while covering the region 108n with the insulating layer 116 that has a high barrier property against oxygen.

[0095] Also, in the region 110d, the impurity element is preferably present in an oxidized state. Such an element that is easily oxidized can be bonded to oxygen in the insulating layer 110 and can be stably present in an oxidized state, and therefore can be prevented from being desorbed even when a high temperature is applied in a later process. In particular, when the insulating layer 110 contains oxygen (also referred to as excess oxygen) that can be desorbed by heating, the excess oxygen and the impurity element are bonded to each other and stabilized, and therefore, it is possible to prevent oxygen from being supplied from the region 110d to the region 108n. In addition, the region 110d containing the impurity element in an oxidized state is in a state in which oxygen is difficult to diffuse, and therefore it is possible to prevent oxygen from being supplied to the region 108n from above the region 110d through the region 110d.

[0096] For example, when boron is used as an impurity element, the boron contained in the regions 108n and 110d may exist in a state of being bonded to oxygen. This can be confirmed by observing a spectrum peak due to the B2O3 bond in the XPS analysis. In addition, in the XPS analysis, a spectrum peak due to the state in which the boron element exists alone is not observed, or the peak intensity becomes so small that it is buried in the background noise at the lower limit of measurement.

[0097] The insulating layer 116 and the insulating layer 118 function as protective layers that protect the transistor 100. Either the insulating layer 116 or the insulating layer 118 preferably has a function of preventing oxygen that may be released from the insulating layer 110 from diffusing to the outside. For example, an inorganic insulating material such as an oxide or a nitride can be used. More specific examples of inorganic insulating materials that can be used include silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate.

[0098] Note that although the protective layer has a stacked structure of the insulating layer 116 and the insulating layer 118 here, either one of the insulating layer 116 or the insulating layer 118 does not have to be provided if it is not necessary.

[0099] Here, the semiconductor layer 108 and oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0100] Oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies and they can become carrier sources. When a carrier source is generated in the semiconductor layer 108, the electrical characteristics of the transistor 100 fluctuate, typically causing a shift in the threshold voltage. Therefore, it is preferable that the semiconductor layer 108 have fewer oxygen vacancies.

[0101] Thus, in one embodiment of the present invention, an insulating film near the semiconductor layer 108, specifically, the insulating layer 110 located above the semiconductor layer 108 and the insulating layer 103 located below the semiconductor layer 108, includes an oxide film. By transferring oxygen from the insulating layer 103 and the insulating layer 110 to the semiconductor layer 108 by heat or the like during a manufacturing process, oxygen vacancies in the semiconductor layer 108 can be reduced.

[0102] The semiconductor layer 108 preferably has a region in which the atomic ratio of In is higher than the atomic ratio of M. The higher the atomic ratio of In, the more the field-effect mobility of the transistor can be improved.

[0103] Here, in the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is weaker than that between Ga and oxygen, so when the atomic ratio of In is large, oxygen vacancies are likely to be formed in the metal oxide film. The same tendency is observed when a metal element represented by M is used instead of Ga. When many oxygen vacancies exist in the metal oxide film, the electrical characteristics and reliability of the transistor are deteriorated.

[0104] However, in one embodiment of the present invention, an extremely large amount of oxygen can be supplied to the semiconductor layer 108 containing a metal oxide, and therefore a metal oxide material with a high atomic ratio of In can be used. As a result, a transistor having extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0105] For example, a metal oxide in which the atomic ratio of In is 1.5 times or more, 2 times or more, 3 times or more, 3.5 times or more, or 4 times or more the atomic ratio of M can be suitably used.

[0106] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is preferably In:M:Zn=5:1:6 or thereabout (when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less). Alternatively, the atomic ratio of In, M, and Zn is preferably In:M:Zn=4:2:3 or thereabout. Furthermore, as the composition of the semiconductor layer 108, the atomic ratio of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the semiconductor layer 108 may contain a material in which the atomic ratio of In, M, and Zn is In:M:Zn=1:1:1 or thereabout.

[0107] For example, by using the transistor with high field-effect mobility in a gate driver that generates a gate signal, a display device with a narrow frame width (also called a narrow frame) can be provided. In addition, by using the transistor with high field-effect mobility in a source driver (particularly, a demultiplexer connected to an output terminal of a shift register of the source driver), a display device with a small number of wirings connected to the display device can be provided.

[0108] Even if the semiconductor layer 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, the field-effect mobility may be reduced if the semiconductor layer 108 has high crystallinity. The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD) or a transmission electron microscope (TEM).

[0109] Here, impurities such as hydrogen or moisture mixed in the semiconductor layer 108 affect transistor characteristics, which is problematic. Therefore, the semiconductor layer 108 preferably contains as few impurities as possible, such as hydrogen or moisture. By using a metal oxide film with a low impurity concentration and a low density of defect states, a transistor with excellent electrical characteristics can be manufactured. By using a metal oxide film with a low impurity concentration and a low density of defect states (reducing oxygen vacancies), the carrier density in the film can be reduced. A transistor using such a metal oxide film for a semiconductor layer rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a transistor using such a metal oxide film can have a significantly low off-current.

[0110] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0111] For example, a semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used. For example, when an In-M-Zn oxide is used, it is preferable to stack two or more films formed from a sputtering target in which the atomic ratio of In, M, and Zn is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn=1:3:2, or a ratio close to these values.

[0112] Alternatively, a semiconductor layer 108 in which two or more metal oxide films with different crystallinity are stacked can be used. In that case, it is preferable to use the same oxide target and to form the films successively under different film formation conditions without exposure to air.

[0113] For example, the oxygen flow ratio during the formation of the first metal oxide film is set to be smaller than the oxygen flow ratio during the formation of the second metal oxide film. Alternatively, oxygen is not allowed to flow during the formation of the first metal oxide film. This allows oxygen to be effectively supplied during the formation of the second metal oxide film. In addition, the first metal oxide film can be a film with lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, by making the second metal oxide film provided on the upper portion a film with higher crystallinity than the first metal oxide film, damage during processing of the semiconductor layer 108 and during the formation of the insulating layer 110 can be suppressed.

[0114] More specifically, the oxygen flow ratio during deposition of the first metal oxide film is set to 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow ratio during deposition of the second metal oxide film is set to 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, further preferably 90% or more and 100% or less, and typically 100%. Although the conditions during deposition of the first metal oxide film and the second metal oxide film, such as pressure, temperature, and power, may be different, it is preferable to make the conditions other than the oxygen flow ratio the same, since this shortens the time required for the deposition process.

[0115] With this structure, a transistor 100 with excellent electrical characteristics and high reliability can be realized.

[0116] The above is a description of configuration example 1.

[0117] [Configuration example 2] The following describes a configuration example of a transistor that is partially different from the above-mentioned configuration example 1. Note that, in the following, a description of parts that overlap with the above-mentioned configuration example 1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-mentioned configuration example 1 may be indicated with the same hatching pattern and may not be assigned reference numerals.

[0118] 3A is a top view of the transistor 100A, FIG. 3B is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 3C is a cross-sectional view of the transistor 100A in the channel width direction.

[0119] The transistor 100A differs from the first structural example mainly in that a conductive layer 106 is provided between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112.

[0120] In the transistor 100A, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 103 functions as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

[0121] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 108 overlapping with the conductive layer 112 may be referred to as a channel formation region hereinafter; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106 (a portion including the region 108n).

[0122] 3C, the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening 142 provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103. In this way, the conductive layer 106 and the conductive layer 112 can be applied with the same potential.

[0123] The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced.

[0124] 3(A) and 3(C), it is preferable that the conductive layer 112 and the conductive layer 106 protrude outward in the channel width direction beyond the end portion of the semiconductor layer 108. In this case, as shown in FIG. 3(C), the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103.

[0125] With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This makes it possible to effectively apply an electric field for inducing a channel in the semiconductor layer 108, thereby increasing the on-state current of the transistor 100A. This also enables miniaturization of the transistor 100A.

[0126] Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other of the pair of gate electrodes. In this case, the threshold voltage when the transistor 100A is driven by the other electrode can also be controlled by the potential applied to one electrode.

[0127] This concludes the description of configuration example 2.

[0128] [Application example] In the following, an example will be described in which a semiconductor film containing an impurity is used as one electrode of a capacitor, and a transistor and a capacitor are formed on the same surface.

[0129] In the cross-sectional view of FIG. 4A, a capacitor 130A is provided next to the transistor 100 illustrated in the first structural example.

[0130] In the cross-sectional view of FIG. 4B, a capacitor 130A is provided next to the transistor 100A illustrated in the second structural example.

[0131] The capacitor 130A has a structure in which an insulating layer 110, an insulating layer 116, and an insulating layer 118 functioning as a dielectric are provided between a semiconductor layer 108c and a conductive layer 120b.

[0132] The semiconductor layer 108c is provided on the same plane as the semiconductor layer 108. For example, the semiconductor layer 108c can be formed by processing the same metal oxide film as the semiconductor layer 108 and then adding the same impurity element as the region 108n.

[0133] With this structure, the capacitor 130A can be manufactured without increasing the number of steps.

[0134] A capacitor 130B shown in FIG. 4C has a structure in which an insulating layer 103 functioning as a dielectric is provided between a conductive layer 106c and a semiconductor layer 108c.

[0135] The conductive layer 106c is provided on the same surface as the conductive layer 106. The conductive layer 106c can be formed by processing the same conductive film as the conductive layer 106.

[0136] The capacitance element 130B can have a thinner dielectric thickness than the capacitance element 130A, and therefore can have a larger capacitance.

[0137] The above is a description of the application example.

[0138] [Components of Semiconductor Devices] Next, components included in the semiconductor device of this embodiment will be described in detail.

[0139] 〔substrate〕 There are no significant limitations on the material of the substrate 102, but the substrate must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may be used as the substrate 102.

[0140] Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device that is partially or entirely completed thereon from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0141] [Insulating layer 103] The insulating layer 103 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, or the like as appropriate. The insulating layer 103 can be formed, for example, as a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the semiconductor layer 108, at least a region of the insulating layer 103 that is in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film. The insulating layer 103 is preferably formed using a film that releases oxygen when heated.

[0142] The insulating layer 103 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like, and may be formed as a single layer or a stacked layer.

[0143] When a film other than an oxide film, such as a silicon nitride film, is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform a pretreatment such as an oxygen plasma treatment on the surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

[0144] [Conductive Film] The conductive layer 112 and the conductive layer 106 functioning as a gate electrode, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, or an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements.

[0145] In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be formed using an oxide conductor or a metal oxide film such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0146] Here, an oxide conductor (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

[0147] Alternatively, the conductive layer 112 or the like may have a stacked structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating film.

[0148] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably contain one or more of the above-mentioned metal elements selected from titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferably used. The tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself, and therefore can be preferably used as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0149] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film of the transistor 100 or the like, can be formed by a PECVD method, a sputtering method, or the like. The insulating layer 110 can be an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers.

[0150] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the insulating layer 110 after the film formation in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0151] Also, a material such as hafnium oxide, which has a higher dielectric constant than silicon oxide or silicon oxynitride, can be used as the insulating layer 110. This allows the insulating layer 110 to be thicker and suppresses leakage current due to tunnel current. In particular, crystalline hafnium oxide is preferable because it has a higher dielectric constant than amorphous hafnium oxide.

[0152] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used for depositing the In-M-Zn oxide preferably has an atomic ratio of In equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such a sputtering target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and the like.

[0153] In addition, it is preferable to use a target containing a polycrystalline oxide as the sputtering target because it is easy to form the semiconductor layer 108 having crystallinity. The atomic ratio of the semiconductor layer 108 to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0154] When the atomic ratio is described as In:Ga:Zn=4:2:3 or thereabout, this includes the case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more and 4 or less. When the atomic ratio of In is described as In:Ga:Zn=5:1:6 or thereabout, this includes the case where, when the atomic ratio of In is 5, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is 5 or more and 7 or less. When the atomic ratio of In is described as In:Ga:Zn=1:1:1 or thereabout, this includes the case where, when the atomic ratio of In is 1, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is more than 0.1 and 2 or less.

[0155] The energy gap of the semiconductor layer 108 is 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

[0156] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure, which will be described later. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0157] In the following, we explain about CAAC (c-axis aligned crystal). CAAC is an example of a crystal structure.

[0158] The CAAC structure is one of the crystal structures of thin films having multiple nanocrystals (crystal regions with a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films having a CAAC structure have the characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the thin film surface.

[0159] CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and have high reliability.

[0160] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis for the three axes (crystal axes) of the a-axis, b-axis, and c-axis that constitute the unit cell. In particular, in crystals having a layered structure, it is common to take two axes parallel to the plane direction of the layer as the a-axis and b-axis, and an axis intersecting the layer as the c-axis. A representative example of such a crystal having a layered structure is graphite, which is classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, a crystal of InGaZnO4 having a layered YbFe2O4 type crystal structure can be classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0161] An example of the crystal structure of a metal oxide will be described. In the following, a metal oxide film formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) will be described as an example. A metal oxide formed by a sputtering method using the above target and with a substrate temperature of 100°C or higher and 130°C or lower is likely to have either a crystalline structure of nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, a metal oxide formed by a sputtering method with a substrate temperature of room temperature (RT) is likely to have an nc crystalline structure. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0162] [Example of manufacturing method] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below, taking the transistor 100A described in Structure Example 2 as an example.

[0163] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device can be formed by using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. Another type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0164] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0165] Furthermore, when processing the thin film constituting the semiconductor device, the thin film can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0166] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0167] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0168] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0169] 5 and 6 show cross sections of the transistor 100A in the channel length direction and the channel width direction at different stages in a manufacturing process.

[0170] [Formation of Conductive Layer 106] A conductive film is formed over the substrate 102 and processed by etching to form a conductive layer 106 that functions as a gate electrode.

[0171] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 5(A)). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0172] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method.

[0173] [Formation of Semiconductor Layer 108] Subsequently, a metal oxide film is formed on the insulating layer 103, and then processed to form island-shaped semiconductor layers 108 (FIG. 5(B)).

[0174] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0175] When forming a metal oxide film, an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed in addition to oxygen gas. Note that the higher the ratio of oxygen gas to the total deposition gas when forming a metal oxide film (hereinafter, also referred to as oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with increased on-current can be obtained.

[0176] The deposition conditions for the metal oxide film are such that the substrate temperature is from room temperature to 200° C., preferably from room temperature to 140° C. For example, the substrate temperature is from room temperature to less than 140° C., which is preferable because it increases productivity. The crystallinity can be reduced by depositing the metal oxide film at room temperature or without intentionally heating the substrate.

[0177] Furthermore, before forming the metal oxide film, it is preferable to perform a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103, and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. Furthermore, when plasma treatment is performed in an atmosphere containing nitric oxide gas, organic substances on the surface of the insulating layer 103 can be suitably removed. After such a treatment, it is preferable to continuously form a metal oxide film without exposing the surface of the insulating layer 103 to the air.

[0178] The metal oxide film may be processed by wet etching or dry etching, or both of them may be used. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner.

[0179] After the metal oxide film is formed or after it is processed into the semiconductor layer 108, heat treatment may be performed in order to remove hydrogen or water in the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment can be typically set to 150° C. or higher and lower than the distortion point of the substrate, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

[0180] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, the heat treatment can be performed in an atmosphere containing oxygen after the heat treatment in the atmosphere. Note that it is preferable that the heat treatment atmosphere does not contain hydrogen, water, or the like. The heat treatment can be performed in an electric furnace, an RTA apparatus, or the like. The use of an RTA apparatus can shorten the heat treatment time.

[0181] [Formation of insulating layer 110 and metal oxide film 114f] Subsequently, an insulating layer 110 and a metal oxide film 114f are laminated to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 5(C)).

[0182] The insulating layer 110 is preferably formed by using an oxide film such as a silicon oxide film or a silicon oxynitride film using a plasma enhanced chemical vapor deposition (PECVD) apparatus or simply a plasma CVD apparatus. Alternatively, the insulating layer 110 may be formed by using a PECVD method using microwaves.

[0183] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. In this way, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f.

[0184] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that for the semiconductor layer 108, the above-mentioned method can be used.

[0185] For example, the metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0186] During deposition of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied to the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0187] In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating layer 110. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 110. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0188] After the metal oxide film 114f is formed, heat treatment may be performed so that oxygen is supplied from the insulating layer 110 to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas.

[0189] Subsequently, after the metal oxide film 114f is formed, the metal oxide film 114f, the insulating layer 110, and the insulating layer 103 are partially etched to form an opening reaching the conductive layer 106. This allows the conductive layer 112 and the conductive layer 106 to be electrically connected to each other through the opening.

[0190] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Subsequently, a conductive film 112f to be the conductive layer 112 is formed on the metal oxide film 114f (FIG. 5D). The conductive film 112f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy.

[0191] Next, the conductive film 112f and the metal oxide film 114f are partly etched to form the conductive layer 112 and the metal oxide layer 114 (FIG. 5E). The conductive film 112f and the metal oxide film 114f are preferably processed using the same resist mask. Alternatively, the metal oxide film 114f may be etched using the etched conductive layer 112 as a hard mask.

[0192] This makes it possible to form the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same.

[0193] In this manner, by covering the top and side surfaces of the semiconductor layer 108 and the insulating layer 103 with the insulating layer 110 without etching the insulating layer 110, it is possible to prevent a portion of the semiconductor layer 108 or the insulating layer 103 from being etched and thinned when the conductive layer 112, etc. are etched.

[0194] [Supply of impurity elements] Next, a process of supplying (also referred to as adding or injecting) the impurity element 140 to the insulating layer 110 and the semiconductor layer 108 is performed using the conductive layer 112 as a mask to form regions 108n, regions 110d, and regions 103d (FIG. 6A). The conductive layer 112 serves as a mask to prevent the impurity element 140 from being supplied to a region of the semiconductor layer 108 and the insulating layer 110 that overlaps with the conductive layer 112.

[0195] The impurity element 140 can be preferably supplied by a plasma ion doping method or an ion implantation method. These methods can control the concentration profile in the depth direction with high precision by the ion acceleration voltage, dose amount, etc. By using the plasma ion doping method, productivity can be improved. In addition, by using the ion implantation method using mass separation, the purity of the supplied impurity element can be increased.

[0196] In the supplying process of the impurity element 140, it is preferable to control the process conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or in a portion close to the interface in the semiconductor layer 108, or in a portion close to the interface in the insulating layer 110. This makes it possible to supply the impurity element 140 at an optimal concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0197] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0198] As the source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically, B2H6 gas or BF3 gas can be used. When supplying phosphorus, typically, PH3 gas can be used. Also, a mixed gas in which these source gases are diluted with a rare gas may be used.

[0199] Other examples of the source gas that can be used include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid that has been heated and vaporized may also be used.

[0200] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110 and the semiconductor layer .

[0201] For example, when boron is added by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 It can be in the following range:

[0202] When phosphorus ions are added by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 10 kV to 100 kV, preferably 30 kV to 90 kV, and more preferably 40 kV to 80 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 It can be in the following range:

[0203] The method of supplying the impurity element 140 is not limited to this, and may be, for example, a plasma treatment or a treatment using thermal diffusion by heating. In the case of the plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used.

[0204] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even when the semiconductor layer 108 has crystallinity, loss of crystallinity during the supply of the impurity element 140 can be suppressed. Therefore, this is preferable in the case where electrical resistance increases due to a decrease in crystallinity.

[0205] [Formation of insulating layers 116 and 118] Next, the insulating layer 116 and the insulating layer 118 are formed in this order (FIG. 6(B)).

[0206] When the insulating layer 116 or the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, impurities contained in the region 108n and the like may diffuse to the peripheral portion including the channel formation region of the semiconductor layer 108, and the electrical resistance of the region 108n may increase. The film formation temperature of the insulating layer 116 or the insulating layer 118 is preferably, for example, 150° C. or higher and 400° C. or lower, preferably 180° C. or higher and 360° C. or lower, and more preferably 200° C. or higher and 250° C. or lower. By forming the insulating layer 116 or the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0207] [Heat Treatment] After the insulating layer 116 or the insulating layer 118 is formed, heat treatment is performed. The heat treatment is preferably performed in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas at a temperature of 150° C. to 450° C., preferably 200° C. to 400° C. By the heat treatment, the region 108n can be made more stable and low-resistance. For example, by performing the heat treatment at the above temperature, the impurity element 140 can be appropriately diffused and locally homogenized, and the region 108n and the region 110d having an ideal concentration gradient of the impurity element can be formed. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel formation region, which may cause deterioration in the electrical characteristics and reliability of the transistor.

[0208] Furthermore, defects that occur in the semiconductor layer 108 or the insulating layer 110 when the impurity element 140 is supplied to the region 108n may be repaired by heat treatment.

[0209] Furthermore, the heat treatment can supply oxygen from the insulating layer 110 to the channel formation region of the semiconductor layer 108. At this time, since the region 110d to which the impurity element 140 is supplied is formed in the insulating layer 110 near the interface with the region 108n, the oxygen released from the insulating layer 110 is suppressed from diffusing into the region 108n. As a result, it is possible to effectively prevent the region 108n from becoming highly resistant again. Furthermore, since the region 110d is not formed in the portion of the insulating layer 110 that overlaps with the channel formation region of the semiconductor layer 108, the oxygen released from the insulating layer 110 can be selectively supplied to the channel formation region.

[0210] In addition, since the region 108n has more oxygen vacancies than the channel formation region, the heat treatment is expected to have the effect of gettering hydrogen contained in the channel formation region by the oxygen vacancies. This reduces the hydrogen concentration in the channel formation region, resulting in a more reliable transistor. In addition, hydrogen supplied from the channel formation region is combined with oxygen vacancies in the region 108n to become a carrier generation source, resulting in a lower resistance region 108n.

[0211] Note that the heat treatment may be performed before the insulating layer 116 is formed; however, it is more preferable to perform the heat treatment after the insulating layer 116 or the insulating layer 118 is formed. For example, by using an insulating film through which oxygen does not easily diffuse as the insulating layer 116 or the insulating layer 118, oxygen released from the insulating layer 110 by heat treatment can be prevented from diffusing to the outside, and the amount of oxygen that can be supplied to the channel formation region of the semiconductor layer 108 can be increased.

[0212] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then parts of the insulating layer 118, the insulating layer 116, and the insulating layer 110 are etched to form an opening 141a and an opening 141b that reach the region 108n.

[0213] [Formation of Conductive Layer 120a and Conductive Layer 120b] Next, a conductive film is formed over the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 6C).

[0214] Through the above steps, the transistor 100A can be manufactured. For example, when the transistor 100A is used in a pixel of a display device, a subsequent step of forming one or more of a protective insulating layer, a planarizing layer, a pixel electrode, and a wiring may be added.

[0215] The above is an explanation of the example of the manufacturing method.

[0216] At least a part of the configuration examples, manufacturing method examples, and corresponding drawings, etc., illustrated in this embodiment mode can be implemented by appropriately combining with other configuration examples, manufacturing method examples, drawings, etc.

[0217] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0218] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0219] [Configuration example] 7A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 attached to each other with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0220] Further, an FPC terminal portion 708 to which an FPC 716 (Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716 via the FPC terminal portion 708 and signal lines 710.

[0221] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0222] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be the transistors that are the semiconductor device of one embodiment of the present invention.

[0223] Examples of the display element provided in the pixel unit 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used.

[0224] The display device 700A shown in Fig. 7B is suitable for use in electronic devices having a large screen. The display device 700A can be suitable for use in, for example, television devices, monitor devices, personal computers (including notebook and desktop computers), tablet terminals, digital signage, and the like.

[0225] The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0226] The multiple source driver ICs 721 are each attached to an FPC 723. One terminal of each of the multiple FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0227] On the other hand, the gate driver circuit portion 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0228] With this configuration, a large-sized, high-resolution display device can be realized. For example, the present invention can be applied to display devices with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. In addition, a display device with an extremely high resolution such as 4K2K or 8K4K can be realized.

[0229] [Cross-section example] In the following, configurations using liquid crystal elements and EL elements as display elements will be described with reference to Fig. 8 to Fig. 10. Fig. 8 to Fig. 10 are cross-sectional views taken along dashed line QR shown in Fig. 7(A). Fig. 8 and Fig. 9 show configurations using liquid crystal elements as display elements, and Fig. 10 shows a configuration using EL elements.

[0230] [Description of common parts of the display device] 8 to 10 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. FIG. 9 illustrates a case where the capacitor 790 is not included.

[0231] The transistors described in Embodiment 1 can be used as the transistors 750 and 752.

[0232] The transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be reduced. Therefore, the retention time of an electric signal such as an image signal can be extended, and the writing interval of an image signal or the like can be set to be long in a power-on state. Therefore, the frequency of a refresh operation can be reduced, which leads to an effect of reducing power consumption.

[0233] In addition, the transistor used in this embodiment mode can be driven at high speed because it has a relatively high field effect mobility. For example, by using such a transistor capable of high speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. In other words, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driver circuit, the number of components in the display device can be reduced. In addition, by using a transistor capable of high speed driving in the pixel portion, a high-quality image can be provided.

[0234] 8 and 10 includes a lower electrode formed by processing the same film as the semiconductor layer of the transistor 750 and having a low resistance, and an upper electrode formed by processing the same conductive film as the source electrode or drain electrode. In addition, two insulating films covering the transistor 750 are provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.

[0235] In addition, a planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0236] The transistor 750 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the source driver circuit portion 704 may be read as a gate driver circuit portion.

[0237] The signal line 710 is formed of the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because signal delays caused by wiring resistance are small and display on a large screen is possible.

[0238] The FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the connection electrode 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752, and the like.

[0239] As the first substrate 701 and the second substrate 705, for example, a flexible substrate such as a glass substrate or a plastic substrate can be used.

[0240] In addition, on the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0241] [Example of the configuration of a display device using a liquid crystal element] A display device 700 shown in FIG. 8 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0242] A material that transmits visible light or a material that reflects visible light can be used for the conductive layer 772. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0243] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich a liquid crystal element.

[0244] 9 shows an example of a display device 700 using a horizontal electric field (e.g., FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0245] 9, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0246] 8 and 9, an alignment film may be provided in contact with the liquid crystal layer 776. Optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0247] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersion type liquid crystal, polymer network type liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. When the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0248] In addition, the liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0249] [Display device using light-emitting element] 10 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0250] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, etc. Materials that can be used for the quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc.

[0251] 10, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element having a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0252] The colored film 736 is provided at a position overlapping the light-emitting element 782, and the light-shielding film 738 is provided at a position overlapping the insulating film 730, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the colored film 736 may not be provided.

[0253] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display device 700 shown in Figures 8 to 10. As the input device, for example, a touch sensor or the like can be given.

[0254] For example, various types of sensors can be used, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0255] The touch panel may be configured as a so-called in-cell type touch panel in which an input device is formed inside a pair of substrates, a so-called on-cell type touch panel in which an input device is formed on the display device 700, or an out-cell type touch panel in which the input device is attached to the display device 700.

[0256] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0257] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0258] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0259] 11A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0260] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0261] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0262] The driver circuit unit 504 has driver circuits such as a gate driver 504a that outputs scanning signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may have at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may also be configured using a shift register.

[0263] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0264] 11A is connected to various wirings such as a scanning line GL between a gate driver 504a and a pixel circuit 501, or a data line DL between a source driver 504b and a pixel circuit 501.

[0265] In addition, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0266] Further, the pixel circuits 501 shown in FIG. 11A can have the configurations shown in FIGS. 11B and 11C, for example.

[0267] 11B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL, and the like.

[0268] The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0269] 11C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a power supply line VL_b, and the like.

[0270] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0271] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0272] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0273] (Embodiment 4) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described below. The transistors described in the first embodiment can be used as the transistors used in the pixel circuits described below.

[0274] [Circuit configuration] 12A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0275] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0276] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be used.

[0277] The node connecting the transistor M1 and the capacitor C1 is defined as N1, and the node connecting the transistor M2 and the circuit 401 is defined as N2.

[0278] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0279] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistor M1 and the transistor M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period during which the potentials of the nodes are held is short (specifically, when the frame frequency is 30 Hz or more), a transistor including a semiconductor such as silicon may be used.

[0280] [Driving method example] Next, an example of an operation method of the pixel circuit 400 will be described with reference to Fig. 12(B). Fig. 12(B) is a timing chart relating to the operation of the pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0281] 12B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0282] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0283] The node N1 is connected to a potential V ref A first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0284] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0285] A second data potential V data At this time, the second data potential V data In response to the change in potential, the potential of the node N2 changes by a potential dV. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Note that although dV is shown to have a positive value in FIG. 12B, it may be a negative value. That is, the potential V data is the potential V ref It may be lower.

[0286] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0287] In this manner, the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including a display element, and therefore, gray scale correction can be performed within the pixel circuit 400.

[0288] In addition, the pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. When a liquid crystal element is used, overdrive driving or the like can be realized.

[0289] [Example of application] [Example using liquid crystal element] A pixel circuit 400LC shown in Fig. 12C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0290] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0291] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted.

[0292] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, and therefore can, for example, realize high-speed display by overdrive driving, apply a liquid crystal material with a high driving voltage, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0293] [Example using light-emitting element] 12D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0294] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, a source and a drain connected to a wiring to which a potential VH is applied, and the other connected to one electrode of the light-emitting element EL. com The light-emitting element EL has the other electrode connected to a wiring that is supplied with a potential V L Connect with the wiring given.

[0295] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0296] In this embodiment, the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3. H and potential V L The value of can be changed appropriately.

[0297] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, and thus, for example, HDR display can be realized. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0298] Note that the circuits are not limited to those illustrated in FIGS. 12C and 12D, and may be configured to include additional transistors, capacitors, and the like.

[0299] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0300] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0301] A display module 6000 shown in FIG. 13A includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0302] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0303] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately according to the size of the display device 6006.

[0304] The display device 6006 may have a function as a touch panel.

[0305] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0306] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0307] FIG. 13(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor.

[0308] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. Also, in an area surrounded by an upper cover 6001 and a lower cover 6002, a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) are provided.

[0309] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guiding portion 6017a and a light guiding portion 6017b.

[0310] Light 6018 emitted from the light-emitting unit 6015 passes through the light-guiding unit 6017a, the upper part of the display device 6006, and the light-guiding unit 6017b to reach the light-receiving unit 6016. When the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0311] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. This makes it possible to obtain information on the position where a touch operation is performed.

[0312] The light emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light receiving unit 6016 may be a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electric signal. Preferably, a photodiode that can receive infrared light may be used.

[0313] The light guiding portion 6017a and the light guiding portion 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, if a resin that absorbs visible light and transmits infrared light is used, it is possible to more effectively prevent the touch sensor from malfunctioning.

[0314] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0315] (Embodiment 6) In this embodiment, electronic devices including a display device manufactured according to one embodiment of the present invention will be described.

[0316] The electronic devices exemplified below each have a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices have high resolution. In addition, the electronic devices can have both high resolution and a large screen.

[0317] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0318] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0319] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0320] FIG. 14A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0321] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, a shutter button 8004, etc. In addition, a detachable lens 8006 is attached to the camera 8000.

[0322] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0323] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0324] The housing 8001 has a mount having electrodes, and can be connected to a strobe device or the like in addition to the finder 8100 .

[0325] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0326] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0327] The button 8103 has a function such as a power button.

[0328] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0329] FIG. 14B is a diagram showing the external appearance of the head mounted display 8200.

[0330] The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 includes a built-in battery 8206.

[0331] A cable 8205 supplies power from a battery 8206 to a main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0332] The mounting unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that contact the user, capable of detecting a current that flows with the movement of the user's eyeballs. The mounting unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The mounting unit 8201 may also have various sensors, such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 according to the movement of the user's head.

[0333] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0334] 14C, 14D, and 14E are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0335] A user can view the display on the display unit 8302 through the lens 8305. Note that it is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing another image displayed in a different area of ​​the display unit 8302 through the lens 8305, it is possible to perform three-dimensional display using parallax. Note that the present invention is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided, with one display unit being provided for each eye of the user.

[0336] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, so that a user cannot see pixels even when the image is enlarged using a lens 8305 as in FIG.

[0337] The electronic devices shown in Figures 15(A) to 15(G) have a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0338] 15(A) to 15(G) have various functions. For example, the electronic devices may have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, and the like. Note that the functions of the electronic devices are not limited to these, and the electronic devices may have various functions. The electronic devices may have multiple display units. In addition, the electronic devices may have a function of providing a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, and the like.

[0339] The electronic devices shown in FIGS. 15A to 15G will be described in detail below.

[0340] 15A is a perspective view of a television set 9100. The television set 9100 can incorporate a display portion 9001 having a large screen, for example, a screen size of 50 inches or more, or 100 inches or more.

[0341] FIG. 15B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 15B shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and phone calls, titles of e-mail and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, the icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0342] 15C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of a display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed at a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and determine, for example, whether to answer a call.

[0343] 15D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch. The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. Hands-free conversation can be performed by causing the mobile information terminal 9200 to communicate with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can transmit data to and from another information terminal and can be charged through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0344] 15(E), (F), and (G) are perspective views showing a foldable mobile information terminal 9201. FIG. 15(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 15(G) is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 15(F) is a perspective view of a state in the middle of changing from one of FIG. 15(E) and FIG. 15(G) to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0345] 16A shows an example of a television set. In a television set 7100, a display portion 7500 is incorporated in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0346] 16A can be operated using an operation switch provided on a housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television set 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0347] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0348] 16B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0349] 16(C) and (D) show an example of digital signage.

[0350] 16C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0351] 16D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0352] The larger the display unit 7500, the more information can be provided at one time, and the larger the display area, the more easily it catches people's attention, which has the effect of increasing the effectiveness of advertising, for example.

[0353] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes, but also for providing information desired by the user, such as route information, traffic information, and commercial facility guide information.

[0354] 16C and 16D, the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0355] Furthermore, a game using the information terminal 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0356] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS.

[0357] Although the electronic device in this embodiment has a display portion, one embodiment of the present invention can also be applied to an electronic device that does not have a display portion.

[0358] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. EXAMPLES

[0359] In this example, the sheet resistance of an oxide semiconductor film in which an impurity was added to reduce the resistance was measured. In addition, a treatment of supplying oxygen to the oxide semiconductor film was performed, and a change in the sheet resistance was evaluated.

[0360] [simulation] First, the implantation amounts of boron and phosphorus used as impurity elements in the depth direction were calculated.

[0361] For the calculation, TRIM (Transport of Ion in Matter), a software for calculating the ion implantation process by the Monte Carlo method, was used.

[0362] The implanted film used in the calculation was a laminated film in which a 100 nm thick silicon oxide film was laminated as the second insulating film, a 40 nm thick InGaZnO4 film was laminated as the oxide semiconductor film, and a 100 nm thick silicon oxide film was laminated as the first insulating film. The calculation was performed for two types of impurity elements, boron and phosphorus. The doses were 5×10 15 cm -2 For boron, five beam energy conditions were set: 10 keV, 15 keV, 20 keV, 30 keV, and 40 keV, and for phosphorus, three conditions were set: 50 keV, 60 keV, and 70 keV.

[0363] In Fig. 17(A), boron ( 11 The calculation results for phosphorus ( 31 The vertical axis shows the volume concentration of boron or phosphorus, and the horizontal axis shows the depth.

[0364] As shown in Figure 17(A), it was confirmed that the higher the beam energy, the higher the impurity concentration in the oxide semiconductor film. It was also confirmed that the higher the beam energy, the deeper the peak position of the highest impurity concentration became and the broader the profile became. It was also confirmed that the highest impurity concentration was observed near the interface between the oxide semiconductor film (IGZO) and the first insulating film (SiO2 on the left) when the beam energy was 20 keV.

[0365] 17B, ​​it was confirmed that the higher the beam energy, the higher the impurity concentration in the oxide semiconductor film. It was also confirmed that a region with the highest impurity concentration could be formed in the vicinity of the interface between the oxide semiconductor film and the first insulating film under all three calculated conditions.

[0366] [Evaluation of sheet resistance] Hereinafter, the results of adding impurities to a film in which an oxide insulating film is stacked over an oxide semiconductor film and measuring the sheet resistance will be described.

[0367] [Evaluation method] The evaluation was carried out according to the following procedure.

[0368] First, an oxide semiconductor film having a thickness of about 40 to 50 nm was formed over a glass substrate by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1.2.

[0369] Next, a silicon oxide film with a thickness of about 100 nm was formed on the oxide semiconductor film. The silicon oxide film was formed by the plasma CVD method using silane gas and dinitrogen monoxide gas as the film formation gas. The substrate temperature during the film formation was 350°C.

[0370] Next, a process for supplying oxygen into the oxide semiconductor film was performed. The process for supplying oxygen was performed by forming a metal oxide film on the silicon oxide film by sputtering in an oxygen-containing atmosphere, supplying oxygen into the silicon oxide film, and then performing heat treatment at 400° C. for 1 hour to supply oxygen from the silicon oxide film to the oxide semiconductor film. Then, the metal oxide film was removed by etching. The metal oxide film was formed under the same conditions as those for the oxide semiconductor film.

[0371] Next, impurities were added. The addition of impurities was carried out using two types of equipment: a plasma ion doping equipment without a mass separation mechanism, and an ion implantation equipment with a mass separation mechanism. In addition, B2H6 gas was used as a gas for supplying boron in the ion doping equipment, and BF3 gas was used in the ion implantation equipment. On the other hand, PH3 gas was used as a gas for supplying phosphorus. Multiple samples were prepared with different impurity doses and acceleration voltages in the plasma ion doping equipment, and different doses and beam energies in the ion implantation equipment. For comparison, samples without added impurities were also prepared.

[0372] Next, the above-described treatment for supplying oxygen into the oxide semiconductor film was performed again. Four types of samples were fabricated: a sample in which the temperature of the heat treatment after the formation of the metal oxide film was changed to three different conditions of 250° C., 350° C., and 400° C., and a sample in which the heat treatment was not performed.

[0373] Finally, the silicon oxide film was removed, and a titanium electrode was formed by sputtering, after which the sheet resistance was measured.

[0374] [Sheet resistance] Each graph in Fig. 18 shows the results of sheet resistance for samples doped with boron by plasma doping. Fig. 18(A) shows the results for an acceleration voltage of 20 kV, Fig. 18(B) shows the results for an acceleration voltage of 40 kV, and Fig. 18(C) shows the results for an acceleration voltage of 60 kV. In each graph, the dose is 1×10 15 cm -2 From 1.5 × 10 16 cm -2In addition, for each dose, the results without heat treatment and the results with heat treatment at each temperature are shown side by side.

[0375] 18A to 18C, it can be seen that the resistance of the oxide semiconductor film is reduced by adding boron. In addition, compared to the condition where the acceleration voltage is 20 kV, the sheet resistance increases as the dose increases at 40 kV and 60 kV. Therefore, in combination with the simulation result of TRIM shown in FIG. 17A, it can be seen that a stable low resistance state is achieved by adding impurities so that the impurity concentration is highest near the interface between the oxide semiconductor film and the oxide insulating film thereon.

[0376] In addition, under the lowest dose condition (1×10 15 cm -2 With the exception of the condition (a), the boron-added samples hardly exhibited the phenomenon of increasing their resistance due to heat treatment, and maintained a low resistance state before and after heat treatment.

[0377] 19(A) and (B) show the results of sheet resistance for a sample doped with phosphorus by plasma doping. Fig. 19(A) shows the results for an acceleration voltage of 60 kV, and Fig. 19(B) shows the results for an acceleration voltage of 70 kV.

[0378] It was confirmed that the resistance of the oxide semiconductor film was reduced even when phosphorus was added as an impurity element. In addition, it was confirmed that the resistance tended to increase as the dose increased, and that there was an optimal range of the dose.

[0379] Next, we will show the evaluation results of the sheet resistance when doping impurity elements using an ion implantation device with a mass separation mechanism. The ion implantation method is a method that can perform more precise control because the mass separation mechanism reduces the inclusion of impurity ions other than the target ions compared to the plasma doping method.

[0380] In Figure 20(A), boron ( 11B) in Fig. 20(B) 31 20(A) and (B) also show the results for samples with no impurity element added.

[0381] It was confirmed that when an ion implantation device was used, the same tendency as in the above-mentioned plasma doping method was observed.

[0382] In addition, when comparing the plasma ion doping method with the ion implantation method, the plasma ion doping method tends to have a low and stable resistance value even with a small dose amount. This is thought to be because the plasma ion doping device does not have a mass analysis mechanism, and impurity ions other than the target ions affect the resistance value of the oxide semiconductor film.

[0383] [Evaluation of impurity concentration] The following describes the results of measuring the concentration distribution of impurity elements in the depth direction using the sample prepared above. The measurement was performed by secondary ion mass spectrometry (SIMS). The sample was an oxide semiconductor film that had been doped with boron ( 11 B) was added, and phosphorus ( 31 The boron doping conditions were a beam energy of 20 keV and a dose of 5×10 15 cm -2 The phosphorus doping conditions were beam energy of 60 keV and dose of 5×10 15 cm -2 It was decided.

[0384] 21(A) shows the SIMS analysis result of the sample doped with boron, and Fig. 21(B) shows the SIMS analysis result of the sample doped with phosphorus. Each figure also shows two profiles, one quantified using a silicon oxide film (SiO2) as the standard sample, and the other quantified using an oxide semiconductor film (IGZO).

[0385] 21A shows that the silicon oxide film has a concentration gradient in which the concentration of boron increases toward the interface with the oxide semiconductor film. On the other hand, the oxide semiconductor film has a concentration gradient in which the concentration of boron increases toward the interface with the silicon oxide film. That is, it was confirmed that the region with the highest concentration of boron is located near these interfaces. It was also found that the slope of the concentration gradient is greater in the oxide semiconductor film than in the silicon oxide film.

[0386] 21B shows a similar tendency to that in Fig. 21A, that is, in the sample to which phosphorus is added, the region with the highest phosphorus concentration is located near the interface between the silicon oxide film and the oxide semiconductor film, and the slope of the concentration gradient is larger in the oxide semiconductor film than in the silicon oxide film.

[0387] From the above results, it was confirmed that a stable oxide semiconductor film with extremely low resistance can be formed by adding an impurity element such as boron or phosphorus to an oxide semiconductor layer through an oxide insulating film. In addition, it was confirmed that by providing a region with the highest concentration near the interface between the oxide insulating film and the oxide semiconductor film, an increase in resistance value is not observed even when a process of supplying oxygen to the oxide semiconductor film is performed. From these results, it can be inferred that adding an impurity element such as boron or phosphorus to the oxide insulating film gives the oxide insulating film a blocking property against oxygen, making it difficult for oxygen to diffuse. EXAMPLES

[0388] Below, a transistor of one embodiment of the present invention was manufactured and its electrical characteristics were evaluated.

[0389] [Sample preparation] The structure of the manufactured transistor can be that of the transistor 100A illustrated in Embodiment 1 and FIG. 3. Here, boron and phosphorus were used as impurity elements, and a number of samples were manufactured under different addition conditions. For comparison, a sample to which no impurity element was added was also manufactured in the same manner.

[0390] First, a tungsten film with a thickness of about 100 nm was formed on a glass substrate by sputtering, and then processed to obtain a first gate electrode. Next, a silicon nitride film with a thickness of about 240 nm, a silicon nitride film with a thickness of about 60 nm, and a silicon oxynitride film with a thickness of about 5 nm were laminated by plasma CVD to form a first gate insulating layer.

[0391] Next, a metal oxide film with a thickness of about 40 nm was formed on the first gate insulating layer, and the semiconductor layer was obtained by processing the metal oxide film. The metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1.2 [atomic ratio]). After that, a heat treatment was performed at 400°C for 1 hour in a nitrogen atmosphere, and then a heat treatment was performed at 400°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0392] Next, a silicon oxynitride film with a thickness of about 100 nm was formed as the second gate insulating layer by plasma CVD. After that, a heat treatment was performed under conditions of a nitrogen atmosphere at a temperature of 400°C for 1 hour. Next, a plasma treatment was performed in an oxygen-containing atmosphere as an oxygen supply treatment.

[0393] Next, a metal oxide film with a thickness of about 20 nm was formed on the second gate insulating layer by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1.2 [atomic ratio]).

[0394] Next, a molybdenum film with a thickness of about 100 nm was formed on the metal oxide film by sputtering, and then the molybdenum film and the metal oxide film were partially removed by etching to obtain a second gate electrode and a metal oxide layer.

[0395] Next, an impurity element was added using the second gate electrode as a mask. A plasma ion doping device was used to add the impurities. B2H6 gas was used to supply boron, and PH3 gas was used to supply phosphorus. Several samples were fabricated with different impurity doses and acceleration voltages. For comparison, a sample was also fabricated without the addition of impurities.

[0396] Next, a silicon oxynitride film with a thickness of about 300 nm was formed by plasma CVD as a protective insulating layer covering the transistor. The film formation temperature of the silicon oxynitride film was set to 220°C. Then, a heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 350°C, and one hour. Next, a part of the insulating layer covering the transistor and the second gate insulating layer was opened, and a molybdenum film was formed by sputtering, and then processed to obtain a source electrode and a drain electrode. Then, an acrylic film with a thickness of about 1.5 μm was formed as a planarizing layer, and a heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250°C, and one hour.

[0397] Through the above steps, a transistor was formed on a glass substrate.

[0398] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated as described above were measured.

[0399] As for the measurement conditions of the Id-Vg characteristics of the transistor, the voltage applied to the first gate electrode (hereinafter also referred to as the gate voltage (Vg)) and the voltage applied to the second gate electrode (hereinafter also referred to as the (Vbg)) were applied in steps of 0.25 V from -15 V to +20 V. In addition, the voltage applied to the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (comm), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was set to 0.1 V and 20 V.

[0400] Figure 22 shows the Id-Vg characteristics of a boron-doped (B-Dope) transistor, and Figure 23 shows the Id-Vg characteristics of a phosphorus-doped transistor. In Figures 22 and 23, the results of different impurity doping conditions are arranged horizontally. Each figure also shows transistors that are not doped with impurities (Non-Doped). Figures 22 and 23 show three types of transistors with a channel width of 50 μm and channel lengths of 2 μm, 3 μm, and 6 μm.

[0401] As shown in FIG. 22, it was found that a larger current can flow in the transistor doped with boron than in the transistor not doped with impurities. This indicates that the resistance of the source region and the drain region is sufficiently low. Furthermore, under the condition of an acceleration voltage of 20 kV, even a transistor with a short channel length of 2 μm shows good characteristics regardless of the dose. On the other hand, under the condition of a high acceleration voltage of 60 kV, the current value tends to be lower than under other conditions. This tendency is consistent with the tendency seen in the results of the sheet resistance and the like in Example 1 above.

[0402] In addition, as shown in Figure 23, the transistors doped with phosphorus also show good electrical characteristics, similar to those of the boron transistor. Note that, under high dose conditions, the threshold voltage of short channel length transistors varies toward the negative side.

[0403] In this case, since a plasma ion doping device without a mass separation mechanism was used as the device used to add the impurity element, hydrogen may have been added in addition to the target element. Therefore, the negative shift in threshold voltage observed in the transistors with short channel lengths in Figures 22 and 23 may be due to the influence of the hydrogen. Therefore, it is presumed that a transistor with better electrical characteristics can be manufactured by using an ion implantation device with a mass separation mechanism. EXAMPLES

[0404] In the following, a transistor according to one embodiment of the present invention was manufactured and its reliability was evaluated.

[0405] The transistor whose reliability was evaluated can be manufactured by the manufacturing process exemplified in the above-mentioned Example 2. Boron was used as the impurity element, and the impurity element was added by using a plasma ion doping apparatus. The acceleration voltage was 20 kV, and the dose amount was 5×10 15 cm -2 The deposition temperature of the silicon oxynitride film functioning as a protective layer was set to 350° C.

[0406] The Id-Vg characteristics of the fabricated transistor are shown in Figure 24(A) The size of the transistor is a channel length of 3 µm and a channel width of 50 µm.

[0407] Next, a gate bias stress test (GBT test) was performed using the above transistor to evaluate its reliability. In the GBT test, the substrate on which the transistor is formed is kept at 60°C, and a voltage of 0V is applied to the source and drain of the transistor, and a voltage of 20V or -20V is applied to the gate, and this state is maintained for one hour. Here, the test environment is dark, and a test in which a positive voltage is applied to the gate is referred to as PBTS, and a test in which a negative voltage is applied is referred to as NBTS. In addition, PBTS in a state in which the sample is irradiated with light is referred to as PBITS, and NBTS is referred to as NBITS. White LED light of approximately 10,000lx was used for the light irradiation.

[0408] 24B shows the change in threshold voltage (ΔVth) before and after the gate bias stress test. As shown in FIG. 24B, it was confirmed that the change in threshold voltage of the fabricated transistor was extremely small.

[0409] From the above, it was confirmed that the transistor of one embodiment of the present invention has favorable electrical characteristics and high reliability. EXAMPLES

[0410] In this embodiment, the oxygen blocking property of an insulating film containing an oxide to which an impurity element is added is evaluated by thermal desorption spectroscopy (TDS).

[0411] [Rating 1] Here, a sample was prepared by supplying oxygen to an oxide insulating film over an oxide semiconductor film and then supplying impurities thereto, and the TDS measurement was performed.

[0412] [Sample Preparation] First, an oxide semiconductor film having a thickness of about 40 nm was formed on a glass substrate by sputtering using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1.2.

[0413] Next, a silicon oxide film with a thickness of about 100 nm was formed on the oxide semiconductor film. The silicon oxide film was formed by the plasma CVD method using silane gas and dinitrogen monoxide gas as the film formation gas. The substrate temperature during the film formation was 350°C.

[0414] Next, a process for supplying oxygen into the oxide semiconductor film was performed. The process for supplying oxygen was performed by forming a metal oxide film on the silicon oxide film by sputtering in an oxygen-containing atmosphere, supplying oxygen into the silicon oxide film, and then performing heat treatment at 400° C. for 1 hour to supply oxygen from the silicon oxide film to the oxide semiconductor film. Then, the metal oxide film was removed by etching. The metal oxide film was formed under the same conditions as those for the oxide semiconductor film.

[0415] Next, impurities were added. The impurities were added using an ion implantation device with a mass separation mechanism. Here, boron ( 11 B), phosphorus ( 31 P), and argon ( 40 In addition, a sample without any impurity implantation was also prepared as a comparison sample.

[0416] The impurity was implanted under conditions optimized so that ions reached the oxide semiconductor film through the silicon oxide film. The boron was implanted under conditions of a beam energy of 20 keV and a dose of 5×10 15 cm -2 The phosphorus implantation conditions were beam energy of 60 keV and dose of 5×10 15 cm -2 The argon implantation conditions were a beam energy of 70 keV and a dose of 5×10 15 cm -2 It was decided.

[0417] [TDS analysis results] 25 shows the results of TDS analysis of oxygen molecules (mass-to-charge ratio (M / z) 32). In each figure, the vertical axis indicates the detection intensity, and the horizontal axis indicates the substrate temperature.

[0418] It can be seen that in the sample that did not undergo ion implantation, oxygen is released when the substrate temperature was between about 150°C and 300°C. On the other hand, it can be seen that almost no oxygen is released in the samples implanted with boron and phosphorus. From this result, it can be seen that the implantation of boron and phosphorus stabilizes the excess oxygen in the silicon oxide film, making it possible to suppress outward diffusion.

[0419] On the other hand, in the sample implanted with argon, oxygen emission was noticeable, and it was confirmed that the effect of suppressing the outward diffusion of oxygen was weak. In addition, although not shown here, in the sample implanted with argon, in addition to oxygen, argon (M / z=20 and M / z=40) was also released at substrate temperatures in the range of about 250°C to 430°C. From this result, it is inferred that argon, which is a rare gas, has little interaction with oxygen in silicon oxide, and therefore cannot be expected to have much effect in stabilizing excess oxygen.

[0420] [Rating 2] Here, a second oxide insulating film was formed over a first oxide insulating film that had been subjected to a treatment to supply oxygen, and a sample was prepared in which impurities were supplied to the second oxide insulating film. The oxygen-blocking property of the second oxide insulating film was evaluated by TDS measurement.

[0421] [Sample Preparation] First, a silicon oxide film having a thickness of about 150 nm was formed as a first oxide insulating film on a glass substrate under the same conditions as those in Evaluation 1 above.

[0422] Next, a process of supplying oxygen to the first oxide insulating film was performed. In the process of supplying oxygen, a metal oxide film was formed on the silicon oxide film by sputtering in an atmosphere containing oxygen, and oxygen was supplied into the silicon oxide film. Then, the metal oxide film was removed by etching. The metal oxide film was formed using an indium tin oxide target containing silicon.

[0423] Subsequently, as a second oxide insulating film, a silicon oxide film having a thickness of about 100 nm was formed by the same method as above.

[0424] Next, impurities were added. The impurities were added using an ion implantation device with a mass separation mechanism. As in Evaluation 1, boron ( 11 B), phosphorus ( 31 P), and argon ( 40 In addition, a sample without any impurity implantation was also prepared as a comparison sample.

[0425] The impurity implantation was performed under optimized conditions so that ions were implanted only into the second silicon oxide film. The boron implantation conditions were a beam energy of 5 keV and a dose of 5×10 15 cm -2 The phosphorus implantation conditions were a beam energy of 10 keV and a dose of 5×10 15 cm -2 The argon implantation conditions were a beam energy of 10 keV and a dose of 5×10 15 cm -2 It was decided.

[0426] [TDS analysis results] FIG. 26 shows the results of the TDS analysis.

[0427] It can be seen that in the sample that did not undergo ion implantation, oxygen is released when the substrate temperature was around 250°C to around 450°C. On the other hand, it can be seen that almost no oxygen is released in the sample implanted with boron and phosphorus. From this result, it can be seen that the implantation of boron and phosphorus stabilizes the excess oxygen in the silicon oxide film, making it possible to suppress outward diffusion.

[0428] On the other hand, it was confirmed that the sample implanted with argon released oxygen at a lower temperature (around 150°C) than the sample without ion implantation. This is presumably due to damage caused to the second oxide insulating film during ion implantation, making it more susceptible to oxygen desorption and diffusion.

[0429] From the above results, it was found that the implantation of boron and phosphorus into the oxide insulating film makes it difficult for excess oxygen to be released. Furthermore, it was confirmed that the implantation of boron and phosphorus can give the oxide insulating film the ability to block oxygen diffusion. EXAMPLES

[0430] In this example, a sample was prepared by ion implantation, and the results of XPS analysis will be described.

[0431] Here, the following two types of samples were prepared and analyzed: the first sample was obtained by directly implanting ions into an oxide semiconductor film, and the second sample was obtained by implanting ions into a stacked film in which an oxide insulating film was stacked over an oxide semiconductor film.

[0432] [Sample Preparation] First, the first sample will be described. An oxide semiconductor film with a thickness of about 40 nm was formed on a glass substrate. The film formation method can be applied to Example 4. Then, boron ( 11 The boron implantation conditions were a beam energy of 5 keV and a dose of 1×10 16 cm -2It was decided.

[0433] For the second sample, the description of Evaluation 1 in Example 4 can be applied, except for the ion implantation conditions. The ion implantation was carried out by ion implantation method, in which boron ( 11 B) was performed under conditions optimized to reach the oxide semiconductor film. The boron implantation conditions were a beam energy of 20 keV and a dose of 1×10 16 cm -2 It was decided.

[0434] [XPS analysis] XPS analysis was performed on the two types of samples prepared above. Mg-Kα (1253.6 eV) was used as the X-ray source for the XPS measurement. The XPS analysis was combined with sputtering to perform depth analysis. Argon ions were used for sputtering, and the acceleration voltage was set to 2.0 kV. The sputtering rate was approximately 5 nm / min in terms of SiO2.

[0435] 27A shows a depth profile obtained by XPS analysis of a sample in which ions are directly implanted into an oxide semiconductor film, in which the horizontal axis indicates the sputtering time and the vertical axis indicates the composition ratio.

[0436] As shown in FIG. 27, boron was detected near the surface of the oxide semiconductor film (IGZO) at a concentration of several atomic percent.

[0437] 27B shows an XPS spectrum in an energy range where a peak associated with the 1s orbital of boron in an oxide semiconductor (IGZO) is obtained. The horizontal axis represents binding energy, and the vertical axis represents photoelectron intensity. A peak is observed near 192 eV, and no peak is observed near 188 eV, which indicates that boron exists in an oxidized state in the oxide semiconductor film, and that elemental boron is hardly present.

[0438] FIG. 27(C) shows the 3d 5 / 2This shows an XPS spectrum in the energy range where orbital-related peaks are obtained. The peak near 443 eV indicates the presence of metallic indium. This suggests that boron is removing oxygen from indium, causing oxygen vacancies.

[0439] 28(A) shows a depth profile obtained by XPS analysis of a sample in which ions were implanted into a stacked film in which an oxide insulating film was stacked on an oxide semiconductor film. Boron was detected at a concentration of several atomic percent near the interface between the oxide insulating film (SiON) and the oxide semiconductor film (IGZO).

[0440] Figure 28B shows an XPS spectrum in the energy range where a peak related to the 1s orbital of boron in the oxide insulating film (SiON) is obtained. It was found that boron exists in an oxidized state in the oxide insulating film as in the oxide semiconductor film, and elemental boron is hardly present. This confirmed that boron is bonded to oxygen in the oxide insulating film.

[0441] From the above results, it was confirmed that boron implanted into the oxide semiconductor film and the oxide insulating film is bonded to oxygen in the films and exists in the form of oxide. EXAMPLES

[0442] In this example, a transistor of one embodiment of the present invention was manufactured, and its electrical characteristics were evaluated.

[0443] [Sample preparation] First, a first gate electrode, a first gate insulating layer, a semiconductor layer, and a second gate insulating layer were formed on a glass substrate by the same method as that shown in Example 2. Next, an aluminum oxide film with a thickness of about 10 nm was formed on the second gate insulating layer by a sputtering method, followed by a titanium film with a thickness of about 5 nm, an aluminum film with a thickness of about 300 nm, and a titanium film with a thickness of about 50 nm, in that order, and these metal films and parts of the aluminum oxide film were removed by etching to obtain a second gate electrode and a metal oxide layer.

[0444] Next, impurity elements were implanted by ion implantation using the second gate electrode as a mask. Here, boron ( 11 B) and phosphorus ( 31 The boron implantation conditions were a beam energy of 15 keV and a dose of 3×10 15 cm -2 The phosphorus implantation conditions were a beam energy of 45 keV and a dose of 1×10 15 cm -2 It was decided.

[0445] Thereafter, a protective insulating layer was formed and a heat treatment was performed in the same manner as in Example 2. A laminated film of a tungsten film with a thickness of about 50 nm, an aluminum film with a thickness of about 400 nm, and a titanium film with a thickness of about 100 nm, which were formed by a sputtering method, was used for the source electrode and the drain electrode. Then, a planarizing layer was formed and a heat treatment was performed in the same manner as in Example 2.

[0446] Through the above process, two types of samples were obtained, one using boron and the other using phosphorus as the impurity element.

[0447] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated above were measured. The measurement conditions can be the same as those in Example 2.

[0448] Figure 29 shows the Id-Vg characteristics of a transistor using boron as an impurity element and a transistor using phosphorus. Figure 29 shows three types of transistors with a channel width of 50 μm and channel lengths of 2 μm, 3 μm, and 6 μm. Each transistor was measured 20 times.

[0449] As shown in FIG. 29, it was confirmed that both the transistor to which boron was added and the transistor to which phosphorus was added showed very favorable electrical characteristics. [Explanation of symbols]

[0450] 100, 100A: transistor, 102: substrate, 103, 110, 116, 118: insulating layer, 103d, 108n, 110d: region, 106, 106c, 112, 120a, 120b: conductive layer, 108, 108c: semiconductor layer, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide film, 130A, 130B: capacitance element, 140: impurity element, 141a, 141b, 142: opening

Claims

1. A method for manufacturing a semiconductor device including an oxide semiconductor layer, comprising the steps of: forming an oxide film in contact with the oxide semiconductor layer; adding an impurity element to the oxide semiconductor layer through the oxide film; forming an insulating layer after the adding step; and performing a heat treatment after the step of forming the insulating layer to release oxygen from the oxide film to the oxide semiconductor layer, the insulating layer is an insulating film containing silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or hafnium aluminate; the impurity element to be added is phosphorus, boron, magnesium, aluminum, or silicon; The doping is performed so that the oxide semiconductor layer has a region in which a concentration of the impurity element becomes higher toward the oxide film.

2. In claim 1, The heat treatment is performed in a temperature range of 200° C. or more and 400° C. or less.

3. In claim 1 or 2, The method for manufacturing a semiconductor device, wherein the insulating layer is formed at a temperature in the range of 150° C. or more and 400° C. or less.

4. In any one of claims 1 to 3, The method for manufacturing a semiconductor device, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

5. In claim 4, forming a metal oxide layer in contact with the oxide film, the metal oxide layer having a higher proportion of gallium than the oxide semiconductor layer and a lower proportion of indium than the oxide semiconductor layer, before the adding step.

6. In any one of claims 1 to 4, The method for manufacturing a semiconductor device further comprises the step of forming a metal oxide layer in contact with the oxide film before the step of adding.

7. In any one of claims 1 to 4, The method for manufacturing a semiconductor device further comprises a step of performing a treatment for supplying oxygen to the oxide film before the step of adding.

8. In any one of claims 1 to 7, the addition is performed so that the oxide film has a region in which a concentration of the impurity element becomes higher toward the oxide semiconductor layer.

9. In any one of claims 1 to 8, the addition is performed so that a concentration of the impurity element is highest at an interface between the oxide semiconductor layer and the oxide film, a portion of the oxide semiconductor layer close to the oxide film, or a portion of the oxide film close to the oxide semiconductor layer.

10. In any one of claims 1 to 9, The method for manufacturing a semiconductor device, wherein the addition is carried out by a plasma ion doping method or an ion implantation method.

11. A first conductive layer; and an oxide semiconductor layer containing indium and gallium; An oxide layer; a metal oxide layer having a region facing the oxide semiconductor layer with the oxide layer interposed therebetween, the metal oxide layer having a higher proportion of gallium than the oxide semiconductor layer and a lower proportion of indium than the oxide semiconductor layer; a second conductive layer in contact with the first conductive layer through the metal oxide layer and an opening provided in the oxide layer; An insulating layer; A method for manufacturing a semiconductor device having forming an oxide film in contact with the oxide semiconductor layer; adding an impurity element to the oxide semiconductor layer through the oxide film; forming the insulating layer after the adding step; and performing a heat treatment after the step of forming the insulating layer to release oxygen from the oxide film to the oxide semiconductor layer, the insulating layer is an insulating film containing silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or hafnium aluminate; the impurity element to be added is phosphorus, boron, magnesium, aluminum, or silicon; The addition is performed so that the oxide semiconductor layer has a region in which a concentration of the impurity element becomes higher toward the oxide film.

12. A first conductive layer; and an oxide semiconductor layer; An oxide layer; a metal oxide layer having a region facing the oxide semiconductor layer with the oxide layer interposed therebetween; a second conductive layer in contact with the first conductive layer through the metal oxide layer and an opening provided in the oxide layer; A method for manufacturing a semiconductor device having an insulating layer, comprising: forming the oxide semiconductor layer containing indium and gallium on the first conductive layer; forming an oxide film in contact with the oxide semiconductor layer; forming a metal oxide layer in contact with the oxide film, the metal oxide layer having a higher gallium content than the oxide semiconductor layer and a lower indium content than the oxide semiconductor layer; forming the opening in the metal oxide layer and the oxide film; forming the second conductive layer on the metal oxide layer; adding an impurity element to the oxide semiconductor layer through the oxide film; forming the insulating layer after the adding step; and performing a heat treatment after the step of forming the insulating layer to release oxygen from the oxide film to the oxide semiconductor layer, the insulating layer is an insulating film containing silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, or hafnium aluminate; the impurity element to be added is phosphorus, boron, magnesium, aluminum, or silicon; The doping is performed so that the oxide semiconductor layer has a region in which a concentration of the impurity element becomes higher toward the oxide film.

Images