Display substrate and its manufacturing method, display device

Abstract

a display substrate and its manufacturing method, and a display device, the display substrate having a plurality of sub-pixels, each sub-pixel having an emissive area (AA) and a non-emissive area (NA); a driving circuit is provided in each sub-pixel, the driving circuit having a storage capacitor (Cst) and a plurality of transistors, the plurality of transistors including a switching transistor (T1), a driving transistor (T2) and a sense transistor (T3); for each sub-pixel, the plurality of transistors are located in the non-emissive area, the storage capacitor is a transparent capacitor, and there is an overlapping area between the orthogonal projection of the storage capacitor on the substrate (10) and the emissive area; a first electrode (C1) of the storage capacitor is located in the same layer as the active layers of the plurality of transistors and is located in a different layer from the source / drain electrodes of the plurality of transistors; a second electrode (C2) of the storage capacitor is located on the side of the first electrode closest to the substrate; a first pole (23) of the driving transistor is electrically connected to the second electrode; and a first pole (43) of the sense transistor is electrically connected to the second electrode.

Description

[Technical field]

[0001] This application claims priority from Chinese Patent Application No. 201911038401.5, filed on October 29, 2019, entitled "Display substrate and its manufacturing method, and display device," the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of display technology, and more particularly to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0003] Displays using organic light-emitting diodes (OLED) are a display technology that differs from conventional liquid crystal displays (LCD). OLEDs have the advantages of actively emitting light, having good temperature characteristics, low power consumption, fast response, flexibility, being extremely light and thin, and low cost. They have already become one of the important discoveries in the field of next-generation display devices, and are attracting more and more attention.

[0004] OLED display substrates may be divided into three types according to the light emission direction: bottom emission OLED, top emission OLED, and double-sided emission OLED. Bottom emission OLED refers to the light emitted from an OLED device toward the substrate. However, since the bottom emission OLED display substrate is limited by the pixel aperture area, the area occupied by each sub-pixel is relatively large, and the number of pixels per unit area (abbreviated as Pixels Per Inch, PPI) in the bottom emission OLED display substrate is relatively small, making it difficult to achieve a high PPI. Summary of the Invention [Means for solving the problem]

[0005] The following is a summary of the subject matter of the detailed description of the present disclosure, which is not intended to limit the scope of the claims. In one aspect, the present disclosure provides a display substrate, comprising: a substrate; and a plurality of sub-pixels disposed on the substrate, each sub-pixel having a light-emitting area and a non-light-emitting area; each sub-pixel is disposed with a driving circuit, the driving circuit comprising a storage capacitor and a plurality of transistors, the plurality of transistors including a switching transistor, a driving transistor and a sense transistor; For each subpixel, the plurality of transistors are located in the non-light-emitting region, the storage capacitor is a transparent capacitor, and a positive projection of the storage capacitor on the substrate and the light-emitting region have an overlapping region, a first electrode of the storage capacitor is disposed in the same layer as active layers of the plurality of transistors and in a different layer from source / drain electrodes of the plurality of transistors, and a second electrode of the storage capacitor is disposed on a side of the first electrode close to the substrate; A first electrode of the drive transistor is electrically connected to the second electrode, and a first electrode of the sense transistor is electrically connected to the second electrode.

[0006] In one exemplary embodiment, the display substrate further comprises a buffer layer and a light-shielding layer disposed on a side of the active layers of the plurality of transistors adjacent to the substrate, the light-shielding layer and the second electrode being disposed on a side of the buffer layer adjacent to the substrate; The orthogonal projection of the second electrode on the substrate covers the orthogonal projection of the light-shielding layer on the substrate, and the surface of the light-shielding layer adjacent to the second electrode is in complete contact with the second electrode.

[0007] In one exemplary embodiment, the light-shielding layer is disposed on a side of the second electrode that is closer to the substrate, or the second electrode is disposed on a side of the light-shielding layer that is closer to the substrate.

[0008] In one exemplary embodiment, the display substrate further includes an interlayer insulating layer disposed between the source / drain electrodes of the plurality of transistors and the active layers of the plurality of transistors; the buffer layer includes a first via and a second via that expose the second electrode, the interlayer insulating layer includes a third via that exposes the first via and a fourth via that exposes the second via, The first pole of the drive transistor is connected to the second electrode by the first via and the third via, and the first pole of the sense transistor is connected to the second electrode by the second via and the fourth via.

[0009] In one exemplary embodiment, the display substrate further comprises a plurality of rows of grid lines and a plurality of columns of data lines disposed on the substrate, each sub-pixel is defined by an intersection of a grid line and a data line, each of the plurality of sub-pixels corresponds to the plurality of rows of grid lines and the plurality of columns of data lines in a one-to-one relationship, and the plurality of rows of grid lines include a first grid line and a second grid line; The first grid lines and the second grid lines are disposed in the same layer as the gate electrodes of the transistors, and the data lines in the columns are disposed in the same layer as the source / drain electrodes of the transistors.

[0010] In one exemplary embodiment, for each sub-pixel, the first electrode is respectively connected to a first pole of the switching transistor and a gate electrode of the driving transistor; A gate electrode of the switching transistor is connected to a first grid line among the grid lines corresponding to the subpixel, a second electrode of the switching transistor is connected to a data line corresponding to the subpixel, and a gate electrode of the sense transistor is connected to a second grid line among the grid lines corresponding to the subpixel.

[0011] In an exemplary embodiment, for each sub-pixel, the non-light-emitting region includes a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region and the second non-light-emitting region are located on both sides of the light-emitting region and are arranged along an extending direction of the data lines of the plurality of columns; The sense transistor and the second grid line are all located in the first non-light-emitting region, and the switching transistor, the driving transistor and the first grid line are all located in the second non-light-emitting region.

[0012] In one exemplary embodiment, the display substrate further includes a power supply line and a sense line disposed in the same layer as the plurality of data lines, and each pixel includes four sub-pixels disposed along an extension direction of the grid lines, and each pixel corresponds to two power supply lines and one sense line; For each pixel, a sense line corresponding to the pixel is located between the second sub-pixel and the third sub-pixel, one row of power cords corresponding to the pixel is located on a side of the first sub-pixel away from the second sub-pixel, and another row of power cords corresponding to the pixel is located on a side of the fourth sub-pixel away from the third sub-pixel; a data line corresponding to the first subpixel is located on a side of the first subpixel adjacent to the second subpixel, a data line corresponding to the second subpixel is located on a side of the second subpixel adjacent to the first subpixel, a data line corresponding to the third subpixel is located on a side of the third subpixel adjacent to the fourth subpixel, and a data line corresponding to the fourth subpixel is located on a side of the fourth subpixel adjacent to the third subpixel; the display substrate further includes power supply connection lines disposed in the same layer as the gate electrodes of the plurality of transistors, and sense connection lines disposed in the same layer as the light-shielding layer, each pixel corresponds to two power supply connection lines disposed along the extension direction of the grid lines and two sense connection lines disposed along the extension direction of the grid lines, the power supply connection lines respectively correspond to power cords, the power supply connection lines are connected to the corresponding power cords, and the two sense connection lines are connected to sense lines; a second electrode of the driving transistor of the second sub-pixel is connected to one of the power supply connecting lines; a second electrode of the driving transistor of the third sub-pixel is connected to the other power supply connecting line; A second electrode of the sense transistor of the first subpixel is connected to one of the sense connection lines; The second electrode of the sense transistor of the fourth sub-pixel is connected to the other sense connecting line.

[0013] In one exemplary embodiment, the buffer layer further includes a fifth via exposing the sense connection line, and the interlayer insulating layer further includes a sixth via exposing the fifth via; The second electrode of the sense transistor is connected to the sense connection line by the fifth via and the sixth via.

[0014] In one exemplary embodiment, the display substrate further comprises a gate insulating layer disposed between the gate electrodes of the plurality of transistors and the active layers of the plurality of transistors; An orthogonal projection of the gate insulating layer on the substrate overlaps with an orthogonal projection of the gate electrodes of the plurality of transistors on the substrate.

[0015] In one exemplary embodiment, the material of the first electrode comprises a transparent metal oxide and the material of the second electrode comprises a transparent conductive material.

[0016] In one exemplary embodiment, each sub-pixel further includes a light-emitting element and an optical filter having the same color as the sub-pixel, the light-emitting element including an anode, an organic light-emitting layer and a cathode, the anode being connected to the first electrode of the sense transistor, the anode being a transmissive electrode, and the cathode being a reflective electrode; There is an overlapping area between the orthogonal projection of the light-emitting element on the substrate and the light-emitting area, the optical filter is located in the light-emitting area and is installed on a side of the light-emitting element close to the substrate, and the orthogonal projection of the anode on the substrate covers the orthogonal projection of the optical filter on the substrate.

[0017] In one exemplary embodiment, the display substrate further comprises a passivation layer and a planarization layer disposed on the side of the source / drain electrodes of the plurality of transistors away from the substrate; the passivation layer is disposed on a side of the optical filter adjacent to the substrate, the planar layer is disposed between the light emitting element and the optical filter, the passivation layer is provided with a seventh via exposing the first electrode of the sense transistor, and the planar layer is provided with an eighth via exposing the seventh via; the anode is connected to the first electrode of the sense transistor by the seventh via and the eighth via; The orthogonal projection of the eighth via on the substrate incompletely overlaps with the orthogonal projection of the fourth via on the substrate.

[0018] In another aspect, the present disclosure provides a display device comprising any of the display substrates described above.

[0019] In a further aspect, the present disclosure provides a method of manufacturing a display substrate, for use in manufacturing any of the display substrates described above, the method comprising: Providing a substrate; forming a plurality of sub-pixels on the substrate, each sub-pixel having a light-emitting region and a non-light-emitting region; each sub-pixel is provided with a driving circuit, the driving circuit including a storage capacitor and a plurality of transistors, the plurality of transistors including a switching transistor, a driving transistor and a sense transistor; For each subpixel, the plurality of transistors are located in the non-light-emitting region, the storage capacitor is a transparent capacitor, and a positive projection of the storage capacitor on the substrate and the light-emitting region have an overlapping region, a first electrode of the storage capacitor is disposed in the same layer as active layers of the plurality of transistors and in a different layer from source / drain electrodes of the plurality of transistors, and a second electrode of the storage capacitor is disposed on a side of the first electrode close to the substrate; A first electrode of the drive transistor is electrically connected to the second electrode, and a first electrode of the sense transistor is electrically connected to the second electrode.

[0020] In one exemplary embodiment, the display substrate further comprises grid lines, data lines, power lines, and sense lines, the grid lines including first grid lines and second grid lines, and forming a plurality of sub-pixels on the substrate includes: forming a light-shielding layer and the second electrode on the substrate; forming active layers and the first electrodes of the plurality of transistors on the light-shielding layer and the second electrodes; forming gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines on active layers of the plurality of transistors and the first electrodes; forming gate electrodes of the transistors, the data lines, the power cords, the sense lines, and source / drain electrodes of the transistors on the first grid lines and the second grid lines; sequentially forming an optical filter and a light emitting element on the data lines, the power cords, the sense lines and source / drain electrodes of the plurality of transistors.

[0021] In one exemplary embodiment, the step of forming a light-shielding layer and the second electrode on the substrate includes: The method includes sequentially forming the light-shielding layer and the second electrode on the substrate, sequentially forming the second electrode and the light-shielding layer on the substrate, or simultaneously forming the second electrode and the light-shielding layer on the substrate.

[0022] In one exemplary embodiment, the step of simultaneously forming the second electrode and the light-shielding layer on the substrate includes: depositing a light-shielding thin film and a transparent conductive thin film in sequence on the substrate; and simultaneously forming the second electrode and the light-shielding layer using a half-tone mask.

[0023] In one exemplary embodiment, the steps of forming active layers and first electrodes of the plurality of transistors on the light shielding layer and the second electrode, forming gate electrodes of the plurality of transistors, first grid lines and second grid lines on the active layers and first electrodes of the plurality of transistors, and forming data lines, power lines, sense lines and source / drain electrodes of the plurality of transistors on the gate electrodes of the plurality of transistors, the first grid lines and the second grid lines include: forming a buffer layer having a first via, a second via and a fifth via in the light-shielding layer and the second electrode, the first via and the second via exposing the second electrode, and the fifth via exposing a sense connection line; forming the active layers and the first electrodes of the plurality of transistors in the buffer layer by a same manufacturing process; forming gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines on active layers of the plurality of transistors and the first electrodes; forming an interlayer insulating layer including a third via, a fourth via, and a sixth via on the gate electrodes of the plurality of transistors, the first grid line, and the second grid line, the third via exposing the first via, the fourth via exposing the second via, and the sixth via exposing the fifth via; forming the data lines, the power cords, the sense lines and source / drain electrodes of the transistors on the interlayer insulating layer; or forming a first insulating thin film on the light-shielding layer and the second electrode; forming active layers and the first electrodes of the plurality of transistors in a first insulating thin film by the same manufacturing process; forming gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines on active layers of the plurality of transistors and the first electrodes; forming a second insulating thin film on the gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines; and processing the first insulating thin film and the second insulating thin film using a patterning process to form a buffer layer having a first via, a second via, and a fifth via, and an interlayer insulating layer having a third via, a fourth via, and a sixth via.

[0024] In one exemplary embodiment, the step of sequentially forming optical filters and light-emitting elements on the data lines, the power cords, the sense lines, and the source / drain electrodes of the plurality of transistors includes: forming a passivation layer having a seventh via on the data line, the power cord, the sense line and the source / drain electrodes of the plurality of transistors, the seventh via exposing the first pole of the sense transistor; forming the optical filter and a planar layer in the passivation layer, the planar layer including an eighth via, the eighth via exposing the seventh via; forming a light-emitting device on the planarization layer. Other features and advantages of the present application will be set forth in the following description, and in part will be obvious from the description, or may be learned by the practice of the present application. Other advantages of the present application may be realized or obtained by the solutions particularly set forth in the description, claims, and drawings.

[0025] Other aspects may be understood after reading and understanding the drawings and detailed description.

[0026] The drawings are intended to provide an understanding of the technical solution of the present application, and are incorporated in the specification. The drawings are used to interpret the technical solution of the present application together with the embodiments of the present application, and are not intended to limit the technical solution of the present application. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is an equivalent circuit diagram of the drive circuit. [Figure 2A] FIG. 2A is a cross-sectional view of a display substrate according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is another cross-sectional view of a display substrate according to an embodiment of the present disclosure. [Diagram 3]FIG. 3 is a top view of a display substrate according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is another top view of a display substrate according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is yet another top view of a display substrate according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a further top view of a display substrate according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a flow chart of a method for manufacturing a display substrate according to an embodiment of the present disclosure. [Figure 8A] FIG. 8A is a schematic diagram of a method for manufacturing a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 8B] FIG. 8B is a schematic diagram of the manufacturing method of the light-shielding layer and the second electrode according to the embodiment of the present disclosure. [Figure 8C] FIG. 8C is a schematic diagram of a manufacturing method of a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 8D] FIG. 8D is a schematic diagram of a manufacturing method of a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 8E] FIG. 8E is a schematic diagram of a manufacturing method of a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 8F] FIG. 8F is a schematic diagram of a manufacturing method of a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 8G] FIG. 8G is a schematic diagram of a manufacturing method of a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 8H] FIG. 8H is a schematic diagram of a manufacturing method of a light-shielding layer and a second electrode according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic diagram of step 100 in a manufacturing method for a display substrate according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram of step 200 in a manufacturing method for a display substrate according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic diagram of step 300 in a manufacturing method for a display substrate according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic diagram of step 400 in a method for manufacturing a display substrate according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic diagram of step 500 in a method for manufacturing a display substrate according to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic diagram of step 600 in a method for manufacturing a display substrate according to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic diagram of step 700 in a method for manufacturing a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Although the present disclosure describes several embodiments, the description is illustrative and not restrictive. And, it will be apparent to those skilled in the art that there may be many more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although several possible combinations of features are shown in the drawings and discussed in specific embodiments, several other combinations of the disclosed features are possible. Unless otherwise limited, any feature or element in any embodiment may be used in combination with any other feature or element in any other embodiment, or may be substituted for any other feature or element in any other embodiment.

[0029] The present disclosure is intended to include combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in the present disclosure may be combined with any conventional features or elements to form a unique technical solution limited by the scope of the claims. Any feature or element in any embodiment may be combined with features or elements from other technical solutions to form other unique technical solutions limited by the scope of the claims. It is therefore understood that any feature indicated and / or discussed in the present disclosure may be implemented independently or in any suitable combination. Therefore, the embodiments are not subject to any other limitations, except those imposed based on the appended claims and their equivalent substitutions. Various modifications and changes may be made within the scope of the appended claims.

[0030] Additionally, when describing representative embodiments, the specification may present a method and / or process in a particular sequence of steps. However, to the extent that the method or process does not depend on the particular order of steps described in the disclosure, the method or process is not limited to said particular order of steps. As one of ordinary skill in the art will appreciate, other order of steps are possible. Thus, the particular order of steps described in the specification should not be construed as limiting the scope of the claims. Additionally, claims to the method and / or process are not limited to performing those steps in the order written, and as one of ordinary skill in the art will readily appreciate, those orders may be varied and still fall within the spirit and scope of the embodiments of the present disclosure.

[0031] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning understood by those skilled in the art in the field to which the present disclosure belongs. The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, number or importance, but are merely used to distinguish different components. Similar terms such as "comprise" or "include" refer to the elements or members described after the term covering the elements or members listed before the term and their equivalents, and do not exclude other elements or members. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but also include electrical connections, whether direct or indirect connections. "Top", "bottom", "left", "right", etc. only refer to relative positional relationships, and if the absolute position of the objects being described changes, the relative positional relationships may change correspondingly.

[0032] In this embodiment, the display substrate includes a plurality of sub-pixels, each of which includes a driving circuit and a light-emitting element. Figure 1 is an equivalent circuit diagram of the driving circuit, which shows a 3T1C driving circuit. As shown in Figure 1, the driving circuit is electrically connected to the first grid line G1, the sense line Sense, the power cord VDD, the data line Data and the second grid line G2, and includes a switching transistor T1, a driving transistor T2, a sense transistor T3 and a storage capacitor Cst.

[0033] In one exemplary embodiment, a gate electrode of a switching transistor T1 in the driving circuit is connected to a first grid line G1, a second electrode of the switching transistor T1 is connected to a data line Data, a first electrode of the switching transistor T1 is connected to a node N1, a gate electrode of a driving transistor T2 is connected to the node N1, a second electrode of the driving transistor T2 is connected to a power supply code VDD, a first electrode of the driving transistor T2 is connected to a node N2, a gate electrode of a sense transistor T3 is connected to a second grid line G2, a second electrode of the sense transistor T3 is connected to a sense line Sense, a first electrode of the sense transistor T3 is connected to the node N2, an anode of a light-emitting element OLED is connected to the node N2, and a cathode of the light-emitting element OLED is connected to a power supply code VSS, and is configured to emit light of a corresponding brightness in response to a current of the first electrode of the driving transistor. When the driving circuit turns on the switching transistor T1 by the first grid line G1, the data voltage Vdata provided by the data line Data is stored in the storage capacitor Cst through the switching transistor T1, thereby generating a current to control the driving transistor T2 to drive the organic light emitting diode OLED to emit light; in addition, the sense transistor T3 can extract the threshold voltage Vth and mobility of the driving transistor T2 in response to the sense sequence, and the storage capacitor Cst is used to maintain the voltage difference between the node N1 and the node N2 within the light emission period of one frame.

[0034] In one exemplary embodiment, the first pole of any one of the transistors is one of the source / drain electrodes, and the second pole is the other of the source / drain electrodes.

[0035] Some embodiments of the present disclosure provide a display substrate. Fig. 2A is a cross-sectional view of the display substrate according to the embodiment of the present disclosure, Fig. 2B is another cross-sectional view of the display substrate according to the embodiment of the present disclosure, and Fig. 3 is a top view of the display substrate according to the embodiment of the present disclosure. As shown in Figs. 2A-2B and 3, the display substrate according to the embodiment of the present disclosure includes a substrate 10 and a plurality of sub-pixels disposed on the substrate 10, each sub-pixel having a light-emitting area AA and a non-light-emitting area NA, each sub-pixel is provided with a driving circuit, the driving circuit includes a storage capacitor Cst and a plurality of transistors, the plurality of transistors including a switching transistor T1, a driving transistor T2 and a sense transistor T3.

[0036] For each subpixel, the transistors are located in the non-light-emitting area NA, the storage capacitor Cst is a transparent capacitor, and the orthogonal projection of the storage capacitor Cst on the substrate 10 overlaps with the light-emitting area AA, the first electrode C1 of the storage capacitor Cst is disposed in the same layer as the active layers of the transistors and is disposed in a different layer from the source / drain electrodes of the transistors, and the second electrode C2 of the storage capacitor Cst is disposed on the side of the first electrode C1 close to the substrate 10. The first pole 23 of the driving transistor T2 is in direct contact with the second electrode C2 to realize electrical connection, and the first pole 43 of the sense transistor T3 is in direct contact with the second electrode C2 to realize electrical connection. As will be seen from the following description, the first pole 23 of the driving transistor T2 may be in direct contact with the second electrode C2 to be electrically connected, and the first pole 23 of the driving transistor T2 may be electrically connected to the second electrode C2 by the light-shielding layer 11, which is determined by the connection relationship between the light-shielding layer 11 and the second electrode C2. When the light-shielding layer 11 is disposed on the side of the second electrode C2 adjacent to the substrate 10, the first electrode 23 of the driving transistor T2 is in direct contact with and electrically connected to the second electrode C2, and when the second electrode C2 is disposed on the side of the light-shielding layer 11 adjacent to the substrate 10, the first electrode 23 of the driving transistor T2 is electrically connected to the second electrode C2 by the light-shielding layer. The first electrode 43 of the sense transistor T3 is similar to the second electrode C2, and a detailed description thereof will be omitted here.

[0037] In one exemplary embodiment, the sub-pixels on the substrate are arranged in an array, and Fig. 2A-2B and Fig. 3 take one sub-pixel as an example, and Fig. 2A and Fig. 2B are cross-sectional views taken at different angles.

[0038] In one exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate. Rigid substrates may be, but are not limited to, one or more of glass and foil metal. Flexible substrates may be, but are not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, aromatic polyester, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0039] In one exemplary embodiment, as shown in Figures 2A-2B and 3, the switching transistor T1 of the embodiment of the present disclosure comprises an active layer 31, a gate electrode 32, a first pole 33 and a second pole 34 disposed on a substrate, the drive transistor T2 comprises an active layer 21, a gate electrode 22, a first pole 23 and a second pole 24 disposed on a substrate, and the sense transistor T3 comprises an active layer 41, a gate electrode 42, a first pole 43 and a second pole 44 disposed on a substrate.

[0040] In one exemplary embodiment, the display substrate according to the embodiments of the present disclosure is a bottom-emission OLED display substrate.

[0041] The storage capacitor in the embodiment of the present disclosure is a transparent capacitor, which does not affect the light emission effect of the display substrate and can ensure smooth light emission.

[0042] In one exemplary embodiment, each subpixel further includes a light-emitting element, which may be an OLED.

[0043] A display substrate according to an embodiment of the present disclosure includes a substrate and a plurality of sub-pixels disposed on the substrate, each of the sub-pixels having a light-emitting region and a non-light-emitting region, and a driving circuit disposed on each of the sub-pixels. The driving circuit includes a storage capacitor and a plurality of transistors. The plurality of transistors include a switching transistor, a driving transistor and a sense transistor. For each sub-pixel, the plurality of transistors are located in the non-light-emitting region, the storage capacitor is a transparent capacitor, and there is an overlapping region between the orthogonal projection of the storage capacitor on the substrate and the light-emitting region, a first electrode of the storage capacitor is disposed in the same layer as the active layers of the plurality of transistors and is disposed in a different layer from the source / drain electrodes of the plurality of transistors, and a second electrode of the storage capacitor is disposed on the side of the first electrode adjacent to the substrate. The first pole of the driving transistor is in direct contact with the second electrode, and the first pole of the sense transistor is in direct contact with the second electrode. In the present disclosure, by setting an overlapping area between the orthogonal projection of the transparent storage capacitor on the substrate and the light-emitting area, the aperture ratio can be ensured and the area ratio occupied by the non-light-emitting area of ​​the storage capacitor can be significantly reduced, thereby reducing the area occupied by each sub-pixel and achieving a high PPI for the display substrate.

[0044] In one exemplary embodiment, as shown in FIGS. 2A-2B and 3, for each transistor, there is an overlapping region between the orthogonal projection of the active layer of the transistor on the substrate and the orthogonal projection of the gate electrode of the transistor on the substrate.

[0045] In one exemplary embodiment, as shown in Figures 2A-2B, the display substrate according to the embodiment of the present disclosure further includes a light-shielding layer 11 and a buffer layer 12 arranged on the side of the transistor active layer adjacent to the substrate 10, and the light-shielding layer 11 and the second electrode C2 are arranged on the side of the buffer layer 12 adjacent to the substrate 10.

[0046] In one exemplary embodiment, the orthogonal projection of the second electrode C2 on the substrate 10 covers the orthogonal projection of the light-shielding layer 11 on the substrate 10, and the surface of the light-shielding layer 11 adjacent to the second electrode C2 is in complete contact with the second electrode C2.

[0047] In one exemplary embodiment, the light-shielding layer 11 is disposed on the side of the second electrode C2 that is closer to the substrate 10, or the second electrode C2 is disposed on the side of the light-shielding layer 11 that is closer to the substrate 10. Figures 2A to 2B and 3 all illustrate the case where the light-shielding layer 11 is disposed on the side of the second electrode C2 that is closer to the substrate 10.

[0048] When the second electrode C2 is disposed on the side of the light-shielding layer 11 closest to the substrate 10, the first electrode 23 of the driving transistor T2 is electrically connected to the second electrode C2 by the conductive light-shielding layer 11, and the first electrode 43 of the sense transistor T3 is electrically connected to the second electrode C2 by the light-shielding layer 11.

[0049] In the embodiment of the present disclosure, the surface of the light-shielding layer 11 adjacent to the second electrode C2 is in full contact with the second electrode C2, thereby avoiding the need to install an insulating layer between the light-shielding layer and the second electrode, which not only reduces the number of layers and thickness of the display substrate, but also reduces the number of masks used, simplifying the manufacturing process, and reducing the manufacturing cost of the display substrate.

[0050] In one exemplary embodiment, the orthogonal projection of the light-shielding layer 11 on the substrate 10 covers the orthogonal projection on the substrate 10 of the channel region A1 of the active layer 21 of the drive transistor T2.

[0051] In one exemplary embodiment, the manufacturing material of the light-shielding layer 11 is a metal, such as silver, aluminum, etc., and the embodiments of the present disclosure are not limited thereto.

[0052] In one exemplary embodiment, as shown in FIGS. 2A-2B, the display substrate according to the embodiment of the present disclosure further includes an interlayer insulating layer 14 disposed between the source / drain electrodes of the transistor and the active layer of the transistor.

[0053] In one exemplary embodiment, as shown in Figures 2A-2B and 3, the buffer layer 12 in a display substrate according to an embodiment of the present disclosure has a first via V1 and a second via V2 that expose the second electrode, and the interlayer insulating layer 14 has a third via V3 that exposes the first via V1 and a fourth via V4 that exposes the second via V2.

[0054] In one exemplary embodiment, the first pole 23 of the drive transistor T2 is connected to the second electrode C2 by a first via V1 and a third via V3, and the first pole 43 of the sense transistor T3 is connected to the second electrode C2 by a second via V2 and a fourth via V4.

[0055] In one exemplary embodiment, as shown in FIGS. 2A-2B and 3, vias are further provided in the interlayer insulating layer 14 to expose active layers of the multiple transistors, and the source / drain electrodes of the multiple transistors are connected to the active layers by the vias.

[0056] In an exemplary embodiment, Fig. 4 is another top view of a display substrate according to an embodiment of the present disclosure. As shown in Fig. 4, the display substrate according to the embodiment of the present disclosure further includes a plurality of rows of grid lines and a plurality of columns of data lines disposed on the substrate, each sub-pixel is defined by the intersection of the grid lines and the data lines, and the grid lines include a first grid line G1 and a second grid line G2. Fig. 4 takes four sub-pixels as an example.

[0057] 2A is a cross-sectional view taken along the line AA in FIG. 4, and FIG. 2B is a cross-sectional view taken along the line BB in FIG.

[0058] In one exemplary embodiment, the first grid line G1 and the second grid line G2 are disposed in the same layer as the gate electrodes of the transistors, and the data line Data is disposed in the same layer as the source / drain electrodes of the transistors.

[0059] In one exemplary embodiment, for each subpixel, the first electrode C1 is connected to the first pole 33 of the switching transistor T1 and the gate electrode 22 of the drive transistor T2, and the second electrode C2 is connected to the first pole 23 of the drive transistor T2 and the first pole 43 of the sense transistor T3, respectively. The gate electrode of the switching transistor T1 is connected to a first grid line G1 of the grid lines corresponding to the subpixel, the second pole 34 of the switching transistor T1 is connected to a data line Data of the subpixel, and the gate electrode of the sense transistor T3 is connected to a second grid line G2 of the grid lines corresponding to the subpixel.

[0060] In one exemplary embodiment, as shown in FIG. 4, for each sub-pixel, the light-emitting area AA is disposed along the extending direction of the data line Data and has a first side and a second side disposed opposite each other.

[0061] In one exemplary embodiment, as can be seen from FIGS. 2A-2B, the sense transistor T3 and the second grid line G2 are all located on a first side of the light-emitting area AA, and the switching transistor T1, the driving transistor T2 and the first grid line G1 are all located on a second side of the light-emitting area AA.

[0062] In one exemplary embodiment, as shown in FIG. 4, the display substrate further includes a power supply line VDD and a sense line Sense arranged in the same layer as the data line Data, and each pixel includes four sub-pixels arranged along the extending direction of the grid line, and each pixel corresponds to two columns of power supplies and one column of sense lines.

[0063] In one exemplary embodiment, the pixel structures of the second sub-pixel and the third sub-pixel are symmetrically disposed, and the pixel structures of the first sub-pixel and the fourth sub-pixel are symmetrically disposed.

[0064] For each pixel, the sense line Sense corresponding to the pixel is located between the second sub-pixel P2 and the third sub-pixel P3, one row of power cords VDD corresponding to the pixel is located on the side of the first sub-pixel P1 away from the second sub-pixel P2, and another row of power cords VDD corresponding to the pixel is located on the side of the fourth sub-pixel P4 away from the third sub-pixel P3.

[0065] The data line Data corresponding to the first subpixel P1 is located on the side of the first subpixel P1 adjacent to the second subpixel P2, the data line corresponding to the second subpixel P2 is located on the side of the second subpixel P2 adjacent to the first subpixel P1, the data line corresponding to the third subpixel P3 is located on the side of the third subpixel P3 adjacent to the fourth subpixel P4, and the data line corresponding to the fourth subpixel P4 is located on the side of the fourth subpixel P4 adjacent to the third subpixel P3.

[0066] In one exemplary embodiment, as shown in FIG. 4 , the display substrate according to the embodiment of the present disclosure further includes a power supply connection line VL arranged in the same layer as the gate electrode of the transistor, and a sense connection line SL arranged in the same layer as the light-shielding layer 11, and each pixel corresponds to two power supply connection lines arranged along the extension direction of the grid line and two sense connection lines SL arranged along the extension direction of the grid line, and the power supply connection line VL corresponds to a power cord VDD, the power supply connection line VL is connected to the corresponding power cord, and the two sense connection lines SL are connected to the sense line Sense.

[0067] In one exemplary embodiment, the second pole of the drive transistor of the second subpixel P2 is connected to one power supply connection line VL, the second pole of the drive transistor of the third subpixel P3 is connected to the other power supply connection line VL, the second pole of the sense transistor of the first subpixel P1 is connected to one sense connection line SL, and the second pole of the sense transistor of the fourth subpixel P4 is connected to the other sense connection line SL.

[0068] In one exemplary embodiment, the sense connecting line SL may have a single-layer structure or a double-layer structure. When the sense connecting line SL has a single-layer structure, the sense connecting line is disposed in the same layer as the light-shielding layer or the second electrode, and when the sense connecting line SL has a double-layer structure, the first layer of the sense connecting line is disposed in the same layer as the light-shielding layer, and the second layer is disposed in the same layer as the second electrode. Figure 4 shows an example in which the sense connecting line is disposed in the same layer as the light-shielding layer.

[0069] In one exemplary embodiment, as shown in FIGS. 2A-2B, the display substrate according to the embodiment of the present disclosure further comprises a gate insulating layer 13 disposed between the gate electrode of the transistor and the active layer of the transistor.

[0070] The orthogonal projection of the gate insulating layer 13 on the substrate 10 overlaps with the orthogonal projection of the gate electrode of the transistor on the substrate 10 .

[0071] In one exemplary embodiment, the fabrication materials of the buffer layer 12, the gate insulating layer 13 and the interlayer insulating layer 14 are silicon oxide, silicon nitride, or a composite of silicon oxide and silicon nitride, and the embodiments of the present disclosure are not limited thereto.

[0072] In one exemplary embodiment, as shown in FIG. 3, for each subpixel, a fifth via V5 is further provided in the buffer layer 12, and the fifth via V5 exposes the sense connection line SL, and a sixth via V6 is further provided in the interlayer insulating layer 14, exposing the fifth via V5, and the second pole 44 of the sense transistor T3 is connected to the sense connection line SL by the fifth via V5 and the sixth via V6.

[0073] In one exemplary embodiment, the manufacturing material of the first electrode C1 includes a transparent metal oxide, such as Indium Gallium Zinc Oxide (abbreviated as IGZO), and the embodiments of the present disclosure are not limited thereto.

[0074] In one exemplary embodiment, the manufacturing material of the second electrode C2 is a transparent conductive material, which includes indium tin oxide (abbreviated as ITO), zinc tin oxide, etc., and the embodiments of the present disclosure are not limited thereto.

[0075] In one exemplary embodiment, Fig. 5 is another top view of the display substrate according to an embodiment of the present disclosure, and Fig. 6 is a further top view of the display substrate according to an embodiment of the present disclosure. As shown in Figs. 2A to 6, each sub-pixel further includes a light-emitting element and an optical filter 50 having the same color as the sub-pixel. The light-emitting element includes an anode 61, an organic light-emitting layer 62, and a cathode 63 arranged in sequence, the anode 61 is connected to the first electrode 43 of the sense transistor T3, the anode 61 is a transmissive electrode, and the cathode 63 is a reflective electrode.

[0076] In one exemplary embodiment, the material of the anode 61 may be a transparent conductive material, such as indium tin oxide (ITO), zinc tin oxide, etc., although the embodiments of the present disclosure are not limited thereto.

[0077] In one exemplary embodiment, the material of manufacture of the cathode 63 is a metal, such as silver, aluminum, etc., although the embodiments of the present disclosure are not limited thereto.

[0078] In one exemplary embodiment, there is an overlapping area between the orthogonal projection of the light-emitting element on the substrate 10 and the light-emitting area AA, the optical filter 50 is located in the light-emitting area AA and is installed on the side of the light-emitting element adjacent to the substrate 10, and the orthogonal projection of the anode 61 on the substrate 10 covers the orthogonal projection of the optical filter 50 on the substrate 10.

[0079] In one exemplary embodiment, as shown in FIGS. 2A-2B , the display substrate according to the embodiment of the present disclosure further includes a passivation layer 15 disposed on a side of the source / drain electrodes of the transistors facing away from the substrate 10, a planar layer 16 disposed between the anode 61 and the optical filter 50, and a pixel definition layer 17 disposed on a side of the planar layer 16 facing away from the substrate 10 and for defining sub-pixel regions.

[0080] In one exemplary embodiment, referring to Figures 2A-2B and 5, the passivation layer 15 is disposed on the side of the optical filter 50 closest to the substrate 10, the planar layer 16 is disposed between the light-emitting element and the optical filter 50, the passivation layer 15 is provided with a seventh via V7 exposing the first electrode 43 of the sense transistor T3, and the planar layer 16 is provided with an eighth via V8 exposing the seventh via V7.

[0081] The anode 61 is connected to the first electrode 43 of the sense transistor T3 by the seventh via V7 and the eighth via V8. The orthogonal projection of the eighth via V8 on the substrate 10 incompletely overlaps with the orthogonal projection of the fourth via V4 on the substrate 10.

[0082] In one exemplary embodiment, as shown in Figures 2A-2B, the display substrate according to the embodiment of the present disclosure further includes a support portion 70 installed on the side of the light-emitting element facing away from the substrate 10, and a cover plate 80 installed on the side of the support portion 70 facing away from the substrate 10.

[0083] In one exemplary embodiment, the cover plate 80 is used to protect the light emitting element. The cover plate 80 may be a glass cover plate.

[0084] Based on the same inventive concept, some embodiments of the present disclosure further provide a method for manufacturing a display substrate, which can be used for manufacturing a display substrate. Figure 7 is a flow chart of the method for manufacturing a display substrate according to an embodiment of the present disclosure. As shown in Figure 7, the method for manufacturing a display substrate according to an embodiment of the present disclosure specifically includes the following steps:

[0085] Step S1, a substrate is provided.

[0086] In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and foil metal. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, aromatic polyester, polyimide, polyvinyl chloride, polyethylene, textile fiber.

[0087] Step S2: forming a plurality of sub-pixels on a substrate.

[0088] In one exemplary embodiment, the sub-pixels on the substrate are arranged in an array, and Figures 2A-2B take one sub-pixel as an example.

[0089] In one exemplary embodiment, each subpixel comprises an emissive region and a non-emissive region, and a driving circuit is provided for each subpixel, the driving circuit comprising a storage capacitor and a plurality of transistors, the plurality of transistors including a switching transistor, a driving transistor and a sense transistor.

[0090] For each subpixel, the plurality of transistors are located in a non-light-emitting region, the storage capacitor is a transparent capacitor, and there is an overlapping region between the orthogonal projection of the storage capacitor on the substrate and the light-emitting region, a first electrode of the storage capacitor is disposed in the same layer as the active layers of the plurality of transistors, and a second electrode of the storage capacitor is located on the side of the first electrode adjacent to the substrate.

[0091] The first electrode of the drive transistor is in direct contact with the second electrode, and the first electrode of the sense transistor is in direct contact with the second electrode.

[0092] The display substrate is the display substrate according to the above embodiment, and the implementation principle and effect are similar, so a detailed description thereof will be omitted here.

[0093] In one exemplary embodiment, the display substrate further comprises grid lines, data lines, power lines and sense lines, the grid lines including first grid lines and second grid lines, and step S2 specifically includes: forming a light-shielding layer and a second electrode on a substrate; forming active layers and first electrodes of a plurality of transistors on the light-shielding layer and the second electrode; forming gate electrodes of the plurality of transistors, first grid lines and second grid lines on the active layers and first electrodes of the plurality of transistors; forming data lines, power cords, sense lines and source / drain electrodes of the plurality of transistors on the gate electrodes of the transistors, the first grid lines and the second grid lines; and sequentially forming optical filters and light-emitting elements on the data lines, power cords, sense lines and source / drain electrodes of the plurality of transistors.

[0094] In one exemplary embodiment, forming the light-shielding layer and the second electrode on the substrate includes sequentially forming the light-shielding layer and the second electrode on the substrate, or sequentially forming the second electrode and the light-shielding layer on the substrate, or simultaneously forming the second electrode and the light-shielding layer on the substrate.

[0095] In one exemplary embodiment, sequentially forming a light-shielding layer and a second electrode on a substrate includes forming a light-shielding layer on the substrate using a first mask and forming the second electrode on the light-shielding layer using a second mask.

[0096] In one exemplary embodiment, sequentially forming the second electrode and the light-shielding layer on the substrate includes forming the second electrode on the substrate by a patterning process using a second mask, and forming the light-shielding layer on the second electrode using a first mask.

[0097] In one exemplary embodiment, simultaneously forming the second electrode and the light-shielding layer on the substrate includes sequentially depositing a light-shielding thin film and a transparent conductive thin film on the substrate, and simultaneously forming the second electrode and the light-shielding layer using a half-tone mask.

[0098] The patterning process includes processes such as photoresist coating, exposing, developing, etching and photoresist stripping.

[0099] Hereinafter, the manufacturing process of the light-shielding layer and the second electrode will be further described with reference to FIGS. 8A to 8H, taking the case where the light-shielding layer is disposed on the side of the second electrode adjacent to the substrate as an example, and the process includes the following steps.

[0100] Step 110, as shown in FIG. 8A, deposit a light-shielding thin film 110 on a substrate, coat the light-shielding thin film 110 with a photoresist 101, and expose the photoresist through a first mask M1.

[0101] Step 120 develops the photoresist 101, as shown in FIG. 8B.

[0102] Step 130, as shown in FIG. 8C, etches the light-shielding thin film that is not covered with the photoresist 101.

[0103] Step 140, as shown in FIG. 8D, strip the photoresist 101 to form the light-shielding layer 11.

[0104] Step 150, as shown in FIG. 8E, deposit a transparent conductive thin film 120 on the light-shielding layer 11, coat the transparent conductive thin film 120 with a photoresist 101, and expose the photoresist through a second mask M2.

[0105] Step 160 develops the photoresist 101, as shown in FIG. 8F.

[0106] Step 170, as shown in FIG. 8G, etches the transparent conductive thin film that is not covered by photoresist 101.

[0107] In step 180, as shown in FIG. 8H, the photoresist 101 is stripped to form the second electrode C2.

[0108] In one exemplary embodiment, forming active layers and first electrodes of a plurality of transistors on the light shielding layer and the second electrode, forming gate electrodes, first grid lines and second grid lines of the plurality of transistors on the active layers and the first electrodes of the plurality of transistors, and forming data lines, power cords, sense lines and source / drain electrodes of the plurality of transistors on the gate electrodes, first grid lines and second grid lines of the transistors includes: forming a buffer layer having a first via, a second via and a fifth via on the light shielding layer and the second electrode by a patterning process; forming active layers and first electrodes of the plurality of transistors in the buffer layer by the same manufacturing process; forming gate electrodes, first grid lines and second grid lines of the plurality of transistors on the active layers and the first electrodes of the plurality of transistors; forming an interlayer insulating layer having a third via, a fourth via and a sixth via on the gate electrodes, first grid lines and second grid lines of the transistors by a patterning process; and forming the data lines, power cords, sense lines and source / drain electrodes of the plurality of transistors in the interlayer insulating layer.

[0109] In one exemplary embodiment, the first and second vias expose the second electrode, the fifth via exposes the sense connection line, the third via exposes the first via, the fourth via exposes the second via, and the sixth via exposes the fifth via.

[0110] In another embodiment, forming active layers and first electrodes of a plurality of transistors on the light shielding layer and the second electrode, forming gate electrodes, first grid lines and second grid lines of the plurality of transistors on the active layers and the first electrodes of the plurality of transistors, and forming data lines, power cords, sense lines and source / drain electrodes of the plurality of transistors on the gate electrodes, first grid lines and second grid lines of the transistors includes: forming a first insulating thin film on the light shielding layer and the second electrode; forming active layers and first electrodes of the plurality of transistors on the first insulating thin film by the same manufacturing process; forming gate electrodes, first grid lines and second grid lines of the plurality of transistors on the active layers and the first electrodes of the plurality of transistors; forming a second insulating thin film on the gate electrodes, first grid lines and second grid lines of the transistors; and processing the first insulating thin film and the second insulating thin film using a patterning process to form a buffer layer having a first via, a second via and a fifth via, and an interlayer insulating layer having a third via, a fourth via and a sixth via.

[0111] Sequentially forming an optical filter and a light-emitting element on the data lines, the power cords, the sense lines, and the source / drain electrodes of the plurality of transistors includes forming a passivation layer having a seventh via on the data lines, the power cords, the sense lines, and the source / drain electrodes of the plurality of transistors, the seventh via exposing a first electrode of the sense transistor; sequentially forming an optical filter and a flat layer having an eighth via on the passivation layer, the eighth via exposing the seventh via; and forming a light-emitting element on the flat layer.

[0112] The above embodiment can simplify the manufacturing process of the display substrate.

[0113] Taking the case where there are four sub-pixels, the sense connecting line has a single-layer structure and is arranged in the same layer as the light-shielding layer, and the light-shielding layer is arranged on the side of the second electrode close to the substrate as an example, the manufacturing method of the display substrate according to the embodiment of the present disclosure will be further described below with reference to Figures 9 to 15, and the method includes the following steps:

[0114] In step 100, as shown in FIG. 9, a light-shielding layer 11 and a sense connection line SL are formed on a substrate 10.

[0115] In step 200, as shown in FIG. 10, a second electrode C2 and a buffer layer (not shown) are sequentially formed on the light-shielding layer 11 and the sense connection line SL.

[0116] In step 300, as shown in FIG. 11, a first electrode C1, an active layer 31 of the switching transistor, an active layer 21 of the driving transistor T2 and an active layer 41 of the sense transistor are formed on the buffer layer.

[0117] Step 400, as shown in FIG. 12, a gate insulating layer is formed on the active layer 31 of the switching transistor, the active layer 21 of the driving transistor T2, and the active layer 41 of the sense transistor, and the gate electrode 32 of the switching transistor, the gate electrode 22 of the driving transistor, the gate electrode 42 of the sense transistor, the first grid line G1, the second grid line G2, and the power supply connecting line VL are formed in the gate insulating layer, and an interlayer insulating layer is formed on the gate electrodes of the transistors, the first grid line, the second grid line, and the power supply connecting line.

[0118] In one exemplary embodiment, the interlayer insulating layer includes a third via V3, a fourth via V4, and a sixth via V6, and the buffer layer includes a first via V1, a second via V2, and a fifth via V5.

[0119] Step 500, as shown in FIG. 13, forms a data line Data, a power supply code VDD, a sense line Sense, a first pole 33 of the switching transistor, a second pole 34 of the switching transistor, a first pole 23 of the driving transistor, a second pole 24 of the driving transistor, a first pole 43 of the sense transistor and a second pole 44 of the sense transistor on the interlayer insulating layer.

[0120] Step 600, as shown in FIG. 14, forms a passivation layer with a seventh via in the data lines, power cords, sense lines and source / drain electrodes of a plurality of transistors, forms an optical filter 50 in the passivation layer, and forms a planar layer with an eighth via V8 in the optical filter.

[0121] Step 700, as shown in FIG. 15, forms an anode 61 on the planar layer.

[0122] In step 800, a pixel definition layer, an organic light-emitting layer and a cathode are sequentially formed on the anode, and a support and a cover plate are sequentially provided on the cathode.

[0123] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device including a display substrate.

[0124] In one exemplary embodiment, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a car navigation system, etc. Other components essential to the display device are well known to those skilled in the art, and detailed descriptions thereof are omitted here and should not be construed as limiting the present disclosure. The implementation of the display device will be described in detail in the above. display board The embodiment described above may be referred to, and detailed description of overlapping parts will be omitted.

[0125] The display substrate may be the display substrate according to any of the above embodiments, and the realization principles and realization effects thereof are the same or similar, so detailed descriptions thereof are omitted here.

[0126] The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0127] For clarity, the thickness and size of layers or microstructures are exaggerated in the figures to illustrate the embodiments of the present disclosure. It is understood that when an element such as a layer, film, region or substrate is referred to as being located "on" or "under" another element, the element may be located "directly" on or "under" the other element, or there may be intermediate elements.

[0128] The above are the embodiments disclosed in the present disclosure, but the above contents are merely embodiments used to facilitate understanding of the present disclosure, and are not intended to limit the present disclosure. Those skilled in the art can make any modifications or changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present disclosure should still conform to the scope defined by the appended claims. [Explanation of symbols]

[0129] 10 Substrate 11 Light blocking layer 12 Buffer layer 13 Gate insulating layer 14 Interlayer insulation layer 15 Passivation layer 16 flat layer 17 Pixel Definition Layer 23 First pole of drive transistor T2 21 Active layer of drive transistor T2 22 Gate electrode of drive transistor T2 23 First pole of drive transistor T2 24 Second pole of drive transistor T2 31 Active layer of switching transistor T1 32 Gate electrode of switching transistor T1 33 First pole of switching transistor T1 34 Second pole of switching transistor T1 41 Active layer of sense transistor T3 42 Gate electrode of sense transistor T3 43 First pole of sense transistor T3 44 Second pole of sense transistor T3 50 Optical Filters 61 Anode 62 Organic light-emitting layer 63 Cathode 70 Support part 80 Cover Plate AA Light Emitting Area NA Non-luminous area C1 First electrode of storage capacitor Cst C2 Second electrode of storage capacitor Cst V1 First via V2 Second via V3 3rd via V4 4th via V5 5th via V6 6th via V7 7th via V8 8th via G1 First grid line G2 Second grid line Data Data line VDD Power cord Sense line P1 First sub-pixel P2 Second sub-pixel P3 Third sub-pixel P4 4th sub-pixel VL Power supply connection line SL Sense connection wire 101 Photoresist 110 Light-shielding thin film 120 Transparent conductive thin film M1 1st Mask M2 2nd Mask

Claims

1. A display substrate, comprising: a substrate; and a plurality of sub-pixels disposed on the substrate, each sub-pixel having a light-emitting region and a non-light-emitting region; each sub-pixel is provided with a driving circuit, the driving circuit comprising a storage capacitor and a plurality of transistors, the plurality of transistors including a switching transistor, a driving transistor and a sense transistor; For each subpixel, the plurality of transistors are located in the non-light-emitting region, the storage capacitor is a transparent capacitor, and a positive projection of the storage capacitor on the substrate and the light-emitting region have an overlapping region, a first electrode of the storage capacitor is disposed in the same layer as active layers of the plurality of transistors and in a different layer from source / drain electrodes of the plurality of transistors, and a second electrode of the storage capacitor is disposed on a side of the first electrode close to the substrate; a first electrode of the drive transistor electrically connected to the second electrode, and a first electrode of the sense transistor electrically connected to the second electrode; The display substrate further includes a plurality of rows of grid lines and a plurality of columns of data lines disposed on the substrate, each sub-pixel is defined by an intersection of the grid lines and the data lines, the plurality of sub-pixels respectively correspond to the plurality of rows of grid lines and the plurality of columns of data lines in a one-to-one relationship, and the plurality of rows of grid lines include first grid lines and second grid lines; For each sub-pixel, the non-light-emitting region includes a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region and the second non-light-emitting region are located on both sides of the light-emitting region and are arranged along an extending direction of the data lines of the plurality of columns; the sense transistor and the second grid line are all located in the first non-light-emitting area, and the switching transistor, the driving transistor and the first grid line are all located in the second non-light-emitting area.

2. the display substrate further includes a buffer layer and a light-shielding layer disposed on a side of the active layers of the plurality of transistors adjacent to the substrate, the light-shielding layer and the second electrode being disposed on a side of the buffer layer adjacent to the substrate; 2. The display substrate of claim 1, wherein the orthogonal projection of the second electrode on the substrate covers the orthogonal projection of the light-shielding layer on the substrate, and the surface of the light-shielding layer adjacent to the second electrode is in complete contact with the second electrode.

3. The display substrate according to claim 2 , wherein the light-shielding layer is disposed on a side of the second electrode that is closer to the substrate, or the second electrode is disposed on a side of the light-shielding layer that is closer to the substrate.

4. the display substrate further includes an interlayer insulating layer disposed between source / drain electrodes of the transistors and active layers of the transistors; the buffer layer includes a first via and a second via that expose the second electrode, the interlayer insulating layer includes a third via that exposes the first via and a fourth via that exposes the second via, The display substrate of claim 3 , wherein the first pole of the driving transistor is connected to the second electrode by the first via and the third via, and the first pole of the sense transistor is connected to the second electrode by the second via and the fourth via.

5. A display substrate as described in claim 4, wherein the first grid line and the second grid line are arranged in the same layer as the gate electrodes of the plurality of transistors, and the plurality of columns of data lines are arranged in the same layer as the source / drain electrodes of the plurality of transistors.

6. For each sub-pixel, the first electrode is respectively connected to a first pole of the switching transistor and a gate electrode of the driving transistor; 6. The display substrate of claim 5, wherein a gate electrode of the switching transistor is connected to a first grid line among the grid lines corresponding to the subpixel, a second electrode of the switching transistor is connected to a data line corresponding to the subpixel, and a gate electrode of the sense transistor is connected to a second grid line among the grid lines corresponding to the subpixel.

7. the display substrate further includes power lines and sense lines arranged in the same layer as the data lines, each pixel includes four sub-pixels arranged along an extending direction of a grid line, each pixel corresponds to two power lines and one sense line, and the four sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel; For each pixel, a sense line corresponding to the pixel is located between the second sub-pixel and the third sub-pixel, one row of power cords corresponding to the pixel is located on a side of the first sub-pixel away from the second sub-pixel, and another row of power cords corresponding to the pixel is located on a side of the fourth sub-pixel away from the third sub-pixel; a data line corresponding to the first sub-pixel is located on a side of the first sub-pixel adjacent to the second sub-pixel, a data line corresponding to the second sub-pixel is located on a side of the second sub-pixel adjacent to the first sub-pixel, a data line corresponding to the third sub-pixel is located on a side of the third sub-pixel adjacent to the fourth sub-pixel, and a data line corresponding to the fourth sub-pixel is located on a side of the fourth sub-pixel adjacent to the third sub-pixel, the display substrate further includes power supply connection lines disposed in the same layer as the gate electrodes of the plurality of transistors, and sense connection lines disposed in the same layer as the light-shielding layer, each pixel corresponds to two power supply connection lines disposed along the extension direction of the grid lines and two sense connection lines disposed along the extension direction of the grid lines, the power supply connection lines respectively correspond to power cords, the power supply connection lines are connected to the corresponding power cords, and the two sense connection lines are connected to sense lines; A second electrode of the driving transistor of the second sub-pixel is connected to one of the power supply connecting lines; A second electrode of the driving transistor of the third sub-pixel is connected to the other power supply connecting line, A second electrode of the sense transistor of the first sub-pixel is connected to one of the sense connection lines; The display substrate according to claim 5 , wherein the second electrode of the sense transistor of the fourth sub-pixel is connected to the other sense connecting line.

8. a fifth via is further provided in the buffer layer to expose the sense connection line, and a sixth via is further provided in the interlayer insulating layer to expose the fifth via; The display substrate of claim 7 , wherein the second electrode of the sense transistor is connected to the sense connection line by the fifth via and the sixth via.

9. the display substrate further includes a gate insulating layer disposed between the gate electrodes of the transistors and the active layers of the transistors; The display substrate of claim 8 , wherein an orthogonal projection of the gate insulating layer on the substrate overlaps with an orthogonal projection of the gate electrodes of the plurality of transistors on the substrate.

10. The display substrate of claim 2 , wherein a material for the first electrode comprises a transparent metal oxide, and a material for the second electrode comprises a transparent conductive material.

11. Each sub-pixel further includes a light-emitting element and an optical filter having the same color as the sub-pixel, the light-emitting element includes an anode, an organic light-emitting layer, and a cathode, which are sequentially arranged, the anode being connected to the first electrode of the sense transistor, the anode being a transmissive electrode, and the cathode being a reflective electrode; 10. The display substrate of claim 9, wherein an overlapping area exists between the orthogonal projection of the light-emitting element on the substrate and the light-emitting area, the optical filter is located in the light-emitting area and is installed on a side of the light-emitting element close to the substrate, and the orthogonal projection of the anode on the substrate covers the orthogonal projection of the optical filter on the substrate.

12. The display substrate further comprises a passivation layer and a planarization layer disposed on the source / drain electrodes of the plurality of transistors on the side away from the substrate; the passivation layer is disposed on a side of the optical filter adjacent to the substrate, the planar layer is disposed between the light emitting element and the optical filter, the passivation layer is provided with a seventh via exposing the first electrode of the sense transistor, and the planar layer is provided with an eighth via exposing the seventh via; the anode is connected to the first electrode of the sense transistor by the seventh via and the eighth via; The display substrate of claim 11 , wherein an orthogonal projection of the eighth via on the substrate incompletely overlaps with an orthogonal projection of the fourth via on the substrate.

13. A display device comprising the display substrate according to any one of claims 1 to 12.

14. A method for manufacturing a display substrate used to manufacture the display substrate according to any one of claims 1 to 12, comprising the steps of: Providing a substrate; forming a plurality of sub-pixels on the substrate, each sub-pixel having a light-emitting region and a non-light-emitting region; each sub-pixel is provided with a driving circuit, the driving circuit including a storage capacitor and a plurality of transistors, the plurality of transistors including a switching transistor, a driving transistor and a sense transistor; For each subpixel, the plurality of transistors are located in the non-light-emitting region, the storage capacitor is a transparent capacitor, and a positive projection of the storage capacitor on the substrate and the light-emitting region have an overlapping region, a first electrode of the storage capacitor is disposed in the same layer as active layers of the plurality of transistors and in a different layer from source / drain electrodes of the plurality of transistors, and a second electrode of the storage capacitor is disposed on a side of the first electrode close to the substrate; a first electrode of the driving transistor electrically connected to the second electrode, and a first electrode of the sense transistor electrically connected to the second electrode.

15. The display substrate further comprises grid lines, data lines, power lines and sense lines, the grid lines including first grid lines and second grid lines, and the step of forming a plurality of sub-pixels on the substrate includes: forming a light-shielding layer and the second electrode on the substrate; forming active layers and the first electrodes of the plurality of transistors on the light-shielding layer and the second electrodes; forming gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines on active layers of the plurality of transistors and the first electrodes; forming gate electrodes of the transistors, the data lines, the power cords, the sense lines, and source / drain electrodes of the transistors on the first grid lines and the second grid lines; 15. The method of claim 14, further comprising: sequentially forming optical filters and light emitting elements on the data lines, the power cords, the sense lines and source / drain electrodes of the plurality of transistors.

16. The step of forming a light-shielding layer and the second electrode on the substrate includes:

16. The method of claim 15, comprising sequentially forming the light-shielding layer and the second electrode on the substrate, or sequentially forming the second electrode and the light-shielding layer on the substrate, or simultaneously forming the second electrode and the light-shielding layer on the substrate.

17. forming active layers and first electrodes of the transistors on the light-shielding layer and the second electrode, forming gate electrodes of the transistors, first grid lines and second grid lines on the active layers and first electrodes of the transistors, and forming data lines, power lines, sense lines and source / drain electrodes of the transistors on the gate electrodes, first grid lines and second grid lines of the transistors, forming a buffer layer having a first via, a second via and a fifth via in the light-shielding layer and the second electrode, the first via and the second via exposing the second electrode, and the fifth via exposing a sense connection line; forming the active layers and the first electrodes of the plurality of transistors in the buffer layer by a same manufacturing process; forming gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines on active layers of the plurality of transistors and the first electrodes; forming an interlayer insulating layer including a third via, a fourth via, and a sixth via on the gate electrodes of the plurality of transistors, the first grid line, and the second grid line, the third via exposing the first via, the fourth via exposing the second via, and the sixth via exposing the fifth via; forming the data lines, the power cords, the sense lines and source / drain electrodes of the plurality of transistors on the interlayer insulating layer; or forming a first insulating thin film on the light-shielding layer and the second electrode; forming active layers and the first electrodes of the plurality of transistors in a first insulating thin film by the same manufacturing process; forming gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines on active layers of the plurality of transistors and the first electrodes; forming a second insulating thin film on the gate electrodes of the plurality of transistors, the first grid lines, and the second grid lines; 17. The method of claim 16, further comprising: treating the first insulating thin film and the second insulating thin film using a patterning process to form a buffer layer comprising a first via, a second via, and a fifth via, and an interlayer insulating layer comprising a third via, a fourth via, and a sixth via.

18. The step of sequentially forming an optical filter and a light emitting element on the data line, the power cord, the sense line and the source / drain electrodes of the plurality of transistors includes: forming a passivation layer having a seventh via on the data line, the power cord, the sense line and the source / drain electrodes of the plurality of transistors, the seventh via exposing the first pole of the sense transistor; forming the optical filter and a planar layer in the passivation layer, the planar layer having an eighth via, the eighth via exposing the seventh via; and forming a light emitting element in the planarization layer.

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