High aspect ratio, n-type source or drain structure with steep dopant profile

Abstract

To provide integrated circuit structures having source or drain structures with abrupt dopant profiles.SOLUTION: An integrated circuit structure includes a vertical arrangement of horizontal nanowires 166B. A gate stack is around the vertical arrangement of horizontal nanowires 166B. A first epitaxial source or drain structure 168B is at a first end of the vertical arrangement of horizontal nanowires 166B. A second epitaxial source or drain structure 168B is at a second end of the vertical arrangement of horizontal nanowires 166B. The first and second epitaxial source or drain structures 168B include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure are in the field of fabricating next generation integrated circuit structures, and in particular, integrated circuit structures that include source or drain structures with abrupt dopant profiles. [Background technology]

[0002] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to ever finer features allows for an increased density of functional units in the limited real estate of a semiconductor chip. For example, reducing the size of transistors allows for a greater number of memory or logic devices to be integrated onto a chip, resulting in an increase in the capabilities of the manufactured products. However, the drive for ever greater capabilities is not without challenges. The need to optimize the performance of each device becomes increasingly important.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors such as tri-gate transistors have become more widely used as device dimensions continue to shrink. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to the lower cost and less complex tri-gate fabrication process they allow. In another aspect, as microelectronic device dimensions scale below the 10 nanometer (nm) node, maintaining mobility improvement and short-channel control presents challenges to device fabrication. Nanowires used to fabricate devices provide improved short-channel control.

[0004] However, multi-gate and nanowire transistors have not been scaled without consequences. As the dimensions of these building blocks of microelectronic circuits decrease, and as the number of very many building blocks manufactured in a given area increases, the constraints on the lithographic processes used to pattern these building blocks become greater. In particular, there can be a trade-off between the minimum dimensions of the features patterned in the semiconductor stack (the critical dimensions) and the spacing between such features.

[0005] Variabilities in conventional and currently known manufacturing processes may limit the ability to extend further into the 10 nanometer or sub-10 nanometer node range, and as a result, fabrication of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into or replacement of current manufacturing processes. [Brief description of the drawings]

[0006] [Figure 1A] 1 shows conventional epitaxial growth of FinFET devices over nanowire devices.

[0007] [Figure 1B] 1 shows cross-sectional views of a starting nanowire structure, a nanowire structure with integrated EPI growth, and a nanowire structure with non-integrated EPI growth, according to one embodiment of the present disclosure.

[0008] [Figure 2A] 1 includes top-down scanning electron microscope (SEM) images of (a) phosphorus-doped silicon epitaxial growth results on a silicon structure, and (b) phosphorus and arsenic co-doped silicon epitaxial growth results on a silicon structure, according to one embodiment of the present disclosure.

[0009] [Figure 2B] 1 includes cross-sectional scanning electron microscope (SEM) images of (a) phosphorus-doped silicon epitaxial growth results on a silicon structure, and (b) phosphorus and arsenic co-doped silicon epitaxial growth results on a silicon structure, according to one embodiment of the present disclosure.

[0010] [Figure 2C] FIG. 2C is a magnified view of a portion of image (b) of FIG. 2B according to one embodiment of the present disclosure.

[0011] [Figure 2D] 1 includes a plot of concentration (atoms / cm3) as a function of depth (nanometers) according to one embodiment of the present disclosure.

[0012] [Figure 2E] 1 includes a plot of concentration (atoms / cm3) as a function of depth (nanometers) according to one embodiment of the present disclosure.

[0013] [Figure 3A] FIG. 2 illustrates a plan view of multiple gate lines above a pair of semiconductor fins according to another embodiment of the present disclosure.

[0014] [Figure 3B] 3B shows a cross-sectional view taken along axis a-a' of FIG. 3A according to one embodiment of the present disclosure.

[0015] [Figure 4] 3 illustrates a cross-sectional view of an integrated circuit structure with trench contacts for NMOS devices according to another embodiment of the present disclosure.

[0016] [Diagram 5] 1 illustrates a cross-sectional view of an integrated circuit structure with conductive contacts on raised source or drain regions according to one embodiment of the present disclosure.

[0017] [Figure 6A]1 illustrates cross-sectional views of various integrated circuit structures, each having a trench contact that includes an overlying insulating cap layer, and a gate stack that includes an overlying insulating cap layer, according to one embodiment of the present disclosure. [Figure 6B] 1 illustrates cross-sectional views of various integrated circuit structures, each having a trench contact that includes an overlying insulating cap layer, and a gate stack that includes an overlying insulating cap layer, according to one embodiment of the present disclosure.

[0018] [Figure 7A] 1 shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to one embodiment of the present disclosure.

[0019] [Figure 7B] FIG. 7B illustrates a source or drain cross-sectional view of the nanowire-based integrated circuit structure of FIG. 7A taken along the a-a′ axis according to one embodiment of the present disclosure.

[0020] [Figure 7C] FIG. 7B shows a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG. 7A taken along the bb′ axis, according to one embodiment of the present disclosure.

[0021] [Figure 8A] 1 illustrates a computing device according to one implementation of the present disclosure.

[0022] [Figure 8B] 1 illustrates an interposer including one or more embodiments of the present disclosure.

[0023] [Figure 9] FIG. 1 is an isometric view of a mobile computing platform utilizing an IC described herein or manufactured by one or more processes including one or more features described herein, according to one embodiment of the disclosure.

[0024] [Figure 10]FIG. 2 illustrates a cross-sectional view of a flip-chip mounted die according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] An integrated circuit structure is described that includes a source or drain structure having an abrupt dopant profile, such as an abrupt dopant profile based on phosphorus and arsenic co-dopants. In the following description, numerous specific details are described, such as specific integration and material regimes, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0026] The following Detailed Description is merely exemplary in nature and is not intended to limit the subject embodiments or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding Technical Field, Background, Summary, or the Detailed Description below.

[0027] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0028] Terminology The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims.

[0029] "Comprising." This term is open-ended. When this term is used in the claims, it does not exclude additional structures or steps.

[0030] "Configured To." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit or component includes structure that performs those one or more tasks during operation. Thus, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently operating (e.g., not powered up or active). Describing a unit or circuit or component as being "configured to" perform one or more tasks expressly does not intend to invoke 35 U.S.C. 112, paragraph 6 for that unit or component.

[0031] As used herein, "first," "second," etc. are used as designators of the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0032] "Coupled." The following description refers to elements or nodes or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to (or in direct or indirect communication with) another element or node or feature, not necessarily by a mechanical coupling.

[0033] Moreover, certain terminology may also be used in the following description for reference purposes only and therefore is not intended to be limiting. For example, terms such as "top", "bottom", "upper" and "lower" refer to directions within the referenced drawings. Terms such as "front", "rear", "rear", "side", "outer", "inner" and the like are intended to describe the orientation and / or location of parts of a component in a consistent but arbitrary coordinate system that becomes apparent by reference to the document and associated drawings that describe the described component. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0034] "Inhibit." As used herein, inhibit is used to describe a reduced or minimized effect. When a component or feature is described as inhibiting an action, operation, or condition, it may completely prevent that result or outcome or future condition. Additionally, "inhibit" may also refer to a decrease or reduction in an outcome, performance, or effect that would otherwise occur. Thus, when components, elements, or features are referred to as inhibiting an outcome or condition, those components, elements, or features need not completely prevent or eliminate that outcome or condition.

[0035] The embodiments described herein may relate to semiconductor processing and construction at the substrate end of line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL generally encompasses everything up to but not including the deposition of metal interconnect layers. After the last FEOL step, the result is typically a wafer with isolated (e.g., no wires) transistors.

[0036] The embodiments described herein may relate to semiconductor processing and structures at the back-end of the interconnect (BEOL). BEOL is the second part of IC manufacturing where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added at the BEOL.

[0037] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, while example processing schemes may be shown using a FEOL processing context, such approaches may also be applied to BEOL processes. Similarly, although example processing schemes may be shown using a BEOL processing context, such approaches may also be applied to FEOL processes.

[0038] According to one or more embodiments of the present disclosure, high aspect ratio N-type source or drain structures with abrupt dopant profiles for high-scale transistor devices are described. In one or more embodiments, in situ phosphorous (P) and arsenic (As) co-doped epitaxial source or drain structures for high-scale transistors are described.

[0039] To provide context, state-of-the-art transistor devices utilize selective epitaxial layers (EPI) for the highly phosphorus-doped source or drain (S / D) regions of the device. The similar {001} and {111} growth rates of the layers can result in broad "mushroom" morphologies (e.g., corresponding significant lateral growth obtained with the requisite layer height). Highly conductive nMOS layers with high height / width aspect ratios specifically require nanowire (NW) / nanoribbon (NR) structures to avoid p-to-n S / D shorts and limitations in device pitch due to the lack of fin spacers.

[0040] Previous approaches included (1) reducing the n-epi fill to limit it to outward growth, and / or (2) increasing the fin pitch to allow for the desired epi fill. The corresponding disadvantages observed include (1) simply reducing the n-epi fill on nanowire / nanoribbon (NW / NR) products can lead to significant difficulties in uniform source-drain fill and in subsequent metal contacts, and / or (2) maintaining a large fin pitch to accommodate high doping morphologies, with selective n-epi layers being technology and Moore's Law limiters.

[0041] According to one embodiment of the present disclosure, selective epitaxial phosphorus and arsenic co-doped Si source / drain layers are implemented to provide large height / width aspect ratio morphology from steep {111} growth rates. The resulting narrow nEPI S / D regions avoid p-to-n shorts and allow large contact areas from metal wraparound to columnar structures. Advantages of implementing n-epi layer morphology embodiments such as those described herein may include removing the limiter of Moore's Law for next generation devices based on nanoribbons and nanowires. It should be appreciated that such devices based on nanoribbons and nanowires may require consistently uniform source / drains optimized with high aspect ratios for increased contact areas and reduced fin pitch. Additionally, device performance and density may be improved in parallel in implementing the embodiments described herein.

[0042] In one embodiment, a growth regime is described for epitaxial selectively co-doped Si:As,P films where performance optimization is comparable to morphology optimization. Source / drain layers can be used for increased contact area, improved uniformity, reduced defects and diffusion, and / or increased device density. In one embodiment, film performance is derived from approximately 20% improvement in resistivity and active carrier concentration from co-doping Si with As and P compared to state-of-the-art nMOS source / drain materials. As best understood, smaller phosphorus (P) paired with larger arsenic (As) in the silicon (Si) lattice reduces defects and dopant diffusion during activation and downstream annealing. Furthermore, changes in growth kinetics allow for high aspect ratio growth, where the requisite nEPI height is realized with a comparatively much narrower lateral profile. Thus, pMOS and nMOS fins can be brought closer together, facilitating Moore's Law scaling.

[0043] The embodiments described herein can be implemented to enable scaling of nanowire and nanoribbon devices, where fin spacers are typically absent (e.g., compared to FinFET devices), and enhanced lateral growth of nMOS regions. To provide context, FIG. 1A shows conventional epitaxial growth for FinFET devices relative to nanowire devices.

[0044] 1A, a cross-sectional view of a FinFET structure 100 is shown above a substrate 102. The FinFET structure 100 includes a fin spacer 106 above a shallow trench isolation structure 104. The fin spacer 106 confines epitaxial growth to a fin neck 108 and a confined mushroom 110. For a given total epitaxial height y1 above the shallow trench isolation structure 104, a corresponding mushroom width x1 is observed.

[0045] 1A, a cross-sectional view of a multi-nanowire structure 120 above a substrate 102 is shown (nanowires 122 into the page are illustrated with dashed circles). The multi-nanowire structure 120 does not include fin spacers above the shallow trench isolation structure 104. In the absence of fin spacers, epitaxial growth results in large, wide mushrooms 124. For a given total epitaxial height y2 above the shallow trench isolation structure 104, a corresponding mushroom width x2 is observed.

[0046] Comparing structures 100 and 120, at a given same height y1=y2, x2 is substantially larger than x1. FinFET structure 100 with spacer 106 limits lateral EPI growth and allows high fin density. However, EPI filling on nanowire structure 120 has much wider EPI growth due to the lack of fin spacer. In EPI growth, the increase in lateral width limits device density.

[0047] The effectiveness of high aspect ratio nEPI for nanowire / nanoribbon devices to avoid short circuits can be shown by looking at the EPI formation at the NW or NR ends. As an example, FIG. 1B shows cross-sectional views of a starting nanowire structure, a nanowire structure with integrated EPI growth, and a nanowire structure with non-integrated EPI growth, according to one embodiment of the present disclosure.

[0048] 1B, the starting structure includes a silicon substrate 152 with alternating sacrificial silicon germanium layers 154 and silicon nanowire layers 156. The structure 150 provides the end of a nanowire stack for EPI source or drain growth. It should be understood that the sacrificial silicon germanium layers 154 may be eventually removed, for example, in a nanowire release process performed during the replacement gate process. However, the sacrificial silicon germanium layers 154 may be present during EPI growth if the EPI growth is performed before the replacement gate process.

[0049] 1B, the P-type structure includes a silicon substrate 162 with alternating sacrificial silicon germanium layers 164A and silicon nanowire layers 166A. P-type epitaxial regions 168A (e.g., boron doped silicon EPI) are formed at the ends of the alternating sacrificial silicon germanium layers 164A and silicon nanowire layers 166A. The N-type structure includes a silicon substrate 162 with alternating sacrificial silicon germanium layers 164B and silicon nanowire layers 166B. N-type epitaxial regions 168B (e.g., phosphorus doped silicon EPI) are formed at the ends of the alternating sacrificial silicon germanium layers 164B and silicon nanowire layers 166B. N-type epitaxial region 168B has a first portion x3 that extends laterally beyond vertically aligned horizontal nanowires 166B and a second portion y3 that extends vertically above vertically aligned horizontal nanowires 166B. In certain embodiments, as shown, second portion y3 has a vertical thickness that is less than or equal to the horizontal thickness of first portion x3. As a result, N-type epitaxial region 168B is disadvantageously integrated with P-type epitaxial region 168A at a device spacing of d1.

[0050] 1B, the P-type structure includes a silicon substrate 172 with alternating sacrificial silicon germanium layers 174A and silicon nanowire layers 176A. P-type epitaxial regions 178A (e.g., boron doped silicon EPI) are formed at the ends of the alternating sacrificial silicon germanium layers 174A and silicon nanowire layers 176A. The N-type structure includes a silicon substrate 172 with alternating sacrificial silicon germanium layers 174B and silicon nanowire layers 176B. N-type epitaxial regions 178B (e.g., phosphorus and arsenic co-doped silicon EPI) are formed at the ends of the alternating sacrificial silicon germanium layers 174B and silicon nanowire layers 176B. N-type epitaxial region 178B has a first portion x4 that extends laterally beyond vertically aligned horizontal nanowires 176B and a second portion y4 that extends vertically above vertically aligned horizontal nanowires 176B. In certain embodiments, as shown, second portion y4 has a vertical thickness that is greater than the horizontal thickness of first portion x4. As a result, N-type epitaxial region 178B can form a gap 180 with P-type epitaxial region 178A at device spacings of d1 and even at device spacings of d2, where d2 is less than d1.

[0051] Referring again to the structure 170 of FIG. 1B, according to one embodiment of the present disclosure, an integrated circuit structure includes a vertically aligned horizontal nanowire 176B. A gate stack is around the vertically aligned horizontal nanowire, and examples of such gate stacks are described in more detail below. An epitaxial source or drain structure 178B is at the end of the vertically aligned horizontal nanowire 176B. The epitaxial source or drain structure 178B includes silicon, phosphorus, and arsenic. In one such embodiment, the atomic concentration of phosphorus is substantially the same as the atomic concentration of arsenic. In a particular embodiment, the epitaxial source or drain structure 178B has a first portion x4 that extends laterally beyond the vertically aligned horizontal nanowire 176B and a second portion y4 that extends vertically above the vertically aligned horizontal nanowire 176B. In a particular embodiment, the second portion y4 has a vertical thickness that is greater than the horizontal thickness of the first portion x4.

[0052] Further illustrating the concepts described herein, nEPI morphology for NW / NR devices can include issues where nEPI "mushroom" morphology (significant lateral growth obtained with the required height) on the NW / NR stack edges leads to S / D shorts with adjacent devices. In one embodiment, co-doped nEPI films with large height / width aspect ratio morphology derived from steep {111} growth rates result in narrow nEPI S / D regions. The morphology can be implemented to avoid S / D shorts and enable the resulting columnar S / D structures from metal wraparound for large contact areas.

[0053] 2A includes top-down scanning electron microscope (SEM) images of (a) phosphorus-doped silicon epitaxial growth results on a silicon structure, and (b) phosphorus and arsenic co-doped silicon epitaxial growth results on a silicon structure, according to one embodiment of the present disclosure. Referring to FIG. 2A, the lateral growth at location 200A for the phosphorus-doped silicon epitaxial growth is substantially larger than the lateral growth at location 200B for the phosphorus and arsenic co-doped silicon epitaxial growth. The width of the space between the nEPI regions (black regions) increases for the phosphorus and arsenic co-doped silicon structure.

[0054] As a further comparative example, FIG. 2B includes cross-sectional scanning electron microscope (SEM) images of (a) silicon epitaxial growth results doped with phosphorus on a silicon structure, and (b) silicon epitaxial growth results co-doped with phosphorus and arsenic on a silicon structure, in accordance with one embodiment of the present disclosure.

[0055] Referring to image (a) of FIG. 2B, a P-type structure 210 includes a pEPI region 214 at the end of a nanowire 212. An adjacent N-type structure 216 includes a phosphorus-doped nEPI region 218. The phosphorus-doped nEPI region 218 is substantially wider than the pEPI region 214 and may result in inadvertent integration with the adjacent pEPI region 214. In contrast, referring to image (b) of FIG. 2B, a device 220 includes a P-type structure with a pEPI region 222 at the end of the nanowire. The adjacent N-type structure includes a phosphorus- and arsenic-codoped nEPI region 224 at the end of the nanowire. The phosphorus- and arsenic-codoped nEPI region 224 is approximately the same width as the pEPI region 222 and is substantially narrower than the phosphorus-doped nEPI region 218 of image (a) of FIG. 2B.

[0056] 2C is an enlarged view of a portion of image (b) of FIG. 2B, according to one embodiment of the present disclosure. Referring to FIG. 2C, the phosphorus and arsenic co-doped nEPI region 224 is only slightly wider than the pEPI region 222 (e.g., 37.86 nm vs. 34.29 nm), allowing a substantial gap (e.g., 27.14 nm) to be maintained between the adjacent phosphorus and arsenic co-doped nEPI region 224 and the pEPI region 222.

[0057] 2A-2C, it should be appreciated that the anisotropy of the phosphorus and arsenic co-doped nEPI region 224 can reduce n-to-p shorts and allow for increased transistor density while achieving essentially identical N and P heights. Although illustrated with respect to the case of nanowires, it should be appreciated that the embodiments described herein can be implemented in NW devices, NR devices, gate-all-around devices, FinFET devices, and the like. In a particular embodiment, the integrated circuit structure includes vertically aligned horizontal nanowires. The epitaxial source or drain structures 224 are at the ends of the vertically aligned horizontal nanowires. The epitaxial source or drain structures include silicon, phosphorus, and arsenic. In one such embodiment, the atomic concentration of phosphorus is substantially the same as the atomic concentration of arsenic. In certain embodiments, the epitaxial source or drain structure has a first portion extending laterally beyond the vertically aligned horizontal nanowires and a second portion extending vertically above the vertically aligned horizontal nanowires, the second portion having a vertical thickness greater than the horizontal thickness of the first portion.

[0058] To provide further context, in modern transistor technology, the gate length (L G ) shrinks, the fraction of the total device resistance due to the channel continues to shrink. The external resistance Rext therefore becomes a significant source of device resistance and plays a large role in limiting device performance. To help minimize Rext, the P dopant concentration is increased to 1-5×10 21 atoms / cm 3Epitaxial N-type Si in the range of active dopant concentration 2-9×10 20 atoms / cm 3 In order to maximize resistivity, P is used in the source or drain (S / D) layers. During high temperature anneals used to activate dopant phosphorus (P) atoms, P can diffuse deep into the channel of the device. Thus, there is often a sacrifice made for dopant activation to maintain some control or suppression of dopant overrun into the channel, which would otherwise result in poor Ion / Ioff behavior, and therefore S / D resistivity. Ideally, epitaxial S / Ds can be grown without P diffusion while attempting to maintain low resistivity. Addressing such a need can be derived from and / or benefit from the effectiveness of selective co-doping of P and As into epitaxial S / D films in the embodiments described herein to limit void-mediated P migration and potentially reduce resistivity even to values ​​below that of highly doped P. The reduced resistivity observed can be attributed to reduced defect density in P and As co-doped structures versus structures doped with P only.

[0059] According to one embodiment of the present disclosure, the doping levels for the co-doped embodiments described herein are 5×10 for each of [P] and [As]. 19 -1.5×10 21 atoms / cm 3 It should be understood that a wide range of temperatures can be observed over which the aforementioned behavior is observed. Films can be grown over a wide range of process conditions, ranging from 600-800° C. at 100-700 Torr, using multiple precursors (e.g., tertiary butylarsine, 1-3% arsine, phosphine, dichlorosilane, tetrachlorosilane, hydrochloric acid).

[0060] The difference in dopant diffusion of co-doped Si:As,P compared to Si:P upon activation anneal is measurable. Furthermore, the resulting reduced dopant diffusion profile may result in a steeper apex at the S / D interface into the channel that provides improved short channel effects in high scale devices. As an example, FIG. 2D shows the concentration (atoms / cm) as a function of depth (nanometers) according to one embodiment of the present disclosure. 3 2E includes a plot 230 of concentration (atoms / cm) as a function of depth (nanometers), according to one embodiment of the present disclosure. 3 2D and 2E show SIMS diffusion dopant depth profiles of P-doped and P / As co-doped Si films, respectively. Specifically, FIG. 2E illustrates the SIMS profile of [P] and [As] in such a co-doped film where the two dopant concentrations are roughly equivalent. After a flash anneal at 1200° C., the P diffused in about 10 nanometers is 1×10 20 atoms / cm 3 In comparison to the Si:P film (FIG. 2D, plot 230), the co-doped Si:P,As film (FIG. 2E, plot 240) shows minor diffusion (eg, 1 nm or less) for the same annealing treatment.

[0061] According to one or more embodiments described herein, the source or drain structure formation includes the growth of an epitaxial material including silicon, phosphorous, and arsenic. In one embodiment, the source or drain structure is comprised of silicon that is co-doped with phosphorous and arsenic atoms, either during deposition (e.g., in situ) or during subsequent deposition (e.g., by implantation), or both. In one such embodiment, phosphine and arsine are used as precursors to provide phosphorous and arsenic dopants in an in situ co-doped silicon epitaxial deposition process. In one embodiment, the atomic concentration of phosphorous in the epitaxial structure is 1E20 atoms / cm. 3 The atomic concentration of the arsenic epitaxial structure is 5E19 atoms / cm3 In one embodiment, the source or drain structure has a phosphorus depth that is substantially the same as the arsenic depth. In one such embodiment, the phosphorus depth is within about 1 nanometer of the arsenic depth. In another such embodiment, the difference between the phosphorus depth and the arsenic depth is less than 5% of the arsenic depth. In one embodiment, the source or drain structure has a resistivity less than about 0.35 mOhm·cm. In one embodiment, the use of arsenic and phosphorus as co-dopants substantially limits or completely prevents the diffusion of phosphorus from the source or drain structure into the channel region of the integrated circuit structure. In one such embodiment, the extent of diffusion of phosphorus from the source or drain structure into the channel region is less than 1 nanometer, and in some embodiments, between 0 and 0.5 nanometers.

[0062] In another aspect, the source or drain structures described herein may be implemented for integrated circuit structures based on architectures other than nanowires and nanoribbons, for example, for fin-based devices. In one example, Figure 3A shows a plan view of multiple gate lines over a pair of semiconductor fins according to another embodiment of the present disclosure.

[0063] 3A, a plurality of active gate lines 304 are formed above a plurality of semiconductor fins 300. Dummy gate lines 306 are at the ends of the plurality of semiconductor fins 300. The spaces 308 between the gate lines 304 / 306 are locations where trench contacts may be placed to provide conductive contact to source or drain regions, such as source or drain regions 351, 352, 353, and 354. In one embodiment, the pattern of the plurality of gate lines 304 / 306 or the pattern of the plurality of semiconductor fins 300 is described as a lattice structure. In one embodiment, the lattice pattern includes a plurality of gate lines 304 / 306 and / or a pattern of the plurality of semiconductor fins 300 spaced at a constant pitch and having a constant width.

[0064] FIG. 3B shows a cross-sectional view taken along axis aa' of FIG. 3A, according to one embodiment of the present disclosure.

[0065] 3B, a plurality of active gate lines 364 are formed above a semiconductor fin 362 formed above a substrate 360. Dummy gate lines 366 are at the ends of the semiconductor fin 362. A dielectric layer 370 is out of the dummy gate lines 366. Trench contact material 397 is between the active gate lines 364 and between the dummy gate lines 366 and the active gate lines 364. A buried lower source or drain structure 368 and a corresponding capping semiconductor layer 369 are in the semiconductor fin 362 between the active gate lines 364 and between the dummy gate lines 366 and the active gate lines 364. In one embodiment, the buried lower source or drain structure 368 has a structure and / or composition such as those described above in connection with the source or drain structure 178B of FIG. 1B and / or other embodiments described herein.

[0066] The active gate line 364 includes a gate dielectric structure 398 / 399, a work function gate electrode portion 374, and a filler gate electrode portion 376, and a dielectric capping layer 378. Dielectric spacers 380 line the sidewalls of the active gate line 364 and the dummy gate line 366.

[0067] In another aspect, a trench contact structure, for example for a source or drain region, is described. In one example, Figure 4 shows a cross-sectional view of an integrated circuit structure with trench contacts for an NMOS device according to another embodiment of the present disclosure.

[0068] Referring to FIG. 4, an integrated circuit structure 450 includes a fin 452, such as a silicon germanium fin. A gate dielectric layer 454 is over the fin 452. A gate electrode 456 is over the gate dielectric layer 454. In one embodiment, the gate electrode 456 includes a conformal conductive layer 458 and a conductive filler 460. In one embodiment, a dielectric cap 462 is over the gate electrode 456 and over the gate dielectric layer 454. The gate electrode has a first side 456A and a second side 456B opposite the first side 456A. ​​The dielectric spacers are along the sidewalls of the gate electrode 456. In one embodiment, the gate dielectric layer 454 is further between a first one of the dielectric spacers 463 and the first side 456A of the gate electrode 456, and between a second one of the dielectric spacers 463 and the second side 456B of the gate electrode 456, as shown. In one embodiment, not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 452 and the gate dielectric layer 454.

[0069] The first and second semiconductor source or drain regions 464 and 466 are adjacent to first and second sides 456A and 456B, respectively, of the gate electrode 456. In one embodiment, the first and second semiconductor source or drain regions 464 and 466 include corresponding source or drain capping buried epitaxial lower regions or semiconductor layers 495 and 497, respectively, formed in recesses 465 and 467 of the fin 452, as shown. In one embodiment, the buried lower source or drain structures 464 and 466 have a structure and / or composition such as those described above in connection with source or drain structure 178B of FIG. 1B and / or other embodiments described herein.

[0070] The first trench contact structure 468 and the second trench contact structure 470 are respectively above the first semiconductor source or drain region 464 and the second semiconductor source or drain region 466 adjacent the first side 456A and the second side 456B of the gate electrode 456. Both the first trench contact structure 468 and the second trench contact structure 470 include a U-shaped metal layer 472 and a T-shaped metal layer 474 on and above the U-shaped metal layer 472. In one embodiment, the U-shaped metal layer 472 and the T-shaped metal layer 474 are different in composition. In one such embodiment, the U-shaped metal layer 472 includes titanium and the T-shaped metal layer 474 includes cobalt. In one embodiment, both the first trench contact structure 468 and the second trench contact structure 470 further include a third metal layer 476 on the T-shaped metal layer 474. In one such embodiment, the third metal layer 476 and the U-shaped metal layer 472 have the same composition. In a particular embodiment, the third metal layer 476 and the U-shaped metal layer 472 include titanium, and the T-shaped metal layer 474 includes cobalt.

[0071] The first trench contact via 478 is electrically connected to the first trench contact 468. In a particular embodiment, the first trench contact via 478 is on and coupled to the third metal layer 476 of the first trench contact 468. The first trench contact via 478 is further over and in contact with a portion of one of the dielectric spacers 463 and over and in contact with a portion of the dielectric cap 462. The second trench contact via 480 is electrically connected to the second trench contact 470. In a particular embodiment, the second trench contact via 480 is on and coupled to the third metal layer 476 of the second trench contact 470. The second trench contact via 480 is further over and in contact with another portion of the dielectric spacer 463 and over and in contact with another portion of the dielectric cap 462.

[0072] In one embodiment, the metal silicide layer 482 is directly between the first trench contact structure 468 and the first semiconductor source or drain region 464 and directly between the second trench contact structure 470 and the second semiconductor source or drain region 466, respectively. In one embodiment, the metal silicide layer 482 includes titanium and silicon. In certain such embodiments, the first semiconductor source or drain region 464 and the second semiconductor source or drain region 466 are first and second N-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 482 further includes phosphorus or arsenic, or both phosphorus and arsenic.

[0073] One or more embodiments described herein relate to the use of metal chemical vapor deposition for wraparound semiconductor contacts. The embodiments may apply to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films. Certain embodiments may include fabrication of titanium or similar metal layers using low temperature (e.g., below 500° C. or in the range of 400-500° C.) chemical vapor deposition of contact metals to provide conformal source or drain contacts. Implementation of such conformal source or drain contacts may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

[0074] To provide context, metal for the semiconductor contact layer may be deposited using sputtering. Sputtering is a line of sight process and may not be well suited for 3D transistor fabrication. Known sputtering solutions result in poor or incomplete metal-semiconductor junctions at the device contact surface and oblique deposition incidence angles. According to one or more embodiments of the present disclosure, a low temperature chemical vapor deposition process is implemented for the fabrication of the contact metal to provide three-dimensional conformality and maximize the metal-semiconductor junction contact area. The resulting larger contact area may reduce the resistance of the junction. The embodiments may include deposition on a semiconductor surface having a non-planar topography, where the topography of the region refers to the shape and features of the surface itself, and non-planar topography includes surface shapes and features that are non-flat, or portions of the surface shapes and features, i.e., surface shapes and features that are not entirely flat. In one embodiment, the deposition is on a semiconductor surface of a source or drain structure with a relatively high germanium content.

[0075] The embodiments described herein may include the fabrication of wrap-around contact structures. In one such embodiment, the use of pure metal conformally deposited on transistor source-drain contacts by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition may be used to increase the available area and reduce the resistance of metal-semiconductor contacts to improve the performance of transistor devices. In one embodiment, the relatively low temperature deposition results in minimized junction resistance per unit area.

[0076] It should be appreciated that a variety of integrated circuit structures may be fabricated using an integration scheme involving a metal layer deposition process as described herein. According to one embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having features thereon. The method also includes ionizing a substrate with titanium tetrachloride (TiCl) to form a titanium (Ti) layer over the substrate features. 4 ) and hydrogen (H 2 ) with 100% Ti. In one embodiment, the titanium layer has a total atomic composition including 98% or greater titanium and 0.5-2% chlorine. In alternative embodiments, a similar process is used to produce high purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) or vanadium (V).

[0077] According to one embodiment of the present disclosure, the substrate features are source or drain contact trenches that expose semiconductor source or drain structures. The titanium layer (or other high purity metal layer) is a conductive contact layer for the semiconductor source or drain structures. An exemplary embodiment of such an implementation is described below in connection with FIG.

[0078] FIG. 5 illustrates a cross-sectional view of an integrated circuit structure with conductive contacts on raised source or drain regions according to one embodiment of the present disclosure.

[0079] 5, the semiconductor structure 550 includes a gate structure 552 above a substrate 554. The gate structure 552 includes a gate dielectric layer 552A, a work function layer 552B, and a gate fill 552C. A source region 558 and a drain region 560 are on opposite sides of the gate structure 552. A source or drain contact 562 is electrically connected to the source region 558 and the drain region 560 and is spaced apart from the gate structure 552 by one or both of an interlayer dielectric layer 564 or a gate dielectric spacer 566. The source region 558 and the drain region 560 include epitaxial or buried underlying material regions formed in etched regions of the substrate 554 and corresponding source or drain capping the semiconductor layer 502. The buried lower source or drain regions 558 and 560 have a structure and / or composition such as those described above in connection with the source or drain structure 178B of FIG. 1B and / or other embodiments described herein.

[0080] In one embodiment, the source or drain contact 562 includes a high purity metal layer 562A, such as those described above, and a conductive trench fill material 562B. In one embodiment, the high purity metal layer 562A has a total atomic composition including 98% or greater titanium. In one such embodiment, the total atomic composition of the high purity metal layer 562A further includes 0.5-2% chlorine. In one embodiment, the variation in thickness of the high purity metal layer 562A is 30% or less. In one embodiment, the conductive trench fill material 562B is comprised of a conductive material such as, but not limited to, Cu, Al, W, Co, or alloys thereof.

[0081] In another aspect, contact over active gate (COAG) structures and processes are described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., gate contact vias) disposed above an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed above an active portion of a gate electrode of the semiconductor structure or device. The approach described herein can be used to reduce standard cell area by enabling gate contact formation above the active gate region. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure.

[0082] In one embodiment, the integrated circuit structure, semiconductor structure or device is a non-planar device, such as, but not limited to, a FinFET or a Tri-Gate device. In such an embodiment, the channel region of the corresponding semiconductor is composed of or formed in a three-dimensional object. In one such embodiment, the gate electrode stack of the gate line surrounds at least the top surface of the three-dimensional object and a pair of sidewalls thereof. In another embodiment, at least the channel region is fabricated to be a discrete three-dimensional object, such as in a gate-all-around device. In one such embodiment, each of the gate electrode stacks of the multiple gate lines completely surrounds the channel region.

[0083] More generally, one or more embodiments relate to approaches for landing a gate contact via directly above an active transistor gate, and structures formed therefrom. Such an approach may eliminate the need to extend a separate gate line for contact purposes. Such an approach may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In one embodiment, the removal of the top feature is achieved by recessing contact metal into the trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer that has different etch characteristics than the gate dielectric material cap layer (e.g., GILA) already used for trench contact alignment in the gate alignment contact process (GAP) processing scheme.

[0084] In one embodiment, providing an integrated circuit structure includes forming a contact pattern that is essentially perfectly aligned with an existing gate pattern, while eliminating the use of lithography steps with very tight alignment tolerances. In one such embodiment, this approach inherently enables the use of highly selective wet etches (e.g., versus dry or plasma etches) to create contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, the present approach enables the elimination of the need for an otherwise significant lithography step to create the contact pattern, as used in other approaches. In one embodiment, the trench contact grid is formed between the poly (gate) lines, rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning, but before the gate grid cut.

[0085] Additionally, the gate stack structure may be fabricated by a replacement gate process. In such a scheme, dummy gate materials, such as polysilicon or silicon nitride pillar materials, may be removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed in this process as opposed to being carried over from previous processing. In one embodiment, the dummy gate is removed by a dry or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and SF 6 In another embodiment, the dummy gate is made of polycrystalline or amorphous silicon and is removed by a dry etching process including hydrous NH 4 The dummy gate is removed with a wet etch process containing tetramethylammonium hydroxide (OH) or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed with a wet etch containing aqueous phosphoric acid.

[0086] In one embodiment, one or more approaches described herein essentially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at an integrated circuit structure. In one such embodiment, a replacement contact process is performed after a replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600° C., for example, after a gate dielectric layer is formed. The annealing is performed prior to the formation of the permanent contacts.

[0087] It should be understood that different structural relationships between the insulating gate cap layer and the insulating trench contact cap layer can be fabricated. By way of example, Figures 6A and 6B show cross-sectional views of various integrated circuit structures according to one embodiment of the present disclosure, each having a trench contact that includes an overlying insulating cap layer and a gate stack that includes an overlying insulating cap layer.

[0088] 6A and 6B, integrated circuit structures 600A and 600B each include a fin 602, such as a silicon germanium fin. Although illustrated as a cross-section, it should be understood that the fin 602 has a top 602A and sidewalls (into and out of the page of the depicted perspective). A first gate dielectric layer 604 and a second gate dielectric layer 606 are above the top 602A of the fin 602 and laterally adjacent the sidewalls of the fin 602. A first gate electrode 608 and a second gate electrode 610 are above the first gate dielectric layer 604 and the second gate dielectric layer 606, respectively, above the top 602A of the fin 602 and laterally adjacent the sidewalls of the fin 602. The first gate electrode 608 and the second gate electrode 610 each include a conformal conductive layer 609A, such as a work function setting layer, and a conductive fill material 609B above the conformal conductive layer 609A. The first gate electrode 608 and the second gate electrode 610 both have a first side 612 and a second side 614 opposite the first side 612. The first gate electrode 608 and the second gate electrode 610 also both have an insulating cap 616 with a top surface 618.

[0089] A first dielectric spacer 620 is adjacent to a first side 612 of the first gate electrode 608. A second dielectric spacer 622 is adjacent to a second side 614 of the second gate electrode 610. A semiconductor source or drain region 624 is adjacent to the first dielectric spacer 620 and the second dielectric spacer 622. A trench contact structure 626 is above the semiconductor source or drain region 624 adjacent to the first dielectric spacer 620 and the second dielectric spacer 622. In one embodiment, the semiconductor source or drain region 624 has a structure and / or composition such as those described above in connection with FIG. 1B source or drain structure 178B and / or other embodiments described herein.

[0090] The trench contact structure 626 includes an insulating cap 628 on the conductive structure 630. The insulating cap 628 of the trench contact structure 626 has a top surface 629 that is substantially coplanar with the top surfaces 618 of the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610. In one embodiment, the insulating cap 628 of the trench contact structure 626 extends laterally into the recesses 632 in the first dielectric spacer 620 and the second dielectric spacer 622. In such an embodiment, the insulating cap 628 of the trench contact structure 626 covers the conductive structure 630 of the trench contact structure 626. However, in other embodiments, the insulating cap 628 of the trench contact structure 626 does not extend laterally into the recesses 632 in the first dielectric spacer 620 and the second dielectric spacer 622 and therefore does not cover the conductive structure 630 of the trench contact structure 626.

[0091] It should be understood that the conductive structure 630 of the trench contact structure 626 may not be rectangular as illustrated in Figures 6A and 6B. For example, the conductive structure 630 of the trench contact structure 626 may have a cross-sectional shape similar to or the same as the shape shown for the conductive structure 630A shown in the projection of Figure 6A.

[0092] In one embodiment, the insulating cap 628 of the trench contact structure 626 has a composition different than the composition of the insulating cap 616 of the first gate electrode 608 and the second gate electrode 610. In one such embodiment, the insulating cap 628 of the trench contact structure 626 comprises a carbide material, such as a silicon carbide material. The insulating cap 616 of the first gate electrode 608 and the second gate electrode 610 comprises a nitride material, such as a silicon nitride material.

[0093] In one embodiment, as illustrated in Figure 6A, the insulating cap 616 of both the first gate electrode 608 and the second gate electrode 610 has a bottom surface 617A that is below a bottom surface 628A of the insulating cap 628 of the trench contact structure 626. In another embodiment, as illustrated in Figure 6B, the insulating cap 616 of both the first gate electrode 608 and the second gate electrode 610 has a bottom surface 617B that is substantially coplanar with a bottom surface 628B of the insulating cap 628 of the trench contact structure 626. In another embodiment, not illustrated, the insulating cap 616 of both the first gate electrode 608 and the second gate electrode 610 has a bottom surface that is below a bottom surface of the insulating cap 628 of the trench contact structure 626.

[0094] In one embodiment, the conductive structure 630 of the trench contact structure 626 includes a U-shaped metal layer 634, a T-shaped metal layer 636 entirely on and above the U-shaped metal layer 634, and a third metal layer 638 on the T-shaped metal layer 636. An insulating cap 628 of the trench contact structure 626 is on the third metal layer 638. In one such embodiment, the third metal layer 638 and the U-shaped metal layer 634 include titanium, and the T-shaped metal layer 636 includes cobalt. In certain such embodiments, the T-shaped metal layer 636 further includes carbon.

[0095] In one embodiment, the metal silicide layer 640 is sandwiched directly between the conductive structure 630 of the trench contact structure 626 and the semiconductor source or drain region 624. In one such embodiment, the metal silicide layer 640 comprises titanium and silicon. In certain such embodiments, the semiconductor source or drain region 624 is an N-type semiconductor source or drain region.

[0096] To highlight an exemplary integrated circuit structure comprising three vertically arranged nanowires, Figure 7A shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to one embodiment of the present disclosure. Figure 7B shows a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 7A taken along the a-a' axis. Figure 7C shows a cross-sectional channel view of the nanowire-based integrated circuit structure of Figure 7A taken along the b-b' axis.

[0097] Referring to FIG. 7A, an integrated circuit structure 700 includes one or more vertically stacked nanowires (set of 704) on a substrate 702. In one embodiment, a relaxed buffer layer 702C, a defect correction layer 702B, and a lower substrate portion 702A are included in the substrate 702 as shown. Any fins below the bottom nanowire and formed from the substrate 702 are not shown for purposes of emphasizing the nanowire portion for illustrative purposes. The embodiments herein are directed to both single-wire and multiple-wire devices. As an example, a three-nanowire-based device is shown for illustrative purposes, comprising nanowires 704A, 704B, and 704C. For ease of description, nanowire 704A is used as an example where the description is focused on one of the nanowires. Where characteristics of one nanowire are described, it should be understood that embodiments based on multiple nanowires would have the same or essentially the same characteristics for each of the nanowires.

[0098] Each of the nanowires 704 includes a nanowire channel region 706. The channel region 706 has a length (L). Referring to FIG. 7C, the channel region also has a perimeter (Pc) perpendicular to the length (L). Referring to both FIGS. 7A and 7C, a gate electrode stack 708 surrounds the entire perimeter (Pc) of each channel region 706. The gate electrode stack 708 includes a gate electrode with a gate dielectric layer (not shown) between the channel region 706 and the gate electrode. In one embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack 708, without any intervening material, such as an underlying substrate material or an overlying channel fabrication material. Thus, in embodiments having multiple nanowires 704, the nanowire channel regions 706 are also discrete with respect to one another.

[0099] 7A and 7B, the integrated circuit structure 700 includes a pair of non-discrete source or drain regions 710 / 712. The pair of non-discrete source or drain regions 710 / 712 are on either side of a channel region 706 of the vertically stacked nanowires 704. Furthermore, the pair of non-discrete source or drain regions 710 / 712 are adjacent with respect to the channel region 706 of the vertically stacked nanowires 704. In one such embodiment, although not shown, the pair of non-discrete source or drain regions 710 / 712 are directly vertically adjacent with respect to the channel region 706 in that the epitaxial growth is on and between portions of the nanowires that extend beyond the channel region 706, with the nanowire ends shown within the source or drain structures. 7A, the pair of non-discrete source or drain regions 710 / 712 are indirectly vertically adjacent with respect to the channel region 706 in that they are formed at the ends of the nanowires, rather than between them. In one embodiment, the non-discrete source or drain regions 710 / 712 have a structure and / or composition such as described above in connection with source or drain structure 178B of FIG. 1B and / or other embodiments described herein.

[0100] In one embodiment, as shown, the source or drain regions 710 / 712 are non-discrete in that there is a separate, non-discrete source or drain region for each channel region 706 of the nanowire 704. Thus, in an embodiment with multiple nanowires 704, the nanowire source or drain regions 710 / 712 are global, or integrated, source or drain regions, as opposed to discrete for each nanowire. That is, the non-discrete source or drain regions 710 / 712 are global in the sense that a single integrated feature is used as a source or drain region for multiple (in this case, three) nanowires 704, and more particularly, for more than one separate channel region 706. In one embodiment, as shown in FIG. 7B, from a cross-sectional perspective view perpendicular to the length of the separate channel regions 706, each pair of non-discrete source or drain regions 710 / 712 is approximately rectangular in shape, with a tapered portion at the bottom and a vertex portion at the top. In other embodiments, however, the nanowire source or drain regions 710 / 712 are relatively large, yet discrete, non-vertically integrated epitaxial structures, such as humps.

[0101] According to one embodiment of the present disclosure, and as illustrated in Figures 7A and 7B, the integrated circuit structure 700 further includes a pair of contacts 714, each contact 714 on one of the pair of non-discrete source or drain regions 710 / 712. In one such embodiment, in a vertical perspective, each contact 714 is completely surrounded by the non-discrete source or drain region 710 / 712, respectively. In another aspect, as illustrated in Figure 7B, the entire perimeter of the non-discrete source or drain region 710 / 712 may not be accessible for contact with the contact 714, and the contact 714 thus only partially surrounds the non-discrete source or drain region 710 / 712. In a contrasting embodiment, not illustrated, the entire perimeter of the non-discrete source or drain region 710 / 712 is surrounded by the contact 714 as cut along the a-a' axis.

[0102] 7A , in one embodiment, the integrated circuit structure 700 further includes a pair of spacers 716. As shown, outer portions of the pair of spacers 716 may extend beyond portions of the non-discrete source or drain regions 710 / 712 to provide "buried" portions of the non-discrete source or drain regions 710 / 712 beneath the pair of spacers 716. Also as shown, the buried portions of the non-discrete source or drain regions 710 / 712 may not extend entirely beneath the pair of spacers 716.

[0103] The substrate 702 may be composed of a material suitable for the fabrication of integrated circuit structures. In one embodiment, the substrate 702 includes a lower bulk substrate composed of a single crystalline material, which may include, but is not limited to, silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or III-V compound semiconductor materials. An upper insulating layer, which may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride, is on the lower bulk substrate. Thus, the structure 700 may be fabricated from a starting semiconductor on insulating substrate. Alternatively, the structure 700 is formed directly from a bulk substrate and localized oxidation is used to form the electrically insulating portion in place of the upper insulating layer described above. In another alternative embodiment, the structure 700 is formed directly from a bulk substrate and doping is used to form electrically isolated active regions thereon, such as nanowires. In one such embodiment, the first nanowire (i.e., closest to the substrate) is in the form of an omegaFET type structure.

[0104] In one embodiment, the nanowires 704 may be wire or ribbon sized and may have square or rounded corners, as described below. In one embodiment, the nanowires 704 are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, with respect to silicon nanowires 704, single crystalline nanowires have a global orientation (100), e.g., a crystalline orientation (100) in the z direction. <100> The nanowire 704 may be based on a plane. As discussed below, other orientations are also possible. In one embodiment, the dimensions of the nanowire 704 are on the nanoscale from a cross-sectional perspective view. For example, in certain embodiments, the smallest dimension of the nanowire 704 is less than about 20 nanometers. In one embodiment, the nanowire 704 is composed of a strained material, particularly in the channel region 706.

[0105] 7C, in one embodiment, each channel region 706 has a width (Wc) and a height (Hc), where the width (Wc) is approximately the same as the height (Hc). That is, in both cases, the channel regions 706 have a square-like, or, if the corners are rounded, a circle-like cross-sectional profile. In another aspect, such as in the case of nanoribbons as generally described, the widths and heights of the channel regions need not be the same.

[0106] As described throughout this application, the substrate may be composed of a semiconductor material that can withstand the manufacturing process and through which charges can be transported. In one embodiment, the substrate described herein is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof, to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a separate crystalline substrate, for example, a silicon epitaxial layer grown on a bulk silicon single crystal substrate doped with boron. The bulk substrate may alternatively be composed of a III-V material. In one embodiment, the bulk substrate is composed of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimony, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a III-V material and the charge carrier dopant impurity atoms include, but are not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0107] As described throughout this application, an isolation region, such as a shallow trench isolation region or a sub-fin isolation region, may ultimately be composed of a suitable material that electrically isolates or contributes to the isolation of portions of a permanent gate structure from the underlying bulk substrate, or that isolates active areas formed in the underlying bulk substrate, such as isolating the active areas of a fin. For example, in one embodiment, the isolation region is composed of one or more layers of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon doped silicon nitride, or combinations thereof.

[0108] As described throughout this application, a gate line or gate structure may be comprised of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Additionally, a portion of the gate dielectric layer may include a layer of native oxide formed from some top layer of a semiconductor substrate. In one embodiment, the gate dielectric layer is comprised of a top high-k portion and a bottom portion comprised of an oxide of the semiconductor material. In one embodiment, the gate dielectric layer is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric may be configured with a "U" shaped structure that includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

[0109] In one embodiment, the gate electrode is comprised of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a particular embodiment, the gate electrode is comprised of a non-work function setting fill material formed above a metal work function setting layer. The gate electrode layer may be comprised of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be comprised of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. In a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer allows for the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. In an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer allows for the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode can be configured with a U-shaped structure that includes a bottom that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode can be simply a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of U-shaped and planar, non-U-shaped structures, for example, the gate electrode may be comprised of one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0110] As described throughout this application, spacers associated with a gate line or gate electrode stack may be composed of any suitable material that ultimately electrically isolates or contributes to the isolation of a permanent gate structure from an adjacent conductive contact, such as a self-aligned contact, For example, in one embodiment, the spacers are composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0111] In one embodiment, the approach described herein may involve the formation of a contact pattern that is very closely aligned to an existing gate pattern while eliminating the use of lithography steps with very tight alignment tolerances. In one such embodiment, the approach inherently allows for the use of highly selective wet etches (e.g., versus dry or plasma etches) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, the present approach allows for the elimination of the need for an otherwise significant lithography step to create the contact pattern as used in other approaches. In one embodiment, the trench contact grid is formed between the poly (gate) lines rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid cut.

[0112] Pitch division processing and patterning schemes may be implemented to enable the embodiments described herein or may be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch division by two, pitch division by four, etc. Pitch division schemes may be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional (e.g., either strictly unidirectional or predominantly unidirectional) lines at a predefined pitch. Pitch division processing is then implemented as a technique to increase line density.

[0113] In one embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hardmask lines is used herein to refer to a dense pitch grating structure. In such an embodiment, the dense pitch is not directly achievable through selected lithography. For example, a pattern based on selected lithography may be formed first, but the pitch may be divided by two by using spacer mask patterning as known in the art. Furthermore, a second spacer mask patterning may divide the original pitch by four. Thus, the grid-like patterns described herein may have metal lines, ILD lines, or hardmask lines with substantially consistent widths spaced apart by a substantially consistent pitch. For example, in some embodiments, the pitch may vary by within 10 percent and the width may vary by within 10 percent, and in some embodiments, the pitch may vary by within 5 percent and the width may vary by within 5 percent. The patterns may be manufactured by pitch division by two or pitch division by four, or by other pitch division approaches. In one embodiment, the grating is not necessarily a single pitch.

[0114] In one embodiment, as used throughout this description, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulator material. Examples of suitable dielectric materials include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO 2 )), doped silicon oxide, fluorinated silicon oxide, carbon doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0115] In one embodiment, as also used throughout this description, metal line or interconnect line material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper lines and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. The term metal as used herein includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnect line may be a single material layer or may be formed from multiple layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect line. In one embodiment, the interconnect lines are comprised of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof, and are sometimes referred to in the art as wiring, wires, lines, metals, or simply interconnects.

[0116] In one embodiment, as also used throughout this description, the hardmask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hardmask layer includes a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hardmask material includes a metal species. For example, the hardmask or other overlying material may include a layer of titanium nitride or another metal (e.g., titanium nitride). Potentially, other materials, such as lesser amounts of oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the art may be used depending on the particular implementation. The hardmask layer may be formed by CVD, PVD, or other deposition methods.

[0117] In one embodiment, as also used throughout this description, the lithography process is performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, or the like. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topography masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0118] It should be understood that not all aspects of the above process need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, the dummy gate does not need to be formed at all prior to fabricating the gate contact above the active portion of the gate stack. The above gate stack may in fact be a permanent gate stack as initially formed. The process described herein may also be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed double gate device, a finFET, a nanowire device, or a nanoribbon device. One or more embodiments may be particularly useful for fabricating semiconductor devices at ten nanometer (10 nm) technology nodes and below ten nanometer (10 nm) technology nodes.

[0119] Additional or intermediate steps for the fabrication of a FEOL layer or structure may include standard microelectronic fabrication processes such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other measures associated with microelectronic component fabrication. It should also be understood that the process steps described in the preceding process flows may be practiced in an alternative order, that not all steps need to be performed, and / or that additional process steps may be performed.

[0120] In the above exemplary FEOL embodiment, it should be understood that in one embodiment, 10 nanometer or sub-10 nanometer node processing is directly implemented in the manufacturing scheme and resulting structures as a technology driver. In other embodiments, BEOL 10 nanometer or sub-10 nanometer processing requirements may drive FEOL considerations. For example, material selection and layout for FEOL layers and devices may need to accommodate BEOL processing. In such an embodiment, for example, material selection and gate stack architecture are selected to accommodate high density metallization of BEOL layers to reduce fringing capacitance in transistor structures formed in FEOL layers but coupled together by high density metallization of BEOL layers.

[0121] The embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. Additionally, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular telephones, personal electronic devices, and the like. The integrated circuits may be coupled with buses and other components of the system. For example, a processor may be coupled with a memory, a chipset, and the like by one or more buses. Each of the processor, memory, and chipset may potentially be manufactured using the approaches disclosed herein.

[0122] 8A illustrates a computing device 800A according to one implementation of the present disclosure. The computing device 800A houses a substrate 802A. The substrate 802A may include a number of components, including, but not limited to, a processor 804A and at least one communication chip 806A. The processor 804A is physically and electrically coupled to the substrate 802A. In some implementations, the at least one communication chip 806A is also physically and electrically coupled to the substrate 802A. In further implementations, the communication chip 806A is part of the processor 804A.

[0123] Depending on its uses, the computing device 800A may include other components, which may or may not be physically and electrically coupled to the substrate 802A. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0124] The communications chip 806A enables wireless communications for data transfer to and from the computing device 800A. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the devices involved do not include any wires, although in some embodiments the devices may not include any wires. The communications chip 806A may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and later generations. The computing device 800A may include multiple communications chips 806A. For example, a first communications chip 806A may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communications chip 806A may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0125] The processor 804A of the computing device 800A includes an integrated circuit die packaged within the processor 804A. In some implementations of the embodiments of the present disclosure, the integrated circuit die of the processor 804A includes one or more structures, such as integrated circuit structures constructed according to an implementation of the present disclosure. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory.

[0126] The communications chip 806A also includes an integrated circuit die packaged within the communications chip 806A. According to another implementation of the present disclosure, the integrated circuit die of the communications chip 806A is constructed according to an implementation of the present disclosure.

[0127] In further implementations, other components contained within computing device 800A may include an integrated circuit die constructed in accordance with implementations of the embodiments of the present disclosure.

[0128] In various embodiments, computing device 800A may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 800A may be any other electronic device that processes data.

[0129] FIG. 8B illustrates an interposer 800B including one or more embodiments of the present disclosure. The interposer 800B is an intervening substrate used to bridge a first substrate 802B to a second substrate 804B. The first substrate 802B can be, for example, an integrated circuit die. The second substrate 804B can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of the interposer 800B is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 800B can bond an integrated circuit die to a ball grid array (BGA) 806B that can then be bonded to the second substrate 804B. In some embodiments, the first and second substrates 802B / 804B are attached to opposing sides of the interposer 800B. In other embodiments, the first and second substrates 802B / 804B are attached to the same side of the interposer 800B. And in further embodiments, three or more substrates are interconnected through interposer 800B.

[0130] Interposer 800B may be formed of epoxy, fiberglass reinforced epoxy, ceramic materials, or polymeric materials such as polyimide, etc. In further implementations, interposer 800B may be formed of alternating rigid or flexible materials, which may include the same materials listed above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0131] The interposer 800B may include metal interconnects 808B and vias 810B, including but not limited to through silicon vias (TSVs) 812B. The interposer 800B may further include embedded devices 814B, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 800B. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the interposer 800B or components included in the interposer 800B.

[0132] FIG. 9 is an isometric view of a mobile computing platform 900 utilizing integrated circuits (ICs) described herein or manufactured by one or more processes including one or more features described herein, in accordance with one embodiment of the disclosure.

[0133] The mobile computing platform 900 may be any portable device configured for electronic data display, electronic data processing, or wireless electronic data transmission. For example, the mobile computing platform 900 may be any of a tablet, a smartphone, a laptop computer, etc., and may include a display screen 905, which in an exemplary embodiment is a touch screen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system 910, and a battery 913. As shown, the greater the level of integration in the integrated system 910 enabled by higher transistor packing density, the larger the portion of the mobile computing platform 900 that may be occupied by the battery 913 or non-volatile storage such as a solid-state drive, or the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in the integrated system 910, the higher the functionality. Thus, the techniques described herein may enable improved performance and form factors in the mobile computing platform 900.

[0134] The integrated system 910 is further shown in an exploded view 920. In an exemplary embodiment, the packaged device 977 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., multi-core microprocessor and / or graphics processor) manufactured by one or more processes described herein or including one or more features described herein. The packaged device 977 is further coupled to the substrate 960 along with one or more of a power management integrated circuit (PMIC) 915, an RF (radio frequency) integrated circuit (RFIC) 925 including a wideband RF (radio frequency) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module further including a power amplifier on the transmit path and a low noise amplifier on the receive path), and their controllers 911. Functionally, the PMIC 915 performs battery power control, DC-DC conversion, etc., and thus has an input coupled to the battery 913 and an output providing a current supply to all other functional modules. As further shown, in an exemplary embodiment, the RFIC 925 has an output coupled to an antenna that is provided to implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, and 5G and beyond. In alternative implementations, each of these board level modules may be integrated on a separate IC coupled to the packaging substrate of the packaged device 977 or within a single IC (SoC) coupled to the packaging substrate of the packaged device 977.

[0135] In another aspect, semiconductor packages are used to protect integrated circuit (IC) chips or dies and to provide the dies with an electrical interface to external circuitry. As the demand for smaller electronic devices increases, semiconductor packages need to be designed even smaller and support greater circuit density. Furthermore, the demand for higher performance devices results in a need for improved semiconductor packages that allow for a thin packaging profile and low overall warpage compatible with subsequent assembly processes.

[0136] In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the die to a ceramic or organic package substrate. In particular, C4 solder ball connections can be implemented to provide flip chip interconnection between the semiconductor device and the substrate. Flip chip or controlled collapse chip connection (C4) is a type of mount used for semiconductor devices, such as integrated circuit (IC) chips, MEMS, or components, that utilizes solder bumps instead of wire bonds. Solder bumps are deposited on C4 pads that are located on the top surface of the substrate package. To mount the semiconductor device to the substrate, the semiconductor device is flipped over onto the mounting area so that the active side faces down. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0137] FIG. 10 illustrates a cross-sectional view of a flip-chip mounted die according to one embodiment of the present disclosure.

[0138] 10, an apparatus 1000 includes a die 1002, such as an integrated circuit (IC), manufactured by one or more processes described herein or including one or more features described herein, according to an embodiment of the disclosure. The die 1002 includes metallized pads 1004 thereon. A packaging substrate 1006, such as a ceramic or organic substrate, includes connections 1008 thereon. The die 1002 and the packaging substrate 1006 are electrically connected by solder balls 1010 bonded to the metallized pads 1004 and connections 1008. An underfill material 1012 surrounds the solder balls 1010.

[0139] Flip chip processing can be similar to traditional IC manufacturing, with a few additional steps. Late in the manufacturing process, the mounting pads are metallized to make them more receptive to solder. Typically, this consists of multiple processes. Small dots of solder are then deposited on each of the metallized pads. The chip is then cut from the wafer as normal. To attach the flip chip to a circuit, the chip is flipped over and the solder dots are contacted, face down, to a connector on the underlying electronic or circuit board. The solder is then remelted, typically using an ultrasonic or alternatively a reflow soldering process, to provide an electrical connection. This also leaves a small space between the chip's circuitry and the underlying mount. In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection and to provide a thermal bridge, thereby ensuring that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0140] In other embodiments, newer packaging and die-to-die interconnect approaches, such as through silicon vias (TSVs) and silicon interposers, are implemented to produce high performance multi-chip modules (MCMs) and systems-in-packages (SiPs) incorporating integrated circuits (ICs) manufactured according to one or more processes described herein or including one or more features described herein in accordance with an embodiment of the present disclosure.

[0141] Accordingly, embodiments of the present disclosure include integrated circuit structures comprising source or drain structures with abrupt dopant profiles as described, and methods of manufacturing integrated circuit structures comprising source or drain structures with abrupt dopant profiles.

[0142] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the disclosure, even if only a single embodiment is described with respect to a particular feature. The examples of features provided in this disclosure are intended to be illustrative rather than limiting, unless otherwise specified. The above description is intended to cover such alternatives, modifications, and equivalents as will be apparent to one skilled in the art having the benefit of this disclosure.

[0143] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly) or any generalization thereof, whether or not it alleviates any or all of the problems described herein. Accordingly, new claims may be devised for any such combination of features during prosecution of this application (or an application claiming priority thereto). In particular, with reference to the appended claims, features according to the dependent claims may be combined with features of the independent claims, and features according to each independent claim may be combined in any suitable manner, not just in the specific combinations recited in the appended claims.

[0144] The following examples relate to further embodiments. The various features of the different embodiments can be combined in various ways, with some features included and other features excluded, to suit a variety of different applications.

[0145] Exemplary embodiment 1: An integrated circuit structure includes a vertically aligned horizontal nanowire. A gate stack surrounds the vertically aligned horizontal nanowire. A first epitaxial source or drain structure is at a first end of the vertically aligned horizontal nanowire. A second epitaxial source or drain structure is at a second end of the vertically aligned horizontal nanowire. The first and second epitaxial source or drain structures include silicon, phosphorus and arsenic, and an atomic concentration of phosphorus is substantially the same as an atomic concentration of arsenic.

[0146] Exemplary embodiment 2: The integrated circuit structure of exemplary embodiment 1 has an atomic concentration of phosphorus of 1E20 atoms / cm 3 The atomic concentration of arsenic is 5E19 atoms / cm 3 Greater than.

[0147] Exemplary embodiment 3: In the integrated circuit structure of exemplary embodiment 1 or 2, the first and second epitaxial source or drain structures have a phosphorus depth that is substantially the same as the arsenic depth.

[0148] Exemplary embodiment 4: In the integrated circuit structure of exemplary embodiment 3, the depth of the phosphorus is within about 1 nanometer of the depth of the arsenic.

[0149] Exemplary Embodiment 5: In the integrated circuit structure of exemplary embodiments 1, 2, 3 or 4, the first and second source or drain structures have a resistivity of less than about 0.35 mOhm·cm.

[0150] Exemplary Embodiment 6: The integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4 or 5, further comprising first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

[0151] Exemplary Embodiment 7: The integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4, 5 or 6, further comprising a first conductive contact on the first epitaxial source or drain structure and a second conductive contact on the second epitaxial source or drain structure.

[0152] Exemplary embodiment 8: An integrated circuit structure includes a vertically aligned horizontal nanowire. A gate stack is around the vertically aligned horizontal nanowire. A first epitaxial source or drain structure is at a first end of the vertically aligned horizontal nanowire. The first epitaxial source or drain structure is The nanowire has a first portion extending laterally beyond the vertically aligned horizontal nanowire and a second portion extending vertically above the vertically aligned horizontal nanowire, the second portion having a vertical thickness greater than the horizontal thickness of the first portion. A second epitaxial source or drain structure is at a second end of the vertically aligned horizontal nanowire. The second epitaxial source or drain structure has a first portion extending laterally beyond the vertically aligned horizontal nanowire and a second portion extending vertically above the vertically aligned horizontal nanowire, the second portion having a vertical thickness greater than the horizontal thickness of the first portion.

[0153] Exemplary Embodiment 9: In the integrated circuit structure of Exemplary Embodiment 8, the first and second epitaxial source or drain structures include silicon, phosphorus and arsenic, and the atomic concentration of phosphorus is substantially the same as the atomic concentration of arsenic.

[0154] Exemplary Embodiment 10: The integrated circuit structure of Exemplary Embodiment 8 or 9, further comprising first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

[0155] Exemplary Embodiment 11: The integrated circuit structure of Exemplary Embodiment 8, 9 or 10, further comprising a first conductive contact on the first epitaxial source or drain structure and a second conductive contact on the second epitaxial source or drain structure.

[0156] Exemplary embodiment 12: A computing device includes a substrate and a component coupled to the substrate. The component includes an integrated circuit structure. The integrated circuit structure includes vertically aligned horizontal nanowires. A gate stack surrounds the vertically aligned horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertically aligned horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertically aligned horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorus and arsenic, and an atomic concentration of phosphorus is substantially the same as an atomic concentration of arsenic.

[0157] Exemplary Embodiment 13: The computing device of exemplary embodiment 12 further includes a memory coupled to the substrate.

[0158] Exemplary embodiment 14: The computing device of exemplary embodiment 12 or 13 further includes a communication chip coupled to the substrate.

[0159] Exemplary Embodiment 15: The computing device of exemplary embodiments 12, 13, or 14 further includes a camera coupled to the substrate.

[0160] Exemplary Embodiment 16: The computing device of exemplary embodiments 12, 13, 14, or 15 further includes a battery coupled to the substrate.

[0161] Exemplary Embodiment 17: The computing device of exemplary embodiments 12, 13, 14, 15, or 16 further includes an antenna coupled to the substrate.

[0162] Exemplary Embodiment 18: In the computing device of exemplary embodiments 12, 13, 14, 15, 16, or 17, the component is a packaged integrated circuit die.

[0163] Exemplary embodiment 19: In the computing device of exemplary embodiment 12, 13, 14, 15, 16, 17 or 18, the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

[0164] Exemplary Embodiment 20: In the computing device of exemplary embodiments 12, 13, 14, 15, 16, 17, 18 or 19, the computing device is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server and a set-top box.

Claims

1. Vertically aligned horizontal nanowires; a gate stack surrounding the vertically aligned horizontal nanowires; a first epitaxial source or drain structure at a first end of the vertically aligned horizontal nanowire; a second epitaxial source or drain structure at a second end of the vertically aligned horizontal nanowire, the first epitaxial source or drain structure and the second epitaxial source or drain structure comprising silicon, phosphorus and arsenic, the atomic concentration of phosphorus being substantially the same as the atomic concentration of arsenic. Integrated circuit structure.

2. The atomic concentration of phosphorus is 1E20 atoms / cm ３ and the atomic concentration of arsenic is 5E19 atoms / cm ３ The integrated circuit structure of claim 1 .

3. 3. The integrated circuit structure of claim 1, wherein the first epitaxial source or drain structure and the second epitaxial source or drain structure have a phosphorus depth substantially the same as an arsenic depth.

4. 4. The integrated circuit structure of claim 3 wherein said depth of phosphorus is within 1 nanometer of said depth of arsenic.

5. 5. The integrated circuit structure of claim 1, wherein the first epitaxial source or drain structure and the second epitaxial source or drain structure have a resistivity of less than 0.35 mOhm-cm.

6. further comprising first and second dielectric gate sidewall spacers along first and second sides of the gate stack, respectively.

6. An integrated circuit structure according to any one of claims 1 to 5.

7. a first conductive contact on the first epitaxial source or drain structure; a second conductive contact on the second epitaxial source or drain structure.

7. An integrated circuit structure according to any one of claims 1 to 6.

8. Vertically aligned horizontal nanowires; a gate stack surrounding the vertically aligned horizontal nanowires; a first epitaxial source or drain structure at a first end of the vertically aligned horizontal nanowire and a second epitaxial source or drain structure at a second end of the vertically aligned horizontal nanowire; the first epitaxial source or drain structure and the second epitaxial source or drain structure comprise silicon, phosphorus and arsenic; the first epitaxial source or drain structure comprises a first portion extending laterally beyond the vertically aligned horizontal nanowires and a second portion extending vertically above the vertically aligned horizontal nanowires, the second portion having a vertical thickness greater than a horizontal thickness of the first portion; the second epitaxial source or drain structure comprises a first portion extending laterally beyond the vertically aligned horizontal nanowires and a second portion extending vertically above the vertically aligned horizontal nanowires, the second portion having a vertical thickness greater than a horizontal thickness of the first portion. Integrated circuit structure.

9. 9. The integrated circuit structure of claim 8, wherein the first epitaxial source or drain structure and the second epitaxial source or drain structure comprise silicon phosphorous and arsenic, the atomic concentration of phosphorous being substantially the same as the atomic concentration of arsenic.

10. 10. The integrated circuit structure of claim 8 or 9, further comprising first and second dielectric gate sidewall spacers along first and second sides, respectively, of the gate stack.

11. a first conductive contact on the first epitaxial source or drain structure; a second conductive contact on the second epitaxial source or drain structure.

11. An integrated circuit structure according to any one of claims 8 to 10.

12. A substrate; a component coupled to the substrate, the component comprising an integrated circuit structure, the integrated circuit structure comprising: Vertically aligned horizontal nanowires; a gate stack surrounding the vertically aligned horizontal nanowires; a first epitaxial source or drain structure at a first end of the vertically aligned horizontal nanowire; a second epitaxial source or drain structure at a second end of the vertically aligned horizontal nanowire, the first epitaxial source or drain structure and the second epitaxial source or drain structure comprising silicon, phosphorus and arsenic, the atomic concentration of phosphorus being substantially the same as the atomic concentration of arsenic. Computing device.

13. further comprising a memory coupled to the substrate. The computing device of claim 12.

14. further comprising a communications chip coupled to the substrate. A computing device according to claim 12 or 13.

15. further comprising a camera coupled to the substrate. A computing device according to any one of claims 12 to 14.

16. further comprising a battery coupled to the substrate. A computing device according to any one of claims 12 to 15.

17. further comprising an antenna coupled to the substrate. A computing device according to any one of claims 12 to 16.

18. 18. The computing device of claim 12, wherein the component is a packaged integrated circuit die.

19. 19. The computing device of claim 12, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20. 20. The computing device of claim 12, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server, and a set-top box.

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