Domain switching element and method for manufacturing same

Abstract

To provide a domain switching element and a manufacturing method of the same.SOLUTION: The domain switching element includes a channel region, a source and a drain connected to the channel region, a gate electrode disposed to be separated from the channel region, an antiferroelectric layer disposed between the channel region and the gate electrode, a conduction layer disposed between the gate electrode and the antiferroelectric layer to be in contact with the conduction layer, and a barrier layer disposed between the antiferroelectric layer and the channel region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a domain switching element and a method for manufacturing the same. [Background technology]

[0002] Existing silicon-based transistors have limitations in terms of improving operational characteristics and scaling down.

[0003] Although the development of nano-fabrication technology has made it possible to manufacture transistor elements smaller, the minimum voltage required for transistor operation is limited by the Boltzmann distribution of electrons. For example, when measuring the characteristics of the operating voltage and operating current of an existing silicon-based transistor, the subthreshold swing (SS) value is given by the following Equation 1, and it is known that the SS value has a limit of about 60mV / dec.

[0004]

number

[0005] where k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and C D is the capacitance of the depletion layer, and C ins is the capacitance of the gate insulator.

[0006] As the size of transistors becomes smaller, the power density increases because it is difficult to reduce the operating voltage below about 0.8 V. Therefore, if the distribution density of elements is increased, it may cause breakdowns due to heat generation, and there is a limit to the scale-down of elements.

[0007] There is a demand for development of devices that can improve operational characteristics such as subthreshold swing (SS), are advantageous for scale-down, and can increase control efficiency. Summary of the Invention [Problem to be solved by the invention]

[0008] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a domain switching element having a low operating voltage and a method for manufacturing the same. [Means for solving the problem]

[0009] According to one type, there is provided a domain switching element including a channel region, a source and a drain connected to the channel region, a gate electrode spaced apart from the channel region, an anti-ferroelectric layer disposed between the channel region and the gate electrode, a conductive layer disposed between the gate electrode and the anti-ferroelectric layer so as to be in contact with the anti-ferroelectric layer, and a barrier layer disposed between the anti-ferroelectric layer and the channel region.

[0010] At least a portion of the antiferroelectric layer adjacent to the conductive layer may be crystallized. The antiferroelectric layer also has a ZrO ratio of 50% or more in an interface region with the conductive layer.

[0011] The conductive layer is also made of a material having a sheet resistance of less than 1 MΩ / square. The conductive layer has a coefficient of thermal expansion less than that of the antiferroelectric layer. The conductive layer has a thermal expansion coefficient greater than that of Mo.

[0012] The conductive layer may include a metal nitride, a metal oxynitride, RuO, MoO, or WO.

[0013] The barrier layer may have a breakdown voltage greater than a breakdown voltage of the antiferroelectric layer.

[0014] The barrier layer may include any one of SiO, AlO, HfO, ZrO, LaO, YO, and MgO, or any one of SiO, AlO, HfO, ZrO, LaO, YO, and MgO doped with a dopant, or a two-dimensional insulator.

[0015] The domain switching element may further include a dielectric layer disposed between the barrier layer and the channel region.

[0016] The dielectric layer may also be of a different material than the barrier layer. The barrier layer has a dielectric constant greater than the dielectric constant of the dielectric layer.

[0017] The dielectric layer may include SiO, AlO, HfO, ZrO, or a two-dimensional insulator.

[0018] The antiferroelectric layer may include at least one of HfO, ZrO, SiO, AlO, CeO, YO, and LaO.

[0019] The antiferroelectric layer may further include a dopant, and the dopant may include at least one of Si, Al, Zr, Y, La, Gd, Sr, Hf, and Ce.

[0020] The channel region may include at least one of Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D materials, quantum dots, transition metal dichalcogenides, and organic semiconductors.

[0021] According to one type, there is provided a method for manufacturing a domain switching device, the method including: providing a substrate including a channel region; forming a layered structure including a barrier layer, a domain switching layer, and a conductive layer on the channel region; forming an electrode material layer on the layered structure; and inducing anti-ferroelectricity in the domain switching layer.

[0022] The domain switching layer may include at least one of HfO, ZrO, SiO, AlO, CeO, YO, and LaO.

[0023] The conductive layer may comprise a metal nitride, a metal oxynitride, RuO, MoO, or WO. The inducing step may include crystallizing at least a portion of the domain switching layer adjacent to the conductive layer.

[0024] The inducing step may include causing the conductive layer to apply a tensile stress to the domain switching layer.

[0025] The inducing step may include annealing the laminate structure.

[0026] The heat treatment may be performed after the step of forming the laminate structure and before the step of forming the electrode material layer, and / or after the step of forming the electrode material layer. Effect of the Invention

[0027] According to the present invention, it is possible to realize a domain switching device that exhibits a negative capacitance effect without hysteresis by utilizing antiferroelectricity.

[0028] According to the present invention, an anti-ferroelectric phase can be realized in the domain switching layer through the interface strain control between the domain switching layer and the adjacent conductive layer.

[0029] According to the present invention, the domain switching element can also be used as a logic transistor to realize various electronic elements / devices / circuits / systems. [Brief description of the drawings]

[0030] [Figure 1] 1 is a cross-sectional view illustrating a schematic structure of a domain switching element according to an embodiment; [Diagram 2] 11 is a cross-sectional view showing a schematic structure of a domain switching element according to a comparative example. FIG. [Figure 3A] 11 is a graph conceptually showing a relationship between charge and energy of a ferroelectric material employed in a domain switching element according to a comparative example. [Figure 3B] 13 is a graph conceptually showing a relationship between an electric field and polarization of a ferroelectric material employed in a domain switching element according to a comparative example. [Figure 4A] 1 is a graph conceptually illustrating a relationship between charge and energy of an antiferroelectric material employed in a domain switching element according to an embodiment. [Figure 4B] 4 is a graph conceptually illustrating a relationship between an electric field and polarization of an antiferroelectric material employed in a domain switching element according to an embodiment. [Diagram 5] This is a graph experimentally confirming that HfZrO can exhibit ferroelectricity and antiferroelectricity depending on the interface strain relationship with adjacent material layers. [Figure 6] This is a graph experimentally confirming that HfZrO can exhibit ferroelectricity and antiferroelectricity depending on the interface strain relationship with adjacent material layers. [Figure 7] 11 is a cross-sectional view showing a schematic structure of a domain switching element according to another embodiment. [Figure 8A]1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 8B] 1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 8C] 1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 8D] 1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 8E] 1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 8F] 1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 8G] 1 is a diagram illustrating a method of manufacturing a domain switching element according to an embodiment; [Figure 9] FIG. 1 is a conceptual diagram illustrating an architecture of an electronic device according to one embodiment. [Figure 10] FIG. 13 is a conceptual diagram illustrating the architecture of an electronic device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. The described embodiment is merely exemplary, and various modifications are possible from such an embodiment. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings is exaggerated for clarity and convenience of description.

[0032] In the following description, the terms "upper" and "above" may include not only something that is directly above in contact with something, but also something that is above without contacting something.

[0033] Terms such as first and second may be used to describe various components, but are used only for the purpose of distinguishing one component from another, and are not intended to limit the materials or structures of the components.

[0034] The singular expression includes the plural expression unless the context clearly indicates otherwise. Furthermore, when a part "includes" a certain element, it does not mean excluding other elements, but means that other elements may be further included, unless otherwise specified to the contrary.

[0035] In addition, terms such as "unit" and "module" used in the specification refer to a unit that processes at least one function or operation, and may be realized by hardware or software, or a combination of hardware and software.

[0036] Use of the terms "said" and similar referents refers to both the singular and the plural.

[0037] The steps constituting the method are performed in any suitable order unless expressly stated to be performed in the order described. In addition, the use of all exemplary terms (such as, for example, etc.) is merely for the purpose of explaining the technical idea in detail, and such terms are not intended to limit the scope of the claims, except as otherwise limited by the claims.

[0038] FIG. 1 is a cross-sectional view showing a schematic structure of a domain switching element according to an embodiment.

[0039] Referring to FIG. 1, the domain switching element 100 includes a channel region CH, a source SR and a drain DR connected to the channel region CH, a gate electrode GA arranged to be spaced apart from the channel region CH, and a conductive layer 150, an anti-ferroelectric layer 140 and a barrier layer 130 arranged between the gate electrode GA and the channel region CH.

[0040] The source SR and drain DR may be electrically connected to or in contact with both sides of the channel region CH. The channel region CH, the source SR, and the drain DR may also be provided within a given substrate 110.

[0041] Impurities may be implanted into two regions spaced apart from each other on the substrate 110 to form a source SR and a drain DR, and the region of the substrate 110 between the source SR and the drain DR is also defined as a channel region CH. The substrate 110 may be, for example, a Si substrate, or a substrate including other materials besides Si, such as Ge, SiGe, or III-V semiconductors. In this case, the channel region CH may include Si, Ge, SiGe, or III-V semiconductors. The material of the substrate 110 is not limited to the above, and may be changed in various ways. The channel region CH may be formed not as a part of the substrate 110, but as a material layer separate from the substrate 110. The material of the channel region CH may include at least one of an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional material (2D (two-dimensional) material), a transition metal dichalcogenide (TMD), a quantum dot, and an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO, the two-dimensional material may include, for example, a transition metal dichalcogenide or graphene, and the quantum dots may include colloidal quantum dots (colloidal QDs), nanocrystalline structures, and the like, which are illustrative and not limited thereto.

[0042] A gate electrode GA is disposed to face the channel region CH and be spaced apart therefrom, and an antiferroelectric layer 140 serving as a domain switching layer may be provided between the channel region CH and the gate electrode GA.

[0043] The gate electrode GA may include any one of Pt, Ru, Au, Ag, Mo, Al, W, and Cu, an alloy, a conductive metal oxide, or a conductive metal nitride.

[0044] The antiferroelectric layer 140 may include at least one of HfO, ZrO, SiO, AlO, CeO, YO, and LaO, and may further include a dopant thereon, such as Si, Al, Zr, Y, La, Gd, Sr, Hf, and Ce. The exemplified materials are materials that exhibit ferroelectricity or anti-ferroelectricity depending on the crystalline phase and / or the stress state at the interface with the adjacent layer. In the domain switching element 100 according to an embodiment, the interface stress is adjusted so that the material exhibits antiferroelectricity, forming the antiferroelectric layer 140.

[0045] For example, the ferroelectric properties of HfO are determined by the crystalline phase of the material, and it is known that antiferroelectric properties are exhibited in the tetragonal phase, and ferroelectric properties are exhibited in the orthorhombic phase. Therefore, after depositing an amorphous HfO thin film, it is possible to make it have antiferroelectric properties through heat treatment and stress control.

[0046] The antiferroelectricity can be explained as follows in comparison with the ferroelectricity. Ferroelectric materials have a non-centrosymmetric charge distribution in a unit cell in a crystallized material structure, and have spontaneous electric dipoles, i.e., spontaneous polarization. Ferroelectric materials have remnant polarization due to electric dipoles even in the absence of an external electric field, and at the same time, the direction of polarization can be switched on a domain-by-domain basis by the application of an external electric field.

[0047] Antiferroelectric materials contain ferroelectric domains in which electric dipoles are aligned, and exhibit a remnant polarization of zero or close to zero in the absence of an applied external electric field. In other words, antiferroelectric materials ideally have the same ratio of electric dipoles with opposite polarization directions in the absence of an applied electric field, and exhibit a remnant polarization of zero or close to zero. When an external electric field is applied to antiferroelectric materials, the direction of polarization can be switched.

[0048] The antiferroelectric layer 140 may have a substantially non-hysteresis behavior characteristic in the polarization change due to an external electric field. In other words, the antiferroelectric layer 140 does not have or substantially does not have a hysteresis characteristic during the domain switching operation.

[0049] In one embodiment of the domain switching element 100, a material capable of exhibiting ferroelectricity or antiferroelectricity is used, and the interface stress and / or crystal phase are adjusted to express antiferroelectricity therein, thereby implementing the antiferroelectric layer 140.

[0050] According to one embodiment, the domain switching element 100 includes a conductive layer 150 in contact with the antiferroelectric layer 140 via a seed layer that applies a tensile stress to the antiferroelectric layer 140 to induce antiferroelectricity.

[0051] The conductive layer 150 is also made of a material having conductivity and a sheet resistance less than 1 MΩ / square. The conductive layer 150 is also made of a material having a thermal expansion coefficient smaller than that of a material used in the antiferroelectric layer 140 so that a predetermined tensile stress can be applied to the antiferroelectric layer 140 during a high-temperature heat treatment process and a cooling process when manufacturing the domain switching device 100. The material of the conductive layer 150 is also selected as a material having a thermal expansion coefficient that makes the tensile stress applied to the antiferroelectric layer 140 within a predetermined range during a cooling process after the heat treatment process. In other words, the material of the conductive layer 150 can be selected so that the difference in thermal expansion coefficient between the conductive layer 150 and the material used in the antiferroelectric layer 140 is smaller than the difference in thermal expansion coefficient at which ferroelectricity is induced. For example, the material of the conductive layer 150 may be selected to have a thermal expansion coefficient that is greater than or less than the thermal expansion coefficient of the material used as the antiferroelectric layer 140, but greater than the thermal expansion coefficient of Mo. The thermal expansion coefficient difference of the conductive layer 150 material may be greater than or equal to 4×10 -6 ~20×10 -6 / K range.

[0052] Conductive layer 150 may include a metal nitride, a metal oxynitride, RuO, MoO, or WO.

[0053] At least a partial region of the antiferroelectric layer 140 adjacent to the conductive layer 150 is crystallized and may include tetragonal crystals. The ratio of ZrO in the antiferroelectric layer 140 at the interface with the conductive layer is 50% or more.

[0054] The barrier layer 130 is also disposed between the channel region CH and the antiferroelectric layer 140. The barrier layer 130 is also disposed in contact with the antiferroelectric layer 140.

[0055] The barrier layer 130 is an insulating layer for suppressing or preventing electrical leakage, and may be made of Si oxide (SiO), Al oxide (AlO), Hf oxide (HfO), Zr oxide (ZrO), or a two-dimensional insulator (2D insulator). As the two-dimensional insulator, a material such as h-BN (hexagonal boron nitride) may be used. However, the material of the barrier layer 130 is not limited thereto.

[0056] A higher dielectric constant of the barrier layer 130 is advantageous for improving the performance of the domain switching element 100. The barrier layer 130 is also made of a material having a higher breakdown voltage than the breakdown voltage of the antiferroelectric layer 140.

[0057] In one embodiment, the domain switching element 100 employs an antiferroelectric layer 140 as a domain switching layer that exhibits negative capacitance and has substantially no or almost no hysteresis in polarization change due to an electric field, allowing for a reduction in operating voltage, which is advantageous for scaling down the element.

[0058] Fig. 2 is a cross-sectional view showing a schematic structure of a domain switching element according to a comparative example. Figs. 3A and 3B are graphs conceptually showing the relationship between charge and energy and the relationship between electric field and polarization of a ferroelectric material used in a domain switching element according to a comparative example, and Figs. 4A and 4B are graphs conceptually showing the relationship between charge and energy and the relationship between electric field and polarization of an antiferroelectric material used in a domain switching element according to an embodiment.

[0059] The domain switching element 10 according to the comparative example includes a channel region CH, a source SR and a drain DR connected to the channel region CH, a gate electrode GA arranged to be spaced apart from the channel region CH, a ferroelectric layer 14 arranged between the gate electrode GA and the channel region CH, and a dielectric layer 12.

[0060] The domain switching element 10 of the comparative example differs from the domain switching element 100 of this embodiment in that a ferroelectric layer 14 is used as a domain switching layer.

[0061] The ferroelectric material and the antiferroelectric material employed in the domain switching element 10 of the comparative example and the domain switching element 100 of the present embodiment each have a ferroelectric domain and can exhibit negative capacitance, i.e., negative electric capacity. Capacitance is an index indicating the ability of a material to store an electric charge. In fact, a typical capacitor (electrical storage device) shown in most electronic devices stores an electric charge when a voltage is applied to the capacitor. Conversely, negative capacitance refers to the property that the charge storage decreases as the applied voltage increases. Such a property can also be explained as being due to the reversal of electric dipoles caused by the applied voltage. Negative capacitance is a unique reaction of an electric charge to an applied voltage, and when a material exhibiting such a property is suitably integrated into a transistor, the power consumed by the transistor or a device including the transistor can be significantly reduced.

[0062] On the other hand, in the case of the domain switching element 10 having the structure of the comparative example, the hysteresis exhibited by the ferroelectric layer 14 limits the performance.

[0063] FIG. 3A exemplarily shows the relationship between charge (Q) and energy (U) of a ferroelectric material, and the polarization distribution of a dipole domain in two energy states.

[0064] Referring to Fig. 3A, a ferroelectric material has two degenerate states in which the polarization directions are either both downward or both upward. When the charge (Q) is zero, such two states are mixed half-and-half due to the formation of multi-domains, and the total polarization direction is either up or down depending on the direction of the applied electric field, and after the applied electric field is removed, it remains in state A or state B. The polarization change related to the applied electric field thereafter has a history that depends on state A or state B.

[0065] The graph in FIG. 3B shows the relationship between electric field (E) and polarization (P). Referring to the graph, depending on the polarization (P) state (A, B) when no electric field is applied, the polarization (P) due to the electric field (E) subsequently applied shows hysteresis having different values. Antiferroelectric materials, on the other hand, show little or no such hysteresis.

[0066] Referring to the charge (Q)-energy (U) graph of FIG. 4A, the most stable state is the state (S) where the polarization directions are repeatedly arranged up and down and the total polarization is 0. If an external electric field is applied in that state, the domains are switched and the state becomes, for example, state C or state D, which has more dipoles in one direction. If the applied electric field is removed in that state, the state returns to state (S) where the polarization is repeatedly arranged up and down, and the polarization (P) due to the electric field (E) applied thereafter shows the same change tendency as before and does not show hysteresis. Such a tendency is maintained in the range where the applied electric field is small, for example, in the range where the state change due to the applied electric field does not become state P or Q on the graph of FIG. 4A.

[0067] The graph in FIG. 4B shows the relationship between electric field (E) and polarization (P). Referring to the graph, when the value of the applied electric field is within a predetermined range, for example, in the region indicated by the dotted circle, the polarization (P) due to the electric field (E) shows a constant trend without hysteresis.

[0068] As such, ferroelectric materials can provide a negative capacitance effect due to domain switching in the absence of hysteresis.

[0069] 5 and 6 are graphs showing experimental results that HfZrO can exhibit ferroelectricity and antiferroelectricity, respectively, depending on the interface strain relationship with the adjacent material layer.

[0070] The layered film used in the experiment in Figure 5 has a structure in which the layers are stacked in the order Mo / HfZrO / Mo from the top. In such a layered structure, the electric field vs. polarization graph of the HfZrO thin film shows clear hysteresis, indicating that HfZrO is in a ferroelectric state.

[0071] The stacked film used in the experiment in Figure 6 has a structure stacked in the order TiN / HfZrO / Mo from the top. In such a stacked structure, the electric field vs. polarization graph of HfZrO shows a clearly reduced hysteresis compared to Figure 5. In particular, in the range where the applied electric field is small, such a tendency is more clearly shown. It can be seen that both ferroelectric and antiferroelectric phases exist in HfZrO in such a stacked structure, and therefore it can be seen that HfZrO can exhibit antiferroelectricity in the TiN / HfZrO / Mo structure.

[0072] Such a tendency is analyzed to be due to stress applied to HfZrO by the adjacent HfZrO layer, that is, due to the difference in thermal expansion coefficient between TiN and HfZrO, and between Mo and HfZrO.

[0073] Both TiN and Mo have a smaller thermal expansion coefficient than HfZrO, and therefore apply tensile stress to HfZrO when cooling after the high-temperature heat treatment process. On the other hand, TiN has a larger thermal expansion coefficient than Mo, and therefore the difference in thermal expansion coefficient between HfZrO and TiN is smaller than the difference in thermal expansion coefficient between HfZrO and Mo. In other words, when cooling after heat treatment, the tensile stress applied to HfZrO in the TiN / HfZrO / Mo structure is smaller than the tensile stress applied to HfZrO in the Mo / HfZrO / Mo structure.

[0074] It is known that Hf oxide and Zr oxide exhibit ferroelectricity in the orthorhombic crystal phase and antiferroelectricity in the tetragonal crystal phase. Therefore, from the experimental results, it is analyzed that HfZrO forms an orthorhombic crystal phase under a relatively large tensile stress state and exhibits ferroelectricity, and forms a tetragonal / orthorhombic crystal phase under a relatively small tensile stress state and exhibits antiferroelectricity / ferroelectricity. In other words, it is found that HfZrO can exhibit antiferroelectricity by appropriately adjusting the tensile stress with the adjacent layer.

[0075] As described above, the domain switching element 100 according to this embodiment includes the conductive layer 150 as a seed layer for antiferroelectricity induction and stress adjustment, and the material of the conductive layer 150 can be selected so that the thermal expansion coefficient of the conductive layer 150 is appropriately set in relation to the thermal expansion coefficient of the material constituting the antiferroelectric layer 140 to embody antiferroelectricity.

[0076] FIG. 7 is a cross-sectional view showing a schematic structure of a domain switching element according to another embodiment.

[0077] 7, the domain switching element 101 includes a channel region CH, a source SR and a drain DR connected to the channel region CH, a gate electrode GA arranged to be spaced apart from the channel region CH, and a conductive layer 150, an antiferroelectric layer 140, and a barrier layer 130 arranged between the gate electrode GA and the channel region CH. In addition, a dielectric layer 120 is provided between the barrier layer 130 and the channel region CH.

[0078] The dielectric layer 120, together with the barrier layer 130, is an insulating layer for suppressing or preventing electrical leakage. The dielectric layer 120 may include a different material than the barrier layer 130. The dielectric layer 120 may have a dielectric constant smaller than that of the barrier layer 130. The dielectric layer 120 may include SiO, AlO, HfO, ZrO, or a two-dimensional insulator. As a two-dimensional insulator, a material such as h-BN may be used. However, the material of the dielectric layer 120 is not limited thereto.

[0079] 8A to 8G are views illustrating a method of manufacturing a domain switching element according to an embodiment. Referring to FIG. 8A, a substrate 110 including a channel region CH is provided.

[0080] The channel region CH may include at least one of Si, Ge, SiGe, a III-V semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional material, a transition metal dichalcogenide, a quantum dot, and an organic semiconductor.

[0081] Impurities can be implanted into two regions spaced apart from each other on the substrate 110 to form a source SR and a drain DR, and the region of the substrate 110 between the source SR and the drain DR is also defined as a channel region CH. The formation of the source SR and the drain DR is performed in this step, but is not limited thereto, and may also be performed in a subsequent step.

[0082] 8B, a laminated structure including a domain switching layer 142 and a conductive layer 150 is formed on the channel region. The laminated structure may include a dielectric layer 120, a barrier layer 130, the domain switching layer 142, and the conductive layer 150. However, the laminated structure is not limited thereto, and the dielectric layer 120 may be omitted.

[0083] The domain switching layer 142 is an amorphous thin film layer and may include at least one of HfO, ZrO, SiO, AlO, CeO, YO, and LaO, any one of which may be further doped with a dopant such as Si, Al, Zr, Y, La, Gd, Sr, Hf, or Ce.

[0084] The conductive layer 150 contacts the domain switching 142 and may include a metal nitride, a metal oxynitride, RuO, MoO, or WO.

[0085] The material of the conductive layer 150 may be selected so as to apply a tensile stress to the domain switching layer 142 during a cooling process after the heat treatment, and so that the applied tensile stress is within a predetermined range. For example, the material of the conductive layer 150 may be selected so that the thermal expansion coefficient of the conductive layer 150 is smaller than that of the domain switching layer 142 and larger than that of Mo.

[0086] The barrier layer 130 and the dielectric layer 120 may include any one of SiO, AlO, HfO, ZrO, LaO, YO, and MgO, or any one of SiO, AlO, HfO, ZrO, LaO, YO, and MgO doped with a dopant, or a two-dimensional insulator, and the barrier layer 130 is also a material having a higher dielectric constant than the dielectric layer 120.

[0087] The laminated structure may be formed by a deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0088] The domain switching layer 142 is an amorphous thin film layer and does not exhibit antiferroelectricity. Therefore, an additional process may be performed to induce antiferroelectricity in the domain switching layer 142. Such a process may be a process of crystallizing at least a portion of the domain switching layer 142 adjacent to the conductive layer 150, or a process of applying a predetermined tensile stress to the domain switching layer 142 by the conductive layer 150. Such a process may be a process of annealing the laminated structure. The detailed steps for this are as follows.

[0089] 8C, a heat treatment process may be performed on the domain switching layer 142. The heat treatment temperature may be, but is not limited to, in the range of about 400° C. to 1,200° C., and may be determined in a range where an appropriate tensile stress is applied to the domain switching layer 142, taking into consideration the materials of the domain switching layer 142 and the conductive layer 150.

[0090] Such a heat treatment process may also crystallize at least a portion of the domain switching layer 142. In addition, during a cooling process after the heat treatment process, a predetermined tensile stress may be applied to the domain switching layer 142. As a result of such a process, the domain switching layer 142 may have a predetermined antiferroelectricity (AF1), as shown in FIG.

[0091] 8E, a gate electrode GA may be formed on the conductive layer 150. The gate electrode GA may be formed by depositing a conductive material. To form the gate electrode GA, the conductive material may be deposited by a process such as ALD, CVD, or PVD.

[0092] 8F, a heat treatment process may be performed on the domain switching layer 142. The heat treatment process with the gate electrode GA in contact with the conductive layer 150 may further facilitate crystallization of the domain switching layer 142. Such a heat treatment process may be performed at this stage instead of omitting the heat treatment process of FIG. 8E, or may be performed after the heat treatment process of FIG. 8E.

[0093] As shown in Figure 8G, a domain switching element 102 having a domain switching layer 142 with a predetermined antiferroelectricity (AF2) can be fabricated. The domain switching element 102 can be substantially identical to the domain switching element 100 of Figure 1 or the domain switching element 101 of Figure 7, with or without the dielectric layer 120.

[0094] The domain switching device according to an embodiment can be applied to various electronic devices, logic devices, etc. as a logic transistor. The logic transistor can also be a basic component of various electronic devices / logic devices. According to an embodiment, a negative capacitance with almost no hysteresis can be implemented, and operational characteristics such as sub-threshold swing (SS) can be improved, control efficiency can be increased, and a logic transistor that is advantageous for scale-down can be implemented, so that electronic devices / logic devices with excellent performance can be manufactured by applying the same.

[0095] FIG. 9 is a schematic diagram illustrating the architecture of an electronic device according to one embodiment. Referring to FIG. 9, a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030 may be formed on one chip 1000. The memory unit 1010, the ALU 1020, and the control unit 1030 may be monolithically integrated on the same substrate to form the chip 1000. Each of the ALU 1020 and the control unit 1030 may include a logic transistor including a domain switching element 100, 101, or 102 according to any one of the above-described embodiments. For example, the logic transistor may include a domain switching layer having antiferroelectricity and substantially non-hysteretic behavior characteristics. The memory unit 1010 may include a memory element. For example, the memory element may include a domain layer having hysteretic behavior characteristics while including a ferroelectric domain. The memory unit 1010, the ALU 1020, and the control unit 1030 may be interconnected on-chip by metal lines and directly communicate with each other. The memory unit 1010 may include both a main memory and a cache memory. Such a chip 1000 may be referred to as an on-chip memory processing unit. An input / output device 2000 coupled to the chip 1000 may further be included.

[0096] Such an electronic device is advantageous in terms of cost since the memory unit and the logic device unit can be integrated and manufactured on one chip. In addition, when the electronic device of the present embodiment is applied to an application field where a large amount of data is transmitted between the memory unit and the logic device unit and the data transmission is performed continuously, for example, in the field of neuromorphic devices, various effects such as improved efficiency, improved speed, and reduced power consumption can be obtained. The basic configuration and operation method of a neuromorphic device are well known, so a detailed description thereof will be omitted.

[0097] In some cases, the electronic device according to the present embodiment may be realized by an architecture in which computing unit elements and memory unit elements are formed adjacent to each other on one chip without division into sub-units.

[0098] FIG. 10 is a schematic diagram illustrating the architecture of an electronic device according to another embodiment.

[0099] 10, a CPU chip 1500 may include a cache memory 1510, an ALU 1520, and a control unit 1530. Each of the ALU 1520 and the control unit 1530 may include a logic transistor including the domain switching element 100, 101, or 102 according to any one of the above-described embodiments. For example, the logic transistor may include a domain switching layer that exhibits antiferroelectricity and has a substantially non-hysteretic behavior characteristic.

[0100] A main memory 1600 and auxiliary storage 1700 may be provided separately from the CPU chip 1500, and an input / output element 2500 may be provided. For example, the cache memory 1510 may also be configured with an SRAM (static random access memory), and the main memory 1600 may also be configured with a DRAM (dynamic random access memory).

[0101] Although many details have been described in detail in the above description, they should be construed as examples of specific embodiments rather than as limiting the scope of the invention. For example, a person skilled in the art to which the present invention belongs would know that the domain switching element of FIGS. 1 to 7 and the electronic element of FIGS. 9 and 10 can be modified in various ways. Also, the method of manufacturing the domain switching element described with reference to FIGS. 8A to 8G can be modified in various ways. Therefore, the disclosed embodiments should be considered from an explanatory perspective, not a limiting perspective. The scope of the present specification is set forth in the claims, not the above description, and all differences within the scope of the equivalents thereto should be construed as being included. [Explanation of symbols]

[0102] 100, 101, 102 Domain switching element 110 Substrate 120 Dielectric layer 130 Barrier Layer 140 Antiferroelectric layer 142 Domain Switching Layer CH Channel Region DR Drain GA gate electrode SR Source

Claims

1. A channel region; a source and a drain coupled to the channel region; a gate electrode disposed so as to be spaced apart from the channel region; an antiferroelectric layer disposed between the channel region and the gate electrode; a conductive layer disposed between the gate electrode and the antiferroelectric layer so as to be in contact with the antiferroelectric layer; a barrier layer disposed between the antiferroelectric layer and the channel region; the conductive layer has a coefficient of thermal expansion less than the coefficient of thermal expansion of the antiferroelectric layer; A domain-switching element, wherein the antiferroelectric layer exhibits antiferroelectricity based on a tensile stress applied to the antiferroelectric layer.

2. The domain switching element of claim 1 , wherein at least a portion of the antiferroelectric layer adjacent to the conductive layer is crystallized.

3. 3. The domain switching element according to claim 1, wherein the antiferroelectric layer has a ZrO ratio of 50% or more in an interface region with the conductive layer.

4. The domain switching element of claim 1 , wherein the conductive layer is made of a material having a sheet resistance of less than 1 MΩ / square.

5. The domain switching element of claim 1 , wherein the conductive layer has a thermal expansion coefficient greater than that of Mo.

6. 6. The domain switching element of claim 1, wherein the conductive layer comprises a metal nitride, a metal oxynitride, RuO, MoO, or WO.

7. The domain switching element of claim 1 , wherein the barrier layer has a breakdown voltage greater than a breakdown voltage of the antiferroelectric layer.

8. 8. The domain switching element of claim 1, wherein the barrier layer includes at least one of SiO, AlO, HfO, ZrO, LaO, YO, and MgO, or includes a material in which any one of SiO, AlO, HfO, ZrO, LaO, YO, and MgO is doped with a dopant, or a two-dimensional insulator.

9. The domain switching element of claim 1 , further comprising a dielectric layer disposed between the barrier layer and the channel region.

10. The domain switching element of claim 9 , wherein the dielectric layer is made of a different material than the barrier layer.

11. The domain switching element of claim 9 or 10, wherein the dielectric constant of the barrier layer is greater than the dielectric constant of the dielectric layer.

12. 12. The domain switching element of claim 9, wherein the dielectric layer comprises SiO, AlO, HfO, ZrO, or a two-dimensional insulator.

13. 13. The domain switching element of claim 1, wherein the antiferroelectric layer comprises at least one of HfO, ZrO, SiO, AlO, CeO, YO, and LaO.

14. the antiferroelectric layer further comprises a dopant; 14. The domain switching element of claim 13, wherein the dopant comprises at least one of Si, Al, Zr, Y, La, Gd, Sr, Hf, and Ce.

15. The domain switching element according to any one of claims 1 to 14, wherein the channel region includes at least one of Si, Ge, SiGe, a III-V group semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional material, a quantum dot, a transition metal dichalcogenide, and an organic semiconductor.

16. providing a substrate including a channel region; forming a layered structure on the channel region, the layered structure including a barrier layer, a domain switching layer, and a conductive layer; forming an electrode material layer on the laminate structure; 2. The method of claim 1, further comprising: inducing antiferroelectricity in the domain switching layer.

17. 17. The method of claim 16, wherein the domain switching layer includes at least one of HfO, ZrO, SiO, AlO, CeO, YO, and LaO.

18. 18. The method of claim 16, wherein the conductive layer comprises a metal nitride, a metal oxynitride, RuO, MoO, or WO.

19. The inducing step includes: The method of claim 16 , further comprising crystallizing at least a portion of the domain switching layer adjacent to the conductive layer.

20. The inducing step includes:

20. The method of claim 16, further comprising the step of applying a tensile stress to the domain switching layer by the conductive layer.

21. The inducing step includes: The method of claim 16 , further comprising the step of heat treating the laminated structure.

22. The heat treatment step includes: and / or The method of claim 21 , performed after the step of forming the electrode material layer.

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