Pillar-shaped semiconductor device and its manufacturing method

Abstract

In plan view, on a semiconductor base 12 which is band-shaped and continuous in a direction (first direction) orthogonal to an X-X' line direction (second direction), an N+ layer 3aa, a P+ layer 3bb, and Si columns 7a, 7b which are each likewise band-shaped and continuous in the first direction are formed. Then, a gate insulating layer 14 and gate conductor layers 15a, 15b are formed around the Si columns 7a, 7b. Then, in an insulating layer 20a, a contact hole is formed with a bottom portion thereof in contact with the N+ layer 3aa and the P+ layer 3bb, and a first conductor W layer 22 is formed at the bottom portion of the contact hole. Then, an insulating layer 24 having a hole 25 is formed in the contact hole. Then, a second conductor W layer 26 is formed in the X-X' line direction in connection with the gate conductor layers 15a, 15b.

Description

[Technical field]

[0001] The present invention relates to a pillar-shaped semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In recent years, three-dimensional structure transistors have been used in LSI (Large Scale Integration). Among them, the pillar-shaped semiconductor element SGT (Surrounding Gate Transistor) has attracted attention as a semiconductor element that provides highly integrated semiconductor devices. Furthermore, there is a demand for semiconductor devices with SGTs to be further integrated and have higher performance.

[0003] In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the channel of an SGT extends perpendicularly to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). Therefore, compared to a planar MOS transistor, an SGT can achieve a higher density semiconductor device.

[0004] 4 shows a schematic structure of an N-channel SGT. When one serves as a source, the other serves as a drain at the top and bottom positions of a Si pillar 100 (hereinafter, a silicon semiconductor pillar is referred to as an "Si pillar") having a P-type or i-type (intrinsic) conductivity. + The layers 101a and 101b (hereinafter, the semiconductor regions containing a high concentration of donor impurities are referred to as “N + The source and drain regions are called "N + The portion of the Si pillar 100 between the layers 101a and 101b becomes a channel region 102. A gate insulating layer 103 is formed to surround the channel region 102. A gate conductor layer 104 is formed to surround the gate insulating layer 103. In the SGT, N +The layers 101a and 101b, the channel region 102, the gate insulating layer 103, and the gate conductor layer 104 are formed in a columnar shape as a whole. A circuit chip having an SGT can achieve a further reduction in chip size compared to a circuit chip having a planar MOS transistor.

[0005] In the SGT shown in Figure 4, N + The layers 101a and 101b and the gate conductor layer 104 are connected to an SGT circuit formed on the same substrate by a source connection line SL, a drain connection line DL, and a gate connection line GL, respectively. In this case, reducing the coupling capacitance between the source connection line SL, the drain connection line DL, and the gate connection line GL leads to high performance of the circuit using the SGT. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2-188966 [Non-patent literature]

[0007] [Non-Patent Document 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991) Summary of the Invention [Problem to be solved by the invention]

[0008] Reducing the parasitic capacitance between the electrodes of each SGT is required to achieve high performance and high integration in SGT circuit formation. [Means for solving the problem]

[0009] In order to solve the above problems, the method for manufacturing a pillar-shaped semiconductor device of the present invention comprises the steps of: A method for manufacturing a pillar-shaped semiconductor device, comprising: a first impurity region at the bottom of a first semiconductor pillar standing vertically to a substrate; and a second impurity region at the top of the semiconductor pillar as a source or drain; the first semiconductor pillar between the first impurity region and the second impurity region as a channel; a first gate insulating layer surrounding the first semiconductor pillar between the first impurity region and the second impurity region; and a first gate conductor layer surrounding the gate insulating layer, forming the first impurity region so as to extend in a band shape in a first direction in a plan view; forming the first semiconductor pillar overlapping the first impurity region in a plan view; forming a first semiconductor platform including the first semiconductor pillar and the first impurity region in a plan view, the first semiconductor platform extending in a strip shape in the first direction and connected to a bottom of the first semiconductor pillar; forming the first gate insulating layer and the first gate conductor layer surrounding the first semiconductor pillar; forming a first insulating layer on an outer periphery of the first gate conductor layer; forming a contact hole in the first insulating layer, the contact hole overlapping the first impurity region in the first semiconductor base in a plan view, the bottom of the contact hole being in contact with the first impurity region, and extending in a strip shape in the first direction; forming a first conductor layer extending in a strip shape in the first direction at a bottom of the contact hole and in contact with the first impurity region; forming a second insulating layer including voids or made of a low dielectric constant material in the contact hole on the first conductor layer; a step of lowering a top surface position of the second insulating layer below a top end of the first gate conductor layer; forming a second conductor layer in contact with the first gate conductor layer and extending in a strip shape in a second direction perpendicular to the first direction in a plan view; The present invention is characterized by having the following.

[0010] The present invention further comprises: forming the first semiconductor pillar using the first mask material layer as an etching mask; forming a third insulating layer surrounding the first semiconductor pillar and having an upper surface located at a bottom of the first mask material layer or at a top of the semiconductor pillar in a direction perpendicular to the substrate; forming a second mask material layer on the third insulating layer, the second mask material layer surrounding the exposed first mask material layer and the top of the first semiconductor pillar with an equal width in a plan view; forming a third mask material layer on the third insulating layer, the third mask material layer partially overlapping the second mask material layer in a plan view and extending in a strip shape in the first direction; forming the semiconductor base by etching the third insulating layer and the first impurity layer using the first mask material layer, the second mask material layer, and the third mask material layer as a mask; The present invention is characterized by further comprising:

[0011] The present invention further comprises: a width of the second conductor layer in the first direction in a plan view is smaller than the longest line segment among distances between two points where a perimeter line of the first gate conductor layer intersects with a straight line extending in the first direction; It is characterized by:

[0012] The present invention is further characterized in that, in a direction perpendicular to the substrate, an upper end position of the first conductive layer is formed lower than a lower end position of the gate conductor layer.

[0013] The present invention is further characterized in that the upper end position of the hole is formed lower than the upper end position of the gate conductor layer in a direction perpendicular to the substrate.

[0014] The present invention further includes a step of forming a second semiconductor pillar on the semiconductor base in the second direction, in a plan view, opposite the first semiconductor pillar with respect to the first conductor layer; forming a second gate insulating layer surrounding the second semiconductor pillar; forming a second gate conductor layer surrounding the second gate insulating layer; forming the second conductor layer, which extends in the second direction in a plan view and is connected to an upper end of the second gate conductor layer; The present invention is characterized by further comprising:

[0015] The present invention further includes a step of forming a third impurity region in the first semiconductor base and adjacent to the first impurity region in the first direction in a plan view; forming a third semiconductor pillar on the third impurity region; forming a third gate insulating layer surrounding the third semiconductor pillar; forming a third gate conductor layer surrounding the third gate insulating layer; forming the second conductor layer so as to extend in the first direction and to be in contact with the third impurity region in a plan view; forming a third conductor layer extending in the second direction in a plan view and connected to the first gate conductor layer and an upper portion of the third gate conductor layer; The present invention is characterized by further comprising:

[0016] The present invention further includes a step of forming a first impurity layer on the substrate, the first impurity region being a base thereof; forming a first semiconductor layer on the first impurity layer, the first semiconductor layer becoming a part of a body of the first semiconductor pillar; forming a second impurity layer on the first semiconductor layer, the second impurity layer being a part of a body of the first semiconductor pillar and at least a part of the second semiconductor region; The present invention is characterized in that it further comprises:

[0017] The present invention is characterized by further comprising the step of forming a third impurity layer of the same polarity, or a conductive layer made of an alloy or a metal, on the second impurity region.

[0018] In order to solve the above problems, the pillar-shaped semiconductor device of the present invention comprises: a first impurity region connected to a bottom of the first semiconductor pillar and extending in a strip shape in a first direction; a second impurity region at the top of the first semiconductor pillar; a first gate insulating layer surrounding the first semiconductor pillar between the first impurity region and the second impurity region; a first gate conductor layer surrounding the first gate insulating layer; a semiconductor base that is connected to a bottom of the first semiconductor pillar, includes the first impurity region, and extends in a strip shape in the first direction in a plan view; a first insulating layer on an outer periphery of the first gate conductor layer; a first material layer in the first insulating layer, the first material layer overlapping the first impurity region in the semiconductor base in a plan view, the first material layer having a bottom portion in contact with the first impurity region, extending in a strip shape in the first direction, and being connected in a vertical direction; a first conductor layer extending in a strip shape in the first direction at a bottom of the first material layer and in contact with the first impurity region; a second insulating layer, the first material layer being on the first conductor layer, the upper surface of which is lower than the upper end of the gate conductor layer, the second insulating layer including voids or made of a low dielectric constant material; a second conductor layer connected to the first gate conductor layer and extending in a strip shape in a second direction perpendicular to the first direction in a plan view; The first conductor layer and the second conductor layer overlap at an intersection in a plan view.

[0019] The present invention is further characterized in that the second conductor layer is in contact with and connected to the gate conductor layer, and the width of the second conductor layer in the first direction in a plan view is formed to be smaller than the longest line segment among the distances between two points where a peripheral line of the first gate conductor layer intersects with a straight line extending in the first direction.

[0020] The present invention is further characterized in that, in a direction perpendicular to the substrate, an upper end position of the first conductive layer is lower than a lower end position of the first gate conductor layer.

[0021] The present invention further provides a semiconductor device comprising: a second semiconductor pillar on the semiconductor base in the second direction, in a plan view, opposite the first semiconductor pillar with respect to the first conductor layer; a second gate insulating layer surrounding the second semiconductor pillar; a second gate conductor layer surrounding the second gate insulating layer; the second conductor layer extending in the second direction and connected to an upper end of the second gate conductor layer in a plan view; The present invention is characterized by having the following.

[0022] The present invention further relates to a semiconductor device including a semiconductor substrate, the semiconductor substrate including a first impurity region and a third impurity region adjacent to the first impurity region in the first direction in a plan view; a third semiconductor pillar on the third impurity region; a third gate insulating layer surrounding the third semiconductor pillar; a third gate conductor layer surrounding the third gate insulating layer; In a plan view, the first conductor layer extends in the first direction and is adjacent to the third semiconductor pillar; a third conductor layer extending in the first direction in a plan view and connected to the first gate conductor layer and an upper portion of the third gate conductor layer; The present invention is characterized by further comprising:

[0023] The present invention further relates to a semiconductor device comprising: a second insulating layer on the third conductor layer; a first contact hole in the second insulating layer on the third conductor layer; the second conductor layer on the second insulating layer and connected to the third conductor layer through the first contact hole; The present invention is characterized by further comprising:

[0024] The present invention is further characterized in that it further comprises a third impurity layer of the same polarity, or a conductive layer made of an alloy or a metal, on the second impurity region. [Brief description of the drawings]

[0025] [Figure 1A] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1B] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1C] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1D] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1E] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1F] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1G] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1H] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1I] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1J]1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1K] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Figure 1L] 1A and 1B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a first embodiment. [Diagram 2] 11A and 11B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a second embodiment. [Diagram 3] 13A and 13B are a plan view and a cross-sectional structural view for explaining a manufacturing method of a pillar-shaped semiconductor device having an SGT according to a third embodiment. [Figure 4] FIG. 1 is a three-dimensional structural diagram for explaining a conventional example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, a method for manufacturing a pillar-shaped semiconductor device according to the present invention will be described with reference to the drawings.

[0027] (First embodiment) 1A to 1J, a method for manufacturing a DRAM circuit according to a first embodiment of the present invention will be described below. In each figure, (a) is a plan view, and (b) is a cross-sectional view taken along line XX' in (a) (an example of the "second direction" in the claims, and the same applies below).

[0028] As shown in FIG 1A, an N layer 2 is formed on a P layer substrate 1 (an example of a "substrate" in the claims). Then, on the N layer 2, a strip-shaped N layer extending in a direction perpendicular to the X-X' line direction in a plan view (an example of a "first direction" in the claims; the same applies below) is formed. + Layer 3a, P + The layer 3b is formed.

[0029] 1B, a P layer 4 is formed by epitaxial growth. Then, mask material layers 5a and 5b (an example of the "first mask material layer" in the claims) having a rectangular shape in a plan view are formed on the P layer 4. + Layer 3a, P + It is formed on layer 3b.

[0030] Next, as shown in FIG. 1C, the mask material layers 5a and 5b are used as masks to remove the P layer 4 and the P layer substrate 1 and N + Layer 3a, P + The upper part of layer 3b is etched to remove N + Si pillar 7a, P on layer 3a + A Si pillar 7b (an example of a "semiconductor pillar" in the claims) is formed on the layer 3b.

[0031] Next, as shown in FIG. 1D, a silicon nitride (SiN) layer 9 (an example of a "third insulating layer" in the claims) is formed on the outer periphery of the Si pillars 7a, 7b so that the upper surface position of the layer is the top of the Si pillars 7a, 7b. Then, silicon oxide (SiO2) layers 10a, 10b (an example of a "second mask material layer" in the claims) are formed so as to surround the tops of the Si pillars 7a, 7b and the side surfaces of the mask material layers 5a, 5b with an equal width in a plan view. Then, a mask material layer 11 (an example of a "third mask material layer" in the claims) is formed so as to overlap with parts of the mask material layers 5a, 5b and the SiO2 layers 10a, 10b in a plan view and extend in a band shape in a direction perpendicular to the X-X' line direction. The SiO2 layers 10a and 10b may be formed by covering the mask material layers 5a and 5b with a SiO2 layer (not shown) and then etching the SiO2 layers by, for example, a reactive ion etching (RIE) method. As a result, the SiO2 layers 10a and 10b are formed with equal widths around the mask material layers 5a and 5b in a plan view. Since the mask material layers 5a and 5b are formed in self-alignment with the Si pillars 7a and 7b, the SiO2 layers 10a and 10b are formed in self-alignment with the Si pillars 7a and 7b. The SiN layer 9 may be formed after a thin SiO2 layer (not shown) is formed on the side surfaces of the Si pillars 7a and 7b.

[0032] Next, as shown in FIG. 1E, the mask material layers 5a and 5b, the mask material layer 11, and the SiO2 layers 10a and 10b are used as masks to form the SiN layers 9 and + Layer 3a, P + The layer 3b, the N layer 2, and the P layer substrate 1 are etched to form the N + Layer 3aa, P + The layer 3bb, the N layer 2a and the P layer substrate 1a form a P layer base 12 (an example of the "semiconductor base" in the claims). In a plan view, the P layer base 12 is a strip-shaped N layer extending in a direction perpendicular to the X-X' line. + Layer 3aa, P + The layer 3bb and parts of the peripheries of the Si pillars 7a, 7b protrude from the mask material layer 11. The P-layer bases 12 in the ... are formed in self-alignment with the Si pillars 7a, 7b because they are formed using the SiN layer 9a, which is formed in self-alignment with the Si pillars 7a, 7b, as an etching mask.

[0033] Next, as shown in FIG. 1F, the mask material layer 11, the SiO2 layers 10a and 10b, and the SiN layer 9a are removed. Then, a SiO2 layer 13 is formed so as to surround the P-layer base 12 and to have its upper surface positioned above the upper surface of the P-layer base 12. Then, a hafnium oxide (HfO2) layer 14 (one example of the "gate insulating layer" in the claims) that becomes a gate insulating layer is formed surrounding the Si pillars 7a to 7d by, for example, an ALD (Atomic Layer Deposition) method. Then, a TiN layer (not shown) that becomes a gate conductor layer and a SiO2 layer (not shown) are formed to cover the HfO2 layer 14. Then, the upper surfaces are polished to the upper surfaces of the mask material layers 5a and 5b by a CMP (Chemical Mechanical Polishing) method. Then, the SiO2 layer and the TiN layer are etched by RIE to the upper surfaces of the Si pillars 7a and 7b to form a TiN layer 15 and a SiO2 layer 16. Then, a SiN layer (not shown) is covered over the entire surface. Then, the SiN layer is etched by the RIE method to form SiN layers 17a and 17b that surround the side surfaces of the mask material layers 5a and 5b and the tops of the Si pillars 7a and 7b with an equal width in a plan view. Note that the width of the SiN layers 17a and 17b may not be uniform in a plan view depending on the RIE etching conditions. It is sufficient that the SiN layers 17a and 17b surround the side surfaces of the mask material layers 5a and 5b and the tops of the Si pillars 7a and 7b.

[0034] Next, as shown in Fig. 1G, the SiO2 layer 16 is removed. Then, the TiN layer 15 is etched by the RIE method using the SiN layers 17a and 17b as a mask to form the TiN layers 15a and 15b (an example of the "gate conductor layer" in the claims) as the gate conductor layers. In this case, since the SiN layers 17a and 17b as the etching masks are formed in self-alignment with the Si pillars 7a and 7b, the TiN layers 15a and 15b are also formed in self-alignment with the Si pillars 7a and 7b.

[0035] Next, as shown in FIG. 1H, a SiO2 layer (not shown) is formed to cover the entire surface, and is polished by a CMP method so that the upper surface position is the upper surface position of the mask material layers 5a and 5b to form a SiO2 layer 20.+ Layer 3aa, P + It overlaps part of the layer 3bb, extends in a strip shape in a direction perpendicular to the X-X' line direction, and has a bottom of N + Layer 3aa, P + A contact hole 21 (one example of a "contact hole" in the claims) is formed so as to overlap the layer 3bb. Then, a tungsten (W) layer (not shown) is deposited on the entire surface, and then polished by CMP so that the upper surface becomes the upper surface of the mask material layers 5a and 5b. Then, the W layer in the contact hole 21 is etched by the RIE method, and N is formed at the bottom of the contact hole 21. + Layer 3aa, P + A W layer 22 (an example of the "first conductor layer" in the claims) is formed in contact with the layer 3bb. The W layer 22 is formed so that the upper surface position is lower than the lower end positions of the TiN layers 15a and 15b. Before forming the W layer 22, the W layer 22 and the N + Layer 2aa, P + A buffer metal layer, for example TaN, may be formed to reduce the contact resistance with layer 3bb.

[0036] Next, as shown in FIG. 1I, a SiO2 layer 24 (an example of the "second insulating layer" in the claims) having voids 25 therein is formed in the contact hole 21. The upper end position of the voids 25 is formed lower than the upper end positions of the TiN layers 15a and 15b. The SiO2 layer 24 may be formed of a low dielectric constant material layer such as silicon carbide (SiOC). In this case, the voids 25 may or may not be formed.

[0037] Next, as shown in FIG. 1J, the SiO2 layers 20 and 24 are etched by the RIE method so that the upper surface position is lower than the upper end position of the TiN layers 15a and 15b to form the SiO2 layers 20a (an example of the "first insulating layer" in the claims), 24a. Then, a W layer (not shown) connected to the TiN layers 15a and 15d is formed on the outer periphery of the TiN layers 15a and 15b. Then, a mask material layer 27 is formed that overlaps a part of the TiN layers 15a and 15b in a plan view and extends in a strip shape in the X-X' direction. Then, the W layer is etched using the mask material layer 27 as a mask. As a result, a W layer 26 (an example of the "second conductor layer" in the claims) connected to the TiN layers 15a and 15b and extending in the X-X' direction in a plan view is formed. The width of the W layer 26 in a direction perpendicular to the XX' line direction in plan view is formed to be smaller than the length of the Si pillars 7a, 7b in the same direction. Then, the mask material layer 27 is removed.

[0038] As shown in FIG. 1K, the width L1 of the W layer 26 in the direction perpendicular to the X-X' line direction is smaller than the width L2 of the outermost periphery of the TiN layers 15a, 15b that will become the gates. In plan view, the shapes of both ends of the Si pillars 7a, 7b in the first direction are usually rounded by the manufacturing process. Therefore, in this case, L2 is the longest line segment among the distances between two points that intersect the outer periphery of the TiN layers 15a, 15b and a straight line extending in the first direction in plan view. Then, as shown in FIG. 1K, a SiO2 layer 28 is formed on the outer periphery of the top side surface of the Si pillars 7a, 7b. Then, a SiO2 layer 28 is formed on the outer periphery of the top side surface of the Si pillars 7a, 7b by, for example, a selective epitaxial method, covering the tops of the Si pillars 7a, 7b. + Layer 29a, P + Then, N is formed on the tops of the Si pillars 7a and 7b by thermal diffusion. + Layer 30a, P + A layer 30b is formed.

[0039] Next, as shown in Figure 1L, + Layer 29a, P +W layers 32a and 32b are formed on the layer 29b. Then, a SiO2 layer 33 is formed to cover the whole. Then, a contact hole C1 is formed in the SiO2 layers 28 and 33 on the W layer 26. A contact hole C2 is formed in the SiO2 layer 33 on the W layer 32a. A contact hole C3 is formed in the SiO2 layer 33 on the W layer 32b. Then, a contact hole C4 is formed on the SiO2 layers 24, 28, and 33 on the W layer 22. Then, an input wiring metal layer Vin is formed connected to the W layer 26 through the contact hole C1. Then, an earth wiring metal layer Vss is formed connected to the W layer 32a through the contact hole C2. Then, a power wiring metal layer Vdd is formed connected to the W layer 32b through the contact hole C3. Then, an output wiring metal layer Vout is formed connected to the W layer 22 through the contact hole C4. This forms an inverter circuit on the P-layer substrate 1a.

[0040] In the description of this embodiment, the Si pillars 7a, 7b are formed in a rectangular shape in a plan view. However, the shape in a plan view may be rounded at both ends in a direction perpendicular to the XX' line, or may be circular or elliptical.

[0041] In FIG. 1F, the thickness of the TiN layer 15, which is to be the gate conductor layer, is thicker than the SiN layers 17a and 17b. In contrast, the thickness of the TiN layer 15 is thinner than the SiN layers 17a and 17b, and a single layer or multiple layers of conductors or insulating materials such as a conductor layer such as TaN or an insulating layer such as a SiN layer may be provided on the outside of the TiN layer 15 as a protective layer for the TiN layer 15. In this case, in the process of forming the gate TiN layers 15a and 15b in FIG. 1G, the side surfaces of the gate TiN layers 15a and 15b are surrounded and left as protective layers. When an insulating protective layer such as a SiN layer is formed, the insulating protective layer on the top side surfaces of the gate TiN layers 15a and 15b is removed before forming the W layer 26 in FIG. 1J.

[0042] In addition, the N formed at the tops of the Si pillars 7a and 7b + Layer 30a, P +The layer 30b is, for example, an N epitaxially grown layer on the P layer 4 in FIG. 1B after the P layer 4 is formed. + layer, P + In this case, a heat treatment is performed as shown in FIG. 1K to form a N + Layer 29a, P + The donor or acceptor impurities are thermally diffused from the layer 29b to the tops of the Si pillars 7a and 7b to form N + Layer 30a, P + When the SiO2 layer 28 is thick, the N + Layer 30a, P + If a long heat treatment is performed at a high temperature so that the lower end of the layer 30b becomes the upper end of the gate TiN layers 15a, 15b, damage to the gate TiN layers 15a, 15b and the HfO2 layer 14, which is a gate insulating layer, becomes a problem. + layer, N + These P + layer, N + The layer provides N + Layer 30a, P + In this way, it is possible to avoid thermal damage to the gate TiN layers 15a and 15b and the HfO2 layer 14, which is the gate insulating layer. In addition, at the stage of FIG. 1K, N + Layer 30a, P + Since there is no need to form the layer 30b, it is easy to form the impurity regions at the tops of the Si pillars 7a and 7b. + Layer 29a, P + The layer 29b may or may not be formed. + Layer 29a, P + Layer 29b may be replaced by a conductive layer such as a metal or alloy. In addition, the W layer 22 is directly + Layer 3aa, P + The N-type junction between the Si pillars 7a and 7b was formed on the layer 3bb. + Layer 3aa, P +Alternatively, the W layer 22 may be formed on the bottom of the W layer 22 after a conductor layer made of a metal or an alloy is formed on the top surface of the layer 3bb. + Layer 3aa, P + A conductive layer may be formed to reduce the contact resistance with the layer 3bb.

[0043] In the description of this embodiment, Si pillar 7a forming N-channel SGT and Si pillar 7b forming P-channel SGT have the same length in a direction perpendicular to line X-X' in plan view. In contrast, the length of Si pillar 7a forming N-channel SGT in a direction perpendicular to line X-X' in plan view may be shorter than that of Si pillar 7b forming P-channel SGT. Furthermore, Si pillar 7a forming N-channel SGT and Si pillar 7b forming P-channel SGT may have different lengths in the direction X-X' in plan view.

[0044] This embodiment provides the following features. 1. In this embodiment, as shown in FIGS. 1H and 1I, after forming the TiN layers 15a and 15b which are gate electrodes, the contact hole 21 is formed, and then N + Layer 3aa, P + A bottom connection wiring W layer 22 connected to the layer 2bb is formed. Then, a SiO2 layer 24 containing voids 25 that effectively become a low dielectric constant layer is formed in the contact hole 21 on the W layer 22. Thereafter, as shown in Fig. 1J, an input wiring W layer 26 connected to the gate electrode TiN layers 15a, 15b is formed on the SiO2 layers 20a, 24a so as to be perpendicular to the bottom connection wiring W layer 22 in a plan view.

[0045] By carrying out the above steps, the following features are obtained. (1) The SiO2 layer 24a, which becomes a low dielectric constant layer by including the voids 25, and the bottom connection W layer 22 are formed in the contact hole 21, so that the input W layer 22 and the SiO2 layer 24a, which is a low dielectric constant layer, are formed in a self-aligned manner. This allows for high integration of the circuit. As shown in FIG. 1L, in the overlapping region of the bottom connection W layer 22 and the input wiring W layer 26 in a plan view, there is the SiO2 layer 24, which effectively becomes a low dielectric constant layer including the voids 25. This allows for a reduction in the capacitance between the bottom connection W layer 22 and the input wiring W layer 26. This allows for high performance of the circuit using the SGT. (2) The bottom-connection W layer 26 connected to the input wiring metal layer Vin is connected only to the upper portions of the gate electrodes 15a and 15b in the height direction. For example, compared to a structure in which the bottom-connection W layer 26a connected to the input wiring metal layer Vin is formed at the same height as the gate electrodes 15a and 15b, the capacitance between the input wiring metal layer Vin and the input wiring metal layer Vin can be significantly reduced.

[0046] 2. In this embodiment, as shown in FIG. 1E, in plan view, the P layer base 12 is + Layer 3aa, P + Outside the layer 3bb, a portion surrounding the Si pillars 7a, 7b is formed in a protruding shape. This protruding portion is formed by self-alignment with the Si pillars 7a, 7b. This self-alignment allows the protruding P layer base 12 to be formed with high precision and in a small area. This allows for high integration of circuits using SGT.

[0047] 3. In this embodiment, as shown in Fig. 1F and Fig. 1G, the TiN layers 15a and 15b serving as the gate electrodes are formed by self-alignment with the Si pillars 7a and 7b. As shown in Fig. 1J, the W layer 26 is connected to a part of the outer periphery of the gate electrode TiN layers 15a and 15b and is formed in a band shape in the X-X' direction. In plan view, the width of the W layer 26 in the direction perpendicular to the X-X' line is formed to be smaller than the length of the outer periphery long side of the TiN layers 15a and 15b.

[0048] By carrying out the above steps, the following features are obtained. (1) The W layer 26 is formed separately from the gate line TiN layers 15a, 15b, using the mask material layer 27 as an etching mask. This allows the width of the W layer 26a in the direction perpendicular to the X-X' line to be as small as possible while still satisfying the condition that the W layer 26 and the gate line TiN layers 15a, 15b are connected. This allows the capacitance between the W layer 26 and the bottom connection W layer 22 to be further reduced. The gate TiN layers 15a, 15b are formed in self-alignment with the Si pillars 7a, 7b. This allows for further integration of circuits using SGT.

[0049] Second embodiment Hereinafter, with reference to FIG. 2, a method for manufacturing an inverter circuit according to a second embodiment of the present invention will be described. In FIG. 2, (a) is a plan view, and (b) is a cross-sectional view taken along the X-X' line in (a). In the first embodiment, a Si pillar 7a forming an N-channel SGT and a Si pillar 7b forming a P-channel SGT are formed on both sides of the bottom connection wiring W layer 22 in the X-X' line direction. In this embodiment, two Si pillars, an N-channel SGT and a P-channel SGT, are arranged in a direction perpendicular to the X-X' line direction, and a W layer corresponding to the bottom connection wiring W layer 22 is formed adjacent to these two Si pillars in a plan view and extending in a direction perpendicular to the X-X' line direction. In this embodiment, a method for manufacturing an inverter circuit in which two N-channel SGTs and two P-channel SGTs are connected in parallel is shown. This manufacturing method is basically the same as that of the first embodiment.

[0050] 2, Si pillars 7A, 7B, 7C, and 7D having rectangular shapes in plan view are formed on a P-layer substrate 1A. Then, the upper part of the P-layer substrate 1A, the N layer 2A, and the P + Layer 3A,N + The semiconductor base 12a is formed of the layer 3B. + The layer 3A is located under the Si pillars 7A and 7B, and the N + The layer 3B is located under the Si pillars 7C and 7D. + Layer 3A,N+ The SiO2 layer 13A is formed so as to be at the upper surface position of the layer 3B. Then, the gate insulating layer 14a is formed surrounding the Si pillars 7A to 7D. Then, the gate TiN layers 15A, 15B, 15C, and 15D are formed surrounding the gate insulating layer 14a on the side surfaces of the Si pillars 7A to 7D. Then, the SiO2 layer 20A, whose upper surface position is lower than the upper ends of the gate TiN layers 15A, 15B, 15C, and 15D, is formed surrounding the gate TiN layers 15A, 15B, 15C, and 15D. Then, in plan view, the P + Layer 3A,N + A contact hole (not shown) is formed on the layer 3B, extending in a strip shape in a direction perpendicular to the line XX'. + Layer 3A,N + Bottom connection wiring W layers 22a and 22b are formed connected to the layer 3B. The bottom connection wiring W layer 22a is formed between the gate TiN layers 15A and 15C and the gate TiN layers 15A and 15C in a plan view.

[0051] Then, as shown in FIG. 2, the contact holes on the bottom connection wiring W layers 22a, 22b are filled to form SiO2 layers 24a, 24b having holes 25a, 25b and having upper surfaces lower than the upper end surfaces of the gate TiN layers 15A to 15D. Then, a wiring conductor W layer 26a connected to the gate TiN layers 15A, 15B and extending in the X-X' direction, a wiring conductor W layer 26b connected to the gate TiN layers 15A, 15C and extending in a direction perpendicular to the X-X' line, and a wiring conductor W layer 26c connected to the gate TiN layers 15B, 15D are formed. Then, the tops of the Si pillars 7A to 7D are exposed, and a SiN layer 28a is formed on the outer periphery thereof. Then, for example, by selective epitaxial growth, the tops of the Si pillars 7A, 7B are covered with P + The layers 29A and 29B are formed to cover the tops of the Si pillars 7C and 7D. + Then, layers 29C (not shown) and 29D (not shown) are formed on the tops of the Si pillars 7A to 7D by thermal diffusion. + Layer 30A, 30B, P + Layers 30C (not shown) and 30D (not shown) are then formed. +Layers 29A, 29B, P + W layers 32A, 32B, 32C (not shown), and 32D (not shown) are formed on layers 29C and 29D. Then, an input wiring metal layer Vin is formed connected to W layer 26a via contact hole C4. Then, a power wiring metal layer Vdd is formed connected to W layers 32A and 32B via contact holes C5a and C5b. Then, an output wiring metal layer Vout is formed connected to W layers 22a and 22b via contact holes C6a and C6b. Then, an earth wiring metal layer Vss is formed connected to W layers 32C and 32D via contact holes C7a and C7b. As a result, an inverter circuit in which two P-channel SGTs and two N-channel SGTs are connected in parallel is formed on P-layer substrate 1A.

[0052] As described above, in an inverter circuit in which a P-channel SGT and an N-channel SGT are connected in parallel, the drive current of the inverter circuit can be increased by increasing the number of P-channel SGTs and N-channel SGTs connected in parallel.

[0053] The gate TiN layers 15A to 15D are electrically connected by the W layers 26a to 26c. Thus, the W layer 26a connected to the input wiring metal layer Vin may be provided anywhere in the direction perpendicular to the XX' line direction in a plan view, as long as it is connected to the gate TiN layers 15A and 15B or the gate TiN layers 15C and 15D.

[0054] In the description of this embodiment, the semiconductor base 12a has a P + Tiers 3A and N + The semiconductor base 12a is connected to the layer 3B. + A first semiconductor base having a layer 3A, and a N + The second semiconductor substrate 3B may be formed separately. In this case, the W layers 22a and 22b are P + Tiers 3A and N + A semiconductor layer 13A is formed between the semiconductor layer 3A and the upper surface of the SiO2 layer 13A.

[0055] In addition, if the wiring resistance of the W layer 26a needs to be reduced for circuit performance reasons, multiple contact holes may be provided in the SiO2 layer 33a on the W layer 26a, and a wiring metal layer connected to the input wiring metal layer Vin through these contact holes may be formed.

[0056] This embodiment provides the following features. 1. As in the first embodiment, the W layers 22a and 22b formed on the semiconductor base and the W layer 26a that is perpendicular to and overlaps them in a plan view are formed apart in the vertical direction, thereby reducing the capacitance between the input wiring metal layer Vin and the output wiring metal layer Vout. Furthermore, as in the first embodiment, the SiO2 layers 24a and 24b, which are effectively low dielectric layers having voids 25a and 25b formed by self-alignment on the W layers 22a and 22b, further reduce the capacitance between the input wiring metal layer Vin and the output wiring metal layer Vout. 2. In this embodiment, the Si pillar 7A of the P-channel SGT and the Si pillar 7C of the N-channel SGT are arranged in a direction perpendicular to the X-X' line to form a first inverter circuit. Similarly, the Si pillar 7B of the P-channel SGT and the Si pillar 7D of the N-channel SGT are arranged in a direction perpendicular to the X-X' line to form a second inverter circuit. For example, when an inverter ring oscillator circuit is formed using these two inverter circuits, the coupling capacitance between the input electrode of the first inverter circuit (in this case, the gate TiN layers 15A and 15C) and the input electrode of the second inverter circuit (in this case, the gate TiN layers 15B and 15D) becomes a problem. In contrast, this coupling capacitance can be reduced by providing the SiO2 layer 24a, which is essentially a low dielectric layer, between the gate TiN layers 15A and 15C and the gate TiN layers 15B and 15D as in this embodiment.

[0057] Third embodiment Hereinafter, a method for manufacturing an inverter circuit according to the third embodiment of the present invention will be described with reference to Fig. 3. In Fig. 3, (a) is a plan view, and (b) is a cross-sectional view taken along line XX' in (a).

[0058] In the second embodiment, as shown in FIG. 2, the input wiring metal layer Vin is connected to the W layer 26a connected to the long side of the gate TiN layers 15A and 15B in a direction perpendicular to the X-X' line in a plan view through a contact hole C4. In contrast, in the present embodiment, as shown in FIG. 3, contact holes C4a and C4b are formed on the W layer 26b connecting the gate TiN layers 15A and 15C arranged in a direction perpendicular to the X-X' line in a plan view and the W layer 26c connecting the gate TiN layers 15B and 15D. Then, the input wiring metal layer VIN is connected to the W layers 26b and 26c through the contact holes C4a and C4b. As a result, an inverter circuit in which two P-channel SGTs and two N-channel SGTs are connected in parallel is formed on the P-layer substrate 1A. Other than the above, this inverter circuit is formed in the same process as FIG. 2.

[0059] This embodiment provides the following features. In the second embodiment, in the overlapping portion of the W layers 22a, 22b and the W layer 26a in plan view, there is a SiO2 layer 24a including voids 25a, 25b between the W layers 22a, 22b and the W layer 26a. In contrast, in the third embodiment, in plan view, the W layers 22a, 22b overlap with the input wiring metal layer VIN. In this overlapping portion, there are a SiO2 layer 24a including voids 25a, 25b and SiO2 layers 28a, 33a between the W layers 22a, 22b and the input wiring metal layer VIN. As a result, in the third embodiment, the capacitance between the input wiring metal layer VIN and the output wiring metal layer Vout can be reduced.

[0060] (Other embodiments) In the first embodiment, for example, a N junction serving as a source or drain at the bottom of one SGT formed in the Si pillar 7a is +The third embodiment has a feature that the W layer 22 connected to the layer 3aa and the W layer 26 connected to the gate TiN layer 15a overlap in plan view through the SiO2 layer 24 which is an effective low dielectric constant layer. Similarly, in the third embodiment, the input wiring metal layer VIN connected to the gate TiN layer 15A through the W layer 26b is characterized in that it overlaps in plan view through the SiO2 layer 24a, SiO2 layers 28a, 33a which are effective low dielectric constant layers. The present invention can be applied to other logic using SGT, or other circuits such as selector elements and peripheral circuits of DRAM (Dynamic Random Access Memory), PCM (Phase Change Memory), MRAM (Magnetic Random Access Memory), and RRAM (Resistive Random Access Memory) as long as it has the above features. This is also the case in the second embodiment.

[0061] In the first embodiment, the Si pillars 7a and 7b are formed, but the semiconductor pillars may be made of a semiconductor material other than Si. This also applies to the other embodiments of the present invention.

[0062] In addition, in the first embodiment, N + Layer 3aa, P + The layer 3bb may be formed of Si or other semiconductor material layers containing donor impurities or acceptor impurities. + Layer 3aa, 29a, P + The layers 3bb and 29b may be made of different semiconductor materials, as is the case in other embodiments of the invention.

[0063] In the description of the first embodiment, the N + Layer 30a, P + The layer 30b is, for example, an N epitaxially grown layer on the P layer 4 in FIG. 1B after the P layer 4 is formed. + layer, P + It was mentioned that layers may be used. + layer, P+ The layers may be formed by methods other than epitaxial crystal growth, as is the case in other embodiments of the present invention.

[0064] In the first embodiment, the inverter circuit has been described. + Layer 29b, 30b, N + Layers 29a and 30a serve as the source, and P + Layer 3bb, N + Although layer 3aa acts as a drain, the upper and lower impurity layers of each SGT can act as a source or drain depending on the circuit being fabricated, as in other embodiments of the present invention.

[0065] In addition, the mask material layers 5a, 5b, 11, and 27 used in the first embodiment may be made of other materials including organic materials or inorganic materials consisting of a single layer or multiple layers, as long as the materials are suitable for the purpose of the present invention. Similarly, the SiO2 layer 9a and the SiN layers 10a and 10b used as the etching masks may be made of other materials including organic materials or inorganic materials consisting of a single layer or multiple layers, as long as the materials are suitable for the purpose of the present invention. This also applies to the other embodiments of the present invention.

[0066] In the first embodiment, the material of the W layer 22 may be not only a metal but also a conductive material such as an alloy, an alloy containing a large amount of acceptor or donor impurities, or a semiconductor layer, and may be configured as a single layer or a combination of multiple layers. This is the same in the other embodiments of the present invention.

[0067] In the first embodiment, TiN layers 15a and 15b are used as gate conductor layers. The TiN layers 15a and 15b may be made of a single or multiple layer material as long as the material is suitable for the purpose of the present invention. The TiN layers 15a and 15b may be made of a conductor layer such as a single or multiple metal layer having at least a desired work function. Other conductive layers such as a W layer may be formed on the outside of the TiN layers. A single or multiple metal layer may be used other than the W layer.

[0068] In the first embodiment, the W layer 26 connected to the TiN layers 15a and 15b may be laminated with another conductive layer or may be formed from another conductive layer. This also applies to the other embodiments of the present invention.

[0069] Although the HfO2 layer 14 is used as the gate insulating layer, other material layers each consisting of a single layer or multiple layers may be used as the gate insulating layer. This also applies to the other embodiments of the present invention.

[0070] 1H and 1I of the first embodiment, a SiO2 layer 24 having voids 25 is formed. Alternatively, the upper part of the contact hole 21 may be covered with a SiN layer by, for example, a CVD (Chemical Vapor Deposition) method to form the voids 25. Alternatively, an insulating layer made of an inorganic or organic layer having voids 25 may be formed by another method.

[0071] In the first embodiment, the shape of the Si pillars 7a, 7b in plan view is rectangular. The shape of these Si pillars in plan view may be not only rectangular but also circular, elliptical, or square. Furthermore, a mixture of these shapes may be formed on the same P layer substrate 1a. This also applies to the other embodiments of the present invention.

[0072] In the first embodiment, an inverter circuit consisting of one N-channel SGT and one P-channel SGT has been described, but in order to obtain a large drive current or to reduce the effective SGT series resistance, a plurality of N-channel and P-channel SGTs may be connected in parallel, which is also the case in the other embodiments of the present invention.

[0073] In addition, the present embodiment has been described with respect to an inverter circuit. In contrast, the impurity region (N + Layer 3aa, or P+ The present invention is also applicable to a circuit using an SGT in which a conductor layer (W layer 22 in the first embodiment) extending in a strip shape in the first direction and connected to a gate conductor layer (TiN layer 15a or TiN layer 15b in the first embodiment) and a wiring conductor layer (W layer 26 in the first embodiment) connected to a gate conductor layer (TiN layer 15a or TiN layer 15b in the first embodiment) and perpendicular to the first direction are formed to overlap each other in a planar view.

[0074] In the embodiment according to the present invention, one SGT is formed in one semiconductor pillar, but the present invention can also be applied to a circuit formation in which two or more SGTs are formed.

[0075] In the first embodiment, the SGT is formed on the P-layer substrate 1, but an SOI (Silicon On Insulator) substrate may be used instead of the P-layer substrate 1. Alternatively, a substrate made of another material may be used as long as it functions as a substrate. This also applies to the other embodiments of the present invention.

[0076] In the first embodiment, N + Layer 3aa, 29a, 30a, P + Although the SGT in which the layers 3bb, 29b, and 30b form the source and drain have been described, the present invention can also be applied to a tunnel-type SGT having a source and drain with different polarities, and this also applies to other embodiments of the present invention.

[0077] In addition, the present invention allows various embodiments and modifications without departing from the broad spirit and scope of the present invention. The above-described embodiment is intended to explain one example of the present invention and does not limit the scope of the present invention. The above-described embodiments and modifications can be combined in any combination. Furthermore, even if some of the constituent elements of the above-described embodiment are omitted as necessary, the present invention will still be within the scope of the technical idea of ​​the present invention. [Industrial Applicability]

[0078] According to the method for manufacturing a pillar-shaped semiconductor device of the present invention, a high-density, high-performance pillar-shaped semiconductor device can be obtained. [Explanation of symbols]

[0079] 1, 1a, 1A: P layer board 2a, 2b, 2aa, 2bb, 29a, 29b, 29c, 29d, 30a, 30b, 30c, 30d: N + layer 4: P layer 2A: N layer 3A: P + layer 5a, 5b, 5c, 5d, 11a, 11b, 27: Mask material layer 7a, 7b, 7c, 7d, 7A, 7B, 7C, 7D: Si pillar 9, 9a, 9b, 17a, 17b, 17c, 17d,: SiN layer 10a, 10b, 10c, 10d, 13, 13A, 16, 20, 20a, 20A, 24a, 24b, 24aa, 24bb, 28, 28a, 33, 33a: SiO2 layer 12, 12a: Semiconductor board 14, 14A: HfO2 layer 15, 15a, 15b, 15A, 15B, 15C, 15D: TiN layer 21a, 21b, C1, C2a, C2b, C3, C4, C4a, C4b, C5a, C5b, C6a, C6b, C7a, C7b: contact holes 22a, 22b, 26a, 26b: W layer 25, 25a, 25b: Holes Vin, VIN: Input wiring metal layer Vout: Output wiring metal layer Vdd: Power supply wiring metal layer Vss: Ground wiring metal layer

Claims

1. A method for manufacturing a pillar-shaped semiconductor device, comprising: a first impurity region at the bottom of a first semiconductor pillar standing vertically to a substrate; and a second impurity region at the top of the semiconductor pillar as a source or drain; the first semiconductor pillar between the first impurity region and the second impurity region as a channel; a first gate insulating layer surrounding the first semiconductor pillar between the first impurity region and the second impurity region; and a first gate conductor layer surrounding the gate insulating layer, forming the first impurity region so as to extend in a band shape in a first direction in a plan view; forming the first semiconductor pillar overlapping the first impurity region in a plan view; forming a first semiconductor base including the first semiconductor pillar and the first impurity region in a plan view, the first semiconductor base extending in a strip shape in the first direction and connected to a bottom of the first semiconductor pillar; forming the first gate insulating layer and the first gate conductor layer surrounding the first semiconductor pillar; forming a first insulating layer on an outer periphery of the first gate conductor layer; forming a contact hole in the first insulating layer, the contact hole overlapping the first impurity region in the first semiconductor base in a plan view, the bottom of the contact hole being in contact with the first impurity region, and extending in a strip shape in the first direction; forming a first conductor layer extending in a strip shape in the first direction at a bottom of the contact hole and in contact with the first impurity region; forming a second insulating layer in the contact hole on the first conductor layer, the second insulating layer including voids or made of a low dielectric constant material; a step of lowering a top surface position of the second insulating layer below a top end of the first gate conductor layer; forming a second conductor layer in contact with the first gate conductor layer and extending in a strip shape in a second direction perpendicular to the first direction in a plan view; 2. A method for manufacturing a pillar-shaped semiconductor device comprising the steps of:

2. forming the first semiconductor pillar using the first mask material layer as an etching mask; forming a third insulating layer surrounding the first semiconductor pillar and having an upper surface located at a bottom of the first mask material layer or at a top of the first semiconductor pillar in a direction perpendicular to the substrate; forming a second mask material layer on the third insulating layer, the second mask material layer surrounding the exposed first mask material layer and the top of the first semiconductor pillar with an equal width in a plan view; forming a third mask material layer on the third insulating layer, the third mask material layer partially overlapping the second mask material layer in a plan view and extending in a strip shape in the first direction; forming the first semiconductor base by etching the third insulating layer and the first impurity region using the first mask material layer, the second mask material layer, and the third mask material layer as a mask; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1, further comprising:

3. a width of the second conductor layer in the first direction in a plan view is smaller than the longest line segment among distances between two points where a perimeter line of the first gate conductor layer intersects with a straight line extending in the first direction; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1,

4. an upper end position of the first conductor layer is formed lower than a lower end position of the gate conductor layer in a direction perpendicular to the substrate; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1,

5. an upper end position of the hole is formed lower than an upper end position of the gate conductor layer in a direction perpendicular to the substrate; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1,

6. forming a second semiconductor pillar on the first semiconductor platform in a direction opposite to the first semiconductor pillar with respect to the first conductor layer in the second direction in a plan view; forming a second gate insulating layer surrounding the second semiconductor pillar; forming a second gate conductor layer surrounding the second gate insulating layer; forming the second conductor layer, in a plan view, extending in the second direction and connected to an upper end of the second gate conductor layer; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1, further comprising:

7. forming a third impurity region in the first semiconductor base and adjacent to the first impurity region in the first direction in a plan view; forming a third semiconductor pillar on the third impurity region; forming a third gate insulating layer surrounding the third semiconductor pillar; forming a third gate conductor layer surrounding the third gate insulating layer; forming the second conductor layer so as to extend in the first direction and to be in contact with the third impurity region in a plan view; forming a third conductor layer extending in the second direction in a plan view and connected to the first gate conductor layer and an upper portion of the third gate conductor layer; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1, further comprising:

8. forming a first impurity layer on the substrate, the first impurity region being a base thereof; forming a first semiconductor layer on the first impurity layer, the first semiconductor layer being a part of a body of the first semiconductor pillar; forming a second impurity layer on the first semiconductor layer, the second impurity layer being a part of a body of the first semiconductor pillar and being at least a part of the second impurity region; 2. The method for manufacturing a pillar-shaped semiconductor device according to claim 1, further comprising:

9. forming a third impurity layer of the same polarity, or a conductive layer made of an alloy or a metal, on the second impurity region; 9. The method for manufacturing a pillar-shaped semiconductor device according to claim 8, further comprising:

10. a first semiconductor pillar standing perpendicular to a substrate; a first impurity region connected to a bottom of the first semiconductor pillar and extending in a strip shape in a first direction; a second impurity region at the top of the first semiconductor pillar; a first gate insulating layer surrounding the first semiconductor pillar between the first impurity region and the second impurity region; a first gate conductor layer surrounding the first gate insulating layer; a semiconductor base that is connected to a bottom of the first semiconductor pillar, includes the first impurity region, and extends in a strip shape in the first direction in a plan view; a first insulating layer on an outer periphery of the first gate conductor layer; a first material layer in the first insulating layer, the first material layer overlapping the first impurity region in the semiconductor base in a plan view, the first material layer having a bottom portion in contact with the first impurity region, the first material layer extending in a strip shape in the first direction, and the first material layer being connected in a vertical direction; a first conductor layer extending in a strip shape in the first direction at a bottom of the first material layer and in contact with the first impurity region; a second insulating layer, the first material layer being on the first conductor layer, the top surface of which is lower than the top end of the first gate conductor layer, the second insulating layer including voids or made of a low dielectric constant material; a second conductor layer connected to the first gate conductor layer and extending in a strip shape in a second direction perpendicular to the first direction in a plan view; The pillar-shaped semiconductor device, wherein, in a plan view, the first conductor layer and the second conductor layer overlap each other at an intersection.

11. the second conductor layer is in contact with and connected to the first gate conductor layer; a width of the second conductor layer in the first direction in a plan view is smaller than the longest line segment among distances between two points where a perimeter line of the first gate conductor layer intersects with a straight line extending in the first direction; The pillar-shaped semiconductor device according to claim 10 .

12. In a direction perpendicular to the substrate, an upper end position of the first conductor layer is lower than a lower end position of the first gate conductor layer. The pillar-shaped semiconductor device according to claim 10 .

13. a second semiconductor pillar on the semiconductor base in a direction opposite to the first semiconductor pillar with respect to the first conductor layer in the second direction in a plan view; a second gate insulating layer surrounding the second semiconductor pillar; a second gate conductor layer surrounding the second gate insulating layer; the second conductor layer extending in the second direction and connected to an upper end of the second gate conductor layer in a plan view; The pillar-shaped semiconductor device according to claim 10 , comprising:

14. A third impurity region is disposed on the semiconductor base and is adjacent to the first impurity region in the first direction in a plan view. a third semiconductor pillar on the third impurity region; a third gate insulating layer surrounding the third semiconductor pillar; a third gate conductor layer surrounding the third gate insulating layer; In a plan view, the first conductor layer extends in the first direction and is adjacent to the third semiconductor pillar; a third conductor layer extending in the first direction in a plan view and connected to the first gate conductor layer and an upper portion of the third gate conductor layer; The pillar-shaped semiconductor device according to claim 10 , further comprising:

15. a second insulating layer on the third conductor layer; and a first contact hole in the second insulating layer on the third conductor layer; the second conductor layer on the second insulating layer and connected to the third conductor layer through the first contact hole; The pillar-shaped semiconductor device according to claim 14 , further comprising:

16. 11. The pillar-shaped semiconductor device according to claim 10, further comprising a third impurity layer of the same polarity, or a conductive layer made of an alloy or a metal, on said second impurity region.

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