Printed circuit board and its manufacturing method

Abstract

To provide a printed circuit board which incorporates a bridge including a high-density circuit layer, and a method for manufacturing the same.SOLUTION: The present invention relates to the printed circuit board including: a substrate part having a recess portion and including a first circuit layer; a bridge arranged in the recess portion and including an insulating layer and a bridge circuit layer; an insulating material filling at least a part of the recess portion and covering at least a part of the bridge; a second circuit layer arranged on the insulating material; and a first via penetrating through the insulating material and a part of the bridge and connecting the second circuit layer and the bridge circuit layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a printed circuit board and a method for manufacturing the same. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, multi-chip packages including memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array) are being used to process data that has increased exponentially.

[0003] Meanwhile, a technology is being developed in which a bridge including a fine circuit is embedded in a printed circuit board used in a multi-chip package to electrically connect semiconductor chips mounted on the board. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENTS One of several objects of the present invention is to provide a printed circuit board having an embedded bridge that includes a high density circuit layer and a method for manufacturing the same.

[0005] Another object of the present invention is to provide a printed circuit board and a method for manufacturing the same, which can minimize electrical connection paths by directly connecting a circuit layer of the printed circuit board and a bridge circuit layer of a bridge built into the printed circuit board. [Means for solving the problem]

[0006] A printed circuit board according to an example provided by the present invention may be a printed circuit board including: a substrate portion having a recessed portion and including a first circuit layer; a bridge disposed in the recessed portion and including an insulating layer and a bridge circuit layer; an insulating material filling at least a portion of the recessed portion and covering at least a portion of the bridge; a second circuit layer disposed on the insulating material; and a first via penetrating the insulating material and a portion of the bridge to connect the second circuit layer and the bridge circuit layer.

[0007] A method for manufacturing a printed circuit board according to an example provided by the present invention may include the steps of: forming a recess in a substrate including a first circuit layer; disposing a bridge including an insulating layer and a bridge circuit layer in the recess; forming an insulating material that fills at least a portion of the recess and covers at least a portion of the bridge; and forming a first via that penetrates the insulating material and a portion of the bridge and is connected to the bridge circuit layer. Effect of the Invention

[0008] Among the several advantages of the present invention is the ability to provide a printed circuit board having an embedded bridge that includes a high density circuit layer, and a method for manufacturing the same.

[0009] Another advantage of the present invention is that it is possible to provide a printed circuit board and a method for manufacturing the same, which can minimize electrical connection paths by directly connecting a circuit layer of the printed circuit board and a bridge circuit layer of a bridge built into the printed circuit board. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] 1 is a cross-sectional view illustrating an example of a printed circuit board according to the present invention. [Figure 4]1A, 1C, and 1E are enlarged cross-sectional views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention, and 1B, 1C, and 1E are enlarged plan views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention. [Diagram 5] 1A, 1C, and 1E are enlarged cross-sectional views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention, and 1B, 1C, and 1E are enlarged plan views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention. [Figure 6] 1A, 1C, and 1E are enlarged cross-sectional views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention, and 1B, 1C, and 1E are enlarged plan views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention. [Figure 7] 10(a) to 10(d) are enlarged plan views each showing a schematic diagram of a modified example of a first circuit layer region disposed on a bottom surface of a recessed portion of a printed circuit board according to the present invention. [Figure 8] 10(a) to 10(d) are enlarged plan views each showing a schematic diagram of a modified example of a first circuit layer region disposed on a bottom surface of a recessed portion of a printed circuit board according to the present invention. [Figure 9a] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9b] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9c] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9d] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9e] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9f] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9g] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9h] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9i] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 9j] 2A to 2C are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention; [Figure 10a] 4 is a diagram illustrating an example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 10b] 4 is a diagram illustrating an example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 10c] 4 is a diagram illustrating an example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 10d] 4 is a diagram illustrating an example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11a] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11b] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11c] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11d] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11e] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11f] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 11g] 5 is a diagram illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of the printed circuit board according to the present invention. [Figure 12] 2 is a cross-sectional view illustrating another example of a printed circuit board according to the present invention. [Figure 13] 4 is a cross-sectional view illustrating another example of a printed circuit board according to the present invention. FIG. [Figure 14] 4 is a cross-sectional view illustrating another example of a printed circuit board according to the present invention. FIG. [Figure 15] 4 is a cross-sectional view illustrating another example of a printed circuit board according to the present invention. FIG. [Figure 16] 1 is a cross-sectional view illustrating an example of a multi-chip package in which a plurality of semiconductor chips are mounted on a printed circuit board according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will be described in detail below with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clarity.

[0012] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0013] 1, an electronic device 1000 includes a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components described below to form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0015] The network-related components 1030 include, but are not limited to, Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated thereafter, as well as any of numerous other wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020.

[0016] The other components 1040 include, but are not limited to, high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Capacitors), etc., and may also include passive components in the form of chip components used for various other applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. The other electronic components may include, but are not limited to, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), and a digital versatile disk (DVD). It goes without saying that the electronic device 1000 may include other components for various purposes depending on the type of electronic device 1000.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0019] FIG. 2 is a perspective view illustrating an example of an electronic device. Referring to FIG. 2, the electronic device may be, for example, a smartphone 1100. A main board 1110 is housed inside the smartphone 1100, and various electronic components 1120 are physically and / or electrically connected to the main board 1110. In addition, other electronic components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the main board 1110, are housed inside the smartphone 1100. A part of the electronic components 1120 may be the above-mentioned chip-related components, for example, a semiconductor package 1121, but is not limited thereto. The semiconductor package 1121 may be in a form in which a semiconductor chip, a passive component, and the like are surface-mounted on a package substrate in the form of a multi-layer electronic component embedded substrate, but is not limited thereto. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0020] Printed Circuit Board FIG. 3 is a cross-sectional view illustrating an example of a printed circuit board according to the present invention.

[0021] 3, the printed circuit board 100A according to an example includes a core substrate part 110, a first substrate part 120A, a second substrate part 120B, a bridge 130, an insulating material 151, a third circuit layer 152, a first via 153A, a second via 153B, and a third via 153C. However, the printed circuit board 100A according to an example may include only some of the first via 153A, the second via 153B, and the third via 153C. It should be noted in advance that the core substrate part 110 and the second substrate part 120B are optional additional components, as in the printed circuit board according to another example described below.

[0022] The core substrate part 110 may include a core layer 111, core circuit layers 112 disposed on both sides of the core layer 111, and through vias 113 that penetrate the core layer 111 and connect the core circuit layers 112 disposed on both sides of the core layer 111 to each other. Although the core layer 111 is shown as a single layer in the drawings, the printed circuit board may have a multi-layer core substrate structure in which a plurality of core layers 111 are stacked depending on the design.

[0023] The core layer 111 can play a role of suppressing warpage of the substrate by improving the rigidity of the substrate. The core layer 111 can have a thickness greater than each of the first insulating layer 121A and the second insulating layer 121B. The material for forming the core layer 111 is not particularly limited, and any material having insulating properties can be used. For example, a copper clad laminate (CCL) or an unclad copper clad laminate (Unclad CCL) can be used. Alternatively, the core layer 111 can be made of other types of materials such as a glass substrate or a ceramic substrate, but is not limited thereto.

[0024] The core circuit layer 112 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc., depending on the design. The core circuit layer 112 may be formed from a conductive material, such as a known metal material that can be used for a circuit layer.

[0025] A conductive material may also be used as a material for forming the through via 113. The through via 113 may be completely filled with the conductive material, or the conductive material may be formed along the wall of the via hole. When the through via 113 is formed with the conductive material formed along the wall of the via hole, the inside of the via hole may be filled with an insulating material.

[0026] The first substrate unit 120A has a recessed portion 121h and may include a first insulating layer 121A, a first circuit layer 122A embedded in the first insulating layer 121A, and a first via layer 123A embedded in the first insulating layer 121A and connecting the first circuit layers 122A arranged in different layers. In this case, the number of the first insulating layer 121A, the first circuit layer 122A, and the first via layer 123A included in the first substrate unit 120A is not particularly limited.

[0027] As shown in the drawing, the first substrate portion 120A may be disposed on one surface of the core substrate portion 110, and may be disposed such that the surface opposite to the surface on which the recessed portion 121h is formed faces the core substrate portion 110.

[0028] The recessed portion 121h penetrates at least a portion of the first insulating layer 121A. As shown in the drawings, the recessed portion 121h may have a shape in which the width narrows along the direction in which the recessed portion 121h penetrates the first insulating layer 121A, or may have a shape in which the width is constant along the direction in which the recessed portion 121h penetrates the first insulating layer 121A. A circuit pad included in the first circuit layer 122A may be disposed in at least a portion of the bottom surface of the recessed portion 121h, as will be described later.

[0029] The first insulating layer 121A may be formed by stacking a plurality of insulating layers. In this case, the boundaries between the plurality of insulating layers may be distinct, or the plurality of insulating layers may be integrated so that the boundaries between the plurality of insulating layers are not clear. The material for forming the first insulating layer 121A may be an insulating material, such as prepreg (PPG).

[0030] The first circuit layer 122A may be connected to at least one of the first circuit layer 122A, the core circuit layer 112, and the third circuit layer 152 arranged in other layers. The first circuit layer 122A may perform various functions according to the design. For example, the first circuit layer 122A may include a ground (GND) pattern, a power (PWR) pattern, a signal (Signal: S) pattern, etc. A conductive material may be used as a material for forming the first circuit layer 122A, for example, a known metal material that can be used for a circuit layer. The first circuit layer 122A may include a circuit pad arranged in at least a part of the bottom surface of the recessed portion 121h.

[0031] The first via layer 123A may penetrate a portion of the first insulating layer 121A to connect the first circuit layer 122A to the first circuit layer 122A and / or the core circuit layer 112 disposed in another layer. A conductive material may also be used as a material for forming the first via layer 123A, and a known shape such as a tapered shape or a cylindrical shape may be applied.

[0032] The second substrate portion 120B may include a second insulating layer 121B, a second circuit layer 122B embedded in the second insulating layer 121B, and a second via layer 123B embedded in the second insulating layer 121B and connecting the second circuit layers 122B arranged in different layers.

[0033] Second substrate part 120B may be disposed on the other surface of core substrate part 110, which is the surface opposite to the surface on which first substrate part 120A is disposed.

[0034] Meanwhile, unlike first substrate unit 120A, second substrate unit 120B does not need to have a recessed portion formed therein, and bridge 130 does not need to be disposed on the second substrate unit 120B side.

[0035] The descriptions of the first insulating layer 121A, the first circuit layer 122A, and the first via layer 123A can be substantially identically applied to the second insulating layer 121B, the second circuit layer 122B, and the second via layer 123B, respectively.

[0036] The bridge 130 is disposed on the first substrate portion 120A, and may be disposed in the recessed portion 121h as shown in the drawing. The bridge 130 may include an insulating layer 131 and a bridge circuit layer 132. There may be a plurality of bridge circuit layers 132, and there may also be a plurality of insulating layers 131. The bridge 130 serves to electrically connect a plurality of semiconductor chips mounted on the substrate to each other.

[0037] The insulating layer 131 may be an organic insulating layer, but is not limited thereto, and may be made of insulating materials such as glass, silicon, ceramic, etc. When the insulating layer 131 is an organic insulating layer, the bridge 130 can be manufactured through a known printed circuit board manufacturing process in which a plurality of insulating layers are laminated.

[0038] The bridge circuit layer 132 may be a high-density circuit layer, and may have a higher density than the first circuit layer 122A. Also, the bridge circuit layer 132 may have a higher density than the second circuit layer 122B. This allows the bridge circuit layer 132 to have finer circuits than the first circuit layer 122A and / or the second circuit layer 122B. The bridge circuit layer 132 may be in contact with the first via 153A, and may be connected to each of the third circuit layer 152 and the first circuit layer 122A through the first via 153A. Also, the bridge circuit layer 132 may be connected to the third circuit layer 152 through the second via 153B.

[0039] Meanwhile, the printed circuit board 100A according to an example may further include an adhesive layer 140 disposed between a bottom surface of the recessed portion 121h and the bridge 130. The adhesive layer 140 may serve to fix the bridge 130 to the bottom surface of the recessed portion 121h. In this case, the first via 153A may penetrate the insulating material 151 and the bridge 130 and further penetrate the adhesive layer 140. The adhesive layer 140 may be formed of a known tape or the like.

[0040] The insulating material 151 may fill at least a portion of the recessed portion 121h and cover at least a portion of the bridge 130. For example, the insulating material 151 may fill a space between the recessed portion 121h and the bridge 130 and extend onto the recessed portion 121h and the bridge 130 to cover one side of each of the recessed portion 121h and the bridge 130. The insulating material may be, for example, an Ajinomoto Build-up Film (ABF), but is not limited thereto.

[0041] The third circuit layer 152 may be disposed on the insulating material 151 and connected to at least one of the first circuit layer 122A and the bridge circuit layer 132. The third circuit layer 152 may include a ground (GND) pattern, a power (PWR) pattern, a signal (Signal: S) pattern, etc., depending on the design. The third circuit layer 152 may be formed of a conductive material, for example, a known metal material that can be used for a circuit layer.

[0042] Meanwhile, the printed circuit board 100A according to an example may include at least one of a first via 153A, a second via 153B, and a third via 153C.

[0043] The first via 153A may penetrate the insulating material 151 and the bridge 130 to connect the third circuit layer 152 to the first circuit layer 122A. In this case, the first via 153A may contact the third circuit layer 152 and the first circuit layer 122A to directly connect the third circuit layer 152 to the first circuit layer 122A. When the printed circuit board 100A according to an example further includes an adhesive layer 140, the first via 153A may further penetrate the adhesive layer 140. The first via 153A and the third circuit layer 152 may be integrated with each other or may be distinguished from each other by having a boundary therebetween.

[0044] In the printed circuit board 100A according to an example, the third circuit layer 152 and the first circuit layer 122A may be directly connected to each other through the first via 153A, thereby minimizing the electrical connection path between the third circuit layer 152 and the first circuit layer 122A.

[0045] The second via 153B may penetrate the insulating material 151 to connect the third circuit layer 152 and the bridge circuit layer 132 to each other. As shown in FIG. 15, when the second via 153B is connected to the bridge circuit layer 132 embedded inside the bridge 130, the second via 153B may penetrate the insulating material 151 and a part of the bridge 130. In this case, the second via 153B may penetrate the insulating material 151 and a part of the insulating layer 131. The second via 153B and the third circuit layer 152 may be integrated. However, the present invention is not limited thereto, and the second via 153B and the third circuit layer 152 may be distinguished from each other by having a boundary therebetween.

[0046] The third via 153C may penetrate the insulating material 151 and the first insulating layer 121A to connect the third circuit layer 152 and the first circuit layer 122A to each other. Unlike what is shown in the drawings, a part of the first circuit layer 122A may be exposed on the first insulating layer 121A and covered with the insulating material 151. In this case, the third via 153C may penetrate only the insulating material 151. The third via 153C and the third circuit layer 152 may be integrated. However, the present invention is not limited thereto, and the third via 153C and the third circuit layer 152 may be distinguished from each other by having a boundary therebetween.

[0047] A conductive material may also be used as a material for forming each of the first via 153A, the second via 153B, and the third via 153C, and a known shape such as a tapered shape or a cylindrical shape may be applied.

[0048] Meanwhile, the printed circuit board 100A according to an example may further include a protective layer 160 disposed on the insulating material 151 and having an opening exposing at least a portion of the third circuit layer 152. The protective layer 160 may be formed of an insulating material, for example, a solder resist.

[0049] In addition, the printed circuit board 100A according to an example may further include a connecting conductor 170 disposed on the protective layer 160 and connected to the third circuit layer 152. The connecting conductor 170 may be formed using a conductive material, for example, a conductive post and / or a solder ball.

[0050] Meanwhile, as shown in the drawing, at least one of an insulating material 151, a third circuit layer 152, a third via 153c, and a protective layer 160 may be disposed on the second substrate unit 120B as well. In this case, since the second substrate unit 120B does not have a recess, the insulating material 151 may be formed to cover one surface of the second substrate unit 120B. However, depending on the design, the insulating material 151 may not be disposed on the second substrate unit 120B, and the third circuit layer 152 may be disposed directly on the second insulating layer 121B.

[0051] Figures 4 to 6(a), (c), and (e) are enlarged cross-sectional views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention, and Figures 4 to 6(b), (d), and (f) are enlarged plan views illustrating a bridge circuit layer and a first via region of a printed circuit board according to the present invention.

[0052] 4(a) and 4(b) are a cross-sectional view and a plan view, respectively, showing an area of ​​a bridge circuit layer 132 and a first via 153A of a printed circuit board 100A according to an example.

[0053] Referring to the drawing, the bridge circuit layer 132 may include a bridge circuit pattern that contacts the side of the first via 153A.

[0054] The bridge circuit pattern may include an area having a hole. For example, the bridge circuit pattern may have a ring shape. In this case, when forming a via hole for forming the first via 153A, the via hole may penetrate an area corresponding to the hole of the bridge circuit pattern, and at least a part of the side of the bridge circuit pattern may be exposed. Thus, the first via 153A may fill the hole of the bridge circuit pattern, and the bridge circuit pattern may surround the side of the first via 153A in the area in contact with the side of the first via 153A.

[0055] 4(c) and 4(d) are a cross-sectional view and a plan view, respectively, showing the region of the bridge circuit layer 132 and the first via 153A according to a modified example of the embodiment.

[0056] When the diameter of the via hole is processed to be larger than the diameter of the hole of the bridge circuit pattern during via hole processing to form the above-mentioned first via 153A, one side of the bridge circuit pattern in the area where the via hole is formed can remain unprocessed. As a result, at least a part of one side of the bridge circuit pattern can be exposed through the via hole, and the first via 153A filling the via hole can cover the exposed side of the bridge circuit pattern. In this case, the exposed side of the bridge circuit pattern can be the side facing the third circuit layer 152.

[0057] Also, the via holes may be further processed along the periphery of the holes of the bridge circuit pattern, and since the bridge circuit pattern is not processed, the further processed lower via hole region may have a narrower width than the upper via hole region exposing the bridge circuit pattern.

[0058] 4(e) and 4(f) are a cross-sectional view and a plan view, respectively, showing the region of the bridge circuit layer 132 and the first via 153A according to a modified example of the embodiment.

[0059] As described above, the via hole may be further processed along the periphery of the hole of the bridge circuit pattern, and at this time, the further processed lower via hole region may have a larger diameter than the hole of the bridge circuit pattern, so that at least a portion of the bridge circuit pattern in contact with the side of the first via 153A may protrude into the via hole region.

[0060] 5(a) and 5(b) are a cross-sectional view and a plan view, respectively, showing a region of a bridge circuit layer 132 and a first via 153A according to another embodiment.

[0061] 4(a) and 4(b), in another embodiment, the bridge circuit layer 132 is not embedded in the insulating layer 131 but is disposed on one side of the insulating layer 131. In the structure shown in FIG.

[0062] 5(c) and 5(d) are a cross-sectional view and a plan view, respectively, showing the region of the bridge circuit layer 132 and the first via 153A according to a modified example of another embodiment.

[0063] 4(c) and 4(d), when the diameter of the via hole is processed to be larger than the diameter of the hole of the bridge circuit pattern during via hole processing to form the first via 153A, one side of the bridge circuit pattern in the area where the via hole is formed may remain unprocessed. As a result, at least a portion of one side of the bridge circuit pattern may be exposed through the via hole, and the first via 153A filling the via hole may cover the exposed side of the bridge circuit pattern. In this case, the exposed side of the bridge circuit pattern may be the side facing the third circuit layer 152.

[0064] 5(e) and 5(f) are a cross-sectional view and a plan view, respectively, showing a region of the bridge circuit layer 132 and a first via 153A according to a modified example of another embodiment.

[0065] As described above, the via hole may be further processed along the periphery of the hole of the bridge circuit pattern, and at this time, the further processed lower via hole region may have a larger diameter than the hole of the bridge circuit pattern, so that at least a portion of the bridge circuit pattern in contact with the side of the first via 153A may protrude into the via hole region.

[0066] 6(a) and 6(b) are a cross-sectional view and a plan view, respectively, showing a region of a bridge circuit layer 132 and a first via 153A according to another embodiment.

[0067] Referring to the drawings, in another embodiment, the bridge circuit pattern in the structure shown in Figures 4(a) and 4(b) does not include an area with a hole, and the end of the bridge circuit pattern contacts the side of the first via 153A.

[0068] Meanwhile, when processing the via hole to form the first via 153A, the via hole can be formed so as to be adjacent to the end of the bridge circuit pattern. When the via hole is formed in this way, the side surface of the bridge circuit pattern can be exposed from the via hole. This allows the first via 153A filling the via hole to contact the exposed side surface of the bridge circuit pattern.

[0069] 6(c) and 6(d) are a cross-sectional view and a plan view, respectively, showing the region of the bridge circuit layer 132 and the first via 153A according to a modified example of another embodiment.

[0070] Referring to the drawing, when processing the via holes to form the first vias 153A, one surface of the bridge circuit pattern in the area where the via holes are to be formed may remain unprocessed. As a result, at least a portion of one surface of the bridge circuit pattern may be exposed through the via holes, and the first vias 153A filling the via holes may cover the exposed surface of the bridge circuit pattern. In this case, the exposed surface of the bridge circuit pattern may be the surface facing the third circuit layer 152.

[0071] 6(e) and 6(f) are a cross-sectional view and a plan view, respectively, showing the region of the bridge circuit layer 132 and the first via 153A according to a modified example of another embodiment.

[0072] As described above, the via hole may be further processed along the periphery of the hole of the bridge circuit pattern, and the further processed lower via hole region may have a larger diameter than the via hole region disposed on the side of the bridge circuit pattern, so that at least a portion of the bridge circuit pattern that contacts the side of the first via 153A may protrude into the via hole region.

[0073] 7 and 8(a) to (d) are enlarged plan views each showing a schematic modification of a first circuit layer region disposed on the bottom surface of a recessed portion of a printed circuit board according to the present invention.

[0074] The first circuit layer 122A of the printed circuit board 100A according to an example includes a circuit pad disposed on at least a portion of a bottom surface of the recessed portion 121h. In this case, the first via 153A may contact the circuit pad to connect the circuit pad to the third circuit layer 152.

[0075] Referring to FIG. 7(a), the circuit pad of the first circuit layer 122A may be a single pad, and may be disposed so as to cover the entire bottom surface of the recessed portion 121h.

[0076] 7(b), 7(c), 8(a), and 8(b), the circuit pads of the first circuit layer 122A may be a plurality of circuit pads, each of which may be spaced apart from one another, and each of which may have various shapes, such as a square or a circle.

[0077] 8(c) and 8(d), the circuit pad of the first circuit layer 122A may have at least one hole, and a portion of the first insulating layer 121A may be exposed through the hole. In this case, the hole formed in the circuit pad may play a role of degassing.

[0078] Meanwhile, the circuit pads included in the first circuit layer 122A can have various shapes, and can play various roles according to the design. For example, each of the circuit pads can play the role of a ground (GND) pad, a power (PWR) pad, a signal (S) pad, etc., and can provide electrical paths for various purposes.

[0079] 9a to 9j are diagrams illustrating a process for manufacturing a printed circuit board according to the present invention.

[0080] 9a, first there is provided a core layer 111. The core layer 111 can be a metal foil laminate having metal foil 111m attached to both sides.

[0081] 9b, core circuit layers 112 are formed on both sides of the core layer 111, and through vias 113 are formed to penetrate the core layer 111 and connect the core circuit layers 112 disposed on both sides of the core layer 111. The core circuit layers 112 and through vias 113 may be formed through a known plating process after forming via holes using a laser drill or a mechanical drill. At this time, the metal foil 111m may serve as a seed layer.

[0082] Next, referring to FIG. 9c, a first substrate portion 120A including a first insulating layer 121A, a first circuit layer 122A, and a first via layer 123A, and a second substrate portion 120B including a second insulating layer 121B, a second circuit layer 122B, and a second via layer 123B are formed on one and the other sides of the core substrate portion 110, respectively.

[0083] The first insulating layer 121A and the second insulating layer 121B can each be formed by laminating a plurality of insulating layers. For example, they can be formed by laminating uncured prepregs and then curing them, but are not limited thereto.

[0084] The first circuit layer 122A, the second circuit layer 122B, the first via layer 123A, and the second via layer 123B can also be formed by forming via holes using a laser drill or a mechanical drill, and then performing a known plating process.

[0085] Next, referring to FIG. 9d, a recessed portion 121h is formed in the first substrate portion 120A. The method of forming the recessed portion 121h is not particularly limited, and a known method such as a laser drill or a mechanical drill can be used. The recessed portion 121h can be formed to penetrate only a portion of the first substrate portion 120A. At this time, the circuit pad included in the first circuit layer 122A can play the role of a processing stop layer. As a result, the recessed portion 121h can expose at least a portion of the circuit pad, and the circuit pad can be disposed in at least a portion of the bottom surface of the recessed portion 121h. At this time, the first insulating layer 121A can be processed deeper in the region where the circuit pad is not disposed. Therefore, the bottom surface of the recessed portion 121h can have a step with one surface of the circuit pad of the first circuit layer 122A exposed through the recessed portion 121h. In addition, the bottom surface of the recessed portion 121h can have a structure that is not flat. For example, the bottom surface of one region of the recessed portion 121h may be located higher or lower than the bottom surface of the other region.

[0086] 9e, the bridge 130 is disposed in the recessed portion 121h. At this time, the bridge 130 can be disposed by using a method of fixing the bridge 130 to the bottom surface of the recessed portion 121h via an adhesive layer 140.

[0087] 9f, an insulating material 151 is formed on the first substrate unit 120A. At this time, the insulating material 151 may also be formed on the second substrate unit 120B. The insulating material 151 may be formed to fill at least a portion of the recessed portion 121h and to cover at least a portion of the bridge 130. The insulating material 151 may be formed by laminating ABF or the like and then curing it.

[0088] Next, referring to FIG. 9g, the first via hole 153Ah, the second via hole 153Bh, and the third via hole 153Ch are formed. The first via hole 153Ah, the second via hole 153Bh, and the third via hole 153Ch may be formed using a laser drill, a mechanical drill, or the like. The first via hole 153Ah may be formed to penetrate the insulating material 151 and the bridge 130 and further penetrate the adhesive layer 140. The second via hole 153Bh may be formed to penetrate the insulating material 151, or may be formed to further penetrate a part of the bridge 130. The third via hole 153Ch may be formed to penetrate the insulating material 151 and the first insulating layer 121A, or may be formed to penetrate only the insulating material 151. The first via hole 153Ah, the second via hole 153Bh, and the third via hole 153Ch may be formed using a laser drill, a mechanical drill, or the like.

[0089] 9h, the first via hole 153Ah, the second via hole 153Bh, and the third via hole 153Ch are filled, respectively, to form the first via 153A, the second via 153B, and the third via 153C, respectively, and to form the third circuit layer 152. The first via 153A, the second via 153B, the third via 153C, and the third circuit layer 152 can be formed through a known plating process, respectively, which will be described in detail in the description of FIGS. 10a to 11g.

[0090] 9i, a protective layer 160 is formed on the insulating material 151. The protective layer 160 can be formed by laminating an insulating material such as a solder resist and then curing the laminate. An opening is formed in the protective layer 160 to expose at least a portion of the third circuit layer 152.

[0091] 9j, a connecting conductor 170 is formed on the protective layer 160. The connecting conductor 170 may be formed through a known plating process, may be formed to fill an opening formed in the protective layer 160, and may be connected to the third circuit layer 152.

[0092] 10a to 10d are diagrams illustrating an example of a process for manufacturing the first to third vias and the third circuit layer of a printed circuit board according to the present invention.

[0093] 10a, a first via hole 153Ah penetrating the insulating material 151, the bridge 130, and the adhesive layer 140, a second via hole 153Bh penetrating the insulating material 151, and a third via hole 153Ch penetrating the insulating material 151 and the first insulating layer 121A are formed. In addition, a first metal layer 211 is formed along the surface of the insulating material 151 and the wall surfaces of the first via hole 153Ah, the second via hole 153Bh, and the third via hole 153Ch. The first metal layer 211 may be formed through electroless plating and may serve as a seed layer.

[0094] 10b, a photoresist layer 300 is formed on the insulating material 151. At this time, openings may be formed in the photoresist layer 300 through an exposure and development process in areas where the first via 153A, the second via 153B, the third via 153C, and the third circuit layer 152 are to be formed.

[0095] 10c, a second metal layer 212 is formed on the first metal layer 211 in the area where the first via 153A, the second via 153B, the third via 153C, and the third circuit layer 152 are to be formed. The second metal layer 212 can be formed via electrolytic plating.

[0096] 10d, the photo resist layer 300 and the first metal layer 211 covered by the photo resist layer 300 are removed. The photo resist layer 300 can be removed by a stripping method, and the first metal layer 211 can be removed by an etching method.

[0097] According to an example manufacturing process, the first via 153A, the second via 153B, the third via 153C, and the third circuit layer 152 each include a first metal layer 211 and a second metal layer 212. The first via 153A, the second via 153B, and the third via 153C each may be formed together with the third circuit layer 152 and integrated with the third circuit layer 152.

[0098] 11a to 11g are diagrams illustrating another example of a process for manufacturing the first to third vias and the third circuit layer of a printed circuit board according to the present invention.

[0099] 11a, a first via hole 153Ah is formed penetrating the insulating material 151, the bridge 130, and the adhesive layer 140, and a first metal layer 211 is formed along the surface of the insulating material 151 and the wall surface of the first via hole 153Ah. The first metal layer 211 may be formed through electroless plating and may serve as a seed layer.

[0100] 11b, a second metal layer 212 is formed on the first metal layer 211. The second metal layer 212 can be formed through electrolytic plating.

[0101] 11c, the first metal layer 211 and the second metal layer 212 disposed on one surface of the insulating material 151 are removed. The first metal layer 211 and the second metal layer 212 may be removed through a chemical mechanical polishing (CMP) process or the like. As a result, the first via 153A is formed.

[0102] 11d, a second via hole 153Bh penetrating the insulating material 151 and a third via hole 153Ch penetrating the insulating material 151 and the first insulating layer 121A are formed. A third metal layer 213 is formed on the surfaces of the insulating material 151 and the first via 153A and along the wall surfaces of the second via hole 153Bh and the third via hole 153Ch. The third metal layer 213 can be formed through electroless plating and can serve as a seed layer.

[0103] 11e, a photoresist layer 300 is formed on the insulating material 151. At this time, openings may be formed in the photoresist layer 300 through an exposure and development process in areas where the first via 153A, the second via 153B, the third via 153C, and the third circuit layer 152 are to be formed.

[0104] 11f, a fourth metal layer 214 is formed on the third metal layer 213 in the area where the second via 153B, the third via 153C, and the third circuit layer 152 are to be formed. The fourth metal layer 214 can be formed via electrolytic plating.

[0105] 11g, the photo resist layer 300 and the third metal layer 213 covered by the photo resist layer 300 are removed. The photo resist layer 300 can be removed by a stripping method, and the third metal layer 213 can be removed by an etching method.

[0106] According to a manufacturing process according to another example, the first via 153A includes a first metal layer 211 and a second metal layer 212 disposed on the first metal layer 211. Also, the third circuit layer 152, the second via 153B, and the third via 153C include a third metal layer 213 and a fourth metal layer 214 disposed on the third metal layer 213, respectively. The second via 153B and the third via 153C can each be formed together with the third circuit layer 152 to be integrated therewith.

[0107] FIG. 12 is a cross-sectional view showing another example of a printed circuit board according to the present invention.

[0108] Referring to FIG. 12, the bridge circuit layer 132 in the printed circuit board 100B according to another example may include bridge circuit patterns having different shapes.

[0109] For example, the bridge circuit layer 132 may include a region having holes as described above in Figures 4 to 6, and may include both a bridge circuit pattern having a ring shape and a bridge circuit pattern whose end is in contact with a side surface of the first via 153A. However, this is merely an example to show that the bridge circuit pattern included in the bridge circuit layer 132 may have various shapes, and the present invention is not limited to the above example.

[0110] FIG. 13 is a cross-sectional view showing another example of a printed circuit board according to the present invention.

[0111] 13, in the printed circuit board 100C according to another example, the bottom surface of the recessed portion 121h has a step with respect to one surface of the circuit pad of the first circuit layer 122A exposed through the recessed portion 121h. In the drawing, the bottom surface of the recessed portion 121h is shown to be located at a level between one surface and the other surface of the circuit pad exposed through the recessed portion 121h, but this is not limited thereto, and for example, the bottom surface of the recessed portion 121h may be located at a lower level than the other surface of the circuit pad exposed through the recessed portion 121h.

[0112] Meanwhile, the adhesive layer 140 may be disposed on the bottom surface of the recessed portion and cover at least a portion of the circuit pad exposed through the recessed portion 121h. For example, the adhesive layer 140 may be disposed on the bottom surface of the recessed portion and cover a portion of each of one surface and side surfaces of the circuit pad exposed through the recessed portion 121h.

[0113] As described above, when the recessed portion 121h is formed, the circuit pad included in the first circuit layer 122A may serve as a processing stop layer. At this time, the first insulating layer 121A may be processed deeper in the area where the circuit pad is not arranged. As a result, as in the printed circuit board 100C according to another example, the bottom surface of the recessed portion 121h may have a step with one surface of the circuit pad of the first circuit layer 122A exposed through the recessed portion 121h. In addition, the bottom surface of the recessed portion 121h may have a non-flat structure, and for example, the bottom surface of the recessed portion 121h in one area may be located higher or lower than the bottom surface of the other area.

[0114] FIG. 14 is a cross-sectional view showing another example of a printed circuit board according to the present invention.

[0115] Referring to FIG. 14, a printed circuit board 100D according to another example does not include a core substrate portion 110 and a second substrate portion 120B.

[0116] Thus, the printed circuit board 100D according to another example includes a first substrate portion 120A having a recessed portion 121h, a bridge 130, an insulating material 151, a third circuit layer 152, a first via 153A, a second via 153B, and a third via 153C.

[0117] The rest of the details are substantially the same as those described above in the description of the printed circuit board 100A according to an example, and therefore a detailed description thereof will be omitted.

[0118] FIG. 15 is a cross-sectional view showing a schematic diagram of another example of a printed circuit board according to the present invention.

[0119] 15, the second via 153B of the printed circuit board 100E according to another example penetrates the insulating material 151 and a portion of the bridge 130 to be connected to the bridge circuit layer 132 embedded inside the bridge 130. In this case, as shown in FIG. 15, the second via 153B may penetrate the insulating material 151 and a portion of the insulating layer 131.

[0120] The rest of the details are substantially the same as those described above in the description of the printed circuit board 100A according to an example, and therefore a detailed description thereof will be omitted.

[0121] FIG. 16 is a cross-sectional view showing an example of a multi-chip package in which a plurality of semiconductor chips are mounted on a printed circuit board according to the present invention.

[0122] Referring to FIG. 16, a plurality of semiconductor chips 410A, 410B, and 410C may be disposed on a printed circuit board 100A according to an example, and the plurality of semiconductor chips 410A, 410B, and 410C may be fixed by a molding material 420.

[0123] The multiple semiconductor chips may include a first semiconductor chip 410A, a second semiconductor chip 410B, and a third semiconductor chip 410C. However, the number of semiconductor chips is not particularly limited, and may be, for example, two, or four or more.

[0124] The first semiconductor chip 410A, the second semiconductor chip 410B, and the third semiconductor chip 410C may each include a pad for connection to the connecting conductor 170.

[0125] Meanwhile, the bridge 130 may serve to connect at least two of the plurality of semiconductor chips to each other. For example, there may be a plurality of bridges 130, and the bridges may include a bridge connecting the first semiconductor chip 410A and the second semiconductor chip 410B to each other and a bridge connecting the second semiconductor chip 410B and the third semiconductor chip 410C to each other.

[0126] The first semiconductor chip 410A and the third semiconductor chip 410C may each be a High Bandwidth Memory (HBM), and the second semiconductor chip 410B may include any of an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), and a Graphics Processing Unit (GPU).

[0127] Alternatively, the first semiconductor chip 410A and the third semiconductor chip 410C may each be a High Bandwidth Memory (HBM), and the second semiconductor chip 410B may include any of an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), and a Graphics Processing Unit (GPU).

[0128] Alternatively, the first semiconductor chip 410A, the second semiconductor chip 410B, and the third semiconductor chip 410C may each be an ASIC (Application Specific Integrated Circuit).

[0129] However, the types of the first semiconductor chip 410A, the second semiconductor chip 410B, and the third semiconductor chip 410C are not limited to the above-mentioned examples.

[0130] In the present invention, the term "connected" refers not only to a direct connection but also to an indirect connection via an adhesive layer, etc. Furthermore, the term "electrically connected" refers to both a physical connection and a non-connection.

[0131] In addition, in the present invention, the terms "first", "second", etc. are used to distinguish one component from another component, and do not limit the order and / or importance of the corresponding components, etc. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the present invention.

[0132] The expressions "one example" or "another example" used in the present invention do not mean the same embodiment, but are provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with features of another example. For example, even if a matter described in a particular example is not described in another example, it can be understood as being related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0133] In addition, the terms used in the present invention are merely explained to explain an example, and are not intended to limit the present invention. In this case, the singular expression includes the plural unless the context clearly indicates otherwise.

Claims

1. a substrate portion having a recessed portion and including a first circuit layer; a bridge disposed in the recess and including an insulating layer and a bridge circuit layer; an insulating material filling at least a portion of the recess and covering at least a portion of the bridge; a second circuit layer disposed on the insulating material; a first via that passes through the insulating material and a portion of the bridge and connects the second circuit layer and the bridge circuit layer.

2. The printed circuit board of claim 1 , wherein the bridge circuit layer is denser than the first circuit layer.

3. The printed circuit board of claim 1 or 2, further comprising a second via penetrating the insulating material and the bridge and connecting the second circuit layer to the first circuit layer.

4. The printed circuit board according to claim 3 , wherein the bridge circuit layer includes a bridge circuit pattern in contact with a side surface of the second via.

5. The printed circuit board according to claim 4 , wherein the bridge circuit pattern surrounds a side surface of the second via in a region in contact with the side surface of the second via.

6. The printed circuit board according to claim 1 , wherein the first circuit layer includes a circuit pad disposed on at least a portion of a bottom surface of the recessed portion.

7. The circuit pads are multiple; The printed circuit board of claim 6 , wherein the circuit pads are spaced apart from one another.

8. 8. The printed circuit board according to claim 6, wherein the circuit pad has at least one hole.

9. The printed circuit board according to claim 1 , further comprising an adhesive layer disposed between a bottom surface of the recess and the bridge.

10. the second via includes a first metal layer and a second metal layer disposed on the first metal layer; the first via and the second circuit layer each include a third metal layer and a fourth metal layer disposed on the third metal layer; The printed circuit board of claim 3 , wherein the first via and the second circuit layer are integral with one another.

11. forming a recess in a substrate portion including a first circuit layer; disposing a bridge in the recess, the bridge including an insulating layer and a bridge circuit layer; forming an insulating material filling at least a portion of the recess and covering at least a portion of the bridge; forming a first via through the insulating material and a portion of the bridge to be connected to the bridge circuit layer.

12. The method of claim 11, further comprising forming a second via penetrating the insulating material and the bridge to be connected to the first circuit layer.

13. forming the second via includes forming a via hole; The method of claim 12, wherein the via hole exposes at least a portion of a side surface of a bridge circuit pattern included in the bridge circuit layer.

14. the bridge circuit pattern includes an area having a hole; The method of claim 13 , wherein the via hole penetrates a region corresponding to the hole to expose at least a portion of a side surface of the bridge circuit pattern.

15. 15. The method of claim 11, wherein in the forming of the recess, the recess exposes at least a portion of a circuit pad included in the first circuit layer.

16. The method of claim 11 , wherein in the step of disposing the bridge, the bridge is disposed in the recessed portion via an adhesive layer.

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