Memory Device

Abstract

To provide a highly integrated memory unit.SOLUTION: A memory 40 includes a first substrate and a circuit element formed on the first substrate. The circuit element includes: a periphery circuit region for providing a row decoder; a cell array region having a word line layered on a second substrate at the top of the periphery circuit region and a channel structure extended to a direction orthogonal to the top surface of the second substrate and penetrating into the word line; and a cell contact region having a first cell contact region and a second cell contact region including cell contacts connected to the word line, disposed at both sides of the cell array region in a first direction parallel to the top surface of the second substrate, and having mutually different lengths in the first direction. In the first cell contact region and the second cell contact region, the respective cell contacts are connected to the word line and a first pad and a second pad extended to mutually different lengths in the first direction are included.SELECTED DRAWING: Figure 6a

Description

[Technical field]

[0001] The present invention relates to memory devices. [Background technology]

[0002] A memory device can provide a function of recording and erasing data, and reading recorded data. Memory devices can be classified into non-volatile memory devices and volatile memory devices, and non-volatile memory devices can maintain recorded data even when power is cut off. The data storage capacity required for memory devices is constantly increasing. Accordingly, various methods for improving the integration density of memory devices have been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the problems that the technical concept of the present invention aims to solve is to provide a memory device in which cell regions included in the memory device are asymmetrically formed in at least one direction parallel to the top surface of a substrate, thereby improving the integration density. [Means for solving the problem]

[0004] According to an embodiment of the present invention, there is provided a memory device comprising: a first substrate; and circuit elements formed on the first substrate, the circuit elements including: a peripheral circuit region providing a row decoder; word lines stacked on a second substrate on an upper portion of the peripheral circuit region; a cell array region having a channel structure extending in a direction perpendicular to an upper surface of the second substrate and penetrating the word lines; and cell contact regions including cell contacts connected to the word lines, the cell array region being disposed on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contact regions having first and second cell contact regions having different lengths in the first direction, the first and second cell contact regions respectively including first and second pads, the cell contacts being connected to the word lines, and the number of the second pads included in the first cell contact region being greater than the number of the second pads included in the second cell contact region.

[0005] According to an embodiment of the present invention, a memory device includes a peripheral circuit region including a pass element formed in a first substrate, and a plurality of cell regions disposed on a second substrate above the peripheral circuit region, each including at least one memory block, each of the cell regions including a cell array region including a plurality of word lines connected to the pass elements and a plurality of channel structures passing through the word lines, and a cell contact region in which the word lines extending from the cell array region are connected to a plurality of cell contacts, and at least one of the pass elements is commonly connected to a pair of word lines included in a pair of adjacent cell regions among the cell regions and disposed at the same height from an upper surface of the second substrate.

[0006] A memory device according to one embodiment of the present invention includes a peripheral circuit region including a pass element providing a row decoder, a first substrate disposed on an upper portion of the peripheral circuit region, and a plurality of cell regions each including a word line stacked in a direction perpendicular to an upper surface of the first substrate, the plurality of cell regions including a first cell region and a second cell region adjacent to each other in a first direction parallel to an upper surface of the first substrate, and at least one of the word lines included in the first cell region and at least one of the word lines included in the second cell region share at least one of the pass elements disposed between the first cell region and the second cell region in the first direction. Effect of the Invention

[0007] According to an embodiment of the present invention, a memory device includes a peripheral circuit region and a cell region disposed thereover, the cell region having a cell array region in which a channel structure is disposed, and a contact region in which a cell contact connected to a word line is disposed. The contact regions extend from the cell array region in a direction parallel to an upper surface of a substrate on which the cell region is formed, and may have different lengths in at least one of the directions parallel to the upper surface of the substrate. Also, at least some of the cell contacts may share a pass element formed in the peripheral circuit region. This can improve the integration density of the memory device.

[0008] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0009] [Figure 1] 1 is a simplified block diagram of a memory device according to an embodiment of the present invention; [Diagram 2] 1 is a simplified block diagram of a memory device according to an embodiment of the present invention; [Diagram 3]2 is a diagram illustrating a connection relationship between a memory cell array and a pass element in a memory device according to an embodiment of the present invention; [Figure 4] 2 is a diagram illustrating a connection relationship between a memory cell array and a pass element in a memory device according to an embodiment of the present invention; [Diagram 5] 1 is a plan view illustrating a memory device according to an embodiment of the present invention; [Figure 6a] FIG. 6 illustrates a portion of the memory device illustrated in FIG. 5. [Figure 6b] FIG. 6 illustrates a portion of the memory device illustrated in FIG. 5. [Figure 7a] 2 is a diagram illustrating a portion of a memory device according to an embodiment of the present invention; [Figure 7b] 2 is a diagram illustrating a portion of a memory device according to an embodiment of the present invention; [Figure 8a] 2 is a diagram illustrating a portion of a memory device according to an embodiment of the present invention; [Figure 8b] 2 is a diagram illustrating a portion of a memory device according to an embodiment of the present invention; [Figure 9] 1 is a diagram illustrating a configuration of a memory device according to an embodiment of the present invention; [Figure 10] 1 is a diagram illustrating a configuration of a memory device according to an embodiment of the present invention; [Figure 11] 1 is a plan view illustrating a memory device according to an embodiment of the present invention; [Figure 12] 1 is a plan view illustrating a memory device according to an embodiment of the present invention; [Figure 13] 1 is a plan view illustrating a memory device according to an embodiment of the present invention; [Figure 14] 1 is a plan view illustrating a memory device according to an embodiment of the present invention; [Figure 15] 12 is a diagram showing a cross section taken along the line II' of FIG. 11. FIG. [Figure 16] 12 is a diagram showing a cross section taken along the line II-II' in FIG. 11. FIG. [Figure 17] 13 is a cross-sectional view taken along the line III-III' in FIG. 12. FIG. [Figure 18] 18(a) and (b) are simplified diagrams showing the pass element shown in FIG. 17. [Figure 19] 2 is a cross-sectional view illustrating a cell contact region of a memory device according to an embodiment of the present invention; [Figure 20] 2 is a cross-sectional view illustrating a cell contact region of a memory device according to an embodiment of the present invention; [Figure 21] 2 is a cross-sectional view illustrating a cell array region of a memory device according to an embodiment of the present invention; [Figure 22] FIG. 22 is an enlarged view of a partial area of ​​FIG. 21. [Diagram 23] 22(a) and (b) are enlarged views showing a partial area of ​​FIG. 21. FIG. [Figure 24] 22(a) and (b) are enlarged views showing a partial area of ​​FIG. 21. FIG. [Diagram 25] 2 is a cross-sectional view illustrating a cell array region of a memory device according to an embodiment of the present invention; [Figure 26] 26(a) and (b) are enlarged views showing a partial area of ​​FIG. 25. FIG. [Figure 27] 26(a) and (b) are enlarged views showing a partial area of ​​FIG. 25. FIG. [Figure 28] 1 is a simplified block diagram of an electronic device including a memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0011] 1 and 2 are simplified block diagrams illustrating a memory device according to an embodiment of the present invention.

[0012] 1, a memory device 10 may include a memory cell array 20 and peripheral circuits 30. The peripheral circuits 30 may include a row decoder 31, a voltage generator 32, a page buffer 33, an input / output circuit 34, and a control logic 35.

[0013] The memory cell array 20 may include a plurality of memory cells and may be divided into a plurality of memory blocks. The plurality of memory cells may be connected to a row decoder 31 via string selection lines SSL, word lines WL, and ground selection lines GSL, and may be connected to a page buffer 33 via bit lines BL. In an embodiment of the present invention, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

[0014] The row decoder 31 may decode address data ADDR input from the control logic 35, etc., and generate and transmit a voltage for driving the word line WL. The row decoder 31 may input a word line voltage generated by the voltage generator 32 to the word line WL in response to the control of the control logic 35. As an example, the row decoder 31 may be connected to the word line WL via a pass element unit 31A, and may input the word line voltage to the word line WL when the pass element 31A is turned on.

[0015] The page buffer 33 is connected to the memory cell array 20 through bit lines BL, and can read information stored in the memory cells or write data in the memory cells. The page buffer 33 can include a column decoder and a sense amplifier. The column decoder can select at least a portion of the bit lines BL of the memory cell array 20, and the sense amplifier can read data from the memory cells connected to the bit lines BL selected by the column decoder during a read operation.

[0016] The input / output circuit 34 can receive data DATA during a program operation and transmit it to the page buffer 33, and during a read operation, the page buffer 33 can output data DATA read from the memory cell array 20 to the outside. The input / output circuit 34 can transmit an address or a command input from an external memory controller to the control logic 35.

[0017] The control logic 35 can control the operation of the row decoder 31, the voltage generator 32, the page buffer 33, etc. In one embodiment, the control logic 35 can operate in response to a control signal and an external voltage transmitted from an external memory controller or the like.

[0018] The voltage generator 32 can generate control voltages, such as a program voltage, a read voltage, an erase voltage, and a pass voltage, required for the operation of the memory device 10, by using a power supply voltage input from the outside. The voltages generated by the voltage generator 32 can be supplied to the peripheral circuit 30 or input to the memory cell array 20 via the row decoder 31 or the like.

[0019] For example, during a program operation, a program voltage may be applied to a selected word line connected to a selected memory cell in which data is to be written, and a pass voltage smaller than the program voltage may be applied to unselected word lines connected to unselected memory cells that are included in one memory cell string and share a channel region with the selected memory cell.

[0020] Also, in one embodiment, during a read operation, a read voltage may be applied to a selected word line connected to a selected memory cell from which data is to be read, and a pass voltage may be applied to unselected word lines connected to unselected memory cells sharing a channel region with the selected memory cell. In one embodiment in which memory cells each store data having multiple bits, row decoder 31 may apply multiple read voltages having different magnitudes to the selected word line.

[0021] Next, referring to FIG. 2, the memory cell array 20 may include a plurality of memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include word lines stacked along a third direction (Z-axis direction) on a plane defined by a first direction (X-axis direction) and a second direction (Y-axis direction), and a channel structure extending along the third direction (Z-axis direction). The word lines and the channel structure may provide memory cells arranged three-dimensionally. Also, each of the memory blocks BLK1 to BLKn may include bit lines extending in the first direction (X-axis direction) or the second direction (Y-axis direction) and connected to the channel structure. As an example, the memory blocks BLK1 to BLKn in the memory cell array 20 are arranged along the first direction (X-axis direction) and the second direction (Y-axis direction).

[0022] 3 and 4 are diagrams illustrating a connection relationship between a memory cell array and a pass element in a memory device according to an embodiment of the present invention.

[0023] Referring to FIG. 3, one memory block BLK may include a plurality of memory cell strings S, and at least some of the memory cell strings S may share word lines WL1 to WLn and bit lines BL1 to BL3.

[0024] Each of the memory cell strings S may include a plurality of memory cells MC connected between first and second string selection transistors SST1 and SST2 and a ground selection transistor GST. The first and second string selection transistors SST1 and SST2 are connected in series to each other, and the second string selection transistor SST2 disposed at the top may be connected to one of the bit lines BL1 to BL3. The ground selection transistor GST may be connected to a common source line CSL.

[0025] The memory cells MC may be connected in series between the first and second string selection transistors SST1, SST2 and the ground selection transistor GST. Depending on the embodiment, the number of the string selection transistors SST1, SST2 and the ground selection transistor GST may be variously modified, and each memory cell string S may further include at least one dummy memory cell.

[0026] Gate electrodes of the memory cells MC may be connected to word lines WL1 to WLn, a gate electrode of the ground selection transistor GST may be connected to a ground selection line GSL, and gate electrodes of the first and second string selection transistors SST1 and SST2 may be connected to string selection lines SSL11 to SSL23.

[0027] The word lines WL1 to WLn, the ground selection line GSL, and the string selection lines SSL11 to SSL23 may be connected to a pass element unit PTU including a pass element PT. The pass element PT may be turned on and off by a block selection signal BS. When the pass element PT is turned on, a program operation, a read operation, an erase operation, etc. may be performed on a plurality of memory cells MC through the voltages GS, S1 to Sn, and SS11 to SS23 input to the word lines WL1 to WLn, the ground selection line GSL, and the string selection lines SSL11 to SSL23. In the embodiment shown in FIG. 3, the pass elements PT connected to the word lines WL1 to WLn included in the block BLK may not be shared by the word lines of other blocks.

[0028] Referring now to Fig. 4, the first memory block BLK1 and the second memory block BLK2 may share at least one of the pass elements. In the embodiment shown in Fig. 4, the pass element unit PTU may include a first pass element PT1 and at least one second pass element PT2, and the second pass element PT2 may be shared by the first memory block BLK1 and the second memory block BLK2 and at least one of the word lines WL1 to WLn. Referring to Fig. 4, the second pass element PT2 may be commonly connected to the first word line WL1 of the first memory block BLK1 and the first word line WL1 of the second memory block BLK2.

[0029] The pass elements connected to the word lines WL1 to WLn of the first memory block BLK1 may be turned on and off by a first block selection signal BS1, and the pass elements connected to the word lines WL1 to WLn of the second memory block BLK2 may be turned on and off by a second block selection signal BS2. Depending on the embodiment, the first block selection signal BS1 and the second block selection signal BS2 may be the same signal or different signals. When the first block selection signal BS1 and the second block selection signal BS2 are the same signal, the pass elements included in the pass element unit PTU may be turned on or off simultaneously. Thus, the first memory block BLK1 and the second memory block BLK2 may be driven simultaneously.

[0030] FIG. 5 is a schematic plan view of a memory device according to an embodiment of the present invention.

[0031] 5, a memory device 40 according to an embodiment of the present invention may include a plurality of cell regions 50. The plurality of cell regions 50 may be arranged on a substrate 41. Each of the cell regions 50 may include a word line stacked in a direction perpendicular to the top surface of the substrate 41, a channel structure extending in a direction perpendicular to the top surface of the substrate 41, a cell contact connected to the word line, etc.

[0032] Each of the cell regions 50 may include a cell array region in which a channel structure is disposed, and a cell contact region extending from the cell array region and connecting a word line and a cell contact to each other. As an example, the cell contact region may be disposed around the cell array region in a direction parallel to the top surface of the substrate 41. Thus, the cell contact regions may be disposed adjacent to each other at the boundaries between the cell regions 50.

[0033] 5, a peripheral circuit region may be disposed under the substrate 41 on which the cell region 50 is disposed. The peripheral circuit region may include at least some of circuits for driving memory cells included in the cell region 50, such as a row decoder, a voltage generator, a page buffer, an input / output circuit, and a control logic.

[0034] The row decoder may include a pass element connected to the word lines of the cell regions 50. In an embodiment of the present invention, at least one of the word lines included in different cell regions 50 may share a pass element. Also, cell contact regions disposed around the cell array region may have an asymmetric structure so that at least one of the word lines included in adjacent cell regions 50 may share a pass element. This will be described in more detail with reference to Figures 6a and 6b.

[0035] 6a and 6b are diagrams illustrating some regions of the memory device illustrated in FIG. 5. As an example, FIG. 6a is an enlarged view of region A1 of FIG. 5, and FIG. 6b is an enlarged view of region A2 of FIG. 5. Referring to FIG. 6a and 6b, the memory device 40 may include a cell region 50 and a peripheral circuit region 60, which are stacked one above the other. As an example, the cell region 50 may be disposed on top of the peripheral circuit region 60.

[0036] Each of the cell regions 50 may include a first cell contact region 51, a second cell contact region 52, and a cell array region 53 disposed therebetween. The cell array region 53 may include word lines stacked on one another and a channel structure penetrating the word lines. The first cell contact region 51 and the second cell contact region 52 may be regions where the word lines extending from the cell array region 53 and the cell contacts are connected to each other, and may be disposed on both sides of the cell array region 53 in a first direction (X-axis direction).

[0037] According to an embodiment, the first cell contact region 51 and the second cell contact region 52 may have different lengths in a first direction (X-axis direction). As an example, in the first direction (X-axis direction), the length L1 of the first cell contact region 51 may be greater than the length L2 of the second cell contact region 52.

[0038] Referring to FIG. 6a, which shows an enlarged view of region A1 of FIG. 5, first cell contact regions 51 may be adjacent to each other between cell regions 50. Referring to FIG. 6b, which shows an enlarged view of region A2 of FIG. 5, second cell contact regions 52 may be adjacent to each other between cell regions 50. As a result, the distance between cell array regions 53 included in adjacent cell regions 50 in the memory device 40 may vary depending on the position. A first distance DC1 between cell array regions 53 in an embodiment shown in FIG. 6a may be larger than a second distance DC2 between cell array regions 53 in an embodiment shown in FIG. 6b.

[0039] In one embodiment, pass elements connected to word lines may be disposed in the peripheral circuit region 60 under the first cell contact region 51 and the second cell contact region 52. The word lines and the pass elements may be connected to each other through cell contacts disposed in the first cell contact region 51 and the second cell contact region 52. In an embodiment of the present invention, at least some of the cell contacts connected to the word lines in the second cell contact region 52 may be commonly connected to one of the pass elements. This allows the number of pass elements included in the peripheral circuit region 60 to be reduced. Furthermore, by reducing the area of ​​the second cell contact region 52, the integration density of the memory device 40 can be improved.

[0040] 7a and 7b are diagrams illustrating some regions of a memory device according to an embodiment of the present invention.

[0041] Figure 7a is a cross-sectional view of a portion of a memory device according to an embodiment of the present invention, and Figure 7b is an equivalent circuit diagram corresponding to Figure 7a. As an example, the embodiment described with reference to Figures 7a and 7b may correspond to a region in which first contact regions are adjacent to each other, as previously described with reference to Figure 6a.

[0042] 7a, the memory device may include a peripheral circuit region 200 and a cell region 100 disposed on the peripheral circuit region 200. The peripheral circuit region 200 may include a first substrate 210, a plurality of circuit elements 220 formed on the first substrate 210, lower wiring lines 230 connected to the circuit elements 220, and a lower interlayer insulating layer 240. The lower interlayer insulating layer 240 may be disposed on the first substrate 210 to cover the circuit elements 220 and the lower wiring lines 230, and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0043] The cell region 100 may include a first cell region 100A and a second cell region 100B, and the first cell region 100A and the second cell region 100B may have the same structure as each other. Hereinafter, the structure of the cell region 100 will be described with reference to the first cell region 100A. As an example, each of the first cell region 100A and the second cell region 100B may provide at least one memory block.

[0044] The first cell region 100A may include a second substrate 110A disposed on the lower interlayer insulating layer 240. A plurality of word lines (131A to 136A: 130A) may be stacked on the second substrate 110A along a third direction (Z-axis direction) perpendicular to the upper surface of the second substrate 110A. String selection lines (141A and 142A: 140A) and a ground selection line 120A may be disposed on the upper and lower parts of the word lines 130A, respectively. The channel structure 150A may extend in the third direction and penetrate the word lines 130A, the string selection lines 140A, and the ground selection lines 120A. The channel structure 150A may include a data storage layer 151A, a channel layer 152A, and a buried insulating layer 153A, and the channel layer 152A may be electrically connected to the bit lines BL via bit line contacts BLC. In one embodiment, the bit lines BL may extend in a second direction (Y-axis direction). A region in which the channel structure 150A and the bit lines BL are arranged may be defined as a cell array region CA.

[0045] The word line 130A may extend along a first direction (X-axis direction) and may be connected to a plurality of cell contacts (161A to 164A: 160A) in a first cell contact region CT1 adjacent to the cell array region CA in the first direction. In one embodiment, the word line 130A may extend to different lengths along the first and second directions to provide pads PAD1 and PAD2. The cell contacts 160A and the word line 130A may be connected to each other via the pads PAD1 and PAD2.

[0046] 7a, the first cell contact region CT1 may include a first pad PAD1 and a second pad PAD2 having an area different from that of the first pad PAD1. The second pads PAD2 may have an area larger than that of the first pads PAD1. In one embodiment, the length of each of the second pads PAD2 in the first direction may be larger than the length of each of the first pads PAD1.

[0047] Vertical vias (181A to 184A: 180A) may be disposed in at least some of the pads PAD1 and PAD2, which are connected to the lower wiring lines 230 of the peripheral circuit region 200 by penetrating some of the word lines 130A and the second substrate 110A. The pads PAD1 and PAD2 in which the vertical vias 180A are disposed may be formed at positions different from the pads PAD1 and PAD2 to which the cell contacts 160A and the word lines 130A are connected in the second direction.

[0048] The vertical via 180A may be connected to the cell contact 160A via the upper wiring line 170A. The second pad PAD2, the word line 130A disposed thereunder, and the vertical via 180A may be electrically isolated from each other. For example, the vertical via 180A may be extended to the lower wiring line 230 via a region where the sacrificial layer for forming the word line 130A remains without being removed.

[0049] Fig. 7b is an equivalent circuit diagram of the memory device shown in Fig. 7a. Referring to Fig. 7b, the first cell region 100A and the second cell region 100B may each include a memory cell MC, a ground selection transistor GST, a first string selection transistor SST1, and a second string selection transistor SST2, etc. The ground selection transistor GST may be connected to a common source line CSL, and the second string selection transistor SST2 may be connected to a bit line BL.

[0050] 7a and 7b, the first cell region 100A and the second cell region 100B may not share the pass element PT. Referring to FIG. 7b, the pass element PT connected to the memory cells MC, the ground selection transistor GST, the first string selection transistor SST1, and the second string selection transistor SST2 of the first cell region 100A may be separated from the second cell region 100B.

[0051] The pass element PT connected to the first cell region 100A may be controlled by a first block selection signal BS1, and the pass element PT connected to the second cell region 100B may be controlled by a second block selection signal BS2. Depending on the settings of the first block selection signal BS1 and the second block selection signal BS2, the first cell region 100A and the second cell region 100B may be driven simultaneously or independently.

[0052] 8a and 8b are diagrams illustrating some regions of a memory device according to an embodiment of the present invention.

[0053] FIG 8a is a cross-sectional view showing a portion of a memory device according to an embodiment of the present invention, and FIG 8b is an equivalent circuit diagram corresponding to FIG 8a. The memory device according to an embodiment described with reference to FIGS. 8a and 8b may be the same device as the memory device according to an embodiment described with reference to FIGS. 7a and 7b. However, the portion of the region shown in FIG 8a may be different from the portion of the region shown in FIG 7a. As an example, the memory device according to an embodiment described with reference to FIGS. 8a and 8b may correspond to the regions in which the second contact regions are adjacent to each other in the memory device as previously described with reference to FIG 6b.

[0054] 8a, the memory device may include a peripheral circuit region 200 and a cell region 100 disposed on the peripheral circuit region 200. The peripheral circuit region 200 may include a first substrate 210, a plurality of circuit elements 220 formed on the first substrate 210, lower wiring lines 230 connected to the circuit elements 220, and a lower interlayer insulating layer 240. The peripheral circuit region 200 may be continuously extended from a portion of the memory device shown in FIG.

[0055] The cell region 100 may include a second cell region 100B and a third cell region 100C, and the second cell region 100B and the third cell region 100C may have the same structure as the first cell region 100A described above with reference to Fig. 7a. The cell array region CA and the second cell contact region CT2 included in the cell region 100 will be described in more detail with reference to the second cell region 100B shown in Fig. 8a.

[0056] The second cell region 100B includes a second substrate 110B disposed on the lower interlayer insulating layer 240, and a plurality of word lines (131B to 136B: 130B) may be stacked on the second substrate 110B along a third direction (Z-axis direction) perpendicular to the upper surface of the second substrate 110B. String selection lines (141B and 142B: 140B) and a ground selection line 120B may be disposed on the upper and lower parts of the word lines 130B, respectively. The channel structure 150B may extend in the third direction and penetrate the word lines 130B, the string selection lines 140B, and the ground selection lines 120B. The channel structure 150B may include a data storage layer 151B, a channel layer 152B, and a buried insulating layer 153B, and the channel layer 152B may be electrically connected to the bit lines BL via bit line contacts BLC. In one embodiment, the bit lines BL may extend in a second direction (Y-axis direction). A region in which the channel structure 150B and the bit lines BL are arranged may be defined as a cell array region CA.

[0057] The word line 130B may extend along a first direction (X-axis direction) and may be connected to a plurality of cell contacts (161B to 164B: 160B) in a second cell contact region CT2 adjacent to the cell array region CA in the first direction. In one embodiment, the word line 130B may extend to different lengths along the first and second directions to provide pads PAD1 and PAD2. The cell contacts 160B and the word line 130B may be connected to each other at portions of the pads PAD1 and PAD2.

[0058] Similar to the first cell contact region CT1 described with reference to Fig. 7a, the second cell contact region CT2 may include at least one second pad PAD2 different from the first pad PAD1. The second pad PAD2 may have a larger area than each of the first pads PAD1. In one embodiment, the length of the second pad PAD2 in the first direction may be larger than the length of each of the first pads PAD1.

[0059] 7a and 8a, in the second cell region 100B, the number of second pads PAD2 included in the first cell contact region CT1 may be greater than the number of second pads PAD2 included in the second cell contact region CT2. This allows the second cell contact region CT2 to extend relatively shorter than the first cell contact region CT1 in the first direction, thereby improving the integration density of the cell regions 100A, 100B, and 100C.

[0060] As an example, the cell regions 100B and 100C adjacent to each other with the second cell contact region CT2 therebetween may share at least one of the pass elements. Referring to Fig. 8a, the circuit element 220 includes a first pass element 221 and a second pass element 222, and at least some of the word lines 130B included in the second cell region 100B may share the second pass element 222 with at least some of the word lines included in the third cell region 100C. The word lines sharing the second pass element 222 may be disposed at the same height in the third direction.

[0061] 8a, the second cell contact region CT2 may include a common vertical via (181B-183B:180B) connecting the lower wiring line 230 connected to the second pass element 222 to some 161B-163B of the cell contacts 160B. The common vertical via 180B may be commonly connected to at least some of the word lines of the second cell region 100B and the third cell region 100C through the common upper wiring line (171B-173B:170B). The common upper wiring lines (171B-173B:170B) may be disposed at different positions in the second direction, and thus may be electrically isolated from each other. The common vertical via 180B may extend to the peripheral circuit region 200 without penetrating the second substrate 110B.

[0062] Meanwhile, some of the cell contacts 160B, 164B, may be connected to the first pass element 221 of the peripheral circuit region 200 through individual vertical vias 191B. The individual vertical vias 191B may be connected to the cell contacts 164B through individual upper wiring lines 192B, and may extend from at least one of the pads PAD1 and PAD2 to the peripheral circuit region 200, for example.

[0063] 8a, in the second cell contact region CT2, some of the word lines included in the adjacent cell regions 100B and 100C are connected to the common vertical via 180B to share the second pass element 222. This reduces the number of second pads PAD2 required for the individual vertical vias 191B to extend to the peripheral circuit region 200. In addition, by reducing the area of ​​the second cell contact region CT2, the integration density of the memory device 100 can be improved.

[0064] Fig. 8b is an equivalent circuit diagram of the memory device shown in Fig. 8a. Referring to Fig. 8b, the second cell region 100B and the third cell region 100C may each include a memory cell MC, a ground selection transistor GST, a first string selection transistor SST1, and a second string selection transistor SST2, etc. The ground selection transistor GST may be connected to a common source line CSL, and the second string selection transistor SST2 may be connected to a bit line BL.

[0065] The pass elements PT1 and PT2 connected to the memory cells MC may be classified into a first pass element PT1 and a second pass element PT2 depending on whether they are commonly connected to the second cell region 100B and the third cell region 100C. For example, the first pass element PT1 may be connected to one of the memory cells MC in the second cell region 100B and the third cell region 100C, and the second pass element PT2 may be commonly connected to at least some of the memory cells MC included in the second cell region 100B and the third cell region 100C.

[0066] When performing a control operation for the third cell region 100C, the second pass element PT2 may be turned on using the first block selection signal BS1. However, the second cell region 100B and the third cell region 100C may be driven independently of each other by controlling a voltage input to the second cell region 100B through the first pass element PT1 connected to the second cell region 100B. Depending on the embodiment, the second cell region 100B and the third cell region 100C may be driven simultaneously.

[0067] 9 and 10 are diagrams illustrating a schematic configuration of a memory device according to an embodiment of the present invention.

[0068] 9, the memory device 300 may include a peripheral circuit region P and cell regions C1, C2. The memory device 300 may have a cell-on-periphery (COP) structure in which the cell regions C1, C2 are disposed on the upper portion of the peripheral circuit region P. In other words, the cell regions C1, C2 may be disposed on the upper portion of the peripheral circuit region P in the third direction (Z-axis direction). The peripheral circuit region P includes a plurality of circuit elements formed on the first substrate 301, and may be divided into a first peripheral circuit region P1 and a second peripheral circuit region P2.

[0069] The cell regions C1 and C2 may include a first cell region C1 and a second cell region C2 arranged along a first direction (X-axis direction). The first cell region C1 and the second cell region C2 may be formed on different second substrates 302 and 303, respectively. The first cell region C1 and the second cell region C2 may include a cell array region CA and a first cell contact region CT1 and a second cell contact region CT2 arranged on both sides of the cell array region CA in the first direction. The first cell region C1 and the second cell region C2 may have the same structure and may be arranged symmetrically with respect to a boundary between the first cell region C1 and the second cell region C2.

[0070] Referring to the first cell region C1, the cell array region CA may include a first memory block BLK1 and a second memory block BLK2 that are separated in a second direction (Y-axis direction). As an example, the first memory block BLK1 and the second memory block BLK2 may be separated from each other by a word line cut region that extends along the first direction.

[0071] The word lines of the first memory block BLK1 may extend in a first direction to provide a first connection region CR1 included in the first cell contact region CT1 and a second connection region CR2 included in the second cell contact region CT2. The word lines of the second memory block BLK2 may extend in the first direction to provide a first connection region CR1 included in the second cell contact region CT2 and a second connection region CR2 included in the first cell contact region CT1.

[0072] The first connection region CR1 and the second connection region CR2 may include a first pad and a second pad provided by a word line. In the first connection region CR1, the first pad and the second pad may form a step in a first direction and a second direction, and in the second connection region CR2, the first pad and the second pad may form a step in the first direction. In one embodiment, each of the first pads may be shorter than each of the second pads in the first direction.

[0073] For example, a word line of the first memory block BLK1 may be connected to a plurality of cell contacts in a first connection region CR1 of the first cell contact region CT1, and at least some of the cell contacts connected to the word lines of the first memory block BLK1 in the first connection region CR1 of the first cell contact region CT1 may be connected to pass elements of the first peripheral circuit region P1 in a second connection region CR2 of the first cell contact region CT1.

[0074] At least some of the first and second pads in the second connection region CR2 of the first cell contact region CT1 may be provided with a plurality of vertical vias connected to pass elements. In one embodiment, the vertical vias may be connected to at least some of the cell contacts connected to the word lines of the first memory block BLK1 in the first connection region CR1 of the first cell contact region CT1 by upper wiring lines extending in the second direction.

[0075] In the first connection region CR1 of the second cell contact region CT2, a cell contact connected to a word line of the first memory block BLK1 may be connected to a pass element of the first peripheral circuit region P1 in the second connection region CR2 of the second cell contact region CT2 or in the boundary region BA between the first cell region C1 and the second cell region C2. A plurality of vertical vias connected to the pass elements may be provided in the second connection region CR2 of the second cell contact region CT2 and the boundary region BA.

[0076] Among the plurality of vertical vias, the vertical vias arranged in the second connection region CR2 of the second cell contact region CT2 may be connected to at least some of the cell contacts connected to the word lines of the second memory block BLK2 in the first connection region CR1 of the second cell contact region CT2 by upper wiring lines arranged on the first cell region C1. Among the plurality of vertical vias, the vertical vias arranged in the boundary region BA may be connected to the cell contacts connected to the word lines of the second memory block BLK2 in the first connection region CR1 of the second cell contact region CT2 by upper wiring lines arranged on the first cell region C1.

[0077] The vertical vias arranged in the boundary area BA may be commonly connected to some of the word lines of the second memory block BLK2 and some of the word lines of the fourth memory block BLK4. Some of the word lines of the second memory block BLK2 and the fourth memory block BLK4 may share a pass element through the vertical vias arranged in the boundary area BA. This reduces the number of second pads PAD2 in the second cell contact area CT2 adjacent to the boundary area BA. In addition, by reducing the distance between the first cell area C1 and the second cell area C2, the integration density of the memory device 300 may be improved.

[0078] 9, some of the pass elements disposed under the second cell contact region CT2 may be shared by word lines included in different memory blocks BLK1 to BLK4, so that the number of pass elements disposed under the first cell contact region CT1 may be greater than the number of pass elements disposed under the second cell contact region CT2.

[0079] 10, the memory device 300A may include a peripheral circuit region P and cell regions C1 and C2. The configurations of the peripheral circuit region P and the cell regions C1 and C2 may be the same as those described above with reference to FIG. 9. However, the first cell region C1 and the second cell region C2 may be formed together on one second substrate 302. Thus, the vertical via formed in the boundary region BA may penetrate the second substrate 302 and be connected to the pass element of the first peripheral circuit region P1. A substrate insulating layer for electrically isolating the vertical via from the second substrate 302 may be provided in the boundary region BA.

[0080] Figures 11 to 14 are plan views each showing a schematic configuration of a memory device according to an embodiment of the present invention. Figure 15 is a cross-sectional view taken along line II' in Figure 11, and Figure 16 is a cross-sectional view taken along line II-II' in Figure 11. Figure 17 is a cross-sectional view taken along line III-III' in Figure 12, and Figures 18(a) and (b) are simplified views of a pass element shown in Figure 17.

[0081] 11 and 12, the memory device 400 may include a first memory block 410 and a second memory block 420. The first memory block 410 and the second memory block 420 may each include a cell array region CA, and a first cell contact region CT1 and a second cell contact region CT2 disposed on both sides of the cell array region CA in a first direction (X-axis direction). The first memory block 410 and the second memory block 420 may be adjacent to each other in a second direction (Y-axis direction).

[0082] The first cell contact region CT1 and the second cell contact region CT2 may include a first connection region CR1 and a second connection region CR2, respectively. Referring to Figures 11 and 12, the first cell contact region CT1 of the first memory block 410 may provide the first connection region CR1, and the second cell contact region CT2 may provide the second connection region CR2. The first cell contact region CT1 of the second memory block 420 may provide the second connection region CR2, and the second cell contact region CT2 may provide the first connection region CR1.

[0083] A first pad PAD1 and a second pad PAD2 may be formed in the first connecting region CR1 and the second connecting region CR2. In the first connecting region CR1, the first pad PAD1 and the second pad PAD2 may form a step in the first direction and the second direction, and in the second connecting region CR2, the first pad PAD1 and the second pad PAD2 may form a step in the first direction.

[0084] The second pad PAD2 may have a larger area than the first pad PAD1. As an example, the second pad PAD2 may extend longer than the first pad PAD1 in the first direction. The first pad PAD1 and the second pad PAD2 shown in Figures 11 and 12 are exemplary embodiments, and the lengths of the first pad PAD1 and the second pad PAD2 may be variously modified. As an example, the lengths of the second pad PAD2 in the first direction may be 10 times or more longer than the lengths of the first pad PAD1.

[0085] The first memory block 410 and the second memory block 420 include a plurality of word lines WL stacked along a third direction (Z-axis direction), and a plurality of channel structures CH extending in the third direction and penetrating the word lines WL may be provided in the cell array region CA. The plurality of word lines WL may be divided into the first memory block 410 and the second memory block 420 by a word line cut WC.

[0086] A first and a second cut line CL1, CL2 may be provided between the word line cuts WC that are closest in the second direction. The first cut line CL1 may be formed across the cell array region CA and the cell contact regions CT1, CT2, and the second cut line CL2 may be formed only in the cell contact regions CT1 and CT2. In an embodiment shown in Figures 11 and 12, the second cut line CL2 is not formed in the second connection region CR2.

[0087] In the first pad PAD1 and the second pad PAD2 formed in the first connection region CR1, the word line WL may be connected to the cell contact CC. At least a portion of the cell contact CC may be connected to at least a portion of the vertical vias VV formed in the second connection region CR2. In the second connection region CR2, the vertical vias VV may be connected to circuit elements under the cell array region CA and the contact regions CT1 and CT2. As an example, the vertical vias VV may be connected to pass elements disposed under the contact regions CT1 and CT2. The number and arrangement of the vertical vias VV are not limited to those shown in FIGS. 11 and 12 and may be variously arranged in the second connection region CR2. The number and arrangement of the vertical vias VV may be determined in consideration of the routing of the word line WL.

[0088] As described above, the second cut line CL2 of the first and second cut lines CL1 and CL2 may not be formed in the second connection region CR2. As a result, the process of replacing the sacrificial layer with the word line WL by phosphoric acid flowing through the trench for forming the word line cut WC and the first and second cut lines CL1 and CL2 may not be performed in a part of the second connection region CR2. The vertical via VV may extend in the third direction in the region where the word line WL is not formed and the sacrificial layer remains, and may be connected to the pass element below.

[0089] 11, the first cell contact region CT1 may include five second pads PAD2 arranged in the first direction. In contrast, referring to FIG 12, the second cell contact region CT2 may include three second pads PAD2 arranged in the first direction. As a result, the first memory block 410 and the second memory block 420 may have an asymmetric structure in the first direction with respect to the cell array region CA.

[0090] 11 and 12, in consideration of the routing of the cell contacts CC connected to the word lines WL and the vertical vias VV connected to the cell contacts CC, some of the second pads PAD2 included in the first cell contact region CT1 that are far from the cell array region CA may be omitted from the second cell contact region CT2. In addition, as an embodiment, when the channel structure CH includes a lower channel structure and an upper channel structure connected to each other in a third direction, the second pads PAD2 included in the second cell contact region CT2 may be provided only by the upper word line through which the upper channel structure passes. In other words, the lower word line through which the lower channel structure passes may provide only the first pad PAD1.

[0091] Since the number of second pads PAD2 included in the second cell contact region CT2 is smaller than that of the first cell contact region CT1, another method is required to arrange the vertical vias VV connecting the cell contacts CC and the pass elements to each other. In one embodiment of the present invention, the vertical vias VV can be arranged between the second cell contact regions CT2 adjacent to each other in the first direction to be connected to the cell contacts CC. Also, the pass elements arranged between the second cell contact regions CT2 adjacent to each other in the first direction are commonly connected to at least some of the word lines of different memory blocks to solve the problem of connecting the cell contacts CC and the pass elements. Hereinafter, this will be described with reference to FIG. 13 and FIG. 14.

[0092] 13 and 14, the memory device 400 may include first to fourth memory blocks 410 to 440. A first connection region CR1 of the first memory block 410 and a first connection region CR1 of the third memory block 430 may be adjacent to each other in a first direction, and a second connection region CR2 of the second memory block 420 and a second connection region CR2 of the fourth memory block 440 may be adjacent to each other in the first direction.

[0093] Pass elements PT1 and PT2 may be disposed between a first cell region 400A having a first memory block 410 and a second memory block 420 and a second cell region 400B having a third memory block 430 and a fourth memory block 440. The pass elements PT1 and PT2 may be formed in a peripheral circuit region disposed below the cell regions 400A and 400B, and may include a first pass element PT1 and a second pass element PT2.

[0094] At least a portion of the second pass element PT2 may be commonly connected to at least a portion of the word lines WL of the first memory region 410 and at least a portion of the word lines WL of the third memory region 430. In order to reduce the complexity of the wiring lines connecting at least a portion of the word lines WL to the second pass element PT2, the second pass element PT2 may be disposed between the second connection region CR2 of the first cell region 400A and the second connection region CR2 of the second cell region 400B.

[0095] In an embodiment shown in Fig. 13, the first cell region 400A and the second cell region 400B may be disposed on different second substrates 401A and 401B. Meanwhile, in an embodiment shown in Fig. 14, the first cell region 400A and the second cell region 400B may be disposed on one second substrate 401A. Thus, in the embodiment shown in Fig. 14, the vertical via VV connected to the second pass element PT2 may penetrate the second substrate 401A. In an embodiment, a substrate insulating layer 403 may be formed on the second substrate 401A to separate the vertical via VV and the second substrate 401A.

[0096] Figure 15 is a cross-sectional view taken along the line I-I' of Figure 11. Referring to Figures 15 and 16 together with Figure 11, the memory device 400 may include a peripheral circuit region P and a cell region C on the upper side of the peripheral circuit region P. The peripheral circuit region P may include a first substrate 405 and circuit elements formed on the first substrate 405. As an example, the circuit elements may be pass elements 406 included in a row decoder and electrically connected to word lines WL, and may be covered by a lower interlayer insulating layer 408.

[0097] The cell region C may be formed in the second substrate 401 on the lower interlayer insulating layer 408. The cross section in the I-I' direction of FIG. 11 shown in FIG. 15 may correspond to the second connection region CR2 of the memory device 400. In the second connection region CR2, the second cut line CL2 is not formed, and the sacrificial layer SL may remain without being removed. Thus, as shown in FIG. 15, the sacrificial layer SL and the insulating layer IL may be alternately stacked on the second substrate 401. The sacrificial layer SL may include an insulating material different from that of the insulating layer IL.

[0098] In the second connection region CR2, the sacrificial layer SL and the insulating layer IL may provide a first pad PAD1 and a second pad PAD2. In the first direction (X-axis direction), the length D1 of the first pad PAD1 may be smaller than the length of each of the second pads PAD2. A vertical via VV is formed in the second pad PAD2, and the vertical via VV may extend to the peripheral circuit region P and be connected to the pass element 406. In the region where the vertical via VV penetrates, the second substrate 401 may be made of an insulating material.

[0099] Figure 16 is a cross-sectional view taken along line II-II' in Figure 11, and Figure 17 is a cross-sectional view taken along line III-III' in Figure 12. Referring to Figures 11 and 12, Figure 16 is a cross-sectional view showing a portion of the second connection region CR2 of the first cell contact region CT1, and Figure 17 is a cross-sectional view showing a portion of the second connection region CR2 of the second cell contact region CT2.

[0100] In an embodiment of the present invention, the second connection region CR2 of the first cell contact region CT1 and the second connection region CR2 of the second cell contact region CT2 may have different structures. Referring to Figures 16 and 17, the second connection region CR2 of the first cell contact region CT1 and the second connection region CR2 of the second cell contact region CT2 may have different structures at a certain height or less from the top surface of the second substrate 401. The difference in structure may be caused by a difference in the number of second pads PAD2 included in the second connection region CR2 of the first cell contact region CT1 and the second connection region CR2 of the second cell contact region CT2.

[0101] In one embodiment, the number of second pads PAD2 included in the second connection region CR2 of the first cell contact region CT1 may be greater than the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2. Since the second connection region CR2 of the first cell contact region CT1 includes a greater number of second pads PAD2 than the second connection region CR2 of the second cell contact region CT2, the first cell contact region CT1 may extend longer in the first direction than the second cell contact region CT2. Thus, at least one of the word lines WL may have a length that is extended to the first cell contact region CT1, which is a first side of the cell array region CA, in the first direction, different from a length that is extended to the second cell contact region CT2, which is a second side of the cell array region CA. For example, the word line WL at the bottom may extend longer in the first direction in the first cell contact region CT1 than in the second cell contact region CT2.

[0102] As an example, the difference between the number of second pads PAD2 included in the second connection region CR2 of the first cell contact region CT1 and the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2 may be 2 or more. In addition, in one embodiment, the length of the second cell contact region CT2 in the first direction is greater than 0.6 times and less than 0.9 times the length of the first cell contact region CT1. In one embodiment, the length of each of the second pads PAD2 in the first direction may be 10 times or more the length of each of the first pads PAD1, and the above-mentioned length shortening effect can be obtained by reducing the number of second pads PAD2 included in the second cell contact region CT2 by 2 or more compared to the first cell contact region CT1.

[0103] 17, the pass elements 406, 407 may include a first pass element 406 and a second pass element 407. The second pass element 407 may be disposed outside the second connection region CR2 of the second cell contact region CT2 in the first direction and may be connected to at least two or more word lines WL through vertical vias VV. By connecting the second pass element 407 to two or more word lines WL and reducing the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2, the integration density of the memory device 400 may be improved.

[0104] The second pass element 407 may have a different shape and / or size than the first pass element 406 because it is connected to two or more word lines WL and needs to drive the two or more word lines WL simultaneously. Referring to FIGS. 18(a) and 18(b), the first pass element 406 and the second pass element 407 may each include a gate G, a source region S on both sides of the gate G, and a drain region D. As an example, a length Lg2 of the gate of the second pass element 407 may be greater than a length Lg1 of the gate of the first pass element 406. Also, in one embodiment, a length H2 of the source region S and the drain region D of the second pass element 407 may be greater than a length H1 of the source region S and the drain region D of the first pass element 406 in the second direction.

[0105] 19 and 20 are cross-sectional views illustrating a cell contact region of a memory device according to an embodiment of the present invention.

[0106] 19, the memory device 500 may include a peripheral circuit region P and a cell region C stacked in a third direction (Z-axis direction). The peripheral circuit region P may include a first substrate 505, circuit elements 506 and 507 formed on the first substrate 505, and a lower interlayer insulating layer 508 covering the circuit elements 506 and 507. As an example, the circuit elements 506 and 507 may be pass elements included in a row decoder.

[0107] The cell region C may include a first cell region 500A and a second cell region 500B. The cell region C may also include a plurality of second substrates 501A, 501B, a plurality of sacrificial layers SL stacked thereon, and an insulating layer IL. The sacrificial layer SL and the insulating layer IL provide steps in a first direction (X-axis direction) and a second direction (Y-axis direction), and the steps may form a first pad PAD1 and a second pad PAD2. The first pad PAD1 may have a length shorter than the second pad PAD2 in the first direction.

[0108] 19, the sacrificial layer SL may be a layer that is not removed but remains in the process for forming the word lines. The sacrificial layer SL may remain in the region where the vertical vias VV are formed, and the sacrificial layer SL may be replaced with the word lines in the region where the vertical vias VV are not formed. The vertical vias VV may be connected to the pass elements 506 and 507 through the sacrificial layer SL and the insulating layer IL.

[0109] For example, at least one of the vertical vias VV may penetrate the sacrificial layer SL and the insulating layer IL in the second pad PAD2 to be connected to the first pass element 506. Also, at least one of the vertical vias VV may be connected to the second pass element 507 in the boundary area BA between the second substrate 501A of the first cell region 500A and the second substrate 501B of the second cell region 500B.

[0110] The second pass element 507 may be connected to a pair of word lines included in the first cell region 500A and the second cell region 500B through a vertical via VV, an upper wiring line UW, and a cell contact CC. As an example, the pair of word lines may be disposed at the same height in the third direction. In an embodiment shown in FIG. 19, the pair of word lines may be located behind the sacrificial layer SL in the second direction.

[0111] 20, the memory device 600 may include a peripheral circuit region P and a cell region C. The configurations of the peripheral circuit region P and the cell region C may be similar to those of the memory device 500 previously described with reference to FIG. 19. For example, the cell region C may include a first cell region 600A and a second cell region 600B adjacent to each other in a first direction.

[0112] 20, the first cell region 600A and the second cell region 600B may be disposed on one second substrate 605. In other words, the second substrate 605 may extend from the first cell region 600A to the second cell region 600B. At least one of the vertical vias VV may extend to the peripheral circuit region P through a substrate insulating layer 603 formed in a boundary region BA between the first cell region 600A and the second cell region 600B.

[0113] The thickness of the word lines in the memory devices 500, 600 may be substantially the same as the thickness of the sacrificial layer SL. The thickness of the word lines determines the gate length of each memory cell, and the characteristics of the memory cell may vary. In the embodiment of the present invention, the thickness of the word lines may vary depending on whether the word lines are connected solely to the first pass element 506, 606, or whether they share the second pass element 507, 607 with at least one of the other word lines, or whether the word lines are located at any position in the cell region C in the third direction.

[0114] FIG. 21 is a cross-sectional view illustrating a cell array region of a memory device according to an embodiment of the present invention.

[0115] 21, the memory device 700 may include a peripheral circuit region P and a cell region C, and the cell region C may be disposed on the peripheral circuit region P. The peripheral circuit region P may include a first substrate 701, circuit elements 702 formed on the first substrate 701, lower wiring lines 703 connected to the circuit elements 702, and a lower interlayer insulating layer 704. As an example, the circuit elements 702 may provide a page buffer, etc.

[0116] The cell region C may include word lines WL stacked on the second substrate 710, channel structures CH penetrating the word lines WL, and word line cuts WC dividing the word lines WL into a plurality of regions. The word lines WL may be stacked alternately with insulating layers IL and may be extended in a first direction (X-axis direction) and a second direction (Y-axis direction) to form pads having steps. As described above in various embodiments, the pads may include first and second pads, and each of the first pads may have a shorter length in the first direction than each of the second pads. As an example, the memory device 700 shown in FIG. 21 may include the first and second cell contact regions described above with reference to FIGS. 11 and 12, and the first and second cell contact regions may be located on both sides of the cell region C in the first direction.

[0117] The channel structures CH may be connected to the bit lines BL by bit line contacts BLC. In the embodiment shown in FIG. 21, the channel structures CH arranged at the same position in the first direction are connected to one bit line BL, but the present invention is not limited to this. The bit line contacts BLC may connect the channel structures CH and the bit lines BL by penetrating the upper interlayer insulating layer 705.

[0118] The second substrate 710 may include first to third layers 711 to 713. The first to third layers 711 to 713 provide an effect of connecting the channel structures CH arranged between the word line cuts WC to one common source line. Hereinafter, the memory device 700 shown in FIG. 21 will be described in more detail with reference to FIGS. 22 to 24(b).

[0119] 22 to 24(b) are enlarged views of a portion of FIG.

[0120] First, Fig. 22 is an enlarged view of region B in Fig. 21. Referring to Fig. 22, a second substrate 710 may include first to third layers 711 to 713. In addition, a channel structure CH may include a data storage layer 720, a channel layer 730, a buried insulating layer 740, and the like.

[0121] Each of the first to third layers 711 to 713 of the second substrate 710 may include polysilicon doped with a first conductive type impurity. As an example, the first to third layers 711 to 713 may be doped with an N-type impurity. Referring to FIG. 21, among the first to third layers 711 to 713 included in the second substrate 710, the first layer 711 and the second layer 712 may be separated from each other in the second direction by the word line cut WC. As a result, the channel structures CH located between a pair of word line cuts WC adjacent to each other in the second direction may be connected to each other by the second substrate 710.

[0122] The data storage layer 720 may include a plurality of layers 721 to 723. For example, the data storage layer 720 may include a blocking layer 721, a charge storage layer 722, and a tunnel layer 723. Here, the number, arrangement order, and materials of the layers 721 to 723 included in the data storage layer 720 may be variously modified. The channel layer 730 may be formed of a semiconductor material, for example, polysilicon, and an internal space of the channel layer 730 may be filled with a buried insulating layer 740, for example, silicon oxide.

[0123] Figures 23(a) and (b) are enlarged views of regions C1 and C2 in Figure 21. Referring to Figures 23(a) and (b), a channel structure CH penetrates a word line WL and an insulating layer IL, and the word line WL and the insulating layer IL can be divided into multiple regions by a word line cut WC.

[0124] In the memory device 700 according to an embodiment shown in FIG. 21, the channel structure CH and the word line cut WC may have a shape in which the width becomes narrower in the third direction (Z-axis direction) toward the second substrate 710. In other words, the side surfaces of the channel structure CH and the word line cut WC on the cross section of FIG. 23(a) and (b) may have a gently inclined shape without being completely perpendicular to the upper surface of the second substrate 710. Referring to FIG. 23(a) and (b), the word line cut WC may have a first width Y1 in a C1 region located at a relatively upper portion and a second width Y2 smaller than the first width Y1 in a C2 region located at a relatively lower portion.

[0125] 23(a) and 23(b), a first width W1 of the word lines WL located in the C1 region may be smaller than a second width W1 of the word lines WL located in the C2 region. Due to the difference in width, the resistance of the word lines WL in the C1 region may be larger than the resistance of the word lines WL in the C2 region. In one embodiment of the present invention, the connection relationship between the word lines WL and the pass elements may be determined taking into account the resistance difference between the word lines WL.

[0126] According to an embodiment of the present invention, the memory device 700 may include a first pass element and a second pass element disposed in a peripheral circuit region P, and each of the second pass elements may be connected to at least two or more word lines WL. As described above, each of the second pass elements may be shared by word lines WL disposed at the same height in different cell regions. In contrast, each of the first pass elements may be connected to one word line WL.

[0127] In one embodiment of the present invention, the second pass element may be connected to a word line WL having a relatively low resistance. For example, in one embodiment shown in Figures 23(a) and 23(b), the word lines WL in the C1 region having a relatively high resistance may be connected to the first pass element, and the word lines WL in the C2 region having a relatively low resistance may be connected to the second pass element. However, in one cell region C of the memory device 700, the number of word lines WL connected to the first pass element may be greater than the number of word lines WL connected to the second pass element.

[0128] In addition, in one embodiment of the present invention, in order to reduce the variation in the resistance characteristics of the word lines WL, at least some of the word lines WL may be formed with different thicknesses. Referring to Figures 24(a) and 24(b), the word lines WL in the C1 region may be formed with a first thickness T1, and the word lines WL in the C2 region may be formed with a second thickness T2. The first thickness T1 may be greater than the second thickness T2.

[0129] 24(a) and 24(b), the difference between the resistance of the word lines WL in the C1 region and the resistance of the word lines WL in the C2 region can be reduced, and the word lines WL in the C1 region can also be connected to the second pass element, if necessary. For example, the word lines WL in the C1 region can be connected to the second pass element, and the word lines WL in the C2 region can be connected to the first pass element.

[0130] 24(a) and 24(b), the word lines WL in the C2 region may be formed to have a greater thickness than the word lines WL in the C1 region, and the word lines WL in the C2 region may be connected to the second pass element. Since the resistance of the word lines WL in the C2 region connected to the second pass element is reduced, the load of the second pass element may be reduced, and depending on the embodiment, the second pass element may be formed to be the same size as the first pass element.

[0131] FIG. 25 is a cross-sectional view illustrating a cell array region of a memory device according to an embodiment of the present invention.

[0132] 25, a memory device 800 includes a peripheral circuit region P and a cell region C, and the cell region C may be disposed on the upper portion of the peripheral circuit region P. The configuration of the peripheral circuit region P may be similar to that of the memory device 700 described with reference to FIG.

[0133] The cell region C may include word lines LWL, DWL, and UWL stacked on the second substrate 810, a channel structure CH penetrating the word lines LWL, DWL, and UWL, and a word line cut WC dividing the word lines LWL, DWL, and UWL into a plurality of regions. The second substrate 810 may include first to third layers 811 to 813, and the configuration of the second substrate 810 may be understood with reference to what has been described above with reference to FIG.

[0134] The word lines LWL, DWL, and UWL may include a lower word line LWL, at least one dummy word line DWL, and an upper word line UWL. The lower word line LWL is stacked from the upper surface of the second substrate 810, and a lower channel structure CH2 extending from the upper surface of the second substrate 810 may penetrate the lower word line LWL. The upper word line UWL is stacked on the lower word line LWL, and an upper channel structure CH1 extending from the lower channel structure CH2 may penetrate the upper word line UWL.

[0135] The dummy word line DWL may be disposed between the lower word line LWL and the upper word line UWL. As an example, the dummy word line DWL may be embedded in a boundary region between the upper channel structure CH1 and the lower channel structure CH2. Depending on the embodiment, other dummy word lines DWL may be added at various positions.

[0136] In the memory device 800 according to an embodiment shown in FIG. 25, the channel structure CH may be formed by dividing it into an upper channel structure CH1 and a lower channel structure CH2. In contrast, the word line cut WC may be formed at once. As a result, in a plane parallel to the first direction (X-axis direction) and the second direction (Y-axis direction), the area of ​​the upper word line UWL may be smaller than the area of ​​the lower word line LWL, and the resistance of the upper word line UWL may be increased. This will be described in more detail with reference to FIG. 26(a) to FIG. 27(b).

[0137] 26(a) to 27(b) are enlarged views showing a partial area of ​​FIG.

[0138] 26(a) and (b) are enlarged views of E1 and E2 regions in FIG. 25. Referring to FIG. 26(a), an upper channel structure CH1 penetrates an upper word line UWL and an insulating layer IL, and the upper word line UWL and the insulating layer IL can be divided into a plurality of regions by a word line cut WC. Similarly, referring to FIG. 26(b), a lower channel structure CH2 penetrates a lower word line LWL and an insulating layer IL, and the lower word line LWL and the insulating layer IL can be divided into a plurality of regions by a word line cut WC.

[0139] The upper channel structure CH1 and the lower channel structure CH2 may each include a data storage layer 820, a channel layer 830, and a buried insulating layer 840. The data storage layer 820 may include a blocking layer 821, a charge storage layer 822, and a tunnel layer 823.

[0140] For example, the height from the bottom surface of the upper channel structure CH1 to the E1 region may be the same as the height from the bottom surface of the lower channel structure CH2 to the E2 region. Thus, the upper channel structure CH1 and the lower channel structure CH2 may have substantially the same size in each of the E1 region and the E2 region. However, the word line cut WC may be formed in a single process in the entire cell region C, and the width of the word line cut WC may gradually decrease closer to the second substrate 810. Referring to FIGS. 26(a) and 26(b), the first width Y1 of the word line cut WC in the E1 region may be greater than the second width Y2 of the word line cut WC in the E2 region.

[0141] Thus, the first width W1 of the upper word line UWL in the E1 region may be smaller than the second width W2 of the lower word line LWL in the E2 region, and the upper word line UWL may have a relatively large resistance compared to the lower word line LWL. In an embodiment of the present invention, the upper word line UWL may be connected to a first pass element and at least a part of the lower word line LWL may be connected to a second pass element in consideration of the resistance characteristics. The first pass elements may be elements connected to one of the upper and lower word lines UWL and LWL, and the second pass elements may be connected to two or more different lower word lines LWL. The two or more lower word lines LWL connected to each of the second pass elements may be included in different cell regions C.

[0142] Next, in an embodiment shown in Figures 27(a) and (b), at least a portion of the upper word line UWL may have a thickness greater than that of the lower word line LWL. Referring to Figures 27(a) and (b), the upper word line UWL may have a first thickness T1, and the lower word line LWL may have a second thickness T2 less than the first thickness T1. This can reduce the resistance of the upper word line UWL, and the upper word line UWL can be connected to the second pass element as necessary. The thicknesses of the upper word line UWL and the lower word line LWL can be modified in various ways. For example, by increasing the thickness of the lower word line LWL connected to the second pass element, the load of the second pass element can be reduced and the driving characteristics can be improved.

[0143] FIG. 28 is a block diagram showing a simplified electronic device including a memory device according to an embodiment of the present invention.

[0144] The electronic device 1000 according to the embodiment shown in FIG. 28 may include a display 1010, a sensor unit 1020, a memory 1030, a communication unit 1040, a processor 1050, and a port 1060. In addition, the electronic device 1000 may further include a power supply device, an input / output device, and the like. Among the components shown in FIG. 28, the port 1060 may be a device provided for the electronic device 1000 to communicate with a video card, a sound card, a memory card, a USB device, and the like. The electronic device 1000 may be a concept that encompasses not only general desktop computers and laptop computers, but also smartphones, tablet PCs, smart wearable devices, and the like.

[0145] The processor 1050 can execute specific calculations, commands, tasks, etc. The processor 1050 can be a central processing unit (CPU) or a microprocessor unit (MCU), a system on chip (SoC), etc., and can communicate with the display 1010, the sensor unit 1020, the memory 1030, the communication unit 1040, and other devices connected to the port 1060 via the bus 1070.

[0146] The memory 1030 may be a storage medium for storing data required for the operation of the electronic device 1000 or multimedia data. The memory 1030 may include a volatile memory such as a random access memory (RAM) or a non-volatile memory such as a flash memory. The memory 1030 may also include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. In an embodiment shown in FIG. 28, the memory 1030 may include a memory device according to various embodiments described above with reference to FIGS. 1 to 27.

[0147] Although the embodiments of the present invention have been described in detail above, it will be apparent to those having ordinary skill in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible within the scope that does not deviate from the technical idea of ​​the present invention described in the claims. [Explanation of symbols]

[0148] 10, 40, 400, 500, 600, 700, 800 memory devices 50, C cell area 60, P peripheral circuit area CA cell array area CT1 First cell contact area CT2 Second cell contact area CR1 1st consolidated area CR2 2nd consolidated area CH Channel structure WL Word Line BL Bit Line WC Word Line Cut PT Pass Element

Claims

1. a first substrate; and circuit elements formed on the first substrate, the circuit elements including a peripheral circuit region providing a row decoder; a cell array region having word lines stacked on a second substrate above the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the word lines; a cell contact region including a cell contact connected to the word line, the cell contact region having a first cell contact region and a second cell contact region disposed on both sides of the cell array region in a first direction parallel to an upper surface of the second substrate, the first cell contact region having a length longer than a length of the second cell contact region in the first direction; each of the first cell contact region and the second cell contact region includes a first pad, the cell contact being connected to the word line, and a second pad extending in the first direction to a length greater than that of the first pad, and a number of the second pads included in the first cell contact region is greater than a number of the second pads included in the second cell contact region; the row decoder includes first and second pass elements connected to the word lines, each of the first pass elements being connected to one of the word lines, and each of the second pass elements being connected to two or more different word lines.

2. 2. The memory device of claim 1, wherein a sum of the areas of the first pad and the second pad included in the first cell contact region is greater than a sum of the areas of the first pad and the second pad included in the second cell contact region.

3. 2. The memory device of claim 1, wherein the two or more different word lines connected to one of the second pass elements are disposed at the same height in a direction perpendicular to an upper surface of the second substrate.

4. The memory device of claim 1 , wherein an area of ​​at least one of the second pass elements is greater than an area of ​​each of the first pass elements.

5. 2. The memory device of claim 1, wherein a total number of word lines coupled to the first pass elements is greater than a total number of word lines coupled to the second pass elements.

6. The memory device of claim 1, wherein the resistance of each of the word lines connected to the second pass element is smaller than the resistance of each of the word lines connected to the first pass element.

7. The memory device of claim 5, wherein a thickness of each of the word lines connected to the second pass element is greater than a thickness of each of the word lines connected to the first pass element.

8. The memory device of claim 7, wherein an area of ​​at least one of the second pass elements is the same as an area of ​​each of the first pass elements.

9. each of the channel structures includes a lower channel structure extending from a top surface of the second substrate and an upper channel structure extending from the lower channel structure; 2. The memory device of claim 1, wherein the word lines include a lower word line through which the lower channel structure passes and an upper word line through which the upper channel structure passes, at least one of the lower word lines being connected to at least one of the second pass elements.

10. 10. The memory device of claim 9, wherein the upper word line is coupled to the first pass element.

11. The memory device of claim 9 , wherein a thickness of at least a portion of the upper word lines is greater than a thickness of the lower word lines.

12. 10. The memory device of claim 9, wherein the word lines include at least one dummy word line disposed between the lower word line and the upper word line and adjacent a boundary between the lower channel structure and the upper channel structure.

13. 13. The memory device of claim 1, wherein the cell contact region includes an upper wiring line connected to the cell contact, and a vertical via connected to the upper wiring line and extending to the peripheral circuit region in a direction perpendicular to the top surface of the second substrate.

14. The memory device of claim 13 , wherein the vertical via passes through at least one of the second pads.

15. The second substrate includes a plurality of second substrates separated from each other, The memory device of claim 13 , wherein at least one of the vertical vias is disposed between the second substrate.

16. a peripheral circuit region including a pass element formed on a first substrate; a plurality of cell regions disposed on the second substrate above the peripheral circuit region, each cell region including at least one memory block; Each of the cell regions includes a cell array region in which a plurality of word lines connected to the pass elements and a plurality of channel structures passing through the word lines are disposed, and a cell contact region in which the word lines extending from the cell array region are connected to a plurality of cell contacts, At least one of the pass elements is commonly connected to a pair of word lines included in a pair of adjacent cell regions among the cell regions and disposed at the same height from an upper surface of the second substrate; Each of the cell regions includes a first cell contact region disposed on a first side of the cell array region and a second cell contact region disposed on a second side of the cell array region opposite the first side, A memory device, wherein an area of ​​the first cell contact region covering the upper surface of the second substrate is greater than an area of ​​the second cell contact region covering the upper surface of the second substrate.

17. The cell region includes a first cell region and a second cell region adjacent to each other in a first direction parallel to an upper surface of the second substrate, and a third cell region and a fourth cell region adjacent to each other in the first direction, the first cell contact region of the first cell region and the first cell contact region of the second cell region are adjacent to each other, and the second cell contact region of the third cell region and the second cell contact region of the fourth cell region are adjacent to each other, 17. The memory device of claim 16, wherein a distance between the cell array region of the first cell region and the cell array region of the second cell region is greater than a distance between the cell array region of the third cell region and the cell array region of the fourth cell region.

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