Forceless vertical transport field-effect transistor with dipole liner.

Abstract

The semiconductor structure may include a lower source / drain, an upper source / drain, and a gate stack. The upper source / drain is above the gate stack, and the lower source / drain is below the gate stack. The semiconductor structure may also include a lower spacer and an upper spacer. The gate stack is between the lower spacer and the upper spacer. The lower spacer and the upper spacer each include a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of a different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the upper source / drain, and the lower source / drain.

Description

[Technical field]

[0001] The present invention relates generally to semiconductor structures and methods of forming same, and more particularly, to semiconductor structures including wimpy vertical transport field effect transistors with dipole liners. [Background technology]

[0002] Devices in non-critical circuit paths preferably have a higher threshold voltage than standard devices. This assists in maintaining low leakage rates without compromising the performance of the circuit. These devices with a higher threshold voltage are called "non-power" devices. Traditionally, non-power devices are fabricated with longer gate lengths and have higher channel doping than standard devices. Non-power devices in non-critical circuit paths reduce the power consumption of the chip. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a lower source drain, an upper source drain, and a gate stack. The upper source drain is above the gate stack, and the lower source drain is below the gate stack. The semiconductor structure may also include a lower spacer and an upper spacer. The gate stack is between the lower spacer and the upper spacer. The lower spacer and the upper spacer each include a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of a different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the upper source drain, and the lower source drain. The lower spacer may include a dielectric. The dielectric may be in direct contact with the dipole liner.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a vertical field effect transistor, the vertical field effect transistor including an upper source drain, a lower source drain, a lower spacer, an upper spacer, and a gate stack. The lower source drain is separated from the gate stack by the lower spacer. The lower spacer may include a dipole liner contacting the lower source drain. The upper source drain may be separated from the gate stack by the upper spacer. The upper spacer may include a dipole liner. The dipole liner may contact the upper source drain. The dipole liner may include a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of a different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the upper source drain, and the lower source drain. The lower spacer may include a dielectric. The dielectric may be in direct contact with the dipole liner.

[0005] According to another embodiment of the present invention, a method is provided. The method may include forming a lower source drain on a substrate, forming a lower spacer that may be in direct contact with the lower source drain and may include a dipole liner, forming a gate stack above the lower spacer, forming an upper spacer above the gate stack that may be in direct contact with the gate stack and may include a dipole liner, and forming an upper source drain above the upper spacer. The dipole liner may include a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of a different material than the first layer. The first layer may be in direct contact with the gate stack, the upper source drain, and the lower source drain. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The lower spacer may include a dielectric. The dielectric may be in direct contact with the dipole liner.

[0006] The following detailed description is given by way of example and is not intended to be limiting of the invention, and will be best understood in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0007] [Figure 1] 1A-1C are cross-sectional views illustrating the formation of vertical fins on a substrate according to an exemplary embodiment. [Diagram 2] 11A-11C are cross-sectional views illustrating forming spacers along vertical sidewalls of a fin according to an exemplary embodiment. [Diagram 3] 1A-1D are cross-sectional views illustrating recessing a substrate according to an exemplary embodiment. [Figure 4] 1 is a cross-sectional view illustrating forming a lower source-drain according to an exemplary embodiment. [Diagram 5] 11A-11C are cross-sectional views illustrating removing a spacer according to an exemplary embodiment. [Figure 6]11A-11C are cross-sectional views illustrating forming a lower spacer with a dual layer dipole liner according to an exemplary embodiment. [Figure 7] 1A-1C are cross-sectional views illustrating deposition of a gate dielectric material, a workfunction metal, and a metal gate according to an exemplary embodiment. [Figure 8] 11A-11C are cross-sectional views illustrating forming an upper spacer with a dual layer dipole liner according to an exemplary embodiment. [Figure 9] 4A-4C are cross-sectional views illustrating removing a portion of the top spacer, the metal gate, and the bottom spacer and filling the resulting opening with an interlevel dielectric according to an illustrative embodiment. [Figure 10] 1 is a cross-sectional view illustrating forming an upper source-drain according to an exemplary embodiment. [Figure 11] 1A-1D are cross-sectional views illustrating forming an interlayer dielectric and contacts according to an exemplary embodiment. [Figure 12] 1A-1C are cross-sectional views illustrating standard and non-force vertical transport field effect transistors according to example embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The drawings are not necessarily to scale. The drawings are merely schematic and are not intended to depict specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, and that the claimed structures and methods may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Instead, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0010] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods as oriented in the drawings. The terms "overlaying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, and there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0011] In order not to obscure the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on the distinctive features or elements of various embodiments of the present invention.

[0012] FIELD OF THE DISCLOSURE

[0002] Embodiments of the present invention relate generally to semiconductor structures and methods of forming the same. More particularly, the present invention relates to semiconductor structures that may include non-force vertical transport field effect transistors having dipole liners. Vertical transport field effect transistors are hereafter referred to as vertical transistors.

[0013] To reduce the power consumption of a chip, non-power devices may be used in non-critical circuit paths. Traditionally, non-power devices are fabricated with longer gate lengths than standard devices and have higher channel doping than standard devices. For lateral field effect transistors, non-power devices have gate lengths 3-4 nm longer than nominal devices, translating into non-power devices with threshold voltages about 20 mV higher. However, for vertical field effect transistors, it is difficult to fabricate standard and non-power devices with different gate lengths. Fabricating vertical transistors with different gate lengths side-by-side creates topography challenges since non-power vertical transistors are shorter than standard vertical transistors. Thus, there is a need for a method and structure for fabricating non-power vertical transistors that can be easily inserted into the normal process of a record flow to form non-power vertical transistors and standard vertical transistors side-by-side.

[0014] The embodiments of the present invention propose a method and structure for fabricating a non-force vertical transistor by having a spacer material with a dipole liner. To form a non-force vertical transistor, the embodiments of the present invention propose forming a bilayer dipole liner along the channel where the lower spacer and the upper spacer are located. The bilayer dipole liner becomes part of the respective lower spacer and upper spacer. The resulting vertical transistor with the dipole liner is non-force since it has a longer effective gate length and less voltage leakage. The embodiments of the present invention use the dipole liner to change the electric field near the source-drain region of the vertical transistor, changing the threshold voltage by a small range.

[0015] 1-12 illustrate an exemplary semiconductor structure including a non-forced vertical transistor with a dipole liner.

[0016] Referring now to FIG. 1, a structure 100 is shown according to an embodiment. The structure 100 may include a substrate 102, a hard mask cap 104, and a fin 200. The substrate 102 may include one or more semiconductor materials. Non-limiting examples of suitable materials for the substrate 102 may include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. In some embodiments, the substrate 102 may include silicon. In one embodiment, the substrate 102 is a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate composed entirely of one or more semiconductor materials. In one example, a bulk semiconductor substrate is composed entirely of silicon.

[0017] A hard mask layer (not shown) may be deposited on the top surface of the substrate 102. The hard mask layer may include any dielectric material, such as, for example, silicon dioxide, silicon nitride, or silicon oxynitride, or a combination thereof. In some embodiments, the hard mask layer may be formed using a conventional deposition process, such as, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In other embodiments, the hard mask layer may be formed using a thermal growth process, such as, for example, thermal oxidation. In yet other embodiments, the hard mask layer may be formed by a combination of a deposition process and a thermal growth process. The hard mask layer may have a thickness ranging from about 10 nm to about 25 nm. Other thicknesses of the hard mask layer are also possible and may be used in the present application.

[0018] After forming the hard mask layer on the top surface of the substrate 102, the hard mask layer and the substrate 102 are patterned (not shown). The patterning may be performed by lithography and etching. The patterning of the hard mask layer and the substrate 102 results in the formation of a hard mask cap 104 and fins 200. The remaining portion of the hard mask layer, i.e., the portion that is not etched, is referred to herein as the hard mask cap 104. The fins 200 each include a pair of vertical sidewalls that are parallel or substantially parallel to one another. Although described and illustrated as two fins 200 being formed, a single fin 200 or multiple fins 200 may be formed. Each fin 200 may have a vertical height ranging from about 20 nm to about 150 nm, a width from 5 nm to 30 nm, and a length from 20 nm to 300 nm. Other vertical heights or widths or lengths or combinations thereof lesser or greater than the ranges stated herein may also be used in the present application.

[0019] Referring now to FIG. 2, a structure 100 with sidewall spacers 106 is shown according to an embodiment. First, a spacer layer (not shown) is conformally deposited on the top surface of the substrate 102 and the hard mask cap 104, as well as on the sidewalls of the fin 200 and the sidewalls of the hard mask cap 104. The spacer layer may include an insulating material such as, for example, silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of spacer layer materials may include a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The spacer layer may be deposited by a deposition process, for example, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The spacer layers may each have a thickness ranging from about 3 nm to about 15 nm, or from about 5 nm to about 8 nm.

[0020] Once the spacer layer is conformally deposited, it is then etched back to form sidewall spacers 106. To form the sidewall spacers 106, the spacer layer may be etched by a dry etching process, e.g., a reactive ion etching process, such that the spacer layer remains on the sidewalls of the hard mask cap 104 and the sidewalls of the fin 200 but is removed from the top surface of the substrate 102 and the top surface of the hard mask cap 104. The sidewall spacers 106 are disposed along the sidewalls of the fin 200 and the sidewalls of the hard mask cap 104. The sidewall spacers 106 protect the sidewalls of the fin 200 from damage during subsequent fabrication processes.

[0021] 3, a structure 100 is shown in which the substrate 102 has been further recessed, according to an embodiment. Once the sidewall spacers 106 have been formed, the substrate 102 may be further recessed using another etching process that is selective to (does not substantially remove) the sidewall spacers 106 or the hard mask cap 104. The etching process may be, for example, a dry anisotropic etching process. Recessing the substrate 102 exposes the sidewalls of the substrate 102 directly below the sidewall spacers 106. Having the sidewall spacers 106 around the fin 200 during the etching process creates a lower portion of the substrate 102 directly below the fin 200 that is wider compared to the width of the fin 200 itself.

[0022] 4, a structure 100 is shown with a source-drain epitaxy 108 and a lower source-drain 110 according to an embodiment. The substrate 102 is further etched back to expose its sidewalls, and the source-drain epitaxy 108 is grown on top of the substrate 102. The source-drain epitaxy 108 may be grown to a thickness such that the top surface of the source-drain epitaxy 108 is substantially flush with the bottom surface of the spacer 106. The source-drain epitaxy 108 may be made of silicon or silicon-germanium and may be in-situ doped. In an embodiment, the source-drain epitaxy 108 may be heavily doped with a dopant, which may be a p-type dopant (e.g., boron or gallium). In an alternative embodiment, the source-drain epitaxy 108 may be heavily doped with a dopant, which may be an n-type dopant (eg, antimony, arsenic, or phosphorous).

[0023] Once the source drain epitaxy 108 is deposited, the structure 100 undergoes a drive-in anneal process to drive some of the dopants from the source drain epitaxy 108 into a portion of the substrate 102 underlying the fin 200. Drive-in annealing of some of the dopants from the source drain epitaxy 108 into the substrate 102 creates a lower source drain near the channel 111, forming a junction. The lower source drain 110 is substrate material doped with some of the p-type dopants transferred from the source drain epitaxy 108. The lower source drain 110 is located laterally adjacent to the source drain epitaxy 108. Once the lower source drain 110 is formed, the remainder of the substrate above the lower source drain 110 may be referred to as the channel 111. The channel 111 is made of the same material as the substrate 102.

[0024] In one embodiment, the structure 100 may also include a shallow trench isolation (STI) (not shown) between the two fins 200. The STI may be formed in a number of ways. In one embodiment, a single etch process or multiple etch processes may also be performed to remove a portion of the source-drain epitaxy 108 and the substrate 102 between the two fins 200. The resulting trench (not shown) may extend from the top surface of the source-drain epitaxy 108 through a portion of the substrate 102. The trench is then filled with a dielectric material forming the STI 136. The STI 136 is in the form of a dielectric plug that separates the two fins 200 such that current applied to one fin does not affect the second fin. Typically, the STI 136 extends through a portion of the substrate 102 to a depth sufficient to electrically isolate the two fins.

[0025] 5, there is shown the structure 100 with the sidewall spacers 106 removed, according to one embodiment. After the lower source-drain 110 is formed, the sidewall spacers 106 are removed from the sidewalls of the fin 200, thereby exposing the sidewalls of the fin 200. The sidewall spacers 106 may be etched using a process that is selective to (does not substantially remove) the hard mask cap 104, the substrate 102, the source-drain epitaxy 108, or the lower source-drain 110.

[0026] Referring now to FIG. 6, a structure 100 with a bottom spacer 118 is shown according to an embodiment. The bottom spacer 118 may include a first layer 112, a second layer 114, and a dielectric 116. The first layer 112 may be made of a material such as, for example, silicon oxide. The second layer 114 may be made of a different material depending on whether the non-power device is a p-type or n-type vertical transistor. For a p-type vertical transistor, the second layer 114 may be made of silicon nitride, and for an n-type vertical transistor, the second layer 114 may be made of aluminum oxide. The first layer 112 and the second layer 114 may be collectively referred to as a bilayer dipole liner. The first layer 112 in combination with the second layer 114 is required for the bilayer dipole liner to function. The dielectric 116 may be made of a low-k dielectric material (k<4.0), including but not limited to silicon oxide.

[0027] A first layer 112 is conformally deposited on the top surface of the structure 100 using known deposition techniques to form a bottom spacer 118. A second layer 114 is then conformally deposited on the top surface of the first layer 112 using known deposition techniques. The first layer 112 and the second layer 114 are deposited to a thickness of 1-2 nm. The thickness of the first layer 112 and the second layer 114 can affect the electric field and, therefore, the threshold voltage. Thus, the thicker the bilayer dipole liner, the greater the range of the threshold voltage. A thickness of 1-2 nm can tune the threshold voltage in a range of <50 mV. Once the first layer 112 and the second layer 114 are deposited, a dielectric 116 is then deposited on the top surface of the second layer 114.

[0028] An etching process that is selective to (does not substantially remove) the first layer 112 and the second layer 114 may be used to remove the dielectric 116 from the top surface of the hard mask cap 104 and the sidewalls of the fin 200. The etching process may be, for example, reactive ion etching. Another etching process may then be used to etch back the first layer 112 and the second layer 114 from the top surface of the hard mask cap 104 and the sidewalls of the fin 200. The resulting structure 100 includes a lower spacer 118 formed along the top surface of the source-drain epitaxy 108 and the lower source-drain 110, as shown in FIG. 6.

[0029] Typically, a standard vertical transistor may include a bottom spacer made of a low-k material, such as silicon oxide. An embodiment of the present invention discloses a bottom spacer 118 including a bilayer dipole liner and a dielectric 116, where the dielectric 116 is made of a low-k material. The combination of the dipole liner and the dielectric 116 creates a non-power vertical transistor due to the longer effective gate length when compared to the gate length of the standard vertical transistor. Furthermore, for a non-power n-type vertical transistor, the dipole liner is made of silicon oxide (first layer 112) and aluminum oxide (second layer 114), which creates a negative charge near the fin 200. For a non-power p-type vertical transistor, the dipole liner is made of silicon oxide (first layer 112) and silicon nitride (second layer 114), which creates a positive charge near the fin 200.

[0030] 7, a structure 100 is shown with a gate stack 126 according to one embodiment. The gate stack 126 may include a gate dielectric material 120, a work function metal, and a metal gate 124.

[0031] Once the bottom spacers 118 are formed, a gate dielectric material 120 is conformally deposited on the top surface of the structure 100. A work function metal 122 is then conformally deposited on an upper portion of the gate dielectric material 120. The gate dielectric material 120 and the work function metal 122 are disposed on the bottom spacers 118, the sidewalls of the fins 200, and the hard mask cap 104.

[0032] The gate dielectric material 120 can be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of materials suitable for the gate dielectric material 120 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, and lead zinc niobate. The high-k materials may further include dopants, such as, for example, lanthanum and aluminum.

[0033] The gate dielectric material 120 separates the sidewalls of the fin 200 from the work function metal 122, reducing leakage current effects while increasing the capacitance of the work function metal 122. The gate dielectric material 120 layer may be formed by a suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition deposition, physical vapor deposition, chemical solution deposition, or other similar processes. The thickness of the gate dielectric material 120 may vary depending on the deposition process, as well as the composition and number of high-k dielectric materials used.

[0034] A work function metal 122 may be disposed on the gate dielectric material 120. The type of work function metal 122 depends on the type of transistor. Non-limiting examples of suitable work function metals 122 include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal 122 may be deposited by a suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, plating, thermal or electron beam evaporation, and sputtering.

[0035] Once the gate dielectric material 120 and the work function metal 122 are conformally deposited on the structure 100, the structure 100 is filled with metal to form a metal gate 124. The structure 100 is filled with metal such that the top surface of the metal gate 124 is just below the top surface of the fin 200. The metal gate 124 is deposited over the gate dielectric material 120 and the work function metal 122. The metal gate 124, the work function metal 122, and the gate dielectric material 120 may be collectively referred to as a gate stack 126. Non-limiting examples of the metal gate 124 may include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal may be deposited by a suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, plating, thermal or electron beam evaporation, and sputtering.

[0036] 7, once the metal gate 124 is deposited, the structure 100 undergoes an etching process to remove the gate dielectric material 120 and the work function metal 122 from the top surface and sidewalls of the hard mask cap 104. The etching process may be selective to the metal gate 124 (does not substantially remove the metal gate 124). The etching process may be, for example, a reactive ion etch. After the etching process is performed, the top surfaces of the gate dielectric material 120 and the work function metal 122 are substantially coplanar with the top surface of the metal gate 124. Additionally, the top surfaces of the gate dielectric material 120, the work function metal 122, and the metal gate 124 are below the top surface of the fin 200.

[0037] Referring now to FIG. 8, a structure 100 with a top spacer 128 is shown, according to an embodiment. The top spacer 128 is substantially identical to the bottom spacer 118 and includes a first layer 112, a second layer 114, and a dielectric 116. The top spacer 128 may be formed by first conformally depositing the first layer 112 on the top surface of the structure 100 such that the first layer 112 is in direct contact with the gate dielectric material 120, the work function metal 122, the metal gate 124, the fin 200, and the hard mask cap 104. The second layer 114 is then conformally deposited on the top surface of the first layer 112 using known deposition techniques. The first layer 112 and the second layer 114 are deposited to a thickness of 1-2 nm. Once the first layer 112 and the second layer 114 are deposited, the dielectric 116 is then deposited on the top surface of the second layer 114.

[0038] The upper spacer 128 may be formed by the same process used to form the lower spacer 118, as described herein with reference to Figure 6. The resulting structure 100 includes the gate dielectric material 120, the work function metal 122, and the upper spacer 128 formed along the upper surface of the metal gate 124, as shown in Figure 8. The upper spacer 128 is laterally disposed adjacent the interface where the upper surface of the fin 200 is in direct contact with the lower surface of the hard mask cap 104. Like the lower spacer 118, the upper spacer 128 also includes the first layer 112, the second layer 114, and the dielectric 116.

[0039] 9, a structure 100 with an inter-layer dielectric (ILD) 130 is shown according to an embodiment. The structure 100 undergoes an etching process to remove a portion of the top spacer 128, a portion of the metal gate 124, a portion of the work function metal 122, a portion of the gate dielectric material 120, and a portion of the bottom spacer 118 to form a trench and expose the top surface of the source-drain epitaxy 108. A mask may first be placed on the exposed top surface of the top spacer 128 and subsequently patterned. The pattern is transferred to the top spacer 128, and a portion of the top spacer 128 is removed to expose the top surface of the metal gate 124. The same process may then be performed to remove a portion of the metal gate 124, a portion of the work function metal 122, a portion of the gate dielectric material 120, and a portion of the bottom spacer 118 to expose the top surface of the source-drain epitaxy 108.

[0040] Once a portion of the top surface of the source-drain epitaxy 108 is exposed, the ILD 130 is deposited such that the top surface of the ILD 130 is substantially coplanar with the top surface of the top spacer 128. The ILD 130 may be formed from a low-k dielectric material (k<4.0) including, for example, but not limited to, silicon oxide, spin-on glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD 130 is deposited by a deposition process including, but not limited to, chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, chemical solution deposition, or a similar process.

[0041] Referring now to FIG. 10, a structure 100 with an upper source drain 132 is shown according to an embodiment. To form the upper source drain 132, first the hard mask cap 104 shown in FIGS. 1-9 is removed. The hard mask cap 104 may be removed utilizing any material removal process, such as chemical mechanical polishing. Once the hard mask cap 104 is removed and the top surface of the fin 200 is exposed, the upper source drain 132 is epitaxially grown from the exposed top surface of the fin 200. The upper source drain 132 is a facetted epitaxial source drain region of a vertical transistor. The facetted upper source drain 132 is grown in the shape of a pointed cone, with the tip of the upper source drain 132 extending horizontally and vertically away from the fin 200. The pointed cone shape of the upper source drain 132 enhances the electric field at the tip of the cone.

[0042] The upper source-drain 132 may be grown using an epitaxial growth process, such as, for example, molecular beam epitaxy. Other methods, such as rapid thermal chemical vapor deposition, low energy plasma deposition, ultra-high vacuum chemical vapor deposition, and atmospheric pressure chemical vapor deposition, may also be used to grow the upper source-drain 132. The temperature of the epitaxial deposition typically ranges from 450°C to 900°C. Typically, higher temperatures result in faster deposition, but faster deposition can result in crystal defects and film cracking.

[0043] 11, a structure 100 with a contact 134 is shown according to an embodiment. Once the upper source-drain 132 is formed, the structure 100 is filled with an ILD 130, which covers the upper source-drain 132. The contact 134 is then formed. The contact 134 extends through the ILD 130 to the upper source-drain 132 and is formed in a trench. A resist, such as a photoresist, may be deposited and patterned to remove the ILD 130 to form a contact trench. An etching process, such as reactive ion etching, may be performed using the patterned resist as an etch mask to remove the ILD 130 until the upper source-drain 132 is exposed. The contact trench is filled with a conductive material or a combination of conductive materials to form the contact 134. The conductive material fill may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as chemical mechanical planarization, is performed to remove any conductive material from the surface of the ILD 130.

[0044] The resulting structure 100 includes two non-force vertical transistors, as shown in Figure 11. Although two non-force vertical transistors are shown, it should be understood that embodiments of the present invention contemplate forming multiple non-force vertical transistors on a single substrate wafer.

[0045] Each of the vertical transistors shown in FIG. 11 includes a dipole liner. The dipole liner is made of a first layer 112 and a second layer 114. In addition to the dipole liner, the vertical transistor also includes a dielectric 116. The dipole liner and the dielectric 116 form a lower spacer 118 and an upper spacer 128. Furthermore, the combination of the dipole liner and the dielectric creates a vertical transistor that is less powerful due to a longer effective gate length when compared to the gate length of a standard vertical transistor. The first layer 112 of the dipole liner may be made of a material such as, for example, silicon oxide. The gate dielectric material 120 may also be made of an oxide material. Furthermore, the gate dielectric material 120 acts as a barrier to separate the sidewalls of the fin 200 from the work function metal 122, reducing leakage current effects while increasing the capacitance of the work function metal 122. Since the first layer 112 may be made of the same material as the gate dielectric material 120, the first layer 112 may also act as a barrier to reduce leakage current effects and increase the effective gate length of the vertical transistor.

[0046] 12, a structure 300 is shown with a standard vertical transistor and a non-power vertical transistor according to an embodiment. The non-power vertical transistor may include a gate stack 126 disposed between a lower source-drain 108 and an upper source-drain 132. The gate stack may include a gate dielectric material 120, a work function metal 122, and a metal gate 124. Additionally, a lower spacer 118 and an upper spacer 128 are fabricated with the dipole liner and dielectric 116.

[0047] The standard vertical transistor includes a gate stack 126 formed by a gate dielectric material 120, a work function metal 122, and a metal gate 124. The standard vertical transistor also includes a lower source drain 108 and an upper source drain 132, as well as a lower spacer and an upper spacer. However, the lower spacer and the upper spacer in the standard vertical transistor are made only of the dielectric 116. The lower spacer and the upper spacer in the standard vertical transistor do not include a dipole liner. As a result, the standard vertical transistor is not non-force. Nevertheless, the standard vertical transistor may be fabricated side-by-side with a non-force vertical transistor. For example, during the formation of the lower spacer and the upper spacer, the first layer 112 and the second layer 114 and the dielectric 116 are deposited to form the non-force vertical transistor, while only the dielectric 116 is deposited to form the standard vertical transistor. During the deposition of the first layer 112 and the second layer 114, the standard vertical transistor may be masked such that the first layer 112 and the second layer 114 are deposited only on the structures that form the non-force vertical transistor. In addition, the actual physical gate length is the same for standard and non-powered vertical transistors. However, the effective gate length is longer for non-powered vertical transistors than for standard vertical transistors due to the dipole liner. The dipole liner affects the electric field near the source-drain regions of the vertical transistor, thereby creating a threshold voltage difference.

[0048] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor structure comprising: a lower source / drain, an upper source / drain, and a gate stack, the upper source / drain being above the gate stack and the lower source / drain being below the gate stack; a lower spacer and an upper spacer, the gate stack being between the lower spacer and the upper spacer, the lower spacer and the upper spacer each comprising a dipole liner; 1. A semiconductor structure comprising:

2. The dipole liner comprises: A first layer; and a second layer in direct contact with the first layer and made of a different material than the first layer; 10. The semiconductor structure of claim 1 comprising:

3. 3. The semiconductor structure of claim 2 wherein said first layer is made of silicon oxide.

4. 3. The semiconductor structure of claim 2 wherein said second layer is made of silicon nitride.

5. 3. The semiconductor structure of claim 2 wherein said second layer is made of aluminum oxide.

6. 3. The semiconductor structure of claim 2 wherein said first layer is in direct contact with said gate stack, said upper source-drain, and said lower source-drain.

7. 10. The semiconductor structure of claim 1 wherein said bottom spacer comprises a dielectric, said dielectric being in direct contact with said dipole liner.

8. 1. A semiconductor structure comprising: A vertical field effect transistor comprising an upper source drain, a lower source drain, a lower spacer, an upper spacer, and a gate stack, the lower source drain being separated from the gate stack by the lower spacer, the lower spacer comprising a dipole liner contacting the lower source drain.

1. A semiconductor structure comprising:

9. 9. The semiconductor structure of claim 8 wherein said upper source-drain is separated from said gate stack by said upper spacer, said upper spacer comprising said dipole liner, said dipole liner contacting said upper source-drain.

10. The dipole liner comprises: A first layer; and a second layer in direct contact with the first layer and made of a different material than the first layer; 9. The semiconductor structure of claim 8 comprising:

11. 11. The semiconductor structure of claim 10 wherein said first layer is made of silicon oxide.

12. 11. The semiconductor structure of claim 10 wherein said second layer is made of silicon nitride.

13. 11. The semiconductor structure of claim 10 wherein said second layer is made of aluminum oxide.

14. 9. The semiconductor structure of claim 8 wherein said bottom spacer comprises a dielectric, said dielectric being in direct contact with said dipole liner.

15. 1. A method comprising: forming a lower source / drain on a substrate; forming a lower spacer in direct contact with the lower source-drain and comprising a dipole liner; forming a gate stack above the lower spacer; forming an upper spacer above the gate stack and in direct contact with the gate stack, the upper spacer comprising the dipole liner; forming an upper source / drain above the upper spacer; A method comprising:

16. The dipole liner comprises: A first layer; and a second layer in direct contact with the first layer and made of a different material than the first layer; The method of claim 15 comprising:

17. 17. The method of claim 16, wherein the first layer is in direct contact with the gate stack, the upper source-drain, and the lower source-drain.

18. The method of claim 16 , wherein the first layer is made of silicon oxide.

19. The method of claim 16 , wherein the second layer is made of silicon nitride or aluminum oxide.

20. The method of claim 15 , wherein the lower spacer comprises a dielectric, the dielectric being in direct contact with the dipole liner.

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