Semiconductor device manufacturing system and manufacturing method

Abstract

To provide a manufacturing system and method capable of manufacturing a semiconductor device more efficiently.SOLUTION: In a manufacturing system X, a design information storage part 3 has first design information d31 on a first functional circuit, second design information d32 on a second functional circuit, and third design information d33 on a third functional circuit formed by combining the first and second functional circuits. A first processing part 1 has a first processing device group 11. A second processing part 2 has a second processing device group 21. A correction step creation part 4 produces correction step information d34 obtained by correcting processing conditions of each process so as to commonalize one or more processes to be performed by the first processing device group 11 and one or more processes to be performed by the second processing device group 21, on the basis of the first design information d31, the second design information d32, and the third design information d33. A processing step control part 6 controls each processing step of the first processing device group 11 and the second processing device group 21 on the basis of the correction step information d34.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a manufacturing system and a manufacturing method for a semiconductor device. [Background technology]

[0002] The miniaturization and high integration of integrated circuits have already reached their limits, and the time it takes from development to manufacture of LSIs (Large Scale Integration), which require an enormous amount of development time and process, is only getting longer.

[0003] On the other hand, in order to recover the costs of development and manufacturing, it is necessary to produce a large number of LSIs at once, so this type of LSI manufacturing has become a heavy, large-scale manufacturing industry that requires large investments in equipment over a long period of time.

[0004] However, to meet the ever-diversifying needs for LSIs, more flexible LSI development and manufacturing methods are also required that take into account high-mix, low-volume production.

[0005] As one solution to the above problem, the idea of ​​"minimal fab," which aims to standardize semiconductor manufacturing processes, has been proposed.

[0006] However, this method has problems such as restrictions on the line width of fine processing in exposure, problems with mass production, restrictions on throughput in EB direct writing, etc. In addition, designing more complex LSIs requires a lot of development time and man-hours.

[0007] For this reason, even in recent years, many LSIs are designed based on the concept of System in Package (SiP), in which multiple separate chips are later assembled into a system, and System on Chip (SoC), in which multiple separate functional circuits are integrated onto a single chip.

[0008] For example, Patent Document 1 describes an invention relating to a SiP that has an analog circuit chip and a computer chip and can be suitably used in a motor drive circuit.

[0009] Moreover, Patent Document 2 describes an invention relating to an SoC for driving a power inverter, in which a logic circuit, a voltage level shifter, and a sense circuit are integrally formed on a single IC.

[0010] Patent Document 3 describes an invention related to an information management system that can improve the efficiency of manufacturing by managing manufacturing process information in association with design information and manufacturing information in the LSI manufacturing process, which becomes increasingly complex as separate chips and functional circuits are combined. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Re-tabled publication 2017 / 086054 [Patent Document 2] JP 2013-223419 A [Patent Document 3] JP 2015-12251 A Summary of the Invention [Problem to be solved by the invention]

[0012] When designing and manufacturing the above-mentioned LSIs in-house, it takes time and effort to design and develop an entire collection of complex separate functions, which is hardly efficient. In particular, when manufacturing SoCs, it takes time and effort to create complex photomasks to match them.

[0013] The inventor therefore wondered whether it might be possible to make more efficient use of existing manufacturing equipment, facilities, and circuit design information (IP cores, Intellectual Property Cores) owned by different companies in order to develop and manufacture LSIs more efficiently. We also wondered whether the standardized processes could be used in the development and manufacturing of LSIs.

[0014] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a manufacturing system for more efficiently manufacturing semiconductor devices. [Means for solving the problem]

[0015] In order to solve the above problems, the present invention provides a manufacturing system for manufacturing a semiconductor device in which a plurality of types of functional circuits based on different design information are formed on a single wafer, the system comprising: The apparatus includes a design information storage unit, a first processing unit, a second processing unit, a correction process creation unit, and a processing process control unit, The design information storage unit has first design information related to a first functional circuit, second design information related to a second functional circuit, and third design information related to a third functional circuit formed by combining the first functional circuit and the second functional circuit. the first processing unit has a first processing device group capable of forming the first functional circuit on the wafer based on the first design information, the second processing unit has a second processing device group capable of forming the second functional circuit on the wafer based on the second design information, the corrected process creation unit creates corrected process information based on the first design information, the second design information, and the third design information, in which process conditions of one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are corrected so as to be common to each other; The processing step control section controls each processing step of the first processing apparatus group and the second processing apparatus group based on the corrected process information.

[0016] According to the present invention, the common processing can be performed in both the first processing unit and the second processing unit, so that a variety of semiconductor devices can be manufactured by forming multiple types of functional circuits on a single wafer while effectively utilizing resources and technologies such as equipment groups and reticles owned by different companies.

[0017] In a preferred form of the present invention, the correction process creation unit creates the correction process when one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are standardized so that the stacking heights of the wafers obtained as a result of each process are approximately the same.

[0018] By configuring in this way, even if the types of processing equipment are different, as long as the processing content is homogeneous, it is possible to standardize each process and create a correction process based on the stack height of the wafers obtained after processing.

[0019] In addition, standard processes can be included in the types of processing equipment. It is also possible to create correction processes for those processes. By standardizing the processes, it becomes easier for IP developers to work on manufacturing the semiconductor device.

[0020] That is, the correction process is expected to reduce the difficulty of starting from the standard process and working on manufacturing. The effect is that the standard process can be combined with various existing processing equipment and processing processes that have a proven track record. Therefore, it is possible to provide a method for easily achieving the process from IP development to manufacturing of semiconductor devices in a shorter period of time.

[0021] In a preferred embodiment of the present invention, the system further includes a wiring design unit, which creates wiring design information for electrically connecting the first functional circuit and the second functional circuit based on the first design information, the second design information, and the third design information, and the processing step control unit controls each processing step of the first processing device group and the second processing device group based on the wiring design information, thereby electrically connecting the first functional circuit and the second functional circuit.

[0022] With this configuration, the electrical connection between the first and second functional circuits is ensured, and the combined and integrated functions of the first and second functional circuits can be executed.

[0023] In a preferred embodiment of the present invention, the system further includes a wafer transport unit, which transports the wafer between the first processing unit and the second processing unit based on the progress of processing performed in the first processing unit group and the second processing unit group.

[0024] With this configuration, wafers can be appropriately exchanged between the first processing device group and the second processing device group, in which some processes are shared, thereby increasing the operating rate of each processing device.

[0025] The present invention also provides a method for manufacturing a semiconductor device having a plurality of types of functional circuits formed on a single wafer based on different design information, comprising the steps of: a correction process creating step of creating corrected process information in which process conditions of one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are corrected so as to be common to each other, based on first design information on a first functional circuit, second design information on a second functional circuit, and third design information on a third functional circuit formed by combining the first functional circuit and the second functional circuit; and forming the first functional circuit and the second functional circuit on one wafer based on the corrected process information.

[0026] According to the present invention, the common processing can be performed in both the first processing unit and the second processing unit, so that a variety of semiconductor devices can be manufactured by forming multiple types of functional circuits on a single wafer while effectively utilizing resources and technologies such as equipment groups and reticles owned by different companies.

[0027] In a preferred embodiment of the present invention, when creating the correction process information, when one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are made common, the correction process information is created so that the stacking heights of the wafer obtained as a result of each process are approximately the same.

[0028] With this configuration, it becomes possible to standardize each process and create a correction process based on the stack height of the wafers. In addition, standard processes can be included in the types of processing equipment. It is also possible to create correction processes for those processes. By standardizing the processes, it becomes easier for IP developers to work on manufacturing the semiconductor device. Effect of the Invention

[0029] According to the present invention, it is possible to provide a manufacturing system for more efficiently manufacturing semiconductor devices. [Brief description of the drawings]

[0030] [Figure 1] 1 is a schematic diagram of a manufacturing system according to an embodiment of the present invention. [Diagram 2] 11A to 11C are diagrams illustrating an example of creating a correction process according to an embodiment of the present invention. [Diagram 3] 11A to 11C are diagrams illustrating an example of creating a correction process according to an embodiment of the present invention. [Figure 4] 1 is a schematic diagram of a manufacturing system according to an embodiment of the present invention. [Diagram 5] FIG. 2 is a schematic diagram of a manufacturing system according to another embodiment of the present invention. [Figure 6] 1 is an example in which a manufacturing system according to an embodiment of the present invention is applied to system-in-package technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] A manufacturing system and a manufacturing method according to an embodiment of the present invention will be described below with reference to Figures 1 to 6. Note that the embodiment described below is an example of the present invention, and the present invention is not limited to the following embodiment. Also, the symbol X indicates a manufacturing system according to an embodiment of the present invention.

[0032] FIG. 1 shows a state before the correction process information is created in one embodiment of the manufacturing system X.

[0033] Here, as an example of a case in which manufacturing system X is utilized, a situation is assumed in which company A has third design information for a third functional circuit that combines a first functional circuit designed by the company A with a second functional circuit designed by company B. Furthermore, it is assumed that company A has a first processing unit 1 as a manufacturing base, and company B has a second processing unit as a manufacturing base.

[0034] As shown in FIG. 1, the manufacturing system X includes a first processing unit 1, a second processing unit 2, a design information storage unit 3, a correction process creation unit 4, a wiring design unit 5, a processing process control unit 6, and a wafer transport unit 7.

[0035] The first processing unit 1 has a first processing device group 11 capable of performing processing steps A1 to A7 for forming a first functional circuit on a wafer. The first processing device group 11 may have any number of devices as long as they are capable of performing each of the processing steps A1 to A7, but it is preferable that one device corresponds to one processing step. Moreover, the process steps A1 to A7 are merely examples, and the number of process steps is not particularly limited.

[0036] The second processing unit 2 has a second processing device group 21 capable of executing processing steps B1 to B7 for forming a second functional circuit on a wafer, similar to the first processing unit 1. The second processing device group 21 may include any number of devices as long as they are capable of executing the processing steps B1 to B7, but it is preferable that one device corresponds to one processing step. Moreover, the process steps B1 to B7 are merely examples, and the number of process steps is not particularly limited.

[0037] The design information storage unit 3 has first design information d31, second design information d32, and third design information d33. The first design information d31, the second design information d32, and the third design information d33 include EDA (Electronic Design Automation) library information in the design stage of each functional circuit, information on the manufacturing process (processing method and processing conditions) of each functional circuit, and the like. The correction process information d34 and the wiring design information d35 are created by a correction process creation unit 4 and a wiring design unit 5, which will be described later, and then stored in the design information storage unit 3. For this reason, in FIG. 1, the correction process information d34 and the wiring design information d35 are indicated by dotted frames.

[0038] The corrected process creation unit 4 can create corrected process information d34 based on the first design information d31, the second design information d32, and the third design information d33, in which the processing conditions of each process are corrected so as to make common the processing conditions of one or more processes performed in the first processing device group 11 and one or more processes performed in the second processing device group 21. The "standardization" of processing and the correction process information d34 will be described in detail later.

[0039] The wiring design unit 5 can create wiring design information d35 for electrically connecting the first functional circuit and the second functional circuit based on the EDA library information of each functional circuit included in the first design information d31, the second design information d32, and the third design information d33. That is, the wiring design information d35 can ensure a reliable electrical connection between the first functional circuit and the second functional circuit.

[0040] The processing process control unit 6 controls the first processing device group 11, the second processing device group 21, and the wafer transport unit 7 described later based on the third design information d33, the correction process information d34, and the wiring design information d35, and can execute a processing process for forming a third functional circuit on the wafer.

[0041] The design information storage unit 3, the correction process creation unit 4, the wiring design unit 5, and the processing process control unit 6 can be implemented using general computer devices equipped with arithmetic devices such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a main memory device such as a RAM (Random Access Memory), an auxiliary memory device such as an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a flash memory, and various input / output devices including a means for connecting to a network. Furthermore, the functions of the design information storage unit 3, the correction process creation unit 4, the wiring design unit 5, and the processing process control unit 6 may be integrated into one device, or may be distributed across multiple devices.

[0042] The wafer transfer unit 7 transfers the wafer between the first processing unit 1 and the second processing unit 2 based on the progress of the processing performed in the first processing unit group 11 and the second processing unit group 21. A wafer transport robot is preferably used for short-distance transport, while an automatic driving vehicle is preferably used for long-distance transport, both of which are controlled by the processing step control unit 6.

[0043] By using the manufacturing system X as described above, company A can combine the first and second function circuits that it has designed to manufacture an LSI having a third function circuit with improved performance. Meanwhile, company B can effectively utilize its own second function circuit, reticles, manufacturing equipment, and technology to improve the technology and flexibility of the manufacturing process and increase the operation and productivity of the factory.

[0044] FIG. 2 shows an example in which "standardization" of processing is performed based on first design information d31, second design information d32, and third design information d33, and correction process information d34 is obtained. For example, consider the "commonalization" of an etching process step Ax in the first design information d31, which is adjusted to etch a portion of the stack height h11 by a depth e1 to result in a stack height h12, and an etching process step Bx in the second design information d32, which is defined to etch a portion of the stack height h21 by a depth e2 to result in a stack height h22. In this case, in order to simplify the explanation, it is assumed that the stack heights h11 and h21 determined by the previous steps are equal to each other. Similarly, it is assumed that h31 is also equal to the stack heights h11 and h21.

[0045] The first design information d31 and the second design information d32 differ in etching depths e1, e2, and also differ in stack heights h12, h22 after etching. Moreover, in the third design information d33, the etching depth e3 is determined to be equal to the stack height h32.

[0046] Here, the correction process creation unit 4 creates a “common” correction process Cx by adjusting the processing conditions in each processing step Ax and Bx based on the first design information d31, the second design information d32, and the third design information d33 so that the stack heights h12, h22 obtained by etching are equal to the stack height h32, respectively.

[0047] In the steps Ax and Bx of each process, the processing contents may be the same but the types of processing equipment may be different. In that case, the correction process creation unit 4 can adjust the processing conditions separately in the steps Ax and Bx of each process by using the obtained stack height h32 as a reference.

[0048] It is more preferable to adjust the stack height h32 to be equal to either the stack height h12 or h22, since this requires only adjusting the processing conditions of either the process Ax or Bx of each process, but the stack height h32 may be a completely different value depending on its relationship with other processes.

[0049] FIG. 3 shows another example in which "standardization" of processing is performed based on first design information d31, second design information d32, and third design information d33, and correction process information d34 is obtained. For example, consider the "commonization" of a film deposition process step Ax in the first design information d31, which is adjusted so that the shaded portion is deposited to a stacking height of h13, h14, and a thickness of t1, and a film deposition process step Bx in the second design information d32, which is adjusted so that the shaded portion is deposited to a stacking height of h23, h24, and a thickness of t2. In order to simplify the conditions, it is assumed here that the layered structure below the shaded area, which is determined by the previous process, is the same in the three diagrams in FIG.

[0050] The first design information d31 and the second design information d32 differ in stacking heights h13, h23, h14, h24, and also differ in thickness t1 and thickness t2. In the third design information d33, the shaded areas are defined to be the stack heights h33 and h34 and the thickness t3.

[0051] Here, the correction process creation unit 4 creates a "common" correction process Cx by adjusting the processing conditions in each processing step Ax and Bx based on the first design information d31, the second design information d32, and the third design information d33 so that the stack heights h13, h14, thickness t1, and the stack heights h23, h24, thickness t2 obtained by film deposition are equal to the stack heights h33, h34, thickness t3, respectively.

[0052] In each process, steps Ax and Bx, the processing contents may be the same but the types of processing equipment may be different. In that case, the correction process creation unit 4 can adjust the processing conditions separately in each process, steps Ax and Bx, by using the obtained stack heights h33, h34, and thickness t3 as references.

[0053] It is more preferable to adjust at least any one of the stacking heights h33, h34 and thickness t3 to be equal to the stacking heights h13, h14, thickness t1 or the stacking heights h23, h24, thickness t2, since it is only necessary to adjust the processing conditions of either one of the processes Ax or Bx of each treatment. However, depending on the relationship with other processes, the stacking heights h13, h14, thickness t1 or the stacking heights h23, h24, thickness t2 may be completely different values.

[0054] FIG. 4 shows the manufacturing system X after the corrected processes C1 to C7 have been created by the corrected process creation unit 4. By the correction processes C1 to C7 and the wiring process (not shown) created by the correction process creation unit 4, it becomes possible to form a third function circuit on the wafer, which is formed by combining the first function circuit and the second function circuit. In addition, the correction steps C1 to C7 are standardized in the manner described in Figures 2 and 3, and are divided into correction steps (C3, C6, C7) that can be executed by both the first processing unit 1 and the second processing unit 2, and correction steps (C1, C2, C4, C5) that are not standardized.

[0055] Since the common correction processes C3, C6, and C7 can be executed by both the first processing section 1 and the second processing section 2, if there is an imbalance in the number of wafers waiting to be processed between the processing sections, the wafers are transported by the wafer transport section 7, thereby reducing the downtime of each processing section.

[0056] In the correction processes C1, C2, C4, and C5 that are not shared, common wafers are distributed and transported in accordance with the throughput of each process. For example, if the correction process C1 is an exposure process using electron beam lithography and the correction process C2 is a batch exposure process using a photomask, N times of the electron beam lithography process in the correction process C1 (one wafer per time) correspond to one batch exposure process in the correction process C2 (N wafers per time), where N is an arbitrary natural number. The same applies to the correction processes C4 and C5.

[0057] As a result, in the manufacturing system X, by selecting a combination of executable processes from the group of devices in each processing section, it becomes possible to manufacture semiconductor devices more efficiently.

[0058] Fig. 5 is a diagram showing another embodiment of the manufacturing system X. The manufacturing system X shown in Fig. 5 differs from the manufacturing system X shown in Fig. 1 in that the manufacturing system X uses process control devices M1 and M2 originally provided in the first processing apparatus 1 and the second processing apparatus 2. In the following, a description of parts that overlap with the manufacturing system X shown in FIG. 1 will be omitted.

[0059] The manufacturing system X includes a process control device M1 in a first processing unit 1, a process control device M2 in a second processing unit 2, a design information memory unit 3, a correction process creation unit 4, a wiring design unit 5, a processing process control unit 6, and a wafer transport unit 7, which are connected via a network NW.

[0060] The first processing section 1 shown in FIG. 5 includes a first processing apparatus group 11 capable of executing processing steps A1 to A7 for forming a first functional circuit on a wafer, and a process management apparatus M1. The process management device M1 includes first design information d31 and a processing process control unit 12(6), and is capable of causing the first processing device group 11 to execute a processing process for forming a first functional circuit on a wafer.

[0061] Similarly to the first processing unit 1, the second processing unit 2 shown in FIG. 5 has a second processing device group 21 capable of executing processing steps B1 to B7 for forming a second functional circuit on a wafer, and a process management device M2. The process management device M2 includes second design information d32 and a processing process control unit 22(6), and is capable of causing the second processing device group 21 to execute a processing process for forming a second functional circuit on a wafer.

[0062] The design information storage unit 3 has third design information d33, correction process information d34, and wiring design information d35.

[0063] The processing step control units 12(6), 22(6) control the first processing step group 11, the second processing step group 21, and the wafer transport unit 7 based on the third design information d33, the correction step information d34, and the wiring design information d35, and can execute the correction steps C1 to C7 for forming a third functional circuit on the wafer.

[0064] With this configuration, the existing process control devices M1 and M2 can be utilized to more efficiently manufacture a variety of semiconductor devices.

[0065] The configurations and functions shown in the above-described embodiments are merely examples and can be modified in various ways based on design requirements, etc.

[0066] Furthermore, the present invention is not limited to use between only two companies, such as company A and company B, as described above. The method or system of the present invention can also be applied to a system between three or more companies.

[0067] Furthermore, the present invention can be combined with SiP (System in Package) technology as follows:

[0068] For example, suppose that Company A and Company B manufacture a semiconductor device chip by combining their functional circuits using the method of the present invention, and Company C manufactures a functional circuit on another semiconductor device chip, then the method of the present invention can be applied as follows, with the original objective of combining the functional circuits of these three companies using system-in-package technology.

[0069] FIG. 6 shows an example of an application in which a semiconductor device chip manufactured by company A and company B using the method of the present invention is designated as chip Ca, and a semiconductor device chip manufactured by company C is designated as chip Cb, and a system is formed in which chips Ca and Cb are packaged in a single package using system-in-package technology.

[0070] Here, by applying the manufacturing system of the present invention, companies A, B, and C can manage and manufacture the semiconductor device chips, package substrates, and system-in-packages in the same system. This allows not only the wiring in chips Ca and Cb, but also the wiring on the package substrate to be managed in one manufacturing system.

[0071] The following description focuses on wiring on a package substrate, but the above-described method and system can be applied to other areas as is.

[0072] The wiring information of the package substrate and the system-in-package design information including the process are also managed by the design information storage unit 3, the correction process creation unit 4, the wiring design unit 5, the process control unit 6, and the wafer transport unit 7.

[0073] When creating the correction process, the aim is to standardize the processes in each processing device group in the manufacturing of the semiconductor device as described above, and the ease of manufacturing the entire process including the wiring process of the package substrate is also considered. In that case, in order to facilitate the wiring process of the package substrate, it may be advantageous for the wiring process of the package substrate to deliberately create elements and parts that are considered to be additional or redundant in the manufacturing of the semiconductor device of the chips Ca and Cb.

[0074] 6, the wiring in the portion P1 surrounded by the dotted circle is dense, and it is technically difficult to add any more wiring to the portion P1. In that case, in the package substrate wiring L that connects the bump Bu1, the bump Bu6, the wiring A in the chip Ca, and the wiring B in the chip Cb, the wiring connected to the wiring A in the chip Ca can be modified in advance based on the information of the design information storage unit 3, the correction process creation unit 4, and the wiring design unit 5 so that the wiring connected to the wiring A in the chip Ca passes through the portion P2, for example, to be connected to the wiring A in the chip Ca, in order to be separated from the portion P1 and other densely-spaced wiring portions.

[0075] That is, although there is no problem with the function of chip Ca and the wiring within chip Ca, when trying to realize the functional integration with chip Cb by using the system-in-package manufacturing technology, a problem occurs with the board wiring of the system-in-package. In solving the problem, it is advantageous for the entire manufacturing process up to the package board to create elements and parts of chip Ca that are unnecessary for the function of chip Ca and the wiring within chip Ca but are considered to be additional or redundant, without changing the design and manufacturing of chip Cb. This is possible on this system based on the information of design information storage unit 3, correction process creation unit 4, and wiring design unit 5.

[0076] The wiring design unit 5 handles not only the wiring in the chips Ca and Cb but also the wiring on the package substrate in a consistent manner. This allows the technical easiness of the wiring process in the chips Ca and Cb, which are handled in the above-mentioned expanded correction process, to be compared with the technical easiness of the wiring process on the package substrate, and determines the optimal balance between the two. Furthermore, the processing control unit 6 handles the manufacture of semiconductor device chips, package substrates, and wiring within the substrates. Thus, according to the present invention, it is possible to carry out the manufacture of a system-in-package. [Explanation of symbols]

[0077] X Manufacturing System 1. First Processing Section 11 First treatment equipment group 2. Second Processing Section 21 Second Processing Unit 3 Design information storage section 4. Correction Process Creation Department 5 Wiring design department 6 Processing Control Section 7 Wafer transport section

Claims

1. A manufacturing system for manufacturing a semiconductor device in which a plurality of types of functional circuits based on different design information are formed on a single wafer, comprising: The apparatus includes a design information storage unit, a first processing unit, a second processing unit, a correction process creation unit, and a processing process control unit, the design information storage unit has first design information related to a first functional circuit, second design information related to a second functional circuit, and third design information related to a third functional circuit formed by combining the first functional circuit and the second functional circuit; the first processing unit has a first processing device group capable of forming the first functional circuit on the wafer based on the first design information, the second processing unit has a second processing device group capable of forming the second functional circuit on the wafer based on the second design information, the corrected process creation unit creates corrected process information based on the first design information, the second design information, and the third design information, in which process conditions of one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are corrected so as to be common to each other; The processing step control unit controls each processing step of the first processing apparatus group and the second processing apparatus group based on the corrected processing step information.

2. 2. The semiconductor device manufacturing system of claim 1, wherein the correction process creation unit creates the correction process information when one or more processes performed in the first processing device group and one or more processes performed in the second processing device group are standardized so that the stacking heights of the wafers obtained as a result of each process are approximately the same.

3. A wiring design unit is further provided, the wiring design unit creates wiring design information for electrically connecting the first functional circuit and the second functional circuit based on the first design information, the second design information, and the third design information; 2. The semiconductor device manufacturing system of claim 1, wherein the processing step control unit controls each processing step of the first processing device group and the second processing device group based on the wiring design information, and electrically connects the first functional circuit and the second functional circuit.

4. Further comprising a wafer transport unit, 2. The semiconductor device manufacturing system of claim 1, wherein the wafer transport unit transports the wafer between the first processing unit and the second processing unit based on the progress of processing performed in the first processing unit group and the second processing unit group.

5. 4. The system for manufacturing a semiconductor device according to claim 3, wherein said wiring design section designs inter-chip wiring information for electrically connecting a plurality of chips based on a density of wiring between said plurality of chips.

6. A manufacturing method for manufacturing a semiconductor device in which a plurality of types of functional circuits based on different design information are formed on a single wafer, comprising the steps of: a correction process creating step of creating corrected process information in which process conditions of one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are corrected so as to be common to each other, based on first design information on a first functional circuit, second design information on a second functional circuit, and third design information on a third functional circuit formed by combining the first functional circuit and the second functional circuit; and a circuit forming step of forming the first functional circuit and the second functional circuit on a single wafer based on the corrected process information.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein, in the correction process creation step, when one or more processes performed in the process of forming the first functional circuit and one or more processes performed in the process of forming the second functional circuit are made common, the correction process information is created so that stacking heights of the wafer obtained as a result of each process are approximately the same.

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