Vertical Memory Device

Abstract

To provide a vertical memory device with improved characteristics.SOLUTION: A vertical memory device according to the present invention comprises: a substrate including a cell region, a through via region formed on each side of the cell region, and a mold region surrounding the cell region and the through via region; a gate electrode structure including a gate electrode laminated in the cell region of the substrate along a first direction perpendicular to the top surface of the substrate and extending in a second direction parallel to the top surface of the substrate; a channel that extends in the first direction on the cell region of the substrate and penetrates at least a part of the gate electrode structure; and a first mold including a first film and a second film alternately and repeatedly laminated along the first direction on the mold region of the substrate and having different insulating materials, and the first film included in the first mold is formed at the same height as the gate electrode included in each of the gate electrode structures, and comes into contact with the gate electrode structures.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to vertical memory devices. [Background technology]

[0002] In a method for manufacturing a VNAND flash memory device, a mold film is formed by alternately stacking insulating films and sacrificial films on a substrate including a chip region and a scribe lane (S / L) region, and then an etching process is performed to pattern the mold film into a staircase shape.

[0003] As the etching process is performed, the mold film formed on the S / L region is removed and an interlayer insulating film is formed to fill it, but as the number of mold film layers increases, the thickness of the interlayer insulating film increases. Since the interlayer insulating film is made of a single material, oxide having compressive strength or nitride having tensile strength, the stress generated in the S / L region increases. This creates a stress difference between the S / L region and the chip region, and the accuracy of tests through the TEG (Test Element Group) formed on the S / L region is limited. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-96880 A Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT DISCLOSURE The present invention has been made in consideration of the above-mentioned problems in the prior art, and an object of the present invention is to provide a vertical memory device having improved characteristics. [Means for solving the problem]

[0006] In order to achieve the above object, a vertical memory device according to one aspect of the present invention includes a substrate including a cell region, through via regions formed on both sides of the cell region, and a mold region surrounding the cell region and the through via region; gate electrode structures stacked on the cell region of the substrate along a first direction perpendicular to an upper surface of the substrate to be spaced apart from each other, each including a gate electrode extending in a second direction parallel to the upper surface of the substrate; a channel extending in the first direction on the cell region of the substrate and penetrating at least a portion of the gate electrode structure; and a first mold including first and second films stacked alternately along the first direction on the mold region of the substrate, each including a different insulating material, wherein the first films included in the first mold are formed to the same height as the gate electrodes included in the gate electrode structures and are in contact therewith.

[0007] According to another aspect of the present invention, a vertical memory device is provided, comprising: gate electrode structures stacked on a substrate along a first direction perpendicular to an upper surface of the substrate to be spaced apart from each other, each including a gate electrode extending in a second direction parallel to an upper surface of the substrate, and spaced apart from each other in a third direction intersecting the second direction parallel to the upper surface of the substrate; a channel extending in the first direction on the substrate and penetrating at least a portion of each of the gate electrode structures; and a first mold stacked alternately along the first direction on the substrate, each including first and second films each including a different insulating material, and in contact with at least one of the gate electrode structures formed on both edges in the third direction, wherein each of the gate electrode structures has a step shape with each of the gate electrodes as a step layer, and a portion of the first mold facing the gate electrode structures has a step shape with one of the first films and one of the second films stacked in sequence as a step layer, and the first film included in each step layer of the first mold and each step layer of the gate electrode structure corresponding thereto are formed to be the same height.

[0008] According to still another aspect of the present invention, a vertical memory device includes a circuit pattern formed on a substrate, a base pattern formed on the circuit pattern, gate electrodes stacked on the base pattern along a first direction perpendicular to an upper surface of the substrate to be spaced apart from each other, each gate electrode extending in a second direction parallel to the upper surface of the substrate, and spaced apart from each other in a third direction intersecting the second direction parallel to the upper surface of the substrate, channels extending in the first direction on the base pattern and penetrating at least a portion of each of the gate electrode structures, charge storage structures formed on outer walls of each of the channels, and coplanar gate electrode structures each formed between the gate electrode structures adjacent in the third direction and extending in the second direction, the first mold contacting at least one sidewall of the gate electrode structures formed at both edges in the third direction, the first mold including first and second films alternately stacked along the first direction on the base pattern, the first and second films including different insulating materials; the second mold being formed between two adjacent gate electrode structures formed at intermediate portions in the third direction of the gate electrode structures and extending in the second direction, the second mold including first and second patterns alternately stacked along the first direction and including substantially the same material as the first and second films; and a through via formed between the gate electrode structures and the first mold, extending in the first direction, and electrically connected to the circuit pattern.

[0009] A method for manufacturing a vertical memory device according to one embodiment includes the steps of: forming a mold film by alternately stacking insulating films and sacrificial films along a first direction perpendicular to an upper surface of a substrate on a substrate including a cell region, through via regions formed on both sides of the cell region, a mold region surrounding the cell region and the through via region, and a scribe lane (S / L) region surrounding the mold region; removing portions of the mold film formed on the through via region and the cell region and the mold region adjacent thereto, forming a first mold on the mold region and the S / L region to form a second mold on the cell region; forming a channel penetrating the second mold to form an opening penetrating the second mold; and replacing the sacrificial film included in the second mold with a gate electrode through the opening.

[0010] According to another embodiment, a method for manufacturing a vertical memory device includes the steps of: forming a mold film on a substrate by alternately stacking insulating films and sacrificial films along a first direction perpendicular to an upper surface of the substrate; forming a first opening through the mold film and surrounded by a stepped shape in a portion of the mold film to partially remove the mold film; forming a channel through the mold film; forming a second opening through the mold film; and replacing the sacrificial film included in the mold film with a gate electrode through the second opening, wherein the sacrificial film included in an edge portion of the mold film is not replaced when the sacrificial film is replaced with the gate electrode.

[0011] According to still another embodiment, a method for manufacturing a vertical memory device includes the steps of: forming a mold film on a substrate by alternately stacking insulating films and sacrificial films along a first direction perpendicular to an upper surface of the substrate; partially removing the mold film and forming a plurality of first openings along a second direction intersecting the third direction parallel to the upper surface of the substrate, the first openings each extending through the mold film along a third direction parallel to an upper surface of the substrate and surrounded by portions of the mold film to have a stepped shape; forming channels extending in the first direction through portions of the mold film formed between the first openings, and forming a plurality of second openings each extending in the second direction through portions of the mold film formed between the first openings, thereby forming a plurality of molds spaced apart from each other along the third direction; and replacing each of the sacrificial films included in the plurality of molds with gate electrodes through the second openings. Effect of the Invention

[0012] According to the present invention, in a method for manufacturing a vertical memory device, during a process of patterning a mold film including insulating films and sacrificial films alternately stacked on a substrate including a chip region and an S / L region to have a stepped shape, a portion of the mold film formed on the S / L region is left instead of being removed, so that the mold film including insulating films and sacrificial films having compressive and tensile forces, respectively, remains in the S / L region the same as in the chip region. This reduces stress generated in the S / L region, and since the S / L region has a similar stress to the chip region, a test for the chip region can be accurately performed through a TEG formed on the S / L region. [Brief description of the drawings]

[0013] [Figure 1] 1 is a plan view illustrating a vertical memory device according to an embodiment; [Diagram 2] FIG. 2 is a plan view of an X region in FIG. [Diagram 3] FIG. 2 is a perspective view of an X region in FIG. [Figure 4] FIG. 2 is a plan view of a region Y in FIG. [Diagram 5] FIG. 2 is a perspective view of a Y region in FIG. [Figure 6] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 7] 2A to 2C are plan views of an X region of FIG. 1 illustrating steps of a method for manufacturing a vertical memory device according to an embodiment. [Figure 8] 2A to 2C are plan views of a Y region of FIG. 1 illustrating steps of a method for manufacturing a vertical memory device according to an embodiment. [Figure 9] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 10] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 11] 1A to 1C are cross-sectional views taken along line BB' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 12] 2A to 2C are plan views of an X region of FIG. 1 illustrating steps of a method for manufacturing a vertical memory device according to an embodiment. [Figure 13] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 14] 1A to 1C are cross-sectional views taken along line CC' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 15] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 16] 1A to 1C are cross-sectional views taken along line CC' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 17]2A to 2C are plan views of a Y region of FIG. 1 illustrating steps of a method for manufacturing a vertical memory device according to an embodiment. [Figure 18] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 19] 1A to 1C are cross-sectional views taken along line BB' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 20] 1A to 1C are cross-sectional views taken along line CC' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 21] 5A to 5C are cross-sectional views taken along line DD' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 22] 2A to 2C are cross-sectional views taken along line AA' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 23] 1A to 1C are cross-sectional views taken along line BB' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 24] 1A to 1C are cross-sectional views taken along line CC' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Diagram 25] 5A to 5C are cross-sectional views taken along line DD' of corresponding plan views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment; [Figure 26] FIG. 2 is a plan view of a Y region in FIG. [Figure 27a] FIG. 2 is a perspective view of a region Y in FIG. [Figure 27b] FIG. 2 is a perspective view of a region Y in FIG. [Figure 28] FIG. 2 is a plan view of a second example of the X region in FIG. [Figure 29] FIG. 2 is a perspective view of a second example of the X region in FIG. [Diagram 30] FIG. 2 is a plan view of a third example of an X region in FIG. [Diagram 31] FIG. 2 is a perspective view of a third example of the X region in FIG. [Diagram 32] FIG. 2 is a plan view of a fourth example of an X region in FIG. [Diagram 33] FIG. 2 is a perspective view of a fourth example of the X region in FIG. [Diagram 34] 2 is a cross-sectional view of a second example of a vertical memory device taken along line AA' of a corresponding plan view according to an embodiment; FIG. [Diagram 35] 11 is a cross-sectional view of a third example of a vertical memory device taken along line AA' of a corresponding plan view according to an embodiment; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0015] In the following, a direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two mutually intersecting horizontal directions substantially parallel to the upper surface of the substrate are defined as a second direction and a third direction, respectively. In this embodiment, the second direction and the third direction are orthogonal to each other.

[0016] 1 to 5 are plan and perspective views illustrating a vertical memory device according to an embodiment, in which Fig. 1, Fig. 2, and Fig. 4 are plan views, and Fig. 3 and Fig. 5 are perspective views.

[0017] Here, Figures 2 and 4 are plan views of regions X and Y in Figure 1, respectively, and Figures 3 and 5 are perspective views of regions X and Y in Figure 1, respectively. Meanwhile, in all the perspective views including Figures 3 and 5, components such as an interlayer insulating film, a capping pattern, and a CSP are omitted and not shown in order to avoid complicating the drawings.

[0018] 1, the substrate 100 includes a first region (I) and a second region (II) surrounding the first region (I). Here, the first region (I) of the substrate 100 is formed in a plurality of regions along the second and third directions, and the second region (II) of the substrate 100 is formed to surround each of the first regions (I).

[0019] The substrate 100 may comprise a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In one embodiment, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0020] The first region (I) of the substrate 100 is a chip region where a semiconductor chip is formed, and the second region (II) of the substrate 100 is a scribe lane (S / L) region surrounding the chip region. In one embodiment, an alignment key for aligning an exposure mask used in a photolithography process to a precise position, a TEG (Test Element Group) for detecting leakage current of a vertical memory device, etc. are formed in the second region (II) of the substrate 100.

[0021] In one embodiment, the vertical memory device has a cell over peri (COP) structure. That is, a circuit pattern for driving a memory cell formed in a cell region included in a first region (I) of the substrate 100 is formed under the memory cell, not around the memory cell. As a result, a circuit pattern region in which a circuit pattern is formed and a cell region are vertically stacked on the substrate 100, and the circuit pattern is called a lower circuit pattern. However, the present invention is not necessarily limited thereto, and the vertical memory device may have a COP structure, and a peripheral circuit region in which a part of the circuit pattern is formed may be further formed around the cell region.

[0022] 2 and 4, the first region (I) of the substrate 100 includes third to fifth regions (III, IV, V).

[0023] The third region (III) of the substrate 100 is a cell region where memory cells are formed. In an embodiment, the third region (III) of the substrate 100 is formed in a plurality of regions along each of the second and third directions.

[0024] Hereinafter, the third region (III) formed on the left side in the plan view illustrating the X region in Fig. 1 will be referred to as the first cell region, and the third region (III) formed on the right side will be referred to as the second cell region. Also, in the plan view illustrating the Y region in Fig. 1, the third region (III) formed on the left side will be referred to as the second cell region, and the third region formed on the right side will be referred to as the third cell region.

[0025] The fourth region (IV) of the substrate 100 is a through via region in which a through via connected to a lower circuit pattern is formed, and is formed on both sides of the third region (III) in the second direction. In one embodiment, the fourth region (IV) of the substrate 100 is formed in a plurality of regions in the second direction, each extending in the third direction.

[0026] The fifth region (V) of the substrate 100 is a region surrounded by the second region (II) while surrounding the third and fourth regions (III, IV). The fifth region (V) of the substrate 100 is called a mold region because the mold remains in the fifth region (V) of the substrate 100 after the mold film is patterned. The fifth region (V) of the substrate 100 has a shape similar to a square ring when viewed from above.

[0027] In one embodiment, the fifth region (V) of the substrate 100 surrounds both sides in the third direction of the third region (III) and one side in the second direction and both sides in the third direction of the fourth region (IV).

[0028] 3 and 5, a gate electrode structure 360 ​​is formed on a third region (III) of the substrate 100, and a first mold 207 is formed on a second region (II) and a fifth region (V) of the substrate 100. In one embodiment, a portion of the gate electrode structure 360 ​​and a portion of the first mold 207 surrounding the fourth region (IV) together form a staircase structure.

[0029] In one embodiment, the first mold 207 is a stepped structure having a stepped shape with one insulating film 200 and one sacrificial film 210 sequentially stacked toward the fourth region (IV) of the substrate 100 as each stepped layer, and the gate electrode structure 360 ​​is a stepped structure having a stepped shape with each gate electrode as each stepped layer.

[0030] In this specification, each layer of the staircase structure is defined as a "staircase layer," and the portion formed at each end of each staircase layer that is not overlapped in the first direction by the upper staircase layer and is exposed to the outside is defined as a "stair."

[0031] In one embodiment, the sacrificial film 210 included in the stepped layer of the first mold 207 is formed to the same height as each corresponding stepped layer of the gate electrode structure 360, and the slope of the sacrificial film 210 included in the stepped layer of the first mold 207 is the same as the slope of the stepped layer included in the gate electrode structure 360.

[0032] In one embodiment, the sacrificial layer 210 in the stepped layer of the first mold 207 and each stepped layer of the corresponding gate electrode structure 360 ​​are connected to each other.

[0033] In one embodiment, the third mold 209 is formed in a middle portion in the third direction of the third region (III) of the substrate 100, extends in the second direction between adjacent gate electrode structures 360, and includes insulating patterns 205 and sacrificial patterns 215 alternately stacked along the first direction.

[0034] In one embodiment, similar to the first mold 207, the third mold 209 is also a staircase structure having a staircase shape with one insulating pattern 205 and one sacrificial pattern 215 stacked in sequence, each of which constitutes a staircase layer.

[0035] In one embodiment, the sacrificial patterns 215 in each step layer of the third mold 209 and the corresponding step layers of the gate electrode structure 360 ​​are connected to each other.

[0036] In the vertical memory device, a first mold 207 is present in a fifth region (V) formed on the edge of the first region (I) of the substrate 100 and in a second region (II) surrounding the first region (I) of the substrate 100. As a result, in a manufacturing method of the vertical memory device described below, insulating films 200 and sacrificial films 210, each having a compressive force and a tensile force, are alternately stacked on the fifth region and the second region of the substrate 100, so that one-sided stress is not applied to the substrate 100.

[0037] 6 to 25 are plan views and cross-sectional views illustrating steps of a method for manufacturing a vertical memory device according to an embodiment. Specifically, FIGS. 7 to 8, 12, and 17 are plan views, and FIGS. 6, 9 to 11, 13 to 16, and 18 to 25 are cross-sectional views.

[0038] Here, Fig. 7 and Fig. 12 are plan views of the X region in Fig. 1, and Fig. 8 and Fig. 17 are plan views of the Y region in Fig. 1. Meanwhile, Fig. 6, Fig. 9, Fig. 10, Fig. 13, Fig. 15, Fig. 18, and Fig. 22 are cross-sectional views taken along the line A-A' in the corresponding plan views, Fig. 11, Fig. 19, and Fig. 23 are cross-sectional views taken along the line B-B' in the corresponding plan views, Fig. 14, Fig. 16, Fig. 20, and Fig. 24 are cross-sectional views taken along the line C-C' in the corresponding plan views, and Fig. 21 and Fig. 25 are cross-sectional views taken along the line D-D' in the corresponding plan views.

[0039] Referring to FIG. 6, a circuit pattern is formed on a substrate 100, and first and second lower interlayer insulating films 130 and 180 for covering the circuit pattern are sequentially formed on the substrate 100.

[0040] The substrate 100 includes a field region having an isolation pattern 110 formed thereon and an active region other than the field region. The isolation pattern 110 is formed by an STI process and includes, for example, an oxide.

[0041] The circuit pattern includes transistors, lower contact plugs 140, lower wirings (150, 170), lower vias 160, and the like.

[0042] For example, a transistor is formed including a lower gate structure 120 formed on a substrate 100 and a first impurity region 105 formed on an active region adjacent to the lower gate structure 120. In one embodiment, the lower gate structure 120 includes a lower gate insulation pattern, a lower gate electrode, and a lower gate mask, which are sequentially stacked on the substrate 100.

[0043] A first lower interlayer insulating film 130 is formed on the substrate 100 to cover the transistor, and a lower contact plug 140 penetrates the first lower interlayer insulating film 130 to contact the first impurity region 105 or the lower gate structure 120. A first lower interconnection 150 is formed on the first lower interlayer insulating film 130 to contact an upper surface of the lower contact plug 140. A first lower via 160 and a second lower interconnection 170 are sequentially stacked on the first lower interconnection 150. A second lower interlayer insulating film 180 is formed on the first lower interlayer insulating film 130 to cover the first and second lower interconnections (150, 170) and the first lower via 160.

[0044] 6 illustrates the circuit pattern formed only on the fourth region (IV) of the substrate 100, but the present invention is not necessarily limited to this. That is, a plurality of circuit patterns are formed on the first to fifth regions (I, II, III, IV, V) of the substrate 100 along the second direction and the third direction.

[0045] Thereafter, a base pattern 190 is formed on the second lower interlayer insulating film 180, and an insulating film 200 and a sacrificial film 210 are alternately and repeatedly stacked on the base pattern 190 to form a mold film.

[0046] The base pattern 190 includes a semiconductor material such as silicon, the insulating film 200 includes an oxide such as silicon oxide, and the sacrificial film 210 includes a material having an etch selectivity with respect to the insulating film 200, such as a nitride such as silicon nitride.

[0047] 7 to 9, a first photoresist pattern (not shown) that covers the first and second regions (I, II) of the substrate 100 but does not cover the fourth region (IV) of the substrate 100 is formed on the top insulating film 200, and the mold film is etched by alternately performing an etching process using this as an etching mask and a trim process that reduces the area of ​​the first photoresist pattern.

[0048] Here, the first photoresist pattern includes a first opening exposing only the fourth region (IV) of the substrate 100, and the size of the first opening is expanded as the trim process is repeatedly performed. Thus, the first opening of the first photoresist pattern is expanded to expose gradually more of the third and fifth regions (III, V) surrounding and adjacent to the fourth region (IV) each time the trim process is repeatedly performed. After performing the etching and trim processes, the first photoresist pattern is removed, for example, by an ashing and / or stripping process.

[0049] After the etching process on the mold film, a first mold 207 remains on the second region (II) and fifth region (V) of the substrate 100, and a second mold 208 remains on the third region (III) of the substrate 100. Here, the first and second molds (207, 208) are in contact with and connected to each other at the boundary between the third region (III) and fifth region (V) of the substrate 100. Meanwhile, the base pattern 190 is exposed on the fourth region (IV) of the substrate 100 through the first opening.

[0050] In one embodiment, the second mold 208 is a staircase structure having one insulating film 200 and one sacrificial film 210 as each staircase layer and oriented in the second direction, and the portion of the first mold 207 facing it is also a staircase structure having one insulating film 200 and one sacrificial film 210 as each staircase layer. In addition, the portions of the first and second molds (207, 208) formed on the portions of the third region (III) and the fifth region (V) adjacent to the fourth region (IV) of the substrate 100 are both staircase structures having a staircase shape surrounding the fourth region (IV).

[0051] In one embodiment, the staircase structure formed by the portions of the first and second molds (207, 208) surrounding the fourth region (IV) together has a square ring shape, when viewed from above, that gradually decreases in size toward the center of the fourth region (IV).

[0052] 10 and 11, a first interlayer insulating film 220 covering the sidewalls of the first and second molds (207, 208) is formed on the base pattern 190, and then a second interlayer insulating film 230 is formed on the upper surface of the top insulating film 200 and the upper surface of the first interlayer insulating film 220.

[0053] The first and second interlayer insulating layers (220, 230) comprise an oxide, such as silicon oxide, and are incorporated with the insulating layer 200 or between each other.

[0054] 12 to 14, a first mask (not shown) is formed on the second interlayer insulating film 230, and then the first mask (not shown) is used as an etching mask to etch the second interlayer insulating film 230, the insulating film 200, and the sacrificial film 210 formed on the third region (III) of the substrate 100, thereby forming a channel hole that penetrates them and partially exposes the top surface of the base pattern 190, and a pillar structure that fills the channel hole is formed as follows.

[0055] That is, after removing the first mask, a selective epitaxial growth (SEG) process is performed using the top surface of the base pattern 190 exposed by the channel hole as a seed to form a semiconductor pattern 240 that partially fills the channel hole. In one embodiment, the top surface of the semiconductor pattern 240 is located between the top and bottom surfaces of the insulating film 200 formed as the second layer in the first direction from the top surface of the base pattern 190 of the insulating film 200. In some cases, the process of forming the semiconductor pattern 240 may be omitted.

[0056] Then, a first blocking layer, a charge storage layer, a tunnel insulating layer, and a first spacer layer (not shown) are sequentially formed on the sidewalls of the channel holes, the top surface of the semiconductor pattern 240, and the top surface of the second interlayer insulating layer 230. The first spacer layer is anisotropically etched to form a first spacer (not shown) that remains only on the sidewalls of the channel holes. The first blocking layer, the charge storage layer, and the tunnel insulating layer are then etched using the first spacer as an etching mask to form a first blocking pattern 250, a charge storage pattern 260, and a tunnel insulating pattern 270 each having a cup shape with an open center at the bottom on the sidewalls of the semiconductor pattern 240 and the channel holes. Here, the top of the semiconductor pattern 240 is also partially removed. The tunnel insulating pattern 270, the charge storage pattern 260, and the first blocking pattern 250 together form a charge storage structure 280.

[0057] The first spacer layer includes a nitride, such as silicon nitride, the tunnel insulating pattern 270 and the first blocking pattern 250 include an oxide, such as silicon oxide, and the charge storage pattern 260 includes a nitride, such as silicon nitride.

[0058] After removing the first spacer, a channel film is formed on the exposed semiconductor pattern 240, the tunnel insulating pattern 270, and the second interlayer insulating film 230, and a charge film filling the remaining part of the channel hole is formed on the channel film. The charge film and the channel film are planarized until the top surface of the second interlayer insulating film 230 is exposed, thereby forming a charge pattern 300 filling the remaining part of the channel hole, and converting the channel film into a channel 290.

[0059] In one embodiment, a plurality of channels 290 are formed along the second and third directions on the third region (III) of the substrate 100, forming a channel block and a channel array.

[0060] Then, a trench (not shown) is formed by removing the charging pattern 300, the channel 290, and the upper portion of the charge storage structure 280, and a capping pattern 310 is formed to fill the trench. As a result, a pillar structure including the semiconductor pattern 240, the channel 290, the charge storage structure 280, the charging pattern 300, and the capping pattern 310 is formed in the channel hole.

[0061] The channel 290 and the capping pattern 310 each include single crystal silicon or polysilicon, which may or may not be doped with impurities.

[0062] Thereafter, a third interlayer insulating film 320 is formed on the second interlayer insulating film 230 and the capping pattern 310, and a second mask (not shown) is formed on the third interlayer insulating film 320, and then the second mask (not shown) is used as an etching mask to form second openings 330 each extending in a second direction through the second and third interlayer insulating films (230, 320), the insulating film 200, and the sacrificial film 210 on the third region (III) of the substrate 100, thereby exposing the upper surface of the base pattern 190. As a result, the insulating film 200 and the sacrificial film 210 included in the second mold 208 remaining on the third region (III) of the substrate 100 are converted into the insulating pattern 205 and the sacrificial pattern 215, respectively.

[0063] The portions of the second opening 330 formed on both edges in the third direction are formed to be spaced a certain distance from the fifth region (V) of the substrate 100 along the third direction, and the second opening 330 is not formed in the middle portion of the third region (III) of the substrate 100 in the third direction.

[0064] 15 and 16, after removing the second mask, the sacrificial pattern 215 exposed by the second opening 330 is removed, for example by a wet etching process, to form a gap 340 between the insulating patterns 205 of each layer, and a portion of the outer wall of the first blocking pattern 250 and a portion of the sidewall of the semiconductor pattern 240 are exposed by the gap 340.

[0065] Here, the second opening 330 is formed only on the third region (III) of the substrate 100, and only the sacrificial pattern 215 included in the second mold 208 remaining on the third region (III) of the substrate 100 is removed by the wet etching process, and the sacrificial film 210 included in the first mold 207 remaining on the second region (II) and fifth region (V) of the substrate 100 is not removed.

[0066] In one embodiment, the first mold 207 is formed on the fifth region (V) portion disposed on both sides in the third direction of the third region (III) of the substrate 100. In another embodiment, the first mold 207 is formed only on the fifth region (V) portion disposed on one side in the third direction of the third region (III) of the substrate 100.

[0067] On the other hand, since the second opening 330 is not formed in the middle part in the third direction of the third region (III) of the substrate 100, the sacrificial pattern 215 remains on the middle part of the third region (III) of the substrate 100 without being removed, and together with the insulating pattern 205, they form the third mold 209. The third mold 209 extends in the second direction on the third region (III) of the substrate 100.

[0068] In one embodiment, the first mold 207 is a stepped structure having a stepped shape in which one insulating film 200 and one sacrificial film 210 are sequentially stacked toward the fourth region (IV) of the substrate 100, forming each of the stepped layers.

[0069] Similarly, the third mold 209 has a stepped structure in which one insulating pattern 205 and one sacrificial pattern 215 are stacked in sequence to form a stepped layer.

[0070] 17 to 21, a second blocking film 350 is formed on the exposed outer wall of the first blocking pattern 250, the exposed sidewall of the semiconductor pattern 240, the inner wall of the gap 340, the surface of the insulating pattern 205, the exposed top surface of the base pattern 190, and the top surface of the third interlayer insulating film 320, and a gate conductive film is formed on the second blocking film 350 to sufficiently fill the remaining portion of the gap 340. A gate barrier film is further formed between the second blocking film 350 and the gate conductive film.

[0071] The second blocking film 350 includes a metal oxide such as aluminum oxide, the gate conductive film includes a low resistance metal such as tungsten or aluminum, and the gate barrier film includes a metal nitride such as titanium nitride or tantalum nitride.

[0072] Thereafter, the gate conductive layer is partially removed to form a gate conductive pattern within the gap 340, and if a gate barrier layer is formed, it is also partially removed to form a gate barrier pattern. The gate conductive pattern and the gate barrier pattern together form a gate electrode. The gate electrodes are stacked in a plurality of layers spaced apart from each other along a first direction to form a gate electrode structure 360, and each gate electrode extends in a second direction on a third region (III) of the substrate 100.

[0073] In an embodiment, a plurality of gate electrode structures 360 are formed along the third direction. That is, the gate electrode structures 360 each extending in the second direction are spaced apart from each other in the third direction by the second openings 330. In an embodiment, portions of the gate electrode structures 360 formed at both ends in the third direction contact the first mold 207.

[0074] In one embodiment, the gate electrode structure 360 ​​contacts the first mold 207 at the boundary between the third region (III) and the fifth region (V) of the substrate 100 and contacts the third mold 209 at a middle portion of the third region (III) of the substrate 100.

[0075] In one embodiment, the gate electrodes included in the gate electrode structures 360 are formed to have substantially the same height as the sacrificial layer 210 included in the first mold 207 and the sacrificial pattern 215 included in the third mold 209, respectively.

[0076] The gate electrodes included in the gate electrode structure 360 ​​are formed by respectively replacing the sacrificial patterns 215 on the third region (III) of the substrate 100, and since the second mold 208 including the sacrificial patterns 215 has a stepped shape, the gate electrode structure 360 ​​also has a stepped shape with each gate electrode as a stepped layer.

[0077] In one embodiment, each step layer of the gate electrode structure 360 ​​is formed in the same layer as the sacrificial film 210 included in each step layer of the corresponding first mold 207, and the slopes of the step layers included in the gate electrode structure 360 ​​are the same as the slopes of the sacrificial films 210 included in the step layers of the first mold 207.

[0078] The gate electrode includes first to third gate electrodes (362, 364, 366) formed in sequence along a first direction. In one embodiment, the first gate electrode 362 is formed in the bottom layer, the third gate electrode 366 is formed in the top layer and one layer below it, i.e., the first and second layers, and the second gate electrode 364 is formed in multiple layers between the first gate electrode 362 and the third gate electrode 366, but the present invention is not limited thereto.

[0079] Then, impurities are implanted into the upper portion of the base pattern 190 exposed through the second opening 330 to form a second impurity region 195 .

[0080] Then, a second spacer film is formed on the upper surface of the base pattern 190 exposed by the second opening 330, the sidewalls of the second opening 330, and the upper surface of the third interlayer insulating film 320, and the second spacer film is then anisotropically etched to form second spacers 370 on each sidewall of the second opening 330.

[0081] Thereafter, a common source pattern (CSP) 380 is formed on the second impurity region 195 to fill the remaining portion of the second opening 330 .

[0082] According to one embodiment, a first conductive layer filling the second opening 330 is formed on the exposed upper surface of the second impurity region 195, the second spacer 370, and the third interlayer insulating layer 320, and then the upper portion of the first conductive layer is planarized until the upper surface of the third interlayer insulating layer 320 is exposed, thereby forming the CSP 380. Here, the portion of the second blocking layer 350 formed on the upper surface of the third interlayer insulating layer 320 is also removed. The CSP 380 is formed in the second opening 330 and contacts the upper surface of the second impurity region 195 below.

[0083] The first to third gate electrodes 362, 364, and 366 formed in the same layer are separated from each other along the third direction by the CSP 380 and the second spacer 370 filling the second opening 330 extending in the second direction.

[0084] 22 to 25, after forming a fourth interlayer insulating film 390 on the third interlayer insulating film 330, the CSP 380, the second spacer 370, and the second blocking film 350, a first contact plug 402 is formed to penetrate the third and fourth interlayer insulating films (320, 390) and contact an upper surface of the capping pattern 310, and second to fourth contact plugs (404, 406, 408) are formed to penetrate the first to fourth interlayer insulating films (220, 230, 320, 390), the insulating pattern 205, and the second blocking film 350 and contact an upper surface of one of the pads of the first to third gate electrodes (362, 364, 366), respectively.

[0085] Thereafter, through via 410 that penetrates through the first to fourth interlayer insulating films (220, 230, 320, 390), base pattern 190, and second lower interlayer insulating film 180 and contacts the upper surface of second lower wiring 170 is formed.

[0086] Thereafter, a fifth interlayer insulating film is formed on the fourth interlayer insulating film 390, the first to fourth contact plugs (402, 404, 406, 408) and the through via 410, and a bit line and an upper interconnection are formed through the fifth interlayer insulating film to contact the upper surface of the first contact plug 402, thereby completing the vertical memory device.

[0087] As described above, when the mold film including the insulating film 200 and the sacrificial film 210 alternately stacked on the substrate 100 is patterned, the mold film portions formed on the second and fifth regions (II, V) of the substrate 100 are not removed but are left on the first mold 207. As a result, since the insulating film 200 and the sacrificial film 210 included in the first mold 207 each include an oxide and a nitride, the compressive and tensile forces of each of them cancel each other out, thereby reducing the stress generated in the second region (II) of the substrate 100.

[0088] 26, 27a, and 27b are plan and perspective views of a vertical memory device according to an embodiment, in which FIG. 26 is a plan view of a Y region of FIG. 1, and FIGS. 27a and 27b are perspective views of the Y region of FIG. 1.

[0089] The vertical memory device is substantially the same as or similar to the vertical memory device described with reference to FIGS. 1 to 5 except for the align key, so a detailed description thereof will be omitted.

[0090] Referring to FIG. 26, before forming the second interlayer insulating film 230, the first mold 207 formed on the second region (II) of the substrate 100 is partially removed to further form an alignment key 225 penetrating the first mold 207 in a first direction.

[0091] In one embodiment, the alignment key 225 is formed by removing the insulating film 200 and the sacrificial film 210 formed on all layers of the first mold 207, in which case the top surface of the base pattern 190 is exposed above the portion where the alignment key 225 is to be formed.

[0092] Alternatively, the align key 225 may be formed by removing the insulating film 200 formed in a specific layer from the top insulating film 200 of the first mold 207 .

[0093] 26 illustrates the align key 225 having a rectangular shape when viewed from above, the present invention is not limited thereto, that is, the align key 225 may have various shapes other than a rectangular shape when viewed from above.

[0094] 26 illustrates one align key 225 formed on the second region (II) of the substrate 100, but the present invention is not necessarily limited to this. That is, a plurality of align keys 225 may be formed on the second region (II) of the substrate 100, and a plurality of align keys 225 may also be formed on the first region (I) of the substrate 100.

[0095] Referring to FIG. 27a, an etching process using a third mask (not shown) is performed to partially remove the first mold 207 formed on the second region (II), so that the align key 225 has sidewalls perpendicular to the top surface of the substrate 100.

[0096] Referring to FIG. 27b, an etching process using a second photoresist pattern (not shown) and a trim process for reducing the area of ​​the second photoresist pattern are alternately performed to partially remove the first mold 207 formed on the second region (II), thereby forming an align key 225 having a step shape with one insulating film 200 and one sacrificial film 210 as each step layer.

[0097] 28 to 33 are plan and perspective views of various examples for explaining a vertical memory device according to an embodiment. Specifically, Figs. 28, 30, and 32 are plan views of an X region in Fig. 1, and Figs. 29, 31, and 33 are perspective views of an X region in Fig. 1.

[0098] The vertical memory device is substantially the same as or similar to the vertical memory device described with reference to FIGS. 1 to 5 except for the shape of the first mold, so detailed description thereof will be omitted.

[0099] 28 and 29, the first mold 207 is formed on the fifth region (V) portions disposed on both sides in the third direction of the first cell region disposed on the left side of the third region (III) of the substrate 100, and on the fifth region (V) portion disposed on one side in the third direction of the second cell region disposed on the right side of the third region (III) of the substrate 100. Thus, the first mold 207 completely surrounds both sides in the third direction of the first cell region, but surrounds only one side in the third direction of the second cell region.

[0100] The first mold 207 is formed by performing processes that are substantially the same as or similar to those described with reference to Figures 6 to 9, and then performing an etching process using a fourth mask (not shown) to remove a portion of the first mold 207 located on one side of the second cell region.

[0101] Here, the portions of the first mold 207 removed on the second and fifth regions (II and V) of the substrate 100 serve as an alignment key.

[0102] 30 and 31, the first mold 207 is formed on the fifth region (V) portions arranged on both sides in the third direction of the first cell region arranged on the left side of the third region (III) of the substrate 100, but is not formed on the fifth region (V) portions arranged on both sides in the third direction of the second cell region arranged on the right side of the third region (III) of the substrate 100. As a result, the first mold 207 completely surrounds both sides in the third direction of the first cell region, but does not surround both sides in the third direction of the second cell region.

[0103] The first mold 207 is formed by performing processes substantially the same as or similar to those described with reference to Figures 6 to 9, and then performing an etching process using a third photoresist pattern (not shown) to remove portions of the first mold 207 located on both sides in the third direction of the second cell region.

[0104] In one embodiment, the remaining portions on both sides of each second cell region of the first mold 207 have a stepped shape with one insulating film 200 and one sacrificial film 210 stacked sequentially toward the second region (II) of the substrate 100, forming each stepped layer.

[0105] In one embodiment, the sacrificial film 210 included in the step layers of the remaining portions on both sides of each second cell region of the first mold 207 is formed in the same layer as each step layer in the second direction of the gate electrode structure 360 ​​and each step layer in the second direction of the first mold 207, and has the same slope as each other.

[0106] Meanwhile, the portions of the substrate 100 on the second and fifth regions (II and V) where the first mold 207 is removed serve as align keys.

[0107] 32 and 33, the first mold 207 is not formed on the fifth region (V) portions disposed on both sides in the second and third directions of the first cell region disposed on the left side of the third region (III) of the substrate 100, but is formed only on the fifth region (V) portions disposed on all sides excluding one side facing the first cell region of the second cell region disposed on the right side of the third region (III) of the substrate 100. Thus, the first mold 207 does not surround all sides of the first cell region, but surrounds all sides excluding one side of the second cell region.

[0108] The first mold 207 is formed by performing processes that are substantially the same as or similar to those described with reference to Figures 6 to 9, and then performing a trim process and an etching process using a fourth photoresist pattern (not shown) only in the first cell region.

[0109] 34 and 35 are cross-sectional views of various examples illustrating a vertical memory device according to an embodiment, taken along line A-A' in the corresponding plan views.

[0110] The vertical memory device is substantially the same as or similar to the vertical memory device shown in Figures 1 to 5, except for the shape of the first mold portion formed on the fifth region of the substrate, so detailed description thereof will be omitted.

[0111] Referring to FIG. 34, the portion of the staircase structure surrounding the fourth region (IV) of the substrate 100 that is formed on the fifth region (V) of the substrate 100 has a steeper slope than the opposing portion, i.e., the portion of the staircase structure formed on the third region (III) of the substrate 100.

[0112] 35, the portion of the staircase structure surrounding the fourth region (IV) of the substrate 100 that is formed on the fifth region (V) of the substrate 100 does not have a staircase shape.

[0113] In one embodiment, the portion of the first mold 207 extending along the third direction and formed on the fifth region (V) adjacent to the fourth region (IV) of the substrate 100 has a sidewall perpendicular to the substrate 100 .

[0114] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0115] 100 Substrates 105, 195 1st and 2nd impurity regions 110 Element isolation pattern 120 Lower Gate Structure 130, 180 First and second lower interlayer insulating films 140 Lower Contact Plug 150, 170 1st and 2nd lower wiring 160 Bottom Via 190 Base Pattern 200 Insulating film 205 Insulation Pattern 207~209 1st~3rd mold 210 Sacrificial membrane 215 Sacrifice Pattern 220, 230, 320, 390 1st to 4th interlayer insulating films 225 Alignment Key 240 Semiconductor Pattern 250 First Blocking Pattern 260 Charge Storage Pattern 270 Tunnel Insulation Pattern 280 Charge Storage Structure 290 Channels 300 Charging Pattern 310 Capping Pattern 330 Second Opening 340 Gap 350 Second Blocking Film 360 Gate electrode structure 362, 364, 366 First to third gate electrodes 370 Second Spacer 380 Common Source Pattern (CSP) 402, 404, 406, 408 1st to 4th contact plugs 410 Through Via

Claims

1. a substrate including a cell region, a through via region formed on each side of the cell region, a mold region surrounding the cell region and the through via region, and a scribe lane (S / L) region surrounding the mold region; gate electrode structures stacked on the cell region of the substrate to be spaced apart from each other along a first direction perpendicular to the top surface of the substrate, each gate electrode extending in a second direction parallel to the top surface of the substrate; a channel extending in the first direction on the cell region of the substrate and penetrating at least a portion of the gate electrode structure; a first mold including insulating layers and sacrificial layers having compressive and tensile strengths formed on the mold region and the S / L region, the first mold including insulating layers and sacrificial layers having compressive and tensile strengths and made of different insulating materials and alternately stacked in the first direction on the mold region of the substrate, 4. The vertical memory device according to claim 1, wherein the insulating film included in the first mold is formed to the same height as the gate electrodes included in the gate electrode structures and is in contact therewith.

2. The through via regions are formed on both sides of the cell region in the second direction, 2. The vertical memory device of claim 1, wherein the mold region is parallel to an upper surface of the substrate and surrounds both sides of the cell region in a third direction intersecting the second direction, and at least one side of the through via region in the second direction and both sides in the third direction.

3. 3. The vertical memory device of claim 2, wherein the first mold is formed on portions of the mold region disposed on both sides of the cell region in the third direction.

4. 3. The vertical memory device of claim 2, wherein the first mold is formed on a portion of the mold region disposed on one side of the cell region in the third direction.

5. The cell regions are formed in a plurality of regions spaced apart from each other in the second direction, 3. The vertical memory device of claim 2, wherein the through via regions are formed on both sides of each of the cell regions in the second direction.

6. 6. The vertical memory device of claim 5, wherein the first mold is formed on a portion of the mold region disposed on both sides of a first cell region in the third direction among the cell regions, and is formed on a portion of the mold region disposed on one side of a second cell region in the third direction among the cell regions.

7. 6. The vertical memory device of claim 5, wherein the first mold is formed on a portion of the mold region disposed on at least one of both sides of a first cell region in the cell region in the third direction, and is not formed on a portion of the mold region disposed on either side of a second cell region in the cell region in the third direction.

8. a second mold including a first pattern and a second pattern formed in a middle portion of the cell region of the substrate in the third direction, extending in the second direction, and stacked alternately along the first direction; 3. The vertical memory device of claim 2, wherein the first pattern and the second pattern comprise substantially the same material as the insulating layer and the sacrificial layer, respectively.

9. 10. The vertical memory device of claim 8, wherein the second mold has a staircase shape with one of the first patterns and one of the second patterns stacked sequentially toward the through via region as each staircase layer.

10. the gate electrode structure is formed in a plurality of portions spaced apart from each other along the third direction, 3. The vertical memory device of claim 2, wherein a portion of the gate electrode structure formed at one end in the third direction contacts the first mold.

11. 2. The vertical memory device of claim 1, wherein the gate electrode structure has a step shape with each of the gate electrodes being a step layer toward the through-via region.

12. 12. The vertical memory device of claim 11, wherein the first mold has a stepped shape with one insulating film and one sacrificial film being sequentially stacked toward the through via region as each stepped layer.

13. 13. The vertical memory device of claim 12, wherein the insulating film included in each step layer of the first mold is formed in the same layer as each step layer of the corresponding gate electrode structure.

14. 14. The vertical memory device of claim 13, wherein the insulating film included in each step layer of the first mold and each step layer of the gate electrode structure corresponding thereto are connected to each other.

15. 13. The vertical memory device of claim 12, wherein the slope of the insulating film included in each of the step layers of the first mold is the same as the slope of each of the step layers included in the gate electrode structure.

16. 13. The vertical memory device of claim 12, wherein the slope of the insulating film included in each of the step layers of the first mold is steeper than the slope of each of the step layers included in the gate electrode structure.

17. A circuit pattern formed on the substrate; A base pattern formed on the circuit pattern, 2. The vertical memory device of claim 1, wherein the gate electrode structure and the first mold are formed on the base pattern.

18. 20. The vertical memory device of claim 17, further comprising a through via extending in the first direction on a through via region of the substrate and electrically connected to the circuit pattern.

19. Gate electrode structures stacked on a substrate along a first direction perpendicular to an upper surface of the substrate including a mold region and a scribe lane (S / L) region surrounding the mold region so as to be spaced apart from each other, each of which includes a gate electrode extending in a second direction parallel to the upper surface of the substrate, and spaced apart from each other in a third direction intersecting the second direction parallel to the upper surface of the substrate; a channel extending in the first direction on the substrate and passing through at least a portion of each of the gate electrode structures; a first mold including insulating films and sacrificial films having compressive and tensile strengths formed on the mold region and the S / L region, the first mold being alternately stacked on the substrate along the first direction and made of different insulating materials, and contacting at least one of the gate electrode structures formed on both edges in the third direction; Each of the gate electrode structures has a step shape with each of the gate electrodes as a step layer, a portion of the first mold facing the gate electrode structure has a step shape in which one of the insulating films and one of the sacrificial films are stacked in sequence to form a step layer; 4. The vertical memory device according to claim 3, wherein the insulating film included in each step layer of the first mold and each step layer of the gate electrode structure corresponding thereto are formed to the same height.

20. A circuit pattern formed on a substrate including a mold area and a scribe lane (S / L) area surrounding the mold area; a base pattern formed on the circuit pattern; gate electrode structures stacked on the base pattern to be spaced apart from each other along a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate, and spaced apart from each other in a third direction intersecting the second direction parallel to the upper surface of the substrate; channels extending in the first direction on the base pattern and each penetrating at least a portion of each of the gate electrode structures; a charge storage structure formed on an outer wall of each of the channels; common source patterns (CSPs) each formed between the gate electrode structures adjacent to each other in the third direction and each extending in the second direction; a first mold including insulating layers and sacrificial layers having compressive and tensile strengths formed on the mold region and the S / L region, the first mold being alternately stacked on the base pattern along the first direction and made of different insulating materials, the first mold contacting at least one sidewall of the gate electrode structure formed on both edges in the third direction; a second mold including first and second patterns formed between two adjacent gate electrode structures formed in intermediate portions in the third direction among the gate electrode structures, extending in the second direction, alternately stacked along the first direction, and including first and second patterns each including substantially the same material as the insulating film and the sacrificial film; a through via formed between the gate electrode structure and the first mold, extending in the first direction, and electrically connected to the circuit pattern.

Images