Photodiode array and image sensor

Abstract

To improve the characteristics of photodiode arrays.SOLUTION: A photodiode array includes a plurality of elements arranged on a substrate. Each element includes a top electrode, a bottom electrode, a photoelectric conversion layer between the top electrode and the bottom electrode, a lower conductor portion located below the bottom electrode, and an insulating layer between the bottom electrode and the lower conductor portion. At least a portion of the lower conductor portion overlaps at least a portion of the bottom electrode in plan view through the insulating layer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to photodiode arrays. [Background technology]

[0002] Flat Panel Detectors (FPDs) used in X-ray sensors etc. are becoming increasingly finer. FPDs used in X-ray sensors are generally classified into direct conversion type and indirect conversion type. Indirect conversion type FPDs use phosphors (scintillators) that convert X-rays into light, such as visible light or ultraviolet light, in the X-ray detection panel, and a photodiode array that converts light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0316159 [Patent Document 2] U.S. Patent No. 7,208,742 Summary of the Invention [Problem to be solved by the invention]

[0004] As FPDs become more highly precise, there is a demand for technology that can detect light efficiently and accurately in photodiode arrays. [Means for solving the problem]

[0005] One aspect of the present disclosure is a photodiode array including a plurality of elements arranged on a substrate. Each of the plurality of elements includes an upper electrode, a lower electrode, a photoelectric conversion section between the upper electrode and the lower electrode, a lower conductor section located below the lower electrode, and an insulating layer between the lower electrode and the lower conductor section. At least a portion of the lower conductor section overlaps with at least a portion of the lower electrode via the insulating layer in a plan view. Effect of the Invention

[0006] According to one aspect of the present disclosure, the characteristics of a photodiode array can be improved. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing a configuration of an image sensor according to an embodiment; [Diagram 2] 2 is a circuit diagram showing an equivalent circuit of a pixel of the image sensor according to the embodiment; [Figure 3A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 3B] 3B is a cross-sectional view taken along line IIIB-IIIB' in FIG. 3A. [Figure 3C] 3C is a cross-sectional view taken along line IIIC-IIIC' in FIG. 3A. [Figure 4] 4 shows a pixel capacitance in the configuration described with reference to FIGS. 3A to 3C; [Figure 5A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 5B] 5B is a cross-sectional view taken along line VB-VB' in FIG. 5A. [Figure 5C] 5B is a cross-sectional view taken along line VC-VC' in FIG. 5A. [Figure 6A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 6B] 6B is a cross-sectional view taken along line VIB-VIB' in FIG. 6A. [Figure 7A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 7B] 7B is a cross-sectional view taken along line VIIB-VIIB′ in FIG. 7A. [Figure 8A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 8B] 8B shows a cross-sectional view taken along line VIIIB-VIIIB' in FIG. 8A. [Figure 9A]FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 9B] 9B is a cross-sectional view taken along line IXB-IXB' in FIG. 9A. [Figure 10A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 10B] 10B is a cross-sectional view taken along line XB-XB' in FIG. 10A. [Figure 11A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 11B] 11B is a cross-sectional view taken along line XIB-XIB' in FIG. 11A. [Figure 12A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 12B] 12B is a cross-sectional view taken along line XIIB-XIIB′ of FIG. 12A. [Figure 13A] FIG. 2 is a plan view illustrating an example of a structure of pixels, gate lines, and signal lines. [Figure 13B] 13B is a cross-sectional view taken along line XIIIB-XIIIB' in FIG. 13A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A photodiode array according to an embodiment of the present disclosure that can be used in an image sensor will be described in detail below with reference to the drawings. Note that the configuration of the photodiode array of the present disclosure can be applied to devices other than image sensors.

[0009] The size and scale of each component in each drawing are appropriately changed to ensure the visibility of the drawing. Hatching in each drawing is for distinguishing each component and does not necessarily mean a cut surface. In addition, the term "transistor" is used to refer to a nonlinear element used as a switching element or an amplifying element, but the term "transistor" includes a thin film transistor (TFT).

[0010] A photodiode array according to an embodiment of the present specification includes a plurality of pixels laid out on a substrate. The pixel includes a lower conductor portion in addition to a photodiode sandwiched between a lower electrode and an upper electrode. The lower conductor portion is located below the lower electrode, and an insulating layer is present between them. The pixel capacitance includes an additional capacitance between the lower electrode and the lower conductor portion in addition to the junction capacitance between the lower electrode and the upper electrode. This increases the pixel capacitance and improves pixel characteristics.

[0011] The image sensor of the present disclosure can be used, for example, in a radiography device in the fields of medical and industrial non-destructive testing. The light detected by the image sensor is an electromagnetic wave having any frequency, and includes infrared light, visible light, and X-rays.

[0012] [Image sensor configuration] 1 is a block diagram showing an example of the configuration of an image sensor according to an embodiment of the present specification. The image sensor 10 includes a sensor substrate 11 and a control circuit. The control circuit includes a drive circuit 14, a signal detection circuit 16, and a main control circuit 18.

[0013] The sensor substrate 11 includes an insulating substrate (e.g., a glass substrate) and a pixel region 12 in which pixels 13 are arranged in a matrix of vertical and horizontal rows on the insulating substrate. The pixels 13 are an example of an element on a substrate including a photodiode. The layout of the pixels 13 is not limited to the matrix layout shown in Fig. 1. A scintillator that emits fluorescence upon receiving radiation, which is detection light, may be arranged in the pixel region 12.

[0014] The pixels 13 are disposed at each intersection of a plurality of signal lines 106 extending vertically and arranged horizontally in Fig. 1 and a plurality of gate lines (scanning lines) 105 extending horizontally and arranged vertically. The pixels 13 are each connected to a bias line 107 extending vertically and arranged horizontally in Fig. 1. In Fig. 1, only one pixel, one signal line, one gate line and one bias line are indicated by the reference characters 13, 106, 105 and 107, respectively.

[0015] Each of the signal lines 106 is connected to a different pixel column. Each of the gate lines 105 is connected to a different pixel row. The signal lines 106 are connected to a signal detection circuit 16, and the gate lines are connected to a drive circuit 14. The bias line 107 is connected to a common bias line 108. A bias potential is applied to a pad 109 of the common bias line 108. The drive circuit 14 drives the gate lines 105 of the pixels 13 for light detection by the pixels 13. The signal detection circuit 16 detects signals from each of the signal lines. A main control circuit 18 controls the drive circuit 14 and the signal detection circuit 16.

[0016] [Pixel circuit configuration] 2 is a circuit diagram showing an equivalent circuit of one pixel 13. The pixel 13 includes a photodiode 121 which is a photoelectric conversion element, and a thin film transistor (TFT) 122 which is a switching element. A gate terminal of the thin film transistor 122 is connected to a gate line 105, one of a source / drain terminal is connected to a signal line 106, and the other of the source / drain terminal is connected to a cathode terminal of the photodiode 121. In the example of FIG. 2, an anode terminal of the photodiode 121 is connected to a bias line 107.

[0017] The thin film transistor 122 may be an a-Si (amorphous silicon) thin film transistor, a polysilicon thin film transistor, or an oxide semiconductor thin film transistor. The thin film transistor 122 has, for example, an n-type conductivity.

[0018] The pixel 13 further includes a junction capacitance 125 of the photodiode 121 and a capacitance element 126. The junction capacitance 125 and the capacitance element 126 are connected in parallel to the photodiode 121 between the switch TFT 122 and the bias line 107.

[0019] The image sensor 10 used as an X-ray imaging device accumulates signal charges corresponding to the amount of light irradiated onto the photodiode 121 in the junction capacitance 125 and the capacitance element 126. By including the capacitance element 126 in addition to the junction capacitance 125 of the photodiode 121, the saturation signal amount can be improved with almost no change in the manufacturing conditions of the photodiode.

[0020] The main control circuit 18 turns on the thin film transistor 122 arranged in the pixel 13 and extracts the charges accumulated in the junction capacitance 125 and the capacitance element 126 to the outside, thereby reading out the signal.

[0021] Specifically, the drive circuit 14 sequentially selects the gate lines 105 and applies a pulse that turns on the thin film transistor 122. The anode terminal of the photodiode 121 is connected to the bias line 107, and a reference potential is applied to the signal line 106 by the signal detection circuit 16. Therefore, the photodiode 121 is charged with a differential voltage between the bias potential of the bias line 107 and the reference potential. In general, this differential voltage is set to a reverse bias voltage in which the cathode potential is higher than the anode potential.

[0022] The charge required to recharge the photodiode 121 to this reverse bias voltage depends on the amount of light irradiated on the photodiode 121. The signal detection circuit 16 reads out the signal charge by integrating the current that flows when the photodiode 121 is recharged to the reverse bias.

[0023] In reading out the signal charge, the voltage of the terminal of the thin film transistor 122 connected to the signal line 106 is equal to or higher than the voltage of the terminal connected to the photodiode 121. That is, in detecting the signal charge, the terminal of the thin film transistor 122 connected to the signal line 106 is the drain, and the terminal connected to the photodiode 121 is the source. Note that the pixel 13 may include additional components (not shown) in addition to the components shown in FIG. 2, such as an additional thin film transistor.

[0024] [Pixel structure example] The following describes some examples of the device structure of the pixel 13. The photodiode 121, the thin film transistor 122, and the capacitor element 126 included in the pixel 13 each have a layered structure on an insulating substrate.

[0025] Fig. 3A is a plan view showing a schematic structure of a pixel 13, a gate line 105, and a signal line 106. In Fig. 3A, the signal line 106 extends in the vertical direction, the gate line 105 extends in the horizontal direction, and a thin film transistor 122 is disposed at the intersection thereof.

[0026] 3A , the entire area of ​​the upper electrode 205 overlaps with the lower electrode 201 in a planar view. That is, the entire area of ​​the upper electrode 205 is included within the area of ​​the lower electrode 201 in a planar view. As will be described later, the photodiode 121 is sandwiched between the lower electrode 201 and the upper electrode 205.

[0027] The pixel 13 further includes a thin film transistor 122, a lower conductor portion 210, and a bias electrode 221. The thin film transistor 122 includes a gate electrode 251, a semiconductor portion 252, a source electrode 253, and a drain electrode 254.

[0028] As described below, the lower layer conductor portion 210 is located in a layer lower than the lower electrode 201. In Fig. 3A, the portion of the lower layer conductor portion 210 that is covered by the lower electrode 201 is indicated by a dashed line. The lower layer conductor portion 210 includes an electrode shape portion 211 and connecting portions 212, 213. The electrode shape portion 211 is a wide portion, and the width (length in the lateral direction) of the connecting portions 212, 213 is smaller than the width of the electrode shape portion 211. The connecting portions 212, 213 extend upward and downward from the electrode shape portion 211.

[0029] The entire area of ​​the electrode shape portion 211 is covered by the lower electrode 201. In other words, the entire area of ​​the electrode shape portion 211 faces the lower electrode 201. A portion of each of the connecting portions 212, 213 faces the lower electrode 201, and the other portion extends outside the lower electrode 201. The lower conductor portion 210 includes a capacitive electrode portion which is the portion facing the lower electrode 201.

[0030] In the example of Fig. 3A, the capacitive electrode portion includes the entire area of ​​electrode shape portion 211 and parts of connecting portions 212, 213. In the configuration example of Fig. 3A, the capacitive electrode portion is substantially composed of electrode shape portion 211. The capacitive electrode portion, the opposing portion of lower electrode 201, and the insulating portion between these portions constitute capacitive element 126. In the configuration example of Fig. 3A, the entire area of ​​electrode shape portion 211 is within the regions of lower electrode 201 and upper electrode 205 in a plan view.

[0031] The bias electrode 221 interconnects the lower conductor section 210 and the upper electrode 205. Specifically, the contact section (interconnecting section) 225 interconnects the coupling section 212 of the lower conductor section 210 and the bias electrode 221. In addition, the contact section 226 interconnects the upper electrode 205 and the bias electrode 221.

[0032] In the configuration example of Fig. 3A, the lower layer conductor portions 210 arranged along the signal lines are connected to transmit a bias potential. In the configuration example of Fig. 3A, the lower layer conductor portions 210 adjacent in the vertical direction are connected via the connecting portion 212 or the connecting portion 213. The lower layer conductor portions 210 adjacent in the horizontal direction are not connected and are spaced apart. Each bias line 107 is included in each lower layer conductor portion group made up of the connected lower layer conductor portions 210. The bias potential is applied from the lower layer conductor portion 210 of the pixel 13 to the upper electrode 205 via the bias electrode 221.

[0033] The bias electrode 221 is connected to the lower conductor portion 210 at the contact portion 225, and is connected to the upper electrode 205 at the contact portion 226. The bias electrode 221 does not pass through the region of the upper electrode 205. An end of the bias electrode 221 in the direction from the contact portion 225 to the contact portion 226 is on the upper electrode 205 in a plan view. That is, in FIG. 3A, an end of the bias electrode 221 below the contact portion 226 is on the upper electrode 205.

[0034] The contact portion 225 exists outside the upper electrode 205 and the lower electrode 201. The upper electrode 205 and the lower electrode 201 each have a recess. The contact portion 225 exists within the region of the recess of the lower electrode 201. The distance from the center of the contact portion 226 to the end of the upper electrode 205 that is first crossed by a virtual line connecting the centers of the contact portions 225 and 226 is shorter than the distance that the virtual line passes from end to end of the upper electrode 205, and is, for example, less than half of that distance.

[0035] Moreover, the ends in the left and right directions from the contact portion 226 are located on the upper electrode 205 in a plan view. In this manner, by reducing the area where the bias electrode 221 and the upper electrode 205 overlap, the light receiving area of ​​the photodiode 121 can be increased.

[0036] 3A, the lower conductor section 210 is separated from the gate line 105 and the signal line 106 without overlapping them in a plan view. The lower electrode 201 and the upper electrode 205 are separated from the gate line 105 and the signal line 106 without overlapping them in a plan view. Furthermore, the lower conductor section 210 is separated from the semiconductor section 252 without overlapping them in a plan view. The lower electrode 201 and the upper electrode 205 are also separated from the semiconductor section 252 without overlapping them in a plan view.

[0037] Next, the cross-sectional structure of pixel 13 shown in Fig. 3A will be described. Fig. 3B shows a cross-sectional view taken along line IIIB-IIIB' in Fig. 3A, and Fig. 3C shows a cross-sectional view taken along line IIIC-IIIC' in Fig. 3A. Note that in the following drawings, the reference numerals of some elements may be omitted.

[0038] 3B and 3C, the thin film transistor 122 (see FIG. 3A) includes a gate electrode 251 formed on an insulating substrate 271, a gate insulating layer 272 on the gate electrode 251, and a semiconductor portion 252 on the gate insulating layer 272.

[0039] 3A, the gate electrode 251 is a portion that protrudes upward from the gate line 105 extending in the horizontal direction, and the gate electrode 251 is continuous with the gate line 105. The gate electrode 251 and the gate line 105 are formed on an insulating substrate (insulating layer) 271, and are included in the same conductor layer. Note that a silicon insulating layer may be present between the insulating substrate 271 and the gate electrode 251 and the gate line 105.

[0040] Continuous or separated conductor parts included in the same conductor layer are made of the same material on the same insulating layer and in direct contact with the insulating layer. In manufacturing, the conductor parts of the same conductor layer are formed in the same process. The conductor layer may have a single layer structure or a multilayer structure.

[0041] In this configuration example, the thin film transistor 122 has a bottom gate structure, and the gate electrode 251 is present below the semiconductor portion 252. The thin film transistor 122 further includes electrodes 253 and 254 on a gate insulating layer 272. The electrodes 253 and 254 are included in the same conductor layer.

[0042] Depending on the flow of carriers, one of the electrodes 253 and 254 is a source electrode and the other is a drain electrode. In detecting charges in the photodiode 121, the electrode 253 is a source electrode and the electrode 254 is a drain electrode. Therefore, hereinafter, the electrode 253 is referred to as a source electrode and the electrode 254 is referred to as a drain electrode.

[0043] The source electrode 253 and the drain electrode 254 are each in direct contact with the semiconductor portion 252. The source electrode 253 and the drain electrode 254 are formed so as to be in contact with the side surface of the island-shaped semiconductor portion 252 and part of the upper surface.

[0044] The gate insulating layer 272 is formed so as to cover the entire surface of the gate electrode 251. The gate insulating layer 272 is formed between the gate electrode 251 and the semiconductor portion 252. The first interlayer insulating layer 273 covers the entire thin film transistor 122. Specifically, the first interlayer insulating layer 273 covers the upper surface of the semiconductor portion 252, and the upper surfaces of the source electrode 253 and the drain electrode 254.

[0045] The substrate 271 is formed of, for example, glass or resin. The gate electrode 251 is a conductor and can be formed of metal or impurity-doped silicon. The gate insulating layer 272 is formed of, for example, silicon thermal oxide. The semiconductor constituting the semiconductor portion 252 is, for example, an oxide semiconductor or amorphous silicon. The oxide semiconductor contains, for example, at least one of In, Ga, and Zn, and examples thereof include amorphous InGaZnO (a-InGaZnO) and microcrystalline InGaZnO.

[0046] The source electrode 253 and the drain electrode 254 are conductors and can be formed of, for example, a metal such as Mo, Ti, Al, or Cr, an alloy thereof, or a laminate thereof. The first interlayer insulating layer 273 is an inorganic or organic insulator. The thin film transistor 122 shown in Figures 3A and 3B has a bottom gate structure, but differently, the thin film transistor 122 may have a top gate structure and may include both a top gate electrode portion and a bottom gate electrode.

[0047] The lower conductor 210 is formed on the first interlayer insulating layer 273. The lower conductor 210 is in direct contact with the first interlayer insulating layer 273. The lower conductor 210 is located above the gate electrode 251 and the gate line 105, and below the lower electrode 201. The first interlayer insulating layer 273 is present between the lower conductor 210 and the gate electrode 251 and the gate line 105. The second interlayer insulating layer 274 is present between the lower conductor 210 and the lower electrode 201. The second interlayer insulating layer 274 is an inorganic or organic insulator. In this example, the second interlayer insulating layer 274 is in direct contact with the lower electrode 201 and the lower conductor 210.

[0048] 3A to 3C, at least a portion of the lower electrode 201 overlaps with at least a portion of the lower conductor 210 in a planar view, with the insulating layer 274 interposed therebetween. That is, at least a portion of the lower electrode 201 covers at least a portion of the lower conductor 210 in a planar view. In this configuration example, a portion of the lower electrode 201 overlaps with a portion of the lower conductor 210.

[0049] 3B, the lower electrode 201 is connected to the source electrode 253 of the thin film transistor 122 through a contact portion 227 in a via hole of the second interlayer insulating layer 274 and the first interlayer insulating layer 273. The lower electrode 201 is a conductor, and can be formed of, for example, a metal such as Cr, Mo, or Al, an alloy thereof, or a laminate thereof.

[0050] The photodiode 121 is composed of a photoelectric conversion section between the lower electrode 201 and the upper electrode 205, and the lower electrode 201 and the upper electrode 205 that are in contact with the photoelectric conversion section. An example of the photodiode 121 shown in Figures 3B and 3C is a PIN diode. A PIN diode can detect light efficiently by forming a wide depletion layer in the film thickness direction. The upper electrode 205 is an electrode that is transparent to the light from the scintillator, and is, for example, ITO.

[0051] The photoelectric conversion portion of the photodiode 121 includes an n-type amorphous silicon layer (film) 202 on a lower electrode 201, an intrinsic amorphous silicon layer (film) 203 on the n-type amorphous silicon layer 202, and a p-type amorphous silicon layer (film) 204 on the intrinsic amorphous silicon layer 203. In this configuration example, the n-type amorphous silicon layer 202 is in direct contact with the lower electrode 201.

[0052] The upper electrode 205 is formed on the p-type amorphous silicon layer 204. In this configuration example, the upper electrode 205 is in direct contact with the p-type amorphous silicon layer 204. Light to be detected is incident on the photodiode 121 from the upper electrode 205 side. Note that the positions of the n-type amorphous silicon layer 202 and the p-type amorphous silicon layer 204 may be reversed, and the intrinsic amorphous silicon layer 203 may be omitted.

[0053] A third interlayer insulating layer 275 is formed to cover the lower electrode 201, the silicon layers 202-204, and the upper electrode 205. The third interlayer insulating layer 275 is an inorganic or organic insulator. The bias electrode 221 and the signal line 106 are formed on the third interlayer insulating layer 275. In this example, the bias electrode 221 and the signal line 106 are in direct contact with the third interlayer insulating layer 275. The signal line 106 is connected to the drain electrode 254 of the thin film transistor 122 through a contact portion 228 in a via hole of the third interlayer insulating layer 275, the second interlayer insulating layer 274, and the first interlayer insulating layer 273.

[0054] The bias electrode 221 is connected to a contact portion 22 formed in a via hole of the third interlayer insulating layer 275. 6 The bias electrode 221 is connected to the upper electrode 205 through a contact portion 22 formed in a via hole of the third interlayer insulating layer 275 and the second interlayer insulating layer 274. 5 3, is connected to the lower conductor portion 210. The bias electrode 221 is a conductor, and can be formed of, for example, a metal such as Mo, Ti, or Al, an alloy thereof, or a laminate thereof.

[0055] A passivation layer (film) 276 is formed so as to cover the signal line 106, the bias electrode 221, and the third interlayer insulating layer 275. The passivation layer 276 covers the entire pixel region 12. The passivation layer 276 is an inorganic or organic insulator. A scintillator (not shown) is disposed on the passivation layer 276.

[0056] The scintillator covers the entire pixel region 12. The scintillator emits light when excited by radiation. Specifically, the scintillator converts incident X-rays into light of a wavelength that is detected by the photodiode 121. The photodiode 121 generates signal charge in response to the light from the scintillator, and accumulates it in the junction capacitance 125 and the capacitance element 126 (see FIG. 2).

[0057] In the above configuration example, the photodiode 121 is in a layer above the thin-film transistor 122. This arrangement can reduce attenuation of incident light due to an insulating layer or the like, and can also facilitate the manufacture of the thin-film transistor and the photodiode in a semiconductor process.

[0058] 3A to 3C, a bias potential is applied to the upper electrode 205 from a lower-layer conductor section 210 located in a layer below the upper electrode 205 via a bias electrode 221. As shown in Fig. 3A, the bias electrode 221 only covers a portion of an end of the upper electrode 205. This configuration can reduce the area of ​​the upper electrode 205 covered by the conductor and increase the light receiving area of ​​the photodiode 121, as compared to a configuration in which a bias line passes from end to end over the upper electrode 205.

[0059] There is a need for higher resolution and higher definition for photodiode arrays, and this can be met by reducing the pixel size. However, as the pixel size decreases, the area of ​​the photodiode also decreases, and the junction capacitance also decreases, resulting in a decrease in the saturation signal amount.

[0060] The saturation signal level is one of the factors that determine the dynamic range, and the upper limit of the dynamic range is determined by the saturation signal level. The saturation signal level is determined by the pixel capacitance and bias potential. In addition to the saturation signal level, the dynamic range also depends on the level of noise caused by various factors including the dark current of the photodiode. The lower limit of the dynamic range is determined by the level of noise.

[0061] Since the dark current depends on the bias potential, the dark current can be reduced by reducing the bias potential. However, the saturation signal level also decreases, so the dynamic range does not expand. If the saturation signal level becomes small, when light (X-rays) with an intensity exceeding this level is irradiated, it is no longer possible to output a signal according to the intensity.

[0062] Therefore, under the constraint of reducing pixel size, it is necessary to increase the saturation signal amount. As described above, since the saturation signal amount depends on the pixel capacitance and the bias potential, the saturation signal amount can be increased by increasing the pixel capacitance.

[0063] Fig. 4 shows the pixel capacitance in the configuration described with reference to Fig. 3A to 3C. The pixel 13 includes a capacitance Cadd between the lower electrode 201 and the lower conductor 210, in addition to the junction capacitance Cpd of the photodiode 121. That is, the lower electrode 201 and the lower conductor 210, together with the insulating layer therebetween (part of the interlayer insulating layer 274), form an additional capacitance element.

[0064] In this way, by disposing the electrode-like lower conductor portion 210 below the lower electrode 201, a capacitance is formed between the lower electrode 201 and the lower conductor portion 210. This means that an additional capacitance element 126 is formed in parallel to the junction capacitance 125 of the photodiode 121 (see FIG. 2). This increases the pixel capacitance and improves the saturation signal amount of the pixel.

[0065] In particular, in products with small pixel sizes, it is difficult to change the junction capacitance by changing the manufacturing conditions, as this affects other characteristics such as quantum efficiency and dark current. However, in this structure, the capacitance element is formed using the conductor layer below the lower electrode 201, so the saturation signal amount can be improved with almost no change in the manufacturing conditions of the photodiode 121. Furthermore, the additional capacitance Cadd can be changed arbitrarily by changing the size of the lower conductor part 210 and the distance from the lower electrode 201 according to the application or purpose.

[0066] In this configuration, by adding a capacitive element 126 in parallel with the photodiode 121 and setting a small bias potential, it is possible to reduce the dark current while suppressing a decrease in the saturation signal amount, thereby increasing the dynamic range.

[0067] Since the lower conductor 210 is located below the lower electrode 201, the area can be increased without affecting the light receiving region. This reduces the possibility of disconnection and effectively reduces noise caused by the gate line 105.

[0068] In the configuration described with reference to Figures 3B and 3C, the lower conductor section 210 is present in the layer between the gate line 105 and the lower electrode 201. The parasitic capacitance formed by the pixel electrode and the gate line 105 can be reduced (electrostatic shielding effect by an electrode at a fixed potential). When the parasitic capacitance is reduced, the noise applied from the gate line 105 to the lower electrode 201 can be reduced.

[0069] The details are as follows. For example, when the lower electrode 201 is connected to the gate line 105 via a parasitic capacitance, the gate line 105 can become a noise source having a noise voltage Vn. Therefore, a noise current flows to the lower electrode 201 via the parasitic capacitance, and noise is generated in the lower electrode 201 by electrostatic induction. At this time, the magnitude of the noise is proportional to the magnitude of the parasitic capacitance.

[0070] The lower conductor section 210 located between the gate line 105 and the lower electrode 201 divides the parasitic capacitance between the gate line 105 and the lower electrode 201 into three capacitances. These capacitances are the capacitance between the gate line 105 and the lower electrode 201, the capacitance between the gate line 105 and the lower conductor section 210, and the capacitance between the lower conductor section 210 and the lower electrode 201. The lower conductor section 210 is always fixed to a bias potential. As a result, the noise current originating from the gate line mainly flows between the gate line 105 and the lower conductor section 210, and the noise current to the lower electrode 201 is reduced.

[0071] In this way, by arranging the lower layer conductor section 210 that transmits the bias potential below the lower electrode 201, the saturation signal amount of the pixel 13 can be increased and noise originating from the gate line can be reduced.

[0072] As mentioned above, the switch transistor of the pixel can be made of a semiconductor having any properties. In one embodiment of the present invention, a semiconductor having a mobility of 5 cm 2 A switch transistor including a semiconductor portion exceeding / Vs is utilized.

[0073] When the capacitance element 126 is added as described above, the pixel capacitance increases, and the write rate decreases when the transistor is turned on. This makes it impossible to read out the signal charge of the pixel 13 sufficiently, which may deteriorate the afterimage characteristics. Therefore, by using a switch element having the above mobility characteristics, it is possible to read the signal more reliably and appropriately. The thin film transistor having the above characteristics is, for example, a switch transistor using a semiconductor having high mobility, such as an oxide semiconductor or low-temperature polysilicon.

[0074] [Other pixel structure examples] Other configuration examples of the pixel will be described below. Fig. 5A is a plan view showing the structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 5B shows a cross-sectional view taken along the VB-VB' line in Fig. 5A, and Fig. 5C shows a cross-sectional view taken along the VC-VC' line in Fig. 5A. The following mainly describes the differences from the configuration described with reference to Figs. 3A to 3C.

[0075] This configuration example includes a bias line 321 instead of the bias electrode 221 in Figures 3A to 3C. The bias line 321 extends in the vertical direction of Figure 3A and is connected to each of the upper electrodes 305 of the multiple pixels 13 via contact parts 323. The bias line 321 passes over the upper electrode 305 from one end of the upper electrode 305 to the opposite end. The bias line 321 can be formed of, for example, the same material as the bias electrode 221.

[0076] In the configuration example shown in Fig. 5A, the upper electrode 305 and the lower electrode 301 do not have recesses like the upper electrode 205 and the lower electrode 201 shown in Fig. 3A. As shown in Figs. 5B and 5C, the bias line 321 is formed in the third interlayer insulating layer 275 and is in direct contact with the third interlayer insulating layer 275. The bias line 321 is connected to the upper electrode 205 by a contact portion 323 that penetrates the third interlayer insulating layer 275.

[0077] The lower conductor section 310 is not interconnected with the upper electrode 305 in the pixel 13 and is electrically isolated. As shown in FIG. 5C , the lower conductor section 310 includes an electrode shape section 311 and connecting sections 312, 313 extending vertically from the electrode shape section. In this configuration example, the width of the connecting sections 312, 313 is equal to or smaller than the width of the bias line 321. The lower conductor sections 310 of the pixels 13 adjacent in the vertical direction are connected by the connecting sections 312, 313. The lower conductor section 310 and the bias line 321 may be interconnected outside the pixel region 12.

[0078] In this configuration example, a bias potential or a constant potential different from the bias potential is applied to each column of the lower conductor section 310, for example, from the signal detection circuit 16. The lower conductor section 310, together with the lower electrode 301 and the second interlayer insulating layer 274, constitutes the additional capacitance element 126. In addition, the lower conductor section 310 can reduce noise from the gate line 105 to the lower electrode 301.

[0079] FIG. 6A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. FIG. 6B shows a cross-sectional view taken along the line VIB-VIB' in FIG. 6A. In the following, differences from the configuration described with reference to FIGS. 3A to 3C will be mainly described. In this configuration example, the lower layer conductor portion is included in the same conductor layer as the source electrode and the drain electrode. This can simplify the manufacturing process.

[0080] As shown in Fig. 6B, the lower conductor section 400 is formed on the gate insulating layer 272 and is in direct contact with the gate insulating layer 272. The lower conductor section 400 is formed of the same material as the source electrode 253 and the drain electrode 254 of the thin film transistor. The lower conductor section 400 is included in the same layer as the source electrode 253 and the drain electrode 254. The planar shape of the lower conductor section 400 may be similar to that of the lower conductor section 210 shown in Fig. 3A.

[0081] Fig. 7A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 7B shows a cross-sectional view taken along line VIIB-VIIB' in Fig. 7A. In the following, differences from the configuration described with reference to Figs. 3A to 3C will be mainly described. As shown in Fig. 7A, in this configuration example, the lower layer conductor portion 410 includes a top gate electrode portion 413 in addition to the electrode portion of the additional capacitance element 126.

[0082] The top gate electrode portion 413 extends from the electrode shape portion 211 toward the thin film transistor 122. In a plan view, the top gate electrode portion 413 covers a channel portion between the source electrode 253 and the drain electrode 254. Note that the top gate electrode portion 413 may cover only a portion of the channel portion.

[0083] 7B, (a part of) the first interlayer insulating layer 273 is present between the top gate electrode portion 413 and the semiconductor portion 252. The top gate electrode portion 413 can control the threshold value of the thin film transistor 122. In addition, the top gate electrode portion 413 can reduce light incidence into the semiconductor portion 252.

[0084] As described above, a high-mobility oxide semiconductor TFT can be used as the thin film transistor 122. The threshold of an oxide semiconductor easily varies with an external stimulus (for example, light, voltage, stress, etc.). Therefore, as in the configuration example shown in FIG. 7A, by having a dual gate structure with a bottom gate electrode 251 and a top gate electrode 413, the thin film transistor 122 can control the threshold with the top gate potential.

[0085] In a photodiode array, the photodiode 121 is generally fixed in a reverse bias mode. When a negative potential is applied to the top gate electrode portion 413, the top gate potential shifts the threshold value in a more positive direction than in the single gate structure. Therefore, when an external stimulus causes a negative shift, this has the effect of offsetting this.

[0086] Fig. 8A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 8B shows a cross-sectional view taken along line VIIIB-VIIIB' in Fig. 8A. In the following, differences from the configuration described with reference to Figs. 3A to 3C will be mainly described.

[0087] 8A, the lower conductor section 420 is connected to the lower conductor sections of adjacent pixels 13 in the horizontal direction as well as to the lower conductor sections of adjacent pixels 13 in the vertical direction. The lower conductor section 420 is connected to the lower conductor sections of adjacent pixels 13 in the horizontal direction via connecting sections 214, 215. The connecting sections 214, 215 are part of the lower conductor section 420. This configuration makes it possible to more effectively avoid breakage of the bias line that transmits the bias potential.

[0088] Fig. 9A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 9B shows a cross-sectional view taken along the line IXB-IXB' in Fig. 9A. In the following, differences from the configuration example shown in Figs. 7A and 7B will be mainly described.

[0089] 9A, the bias electrode 435 is connected to the top gate electrode portion 433 of the lower layer conductor portion 430 via a contact portion 437 (first contact portion). The bias electrode 435 is connected to the upper electrode 439 via a contact portion 436 (second contact portion). The bias electrode 435 may have a shape similar to that of the bias electrode shown in FIG. 7A.

[0090] As shown in FIG. 9B, the contact portion 436 penetrates the third interlayer insulating layer 275 to connect the bias electrode 435 and the upper electrode 439 The contact portion 437 penetrates the third interlayer insulating layer 275 and the second interlayer insulating layer 274, and interconnects the bias electrode 435 and the top gate electrode portion 433 (the lower layer conductor portion 430).

[0091] 7A, the lower electrode 438 and the upper electrode 439 shown in Fig. 9A do not have a recess on the side opposite to the thin film transistor 122. This can improve the light receiving area (aperture ratio) of the photodiode 121. As shown in Fig. 9A, the lower conductor 430 is connected to the lower conductor of the vertically adjacent pixel at the connecting portions 432 and 213.

[0092] FIG. 10A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. FIG. 10B shows a cross-sectional view taken along the line XB-XB' in FIG. 10A. In the following, differences from the configuration example shown in FIGS. 7A and 7B will be mainly described. In this configuration example, the photodiode is disposed so as to cover a part or the whole of the thin film transistor in a plan view. A part of the photodiode is located directly above the thin film transistor. This can improve the light receiving area (aperture ratio) of the photodiode.

[0093] 10A, the lower electrode 446 and the upper electrode 445 cover a portion of the thin film transistor 122. In this example, the entire semiconductor portion 252 is covered by the lower electrode 446 and the upper electrode 445. As shown in Fig. 10B, the photoelectric conversion portion 443 also covers a portion of the thin film transistor 122. In this example, the photoelectric conversion portion 443 is a PIN silicon laminate, and covers the same area as the upper electrode 445 in a plan view.

[0094] Fig. 11A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 11B shows a cross-sectional view taken along line XIB-XIB' in Fig. 11A. In the following, differences from the configuration example shown in Figs. 3A to 3C will be mainly described.

[0095] In this configuration example, the lower layer conductor portion 440 has an opening 444 in the electrode shape portion 441. The opening 444 is formed in a region overlapping with the lower electrode 201 in a plan view. Therefore, by adjusting the size of the opening 444, a desired additional capacitance can be obtained.

[0096] 11A, a part of the electrode shape portion 441 extends to the outside of the upper electrode 205 in a plan view. The entire area of ​​the electrode shape portion 441 is within the area of ​​the lower electrode 201 in a plan view. The lower conductor portion 440 is connected to the lower conductor portion of the vertically adjacent pixel 13 at connecting portions 442 and 443.

[0097] Fig. 12A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 12B shows a cross-sectional view taken along line XIIB-XIIB' in Fig. 12A. In the following, differences from the configuration examples shown in Figs. 3A to 3C will be mainly described.

[0098] 12A and 12B, a part of the electrode shape portion 451 of the lower layer conductor portion 450 extends outward beyond the upper electrode 205 and the lower electrode 201 in a plan view. The part of the electrode shape portion 451 outside the lower electrode 201 partially overlaps with the gate line 105. This configuration can more effectively reduce noise from the gate line 105.

[0099] Fig. 13A is a plan view showing a schematic structure of the pixel 13, the gate line 105, and the signal line 106. Fig. 13B shows a cross-sectional view taken along line XIIIB-XIIIB' in Fig. 13A. In the following, differences from the configuration example shown in Figs. 12A and 12B will be mainly described.

[0100] A portion of the lower electrode 461 is located directly above the gate line 105, sandwiching a portion of the electrode shape portion 451 of the lower conductor 450. A portion of the upper electrode 465 and the photoelectric conversion portion 467 is also located directly above the gate line 105, sandwiching a portion of the lower electrode 461. The lower electrode 461, the upper electrode 465, and the photoelectric conversion portion 467 extend to an area covering a portion of the gate line 105 in a plan view. This makes it possible to further improve the light receiving area (aperture ratio) of the photoelectric conversion portion.

[0101] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0102] 10 image sensor, 11 sensor substrate, 12 pixel region, 13 pixel, 14 drive circuit, 16 signal detection circuit, 18 main control circuit, 105 gate line, 106 signal line, 107 bias line, 121 photodiode, 122 thin film transistor, 125 junction capacitance, 126 capacitance element, 201, 301, 438, 446, 461 lower electrode, 205, 305, 439, 445, 465 upper electrode, 210, 310, 400, 410, 420, 430, 440, 450 lower layer conductor portion, 211, 311, 441, 451 electrode shape portion, 212-215, 312, 313, 432, 442, 443, 452, 453 connection portion, 221, 435 Bias electrode, 225, 226, 227, 228, 323, 436, 437 Contact portion, 251 Gate electrode, 252 Semiconductor portion, 253 Source electrode, 254 Drain electrode, 271 Insulating substrate, 272-276 Insulating layer, 413, 433 Top gate electrode portion, 443, 467 Photoelectric conversion portion, 444 Opening

Claims

1. A photodiode array including a plurality of elements arranged on a substrate, Each element of the plurality of elements comprises: An upper electrode; A lower electrode; a photoelectric conversion portion between the upper electrode and the lower electrode; a lower layer conductor portion located below the lower electrode; an insulating layer between the lower electrode and the lower conductor; Including, The photodiode array includes: A signal line; a switch transistor for switching between electrical continuity between the signal line and the element; A bias electrode; a first contact portion that electrically connects the bias electrode and a portion of the lower conductor portion that covers at least a part of the channel of the switch transistor in a plan view; A second contact portion that electrically connects the bias electrode and the upper electrode; Including, the switch transistor includes a gate electrode located below the lower electrode, At least a portion of the lower conductor overlaps with at least a portion of the lower electrode via the insulating layer in a plan view; a portion of the lower layer conductor portion covers at least a portion of a channel of the switch transistor in a plan view; Photodiode array.

2. The photodiode array of claim 1, The plurality of elements are laid out in a matrix, The lower layer conductor portion is connected to other lower layer conductor portions adjacent thereto in the horizontal and vertical directions. Photodiode array.

3. The photodiode array of claim 1, the source / drain electrodes of the switch transistor and the lower layer conductor portion are made of the same material on the same insulating layer; Photodiode array.

4. The photodiode array of claim 1, the lower conductor portion has an opening in a region facing the lower electrode in a plan view; Photodiode array.

5. The photodiode array of claim 1, a portion of the lower layer conductor portion covers, in a plan view, at least a portion of a gate line that transmits a signal to the gate electrode; Photodiode array.

6. The photodiode array of claim 5, a portion of the photoelectric conversion unit covers at least a portion of the gate line in a plan view; Photodiode array.

7. A photodiode array according to claim 1; a circuit for driving and controlling the photodiode array; an image sensor including

Images