Semiconductor Device

Abstract

To provide a novel nonvolatile latch circuit and a semiconductor device using the same.SOLUTION: A semiconductor device includes: a latch part having a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element; and a data holding part for holding data of the latch part, where a nonvolatile latch circuit is configured by the latch part and the data holding part. The data holding part used a transistor using an oxide semiconductor as a semiconductor material which configures a channel formation region as a switching element. In addition, the data holding part has capacitance electrically connected to a source electrode or a drain electrode of the transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention is a non-volatile logic circuit and In particular, the present invention relates to a non-volatile latch circuit and a semiconductor device using the same. Relating to the body apparatus. [Background technology]

[0002] Non-volatile logic circuitry that retains its memory even when the power is turned off. For example, integrated circuits that integrate ferroelectric A non-volatile latch circuit using such elements has been proposed (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2003 / 044953 Summary of the Invention [Problem to be solved by the invention]

[0004] However, non-volatile latch circuits using ferroelectric elements have problems such as reliability in terms of the number of rewrites and low voltage operation. In addition, ferroelectric elements are polarized by the electric field applied to the element, and this polarization However, if this residual polarization is small, the amount of charge can vary. The impact may become greater, and a highly accurate readout circuit may be required.

[0005] In view of the above problem, one aspect of the present invention is a novel nonvolatile latch circuit and An object of the present invention is to provide a semiconductor device. [Means for solving the problem]

[0006] In one aspect of the present invention, an output of a first element is electrically connected to an input of a second element, a latch section having a loop structure in which an output of the first element is electrically connected to an input of the second element; The data holding section holds data from the latch section. A volatile latch circuit is formed. The data holding section forms a channel forming region. A transistor using an oxide semiconductor as a semiconductor material is used as a switching element. is.

[0007] Also, a capacitance is electrically connected to the source electrode or the drain electrode of the transistor. The transistor is used to enable data held in the latch section by the data holding section. In addition, the above transistor can be used to effectively store data. The data written in the capacitor can be held. The data held in the capacitance of the data holding section can be read out to the latch section.

[0008] That is, one aspect of the present invention is a latch unit, a data holding unit that holds data of the latch unit, The data storage unit has a transistor and a capacitance. The hole formation region has an oxide semiconductor layer, and one of the source electrode and the drain electrode of the transistor is The other is electrically connected to one electrode of the capacitor and is connected to the source electrode and drain electrode of the transistor. The other pole is electrically connected to a latch section to form a non-volatile latch circuit. This is what we have in mind.

[0009] In the above, the latch section has a first element and a second element, and the output of the first element is a second element. The input of the second element is electrically connected to the input of the first element, and the output of the second element is electrically connected to the input of the first element. The input of the first element is connected to a wiring The output of the first element is electrically connected to a wiring to which an output signal is provided. For example, an inverter is used as the first element and a For example, a NAND may be used as the first element, and an inverter may be used as the second element. A clocked inverter can be used as element 2.

[0010] In the above, the other of the source electrode and the drain electrode of the transistor is connected to the first The transistor is electrically connected to the input of the element. The other end is electrically connected to a wiring to which an input signal is applied.

[0011] In the above, the transistor transfers the data held in the latch unit to the capacity of the data holding unit. The transistor also has the function of writing data to the capacitance of the data storage section. The transistor has the function of storing the data. It has a function of reading out the held data to the latch section.

[0012] Another aspect of the present invention is a data storage device having a latch section and a data storage section for storing data of the latch section. The data storage unit includes a first transistor, a second transistor, a first capacitor, and a second The channel formation regions of the first and second transistors are made of an oxide semiconductor. One of the source electrode and the drain electrode of the first transistor is connected to the first capacitor. a source electrode and a drain electrode of the first transistor electrically connected to one electrode of the second transistor; The other electrode of the second transistor is electrically connected to the latch section. One of the drain electrodes is electrically connected to one electrode of the second capacitor, and a second transistor The other of the source electrode and the drain electrode is electrically connected to the latch section. This constitutes a non-volatile latch circuit.

[0013] In the above, the latch section has a first element and a second element, and the output of the first element is a second element. The input of the second element is electrically connected to the input of the first element, and the output of the second element is electrically connected to the input of the first element. The input of the first element is connected to a wiring The output of the first element is electrically connected to a wiring to which an output signal is provided. For example, an inverter is used as the first element and a For example, a NAND may be used as the first element, and an inverter may be used as the second element. A clocked inverter can be used as element 2.

[0014] In the above, the other of the source electrode and the drain electrode of the first transistor is connected to the latch section. The first element is electrically connected to the source electrode of the first transistor and The other of the drain electrodes is electrically connected to a wiring to which an input signal is applied. The other of the source electrode and the drain electrode of the second transistor is connected to the first element of the latch section. The source electrode and the drain electrode of the second transistor are electrically connected to the output of the second transistor. The other electrode is electrically connected to a wiring to which an output signal is applied.

[0015] In the above, the first and second transistors transfer the data held in the latch unit to the data The first and second transistors have a function of writing data to the first and second capacitors of the data holding unit. The master has a function of retaining data written in the first and second capacitors of the data retaining unit. The first and second transistors are held by the first and second capacitors of the data holding section. The data stored in the latch section is read out to the latch section.

[0016] In the above, an oxide semiconductor layer formed of an oxide semiconductor material is provided in a channel formation region. The transistor used has a channel width W of, for example, 1×10 4 The channel length (L) is 3 μm. Even with a device with a size of 1 μm, the off-state current at room temperature is 1×10 -13 Below A, subthreshold A swing value (S value) of about 0.1V / dec. (gate insulating film thickness 100nm) was obtained. In addition, the above transistor is a normally-off transistor (in the case of an n-channel type, the threshold voltage The transistor characteristics are such that the voltage across the transistor becomes positive.

[0017] Therefore, the off-state current when the voltage between the gate and source electrodes is almost zero, that is, the leakage current The current is significantly smaller than that of silicon-based transistors. For example, the above W=1× 10 4 For a 1 μm transistor, the leakage current at room temperature is calculated per 1 μm of channel width. The current is 10 aA or less (hereinafter, in this specification, the unit channel width leakage current at room temperature is 10 a A / μm or less).

[0018] Therefore, a transistor using an oxide semiconductor layer in a channel formation region is used as a switching element. By using it as a latch circuit, the data retention part can be maintained even after the supply of power supply voltage to the latch circuit is stopped. The charge stored in the capacitor can be kept as it is. The written data can be retained as is.

[0019] For example, it is more efficient than DRAM with transistors that use silicon for the channel formation region. It is possible to achieve much longer recovery times and retention times than non-volatile memory. The memory retention (data retention) can be as high as that of the latch. After the supply of power to the circuit is resumed, the data is The data held in the data holding section can be read out to the latch section. The logic state prior to the interruption of the supply of power can be restored.

[0020] In addition, it is possible to obtain a device with sufficiently low off-current and sufficiently high on-current even at high temperatures. For example, the V G - I D The characteristics are temperature dependence of on-current, mobility, and S value in the range of -25℃ to 150℃. The data shows that the off-state current is less than 1×10 -13 The data obtained is extremely small, less than A. This is because, as an oxide semiconductor, The concentration is sufficiently reduced to be highly purified, and the carrier concentration is sufficiently low, i-type or substantially One possible reason for this is that the i-type is used.

[0021] In this specification, the carrier concentration is 1×10 11 / cm 3 The oxide semiconductor with " or "i-type", or more, but not more than 1×10 12 / cm 3"Substantially These are called "substantially type I" or "substantially type I".

[0022] In this way, one embodiment of the present invention has a wide temperature operating range and operates stably even at high temperatures. The present invention provides a nonvolatile latch circuit in which the stored logic state is not erased even if a voltage is applied.

[0023] In the above, various logic circuits can be provided by using a non-volatile latch circuit. In addition, various semiconductor devices using the above-described logic circuit can be provided. For example, among a plurality of block circuits included in a logic circuit, one or more unused blocks may be The supply of power supply voltage to the latch circuit can be stopped. This allows the logic state of the block circuit to be recorded even after the supply of power to the block circuit is stopped. In addition, after the supply of power to the block circuit is resumed, This allows the logic state stored in the memory to be read out without interrupting the supply of the power supply voltage. The previous logical state can be restored.

[0024] In the above, the oxide semiconductor layer is formed of a quaternary metal oxide, In-Sn-Ga-Zn -O system, ternary metal oxides such as In-Ga-Zn-O system and In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-A l-Zn-O system, binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al -Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O and other single-component metals It is formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. In addition, the above oxide semiconductor may contain SiO2.

[0025] In this specification, for example, an In-Sn-Ga-Zn-O-based oxide semiconductor is at least Both of these terms refer to oxide semiconductors containing In, Sn, Ga, and Zn, There is no restriction on the composition ratio, and metal elements other than In, Sn, Ga, and Zn may be included. good.

[0026] In addition, the oxide semiconductor layer is InMO3(ZnO) m Contains materials represented by (m>0) Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and In addition, Mn, Ga, Co, etc. can be applied.

[0027] In the above, the hydrogen concentration in the oxide semiconductor layer is 5×10 19 / cm 3 Below, preferably 5x 10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Less than or equal to 1x 10 16 / cm 3 In addition, the carrier concentration of the oxide semiconductor layer can be less than 1× 10 14 / cm 3 Less than 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Such an i-type or substantially i-type acid may be The off-state current of a transistor using a carbide semiconductor is 1×10 -17 A or less, preferably 1x 10 -18 It can be A.

[0028] In the above, the transistor including an oxide semiconductor may be a bottom-gate transistor. Alternatively, it may be a bottom contact type or a top gate type. A bottom gate transistor may be a contact type. A gate electrode, a gate insulating film on the gate electrode, and a gate insulating film overlapping the gate electrode and an oxide semiconductor layer which serves as a channel formation region.

[0029] A top-gate transistor is a transistor in which an oxide layer that forms a channel region on at least an insulating surface is formed. A semiconductor layer, a gate insulating film on the oxide semiconductor layer, and an oxide semiconductor on the gate insulating film. A bottom-contact transistor has a source electrode and a gate electrode overlapping the layer. The drain electrode is provided with an oxide semiconductor layer that serves as a channel formation region. The transistor has a source electrode and a drain electrode on an oxide semiconductor layer that serves as a channel formation region. It has poles.

[0030] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly under" the gate insulating layer. If the expression "gate electrode" is used, it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in cases where this is the case, it also includes those with the top and bottom reversed.

[0031] In addition, the terms "electrode" and "wiring" used in this specification do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the term "electrode" or "wire" may be used to refer to a plurality of "electrodes" or "wires". " is formed as an integral part.

[0032] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It is possible.

[0033] In this specification, "electrically connected" means "something that has some electrical effect." This includes cases where the device is connected via a wire. is not subject to any particular restriction as long as it enables transmission and reception of electrical signals between connected objects.

[0034] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistors, inductors, capacitors, and other various devices This includes elements having functions such as:

[0035] In general, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor layer of an "SOI substrate" is is not limited to silicon semiconductor layers.

[0036] In addition, the substrate in the "SOI substrate" is not limited to semiconductor substrates such as silicon wafers, but also glass. This also includes non-semiconductor substrates such as semiconductor substrates, quartz substrates, sapphire substrates, and metal substrates. The term "SOI substrate" broadly includes substrates that have a layer of semiconductor material on a solid or insulating substrate. Can be enjoyed.

[0037] Furthermore, in this specification, the term "semiconductor substrate" refers only to a substrate made of semiconductor material. In other words, in this specification, " "SOI substrates" are also broadly included in the "semiconductor substrates". Effect of the Invention

[0038] According to one embodiment of the present invention, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. The transistor used is used as a switching element for the data storage section, It has a wide operating range and operates stably even at high temperatures, and is non-volatile, so the stored logic state is not lost even when the power is turned off. A latch circuit that is self-refreshing or a latch circuit that has a data holding section with a sufficiently long refresh period. The circuit can be realized by switching the transistors to write data. Since the data is written in a single transistor, there is no limit to the number of times it can be rewritten. The threshold voltage is about the same as that of the data storage section, so it can operate at a low voltage. Since the accumulated charge is retained as data, the residual polarization component is used as data. Compared with the conventional method, the variation in the amount of charge stored as data can be suppressed to a small extent. The data can be easily read.

[0039] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, in a logic circuit using a non-volatile latch circuit, the power supply for an unused block is By turning off the power, power consumption can be reduced. Since the system remembers the state of the power supply, it can start up the system when the power is turned on and when the power is turned off. This allows the system to be shut down quickly and with low power consumption. [Brief description of the drawings]

[0040] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Diagram 2] FIG. 2 is a diagram showing an example of a partial configuration of a nonvolatile latch circuit. [Diagram 3] FIG. 13 is a diagram showing an example of a cross section of an element included in a nonvolatile latch circuit. [Figure 4] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Diagram 5] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 6] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 7] FIG. 1 illustrates an example of a cross-sectional structure of a transistor including an oxide semiconductor. [Figure 8] 8 is an energy band diagram (schematic diagram) taken along the line A-A' of FIG. 7. [Figure 9] (A) shows the state when a positive voltage (VG>0) is applied to the gate (GE1), and (B) shows the state when a negative voltage (VG<0) is applied to the gate (GE1). [Figure 10] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 11] FIG. 1 is a diagram showing the energy required for hot carrier injection in silicon (Si). [Figure 12] A diagram showing the energy required for hot carrier injection in an In-Ga-Zn-O oxide semiconductor (IGZO). [Figure 13] FIG. 1 is a diagram showing the energy required for hot carrier injection in silicon carbide (4H-SiC). [Figure 14] FIG. 13 is a diagram showing the results of a device simulation regarding a short channel effect. [Figure 15] FIG. 13 is a diagram showing the results of a device simulation regarding a short channel effect. [Figure 16] FIG. 13 is a diagram showing an example of a cross section of an element included in a nonvolatile latch circuit. [Figure 17] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 18] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 19] 1A and 1B are diagrams showing an example of the configuration and operation of a nonvolatile latch circuit; [Figure 20] FIG. 13 is a diagram showing an example of the operation of a nonvolatile latch circuit. [Figure 21] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 22] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Diagram 23] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 24] FIG. 13 is a diagram showing an example of the operation of a nonvolatile latch circuit. [Diagram 25] FIG. 13 is a diagram showing an example of the operation of a nonvolatile latch circuit. [Figure 26] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 27] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 28] 1A to 1C are diagrams illustrating an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 29] 1A to 1C are diagrams illustrating examples of electronic devices including a semiconductor device using a nonvolatile latch circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] The present invention will be described below with reference to the drawings. The present invention is not limited to the above description without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. In explaining the configuration of the present invention with reference to the drawings, the same reference numerals are used to indicate the same things. is commonly used among different drawings.

[0042] The size, layer thickness, or area of ​​each component shown in the drawings of each embodiment is In some cases, the figures are exaggerated for clarity. Therefore, the figures are not necessarily limited to the scale. Not determined.

[0043] In this specification, terms using ordinal numbers such as first, second, and third are used to identify components. These are added for convenience of distinction and are not intended to limit the number.

[0044] (Embodiment 1) This embodiment describes a configuration, an operation, and a nonvolatile latch circuit according to one embodiment of the present invention. The configuration and manufacturing method of the elements of the latch circuit are shown in FIG. The description will be made with reference to FIGS. 6 to 10, and 11 to 15.

[0045] <Configuration and operation of non-volatile latch circuit> FIG. 1 shows a latch unit 411 and a data holding unit 401 that holds data from the latch unit. 2 shows the configuration of a non-volatile latch circuit 400.

[0046] In the nonvolatile latch circuit 400 shown in FIG. 1, the output of the first element (D1) 412 is input to the second element (D2) 413. The output of the second element (D2) 413 is electrically connected to the input of the first element (D3) 413. A latch unit 411 having a loop structure electrically connected to an input of an element (D1) 412; It has a data holding unit 401 for holding data from the latch unit.

[0047] The input of the first element (D1) 412 is connected to a wiring 414 to which an input signal of the latch circuit is applied. The output of the first element (D1) 412 is electrically connected to the output of the latch circuit. The wiring 415 is electrically connected to the wiring 415.

[0048] If the first element (D1) 412 has multiple inputs, one of them is used as the input signal of the latch circuit. The second element (D2) 413 can be electrically connected to a wiring 414 to which a signal is applied. If there are multiple inputs, one of them is electrically connected to the output of the first element (D1) 412. It can continue.

[0049] The first element (D1) 412 uses an element that outputs an inverted version of the input signal. For example, the first element (D1) 412 may include an inverter, a NAND (NAND gate), ), NOR, clocked inverter, etc. can be used. (D2) 413 can be an element in which the inverted input signal is the output. For example, the second element (D2) 413 includes an inverter, a NAND, a NOR (NOR), a clocked inverter, etc. can be used.

[0050] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistor 402 is used as a switching element. The capacitor 404 is electrically connected to the source electrode or drain electrode of the transistor 02. That is, the electrode of the capacitor 404 is connected to one of the source electrode and drain electrode of the transistor 402. One of the source and drain electrodes of the transistor 402 is electrically connected to the The other is electrically connected to a wiring to which an input signal of the first element or an input signal of the latch circuit is given. The other electrode of the capacitor 404 is applied with a potential Vc.

[0051] The data storage unit 401 may have the structure shown in FIG. 2(A) and FIG. 2(B) instead of the structure shown in FIG. It can be said that it is completed.

[0052] In the data storage unit 401 shown in FIG. 2A, a transistor 402 is connected between a first gate electrode and a second gate electrode. The second gate electrode is made of an oxide semiconductor that constitutes a channel forming region. The first gate electrode is disposed on the opposite side of the first gate electrode with the conductor layer in between. The second gate electrode is electrically connected to a wiring to which a signal is applied. For example, the second gate electrode is electrically connected to a wiring having a negative potential or a It is electrically connected to a wiring that provides ground potential (GND).

[0053] The data storage portion 401 shown in FIG. 2A includes a source electrode and a drain electrode of a transistor 402. One of the electrodes of the capacitor 404 is electrically connected to one of the in-electrodes of the transistor 40. The other of the source electrode and drain electrode of the second transistor is connected to the input of the first element or the input signal of the latch circuit. The other electrode of the capacitor 404 is electrically connected to a wiring to which a potential Vc is applied. can be done.

[0054] In the nonvolatile latch circuit using the data holding unit 401 shown in FIG. 2A, In addition to the effects that the volatile latch circuit has, the electrical characteristics of transistor 402 (e.g., The effect of making it easier to adjust the threshold voltage (Vth) of the transistor 402 is as follows. By applying a negative potential to the second gate electrode of the transistor 402, the transistor 402 can be easily switched to a normally-on state. It can be said that it is f.

[0055] In the data storage unit 401 shown in FIG. 2B, a transistor 402 is connected between a first gate electrode and a second gate electrode. The second gate electrode is made of an oxide semiconductor that constitutes a channel forming region. The second gate electrode is disposed on the opposite side to the first gate electrode with the conductor layer interposed therebetween. The data storage unit 401 shown in FIG. One of the source and drain electrodes of the transistor 402 is connected to one of the electrodes of the capacitor 404. The other of the source electrode and the drain electrode of the transistor 402 is electrically connected to The input of the first element and the input signal of the latch circuit are electrically connected to a wiring to which the input signal is applied. A potential Vc is applied to the other electrode of the capacitor 404. In the nonvolatile latch circuit using the nonvolatile latch circuit shown in FIG. In addition, the amount of current through the transistor 402 is increased.

[0056] In the nonvolatile latch circuit having the configuration shown in FIG. 1 and FIG. 2, information is written as follows. The following description will be based on the configuration shown in FIG. 1, but other configurations may also be used. The same is true for the formation of

[0057] The transistor 402 using an oxide semiconductor is a transistor for storing data held in the latch portion 411. The data is written to the capacitor 404 of the data storage unit 401. The data storage unit 401 has a function of storing data written in the capacity 404 of the data storage unit 401. In addition, the transistor 402 is held in the capacitance 404 of the data holding unit 401. The latch unit 411 has a function of reading out the data stored in the latch unit 411.

[0058] The data held in the latch unit 411 is written to the data holding unit 401, held, and decoded. Data is read from the data holding unit 401 to the latch unit 411, and data is First, the gate electrode of the transistor 402 is connected to the transistor The transistor 402 is turned on by supplying a potential to the transistor 402. As a result, the data held in the latch unit, i.e., the first The potential of the input of the element (D1) 412 is applied to one electrode of the capacitor 404. One electrode of the capacitance 404 is connected to the input of the first element (D1) 412 held in the latch section. A charge according to the potential of the pixel is accumulated (write).

[0059] After that, the potential of the gate electrode of the transistor 402 is changed so that the transistor 402 is turned off. When the transistor 402 is turned off, one electrode of the capacitor 404 is The electric charge stored in the first element (D1) 412 is held (held). After the transistor 402 is set in a floating state, the gate electrode of the transistor 40 2 is turned on, and the transistor 402 is turned on. The charge is shared between one electrode of the capacitance 404 and the input of the first element (D1) 412. As a result, the potential of one electrode of the capacitor 404 is stored in the input of the first element (D1) 412. A potential corresponding to the charge is applied. The data is then held in the latch section. The data can be read (read). The data can be rewritten by This can be done similarly to inserting and retaining.

[0060] The oxide semiconductor layer of the transistor 402 is made of In-Sn-G a-Zn-O system, ternary metal oxides In-Ga-Zn-O system, In-Sn-Zn -O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, binary metal oxides such as In-Zn-O system and Sn-Zn-O Based on Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, etc. Using oxide semiconductors such as In-O, Sn-O, and Zn-O, which are elemental metal oxides, In addition, the above-mentioned oxide semiconductor may contain SiO2. stomach.

[0061] In addition, the oxide semiconductor layer is InMO3(ZnO) m Contains materials represented by (m>0) Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and In addition, Mn, Ga, Co, etc. can be applied.

[0062] The oxide semiconductor layer is highly purified by sufficiently removing impurities such as hydrogen and supplying oxygen. Specifically, secondary ion mass spectrometry (SIMS) is used. Oxide semiconductors measured by Ondary Ion Mass Spectroscopy The hydrogen concentration of the layer is 5×10 19 / cm3 Less than 5×10 18 / cm 3 More details below. Preferably 5 x 10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 Less than Make it so.

[0063] The carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 Less than 1×10 12 / cm 3 Less than 1×10 11 / cm 3 It can be less than. In the oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced and oxygen is supplied and the layer is highly purified, Ordinary silicon wafers (silicon wafers with trace amounts of impurity elements such as phosphorus and boron added) Carrier concentration (1×10 14 / cm 3 A sufficiently low carry compared to the degree The value of the concentration (e.g., 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Not yet (Full)

[0064] In this way, the hydrogen concentration is sufficiently reduced to achieve high purification, and the carrier concentration is sufficiently low, i By using an oxide semiconductor that is made into an n-type or substantially i-type, extremely excellent off-current characteristics can be obtained. For example, a transistor 402 having a channel width W of 1×10 4 In μm Even if the channel length L is 3 μm, the drain voltage V applied to the drain electrode D + When the gate voltage V is 1V or +10V, Gfrom -5V In the -20V range, the off-state current at room temperature is 1×10 -13 A or lower. Also, the above The transistor has normally-off transistor characteristics. Therefore, the gate and source The off-state current when the voltage between the electrodes is almost zero, that is, the leakage current, is For example, the leakage current per unit channel width at room temperature is 10 It will be less than aA / μm.

[0065] In addition, it is possible to obtain a device with sufficiently low off-current and sufficiently high on-current even at high temperatures. For example, the V of transistor 402 can be G -I D Characteristics range from -25℃ to 150℃ Data has been obtained showing that the on-current, mobility, and S value have little temperature dependence. In addition, the off-state current is 1×10 -13 Below A (below the measurement limit) This is because the hydrogen concentration in the oxide semiconductor is sufficiently reduced. The carrier concentration is sufficiently low, and the i-type or substantially i-type is obtained by subjecting the material to high purification. One factor is thought to be the use of

[0066] In this way, the hydrogen concentration is sufficiently reduced to achieve high purification, and the carrier concentration is sufficiently low, i A transistor 402 using a doped or substantially i-type oxide semiconductor is By using it as a decoupling element, the device can be decoupled even after the supply of power supply voltage to the latch circuit 400 is stopped. The charge stored in the capacitor 404 of the data storage unit 401 is held for an extremely long period of time. In other words, the data written in the data storage unit 401 can be stored for an extremely long time. You can continue to hold it.

[0067] For example, it is more efficient than DRAM with transistors that use silicon for the channel formation region. It is possible to achieve much longer recovery times and retention times than non-volatile memory. It is possible to have a memory retention (data retention) level equivalent to that of the By reading out the data stored in the storage unit 401, the logic state before the supply of the power supply voltage was stopped can be obtained. In this way, the hydrogen concentration is sufficiently reduced and the hydrogen is highly purified, A transistor using an oxide semiconductor that has a sufficiently low carrier concentration and is made i-type or substantially i-type. By using the transistor 402 as a switching element, the temperature operating range is wide and it can operate even at high temperatures. A novel non-volatile latch that is stable and retains its stored logic state even after power is turned off. The circuit can be realized.

[0068] <Configuration of elements in non-volatile latch circuit> Among the elements included in the nonvolatile latch circuit 400, the transistor 4 using an oxide semiconductor In the elements other than 02, a material other than an oxide semiconductor can be used as a semiconductor material. Materials other than nitride semiconductors include single crystal silicon and crystalline silicon. For example, elements other than the transistor 402 may be provided on a substrate including a semiconductor material. Substrates containing semiconductor materials include silicon wafers, SOI (Silicon on Insulator) The substrate may be a silicon film on an insulating surface. By using materials other than nitride semiconductors, high speed operation is possible. For example, the latch part is The first element (D1) 412 and the second element (D2) 413 are made of a material other than an oxide semiconductor. The transistor can be formed using a material other than the insulating film.

[0069] FIG. 3 is a cross-sectional view showing an example of the configuration of an element included in the nonvolatile latch circuit. 1A has a transistor 160 using a material other than an oxide semiconductor in the lower part and an oxide semiconductor in the upper part. The transistor 402 includes a transistor using a material other than an oxide semiconductor. The transistor 160 used is the first element (D1) 412 and the second element (D2) 413 of the latch section. (D2) 413 can be used as a transistor constituting the nonvolatile memory. Other elements in the switch circuit are configured in the same or similar manner as the transistor 160. It is possible.

[0070] In addition, elements such as the capacitor 404 included in the nonvolatile latch circuit are implemented by the transistor 402. Alternatively, the transistor 160 may be formed using a conductive film, a semiconductor film, an insulating film, or the like. The transistor 160 and the transistor 402 are both n-type Although the transistor is described as a p-type transistor, a p-type transistor may also be used. Transistor 16 3B shows a structure in which the transistor 402 and the This is an example of a case where the connection relationship with the electrodes (or wiring) is different from that shown in FIG. The configuration of FIG. 3(A) will be mainly described.

[0071] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 are provided so as to sandwich the channel forming region 116. A pure region 120 (collectively referred to as an impurity region) and a channel forming region 11 6, and a gate insulating layer 108a provided on the gate insulating layer 108a. The electrode 110a and the source or drain electrode 111 electrically connected to the impurity region 114 30a, and a source or drain electrode 130b (see FIG. 3(A)).

[0072] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, A high concentration impurity region 120 is provided, and a metal compound region 124 is provided in contact with the high concentration impurity region 120. In addition, an element isolation insulating layer 106 is formed on the substrate 100 so as to surround the transistor 160. , and an interlayer insulating layer 126 and an interlayer insulating A layer 128 is provided.

[0073] The source or drain electrode 130a and the source or drain electrode 130b are formed on a layer Through the openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128, the metal compound region 12 4. That is, the source electrode or drain electrode 130a, the source The drain electrode 130b is connected to the high concentration impurity region 110 via the metal compound region 124. 20 and the impurity region 114 .

[0074] The transistor 402 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d. An oxide semiconductor layer 140 and a second insulating film provided on the oxide semiconductor layer 140. A source electrode or drain electrode 142a, which is electrically connected to the source electrode or drain electrode 142b, and an inner electrode 142b (see FIG. 3(A)).

[0075] In addition, a protective film is provided over the transistor 402 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b.

[0076] At the same time as the formation of the electrodes 150d and 150e, the gate insulating layer 138 and the protective insulating layer 1 44, the electrodes 136a, 136b, and 136c are formed through the openings in the interlayer insulating layer 146. Electrodes 150a, 150b, and 150c are formed in contact with the electrodes 136a, 136b, and 136c. Although an example of a bottom-gate transistor is shown as the transistor 402, the present invention is not limited to this. A top-gate type transistor may also be used.

[0077] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, oxygen is supplied to the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is heated to 3000° C. It is desirable to use highly purified materials. Specifically, secondary ion mass spectrometry (SIM S: Secondary Ion Mass Spectroscopy The hydrogen concentration in the compound semiconductor layer 140 is 5×10 19 / cm 3 Less than 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 The value should be less than 100%.

[0078] Note that the oxide semiconductor layer 14 in which the hydrogen concentration is sufficiently reduced and oxygen is supplied and highly purified is In 0, a typical silicon wafer (a silicon wafer with trace amounts of impurity elements such as phosphorus and boron added) is used. Carrier concentration in silicon wafer (1×10 14 / cm 3 Compared to the degree Low carrier concentration values ​​(e.g., 1×10 12 / cm 3 Less than 1×10 11 / cm 3 (Less than)

[0079] In this way, by using an i-type or substantially i-type oxide semiconductor, extremely excellent A transistor 402 having the off-state current characteristic can be obtained. For example, when the drain voltage V D When the gate voltage V G ranges from -5V to -20V The off-state current at room temperature is 1×10 -13 A or less. Therefore, the voltage between the gate and source electrodes is almost The off-state current, or leakage current, in a silicon-based transistor is For example, the leakage current per unit channel width at room temperature is less than 10 aA / μm. become.

[0080] In addition, it is possible to obtain a device with sufficiently low off-current and sufficiently high on-current even at high temperatures. For example, the V of transistor 402 can be G -I D Characteristics range from -25℃ to 150℃ Data has been obtained showing that the on-current, mobility, and S value have little temperature dependence. In addition, the off-state current is 1×10 -13 A and extremely small data were obtained. This is because the hydrogen concentration is sufficiently reduced and the oxide semiconductor is highly purified. The carrier concentration is sufficiently low, and the carrier is either i-type or substantially i-type. This is thought to be one of the factors.

[0081] In this manner, the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified is used. By reducing the off-state current of the transistor 402, a semiconductor device with a new structure can be realized. It is possible.

[0082] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0083] That is, the source or drain electrode 142a of the transistor 402 is connected to the electrode 130c. , other elements (oxidation) through electrodes 136c, 150c, 154c, and 150d. (e.g., transistors using materials other than solid semiconductors) (Figure 3(A) In addition, the source or drain electrode 142b of the transistor 402 is 150e and the electrode 154d are electrically connected to other elements. electrodes (electrode 130c, electrode 136c, electrode 150c, electrode 154c, electrode 150d, etc.) The configuration is not limited to the above, and additions, omissions, etc. can be made as appropriate.

[0084] In FIG. 3B, the source or drain electrode 142a of the transistor 402 is This shows a case where the connection relationship is different from that in (A). Specifically, The electrode 142a is connected to the electrodes 130c, 136c, 150c, 154c, and 15 0d, the electrode 110b is electrically connected to the gate electrode 110c. The electrode 110b is formed in the same manner as the transistor structure. It may be a component or a part of wiring, etc. The configuration of the electrodes (electrodes 30c, 136c, 150c, 154c, 150d, etc.) is as described above. The above is not limited to the above, and additions, omissions, etc. are possible as appropriate.

[0085] In the above, two examples of typical connection relationships are shown, but one embodiment of the disclosed invention is not limited to these. For example, the configuration shown in FIG. 3(A) and the configuration shown in FIG. 3(B) may be combined. In addition, the gate electrode 110a of the transistor 160 and the gate electrode 110b of the transistor 402 may be The source electrode or drain electrode 142a may be electrically connected to the source electrode or drain electrode 142b.

[0086] <Method for manufacturing elements included in nonvolatile latch circuit> Next, an example of a method for manufacturing an element included in the nonvolatile latch circuit will be described. First, a method for manufacturing the transistor 160 will be described with reference to FIG. A method for manufacturing the transistor 402 will be described with reference to FIGS. By the manufacturing method, an element included in the nonvolatile latch circuit can be manufactured. 4 shows only a cross section corresponding to A1-A2 in FIG. 3(A). FIG. 6 shows cross sections corresponding to A1-A2 and B1-B2 in FIG.

[0087] <How to fabricate the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 4(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. An example will be given.

[0088] Generally, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is The layer is not limited to a silicon semiconductor layer. In addition, the SOI substrate may be formed on an insulating substrate such as a glass substrate. The term includes a configuration in which a semiconductor layer is provided on a substrate.

[0089] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 4(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of a material such as silicon oxynitride can be used. In order to control the threshold voltage of a transistor, an impurity that imparts n-type conductivity is added. The substrate 100 may be doped with an element or an impurity element that imparts p-type conductivity. In the case of a capacitor, impurities that give it n-type conductivity include, for example, phosphorus and arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. Umium, gallium, etc. can be used.

[0090] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor device is not attached (the exposed area) is removed. The conductive region 104 is formed (see FIG. 4(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0091] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing such as CMP and etching. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulation After the layer 106 is formed, the protective layer 102 is removed.

[0092] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0093] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. It is performed using a mixture of rare gases such as e, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. m or less.

[0094] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, polycrystalline silicon containing an impurity element that provides electrical conductivity can be used. Alternatively, a layer containing a conductive material may be formed using a semiconductor material such as silicon. Various deposition methods such as deposition, CVD, sputtering, and spin coating are used. In this embodiment, the layer containing a conductive material is formed using a metal material. An example of how this can be achieved is given below.

[0095] Thereafter, the insulating layer and the layer containing a conductive material are selectively etched to form a gate insulating layer 1 In step 08a, a gate electrode 110a is formed (see FIG. 4(C)).

[0096] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 4(C)). The semiconductor region 104 is doped with phosphorus (P) or arsenic (As) to form a shallow junction impurity. A region 114 is formed (see FIG. 4(C)). Note that an n-type transistor is formed here. To achieve this, phosphorus or arsenic is added, but to form a p-type transistor, boron (B) is added. An impurity element such as aluminum (Al) may be added.

[0097] By forming the impurity region 114, the semiconductor region 104 is doped with a material having a lower portion of the gate insulating layer 108a. In this case, a channel formation region 116 is formed (see FIG. 4C). The concentration of the fluorine atom can be appropriately set, but when the semiconductor element is highly miniaturized, It is desirable to increase the concentration. The step of forming the impurity region 114 is adopted, but after the impurity region 114 is formed, the insulating layer 11 This may also be a process for forming 2.

[0098] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The layer 118 is formed by forming an insulating layer so as to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, the film can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the impurity region It is advisable to expose the top surface of 114.

[0099] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus is added to the region where the insulating layer contacts the impurity region 114. By doping the silicon substrate with ions such as phosphorus (P) or arsenic (As), a high concentration impurity region 120 is formed. The insulating layer is removed, and the gate electrode 110a, the sidewall insulating layer 118, and the high concentration impurity region are removed. A metal layer 122 is formed so as to cover the region 120 and the like (see FIG. 4(E)).

[0100] The metal layer 122 can be formed by various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by using a method such as the method for forming the semiconductor region 104. It is preferable to form the insulating layer using a metal material that reacts with the material to form a low-resistance metal compound. Examples of such metal materials include titanium, tantalum, tungsten, nickel, and copper. Examples include zinc and platinum.

[0101] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of 0a that contacts the metal layer 122.

[0102] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0103] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using silicon oxide. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the substrate has a two-layer structure of an edge layer 126 and an interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is not subjected to a CMP or etching process. Therefore, it is desirable to flatten it.

[0104] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. A source electrode or drain electrode 130a and a source electrode or drain electrode 130b are provided on the The source electrode or drain electrode 130a and the source electrode or The drain electrode 130b is formed by, for example, depositing a layer on a region including an opening using a PVD method, a CVD method, or the like. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by removing

[0105] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface of the electrode is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. Removes unnecessary tungsten, titanium, titanium nitride, etc. and improves the flatness of the surface. In this way, the source electrode or drain electrode 130a, the source electrode Alternatively, the surface including the drain electrode 130b may be planarized to improve the quality of the resulting product in a later process. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0106] As the source or drain electrode 130a, the source or drain electrode 130b There is no particular limitation on the material that can be used, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, nickel, Conductive materials such as ZnO, ZnO, and ZnS can be used. A source or drain electrode 130a or a source or drain electrode 130b in contact with the compound region 124 Although only the rain electrode 130b is shown, in this process, the electrode 130c in FIG. etc. can be formed together.

[0107] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then the titanium film is removed by the CVD method. After forming a thin titanium nitride film by , a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is a metallized The oxide film that may form on the surface of the compound region is reduced, and the contact resistance with the metal compound region is reduced. In addition, the titanium nitride film formed after that has the function of suppressing the diffusion of the conductive material. After forming a barrier film using titanium or titanium nitride, The copper film may be formed by plating. A dual damascene process may also be applied.

[0108] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0109] <How to fabricate the upper transistor> Next, a process for forming a transistor 402 on the interlayer insulating layer 128 will be described with reference to FIGS. 5 and 6 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows a manufacturing process of the transistor 402, etc., The transistor 160 and other components that correspond to it are omitted.

[0110] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 5(A)). The source electrode or drain electrode 130a is connected to the insulating layer 132. An opening is formed that reaches the drain electrode 130b and the electrode 130c. A conductive layer 134 is formed so as to fill the opening (see FIG. 5B). A part of the conductive layer 134 is removed by a method such as grinding or CMP, and the insulating layer 132 is left. The exposed portion is used to form electrodes 136a, 136b, 136c, and a gate electrode 136d. (See FIG. 5(C)).

[0111] The insulating layer 132 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating film can be formed using a material containing an inorganic insulating material such as aluminum.

[0112] The openings in the insulating layer 132 can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching method, either wet etching or dry etching may be used. From the viewpoint of fine processing, it is preferable to use dry etching.

[0113] The conductive layer 134 can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer include molybdenum, titanium, chromium, and tantalum. Conductive materials such as tungsten, aluminum, copper, neodymium, and scandium, as well as Examples of such materials include alloys and compounds (for example, nitrides) (see FIG. 5(B)).

[0114] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is A bottom electrode (here, a source electrode or a drain electrode 130a, The oxide film that may be formed on the surface of the electrode 130b, electrode 130c, etc. is reduced, and the connection with the lower electrode is established. It has the function of reducing contact resistance.

[0115] In addition, the titanium nitride film formed afterwards has a barrier function that suppresses the diffusion of conductive materials. In addition, after forming a barrier film using titanium or titanium nitride, a copper plating method is used. The method is not limited to the so-called single damascene method, but may be a dual damascene method. etc. may also be applied.

[0116] After the conductive layer 134 is formed, the conductive layer 134 is etched or CMP is performed. 34 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 136c are then 36c and a gate electrode 136d can be formed (see FIG. 5(C)). A part of the electrode layer 134 is removed to form the electrodes 136a, 136b, 136c, and the gate electrode 1 When forming 36d, it is desirable to process it so that the surface is flat. , the insulating layer 132, the electrodes 136a, 136b, 136c, and the gate electrode 136d. By flattening the surface, it is possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. in the subsequent processes. It is possible to form the following:

[0117] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are The gate insulating layer 138 is formed so as to cover the gate insulating layer 138 (see FIG. 5(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, alumina oxide It is preferable that the oxide layer is formed so as to contain aluminum, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 138 may have either a single layer structure or a stacked layer structure.

[0118] For example, the plasma CVD method uses silane (SiH4), oxygen, and nitrogen as raw material gases. As a result, the gate insulating layer 138 made of silicon oxynitride can be formed. The thickness of the layer 138 is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. In the case of a laminated structure, for example, a first gate electrode having a thickness of 50 nm to 200 nm is formed. an insulating layer; and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer. It is preferable to use a laminate of the above.

[0119] If hydrogen or water is contained in the gate insulating layer 138, hydrogen may penetrate into the oxide semiconductor layer. In addition, oxygen in the oxide semiconductor layer is extracted by hydrogen, and the characteristics of the transistor are deteriorated. Therefore, the gate insulating layer 138 should contain as little hydrogen and water as possible. It is preferable to form it as follows.

[0120] For example, when using a sputtering method, the gate is deposited in a state where moisture is removed from the processing chamber. It is preferable to form a thin insulating layer 138. In addition, in order to remove moisture from the processing chamber, Adsorption type vacuum pumps such as cryopumps, ion pumps, and titanium sublimation pumps It is preferable to use a turbo pump with a cold trap. The processing chamber is evacuated using a cryopump or other device to ensure that hydrogen, water, etc. are sufficiently removed. Therefore, the concentration of impurities contained in the gate insulating layer 138 can be reduced.

[0121] In addition, when forming the gate insulating layer 138, impurities such as hydrogen and water are kept at a few ppm or less ( It is desirable to use a high purity gas with the purity reduced to a level of several ppb or less.

[0122] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities can be used. Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When using such an oxide semiconductor for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high quality There will be a demand for quality improvement.

[0123] For example, the high-density plasma CVD method using microwaves (frequency 2.45 GHz) produces dense, insulating This is advantageous in that a high-quality gate insulating layer 138 with high withstand voltage can be formed. The close contact between the oxide semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can improve the properties.

[0124] Of course, if a high-quality insulating layer can be formed as the gate insulating layer 138, high purification is possible. Even when a thin oxide semiconductor layer is used, the thin oxide semiconductor layer is formed by a sputtering method, a plasma CVD method, or the like. In addition, the film quality and oxide semiconductor can be changed by heat treatment after formation. Alternatively, an insulating layer may be applied that modifies the interface characteristics with the gate insulating layer. The quality of the film 138 is good, and the interface state density with the oxide semiconductor layer is reduced. It is sufficient to form a material that can form a good interface.

[0125] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 5(E)).

[0126] The oxide semiconductor layer may be a quaternary metal oxide such as In-Sn-Ga-Zn-O. , ternary metal oxides In-Ga-Zn-O, In-Sn-Zn-O, In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O system, binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al-Zn- O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, and single-component metal oxides It can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. Moreover, the above oxide semiconductor may contain SiO2.

[0127] In addition, the oxide semiconductor layer is InMO3(ZnO) m Contains materials represented by (m>0) Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and In addition, Mn, Ga, Co, etc. can be applied.

[0128] In this embodiment, an In-Ga-Zn-O metal oxide target is used as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using a fluorine-containing oxide semiconductor layer. In addition, by adding silicon to the amorphous oxide semiconductor layer, crystallization of the amorphous oxide semiconductor layer can be suppressed. Therefore, for example, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less can be used. An oxide semiconductor layer may be formed.

[0129] Examples of metal oxide targets for forming an oxide semiconductor layer by sputtering include For example, the composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. Metal oxide targets can be used. Other examples include In2O3:Ga2O3:Zn O = 1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO = 1:1:4 [molar ratio] A metal oxide target having a composition ratio of [mol ratio] may be used. The filling rate of the nozzle is 90% or more and 100% or less, preferably 95% or more (e.g., 99.9%). By using a metal oxide target with a high filling rate, a dense oxide semiconductor layer can be formed. is formed.

[0130] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a fluorine-containing gas atmosphere. Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. In general, impurities such as hydrogen, water, hydroxyl groups, and hydrides are less than a few ppm (preferably It is preferable to use a high-purity gas in which the concentration of contaminants has been reduced to a level of several ppb or less.

[0131] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while performing the above-mentioned step, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage caused by sputtering can be reduced. The moisture in the gas is removed while introducing a sputtering gas from which hydrogen and water have been removed, and the metal oxide is sputtered. An oxide semiconductor layer is formed as a target.

[0132] In order to remove moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. In addition, the exhaust means may be a turbo pump with a cold trap. In a deposition chamber evacuated using a cryopump, hydrogen atoms, water (H2 O) and other compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor layer formed in the deposition chamber can be reduced.

[0133] The formation conditions are, for example, a distance between the substrate and the target of 100 mm and a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%) The following conditions can be applied. If a pulsed direct current (DC) power source is used, the dust The thickness of the oxide semiconductor layer is preferably 2 nm or less. The thickness is set to 200 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the conductor material, so the thickness should be selected appropriately depending on the material used. good.

[0134] Note that before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. Then, a reverse sputtering process is performed to generate plasma, and the gold adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering. Instead of bombarding the sputter target with ions, the treatment surface is bombarded with ions. This refers to a method of modifying the surface by bombarding the treated surface with ions. In this method, a high-frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. It is also possible to use nitrogen, helium, oxygen, etc. instead of argon atmosphere. It's fine if you're there.

[0135] The etching of the oxide semiconductor layer can be performed by either dry etching or wet etching. Of course, both can be used in combination. In order to match the etching conditions (etching gas, etching solution, etc.) to the material, The etching time, temperature, etc. should be set appropriately.

[0136] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride In addition, gases containing fluorine (fluorine-based gases, for example, tetrafluoroethylene (CCl4)) Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (H e) or a gas containing an added rare gas such as argon (Ar), etc. may also be used.

[0137] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0138] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide) can be used. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0139] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. The temperature of the first heat treatment can be set to 300°C or higher and 800°C or lower, preferably 400°C or higher and 700°C or lower, more preferably 45 The temperature can be 0°C or higher and 700°C or lower, and more preferably 550°C or higher and 700°C or lower.

[0140] The temperature of the first heat treatment is set to 350° C. or higher, whereby the oxide semiconductor layer is dehydrated or dehydrated. In addition, the hydrogen concentration in the oxide semiconductor layer can be reduced by the first heat treatment. By setting the temperature to 450° C. or higher, the hydrogen concentration in the oxide semiconductor layer can be further reduced. In addition, by setting the temperature of the first heat treatment to 550° C. or higher, the oxide semiconductor layer For example, the hydrogen concentration in the electric furnace using a resistance heating element can be further reduced. The substrate is introduced, and the oxide semiconductor layer 140 is heated at 450° C. for 1 hour in a nitrogen atmosphere. During this treatment, the oxide semiconductor layer 140 is not exposed to the air and is not re-mixed with water or hydrogen. Prevent unauthorized access to the network.

[0141] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as a heated gas, or The apparatus may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. A suction device may be used.

[0142] LRTA devices are available with halogen lamps, metal halide lamps, xenon arc lamps, and car Light emitted from lamps such as Bonn arc lamps, high pressure sodium lamps, and high pressure mercury lamps ( The GRTA device heats the material to be treated by radiating high-temperature gas. The gas used for heat treatment is a rare gas such as argon or nitrogen. In the present embodiment, an inert gas that does not react with the object to be treated by the heat treatment is used.

[0143] For example, the first heat treatment is performed in an inert gas atmosphere heated to a high temperature of 650°C to 700°C. The substrate is placed in the GRTA, heated for a few minutes, and then removed from the inert gas atmosphere. The GRTA treatment allows high-temperature heat treatment in a short time. Since this is a short-term heat treatment, it can be applied even at temperatures that exceed the distortion point of the substrate. For example, when using an SOI substrate including a substrate with relatively low heat resistance such as a glass substrate, If the temperature exceeds the heat resistance temperature (strain point), shrinkage of the board becomes an issue, but if the heat treatment is performed for a short period of time, In this case this is not a problem.

[0144] The inert gas atmosphere for the first heat treatment may be nitrogen or a rare gas (helium, An atmosphere that is mainly composed of argon, neon, etc. and does not contain water, hydrogen, etc. For example, nitrogen, helium, or neon introduced into the heat treatment device may be used. The purity of the rare gas such as argon is 6N (99.9999%) or more, preferably 7N (99 .99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm (hereinafter)

[0145] During the treatment, the inert gas atmosphere may be replaced with an atmosphere containing oxygen. For example, When an electric furnace is used for the first heat treatment, the atmosphere can be switched when the temperature is lowered during the heat treatment. For example, the atmosphere during heat treatment (constant temperature) can be nitrogen or rare gas (helium, neodymium, etc.). The atmosphere is then switched to an inert gas such as benzene or argon, and when the temperature is lowered, the atmosphere is switched to an oxygen-containing atmosphere. The oxygen-containing atmosphere can be oxygen gas or a mixture of oxygen gas and nitrogen gas. When using an atmosphere containing oxygen, the atmosphere should not contain water, It is preferable that hydrogen and the like are not contained. Alternatively, the purity of the oxygen gas and nitrogen gas used is 6 N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. impure It is preferable to keep the concentration of oxygen-containing substances at 1 ppm or less, preferably 0.1 ppm or less. By performing the first heat treatment in an atmosphere containing oxygen, defects due to oxygen vacancies can be reduced. can.

[0146] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In some cases, the crystallinity is 90% or more, or 80% or less. % or more of the crystallinity of the oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be amorphous and not contain crystalline components. There are also cases where this is the case.

[0147] In addition, microcrystals (grain size of 1 nm or less) are formed in an amorphous oxide semiconductor (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer is a mixture of 20 nm or less (typically 2 nm or more and 4 nm or less). There are cases like this.

[0148] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in an amorphous material. For example, it is possible to use an In-Ga-Zn-O metal oxide target. When forming a ZnO semiconductor layer, the crystal grains of In2Ga2ZnO7, which have electrical anisotropy, are By forming a microcrystalline region in which the crystals are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. can be done.

[0149] For example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. The orientation improves the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer, and the oxide semiconductor In addition, the insulating properties in the direction perpendicular to the surface of the layer can be improved. The region has a function of preventing impurities such as water and hydrogen from entering the oxide semiconductor layer.

[0150] Note that the oxide semiconductor layer having the above-described microcrystalline region is an oxide semiconductor layer formed by GRTA treatment. The Zn content can be reduced by heating the surface of the Zn alloy. By using a sputtering target smaller than the amount of .

[0151] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0152] The heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Such dehydration and dehydrogenation treatments can also be called dehydration treatments, dehydrogenation treatments, etc. The process is performed by forming a source electrode or a drain electrode on the oxide semiconductor layer 140 after forming the oxide semiconductor layer. After laminating electrodes, forming a protective insulating layer on the source electrode or drain electrode, etc. In addition, such dehydration and dehydrogenation treatments can be carried out at the timing of The treatment may be carried out not only once but also multiple times.

[0153] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 5(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer so as to cover 40, the conductive layer is selectively etched. It can be formed.

[0154] The conductive layer is formed by PVD (Physical Vapor Deposition) methods, including sputtering. deposition method and CVD (Chemical Vapor Deposition) method, etc. The conductive layer can be formed by a deposition method. The materials used are aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. and alloys containing the above elements. , magnesium, zirconium, beryllium, yttrium Selected materials may be used. Aluminum may also be combined with titanium, tantalum, tungsten, etc. One or more elements selected from the group consisting of tin, molybdenum, chromium, neodymium, and scandium. A combination of materials may also be used.

[0155] The conductive layer may be formed using an oxide conductive film. Indium (In2O3), Tin oxide (SnO2), Zinc oxide (ZnO), Indium oxide Tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), indium oxide Zinc oxide alloy (In2O3-ZnO), or these metal oxide materials with silicon or Alternatively, a material containing silicon oxide can be used.

[0156] In this case, the material has a higher electrical conductivity or a higher resistivity than the material used for the oxide semiconductor layer 140. It is preferable to use a material having a low conductivity for the oxide conductive film. The carrier concentration of the oxide conductive film can be increased by increasing the hydrogen concentration. The carrier concentration of the oxide conductive film can be increased by increasing the oxygen vacancy. You can increase it by doing this.

[0157] The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing conductors, and a two-layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and a titanium film are laminated. In this case, a three-layer structure of a titanium film, an aluminum film, and another titanium film is applied.

[0158] Note that an oxide conductor layer may be formed between the oxide semiconductor layer 140 and the conductive layer. The compound conductor layer and the conductive layer can be formed successively (successive film formation). By providing an oxide conductive layer, the resistance of the source region or drain region can be reduced. This allows high-speed operation of the transistor.

[0159] Next, the conductive layer is selectively etched to form the source or drain electrode 142a, The source electrode or drain electrode 142b is formed (see FIG. 5(F)). For exposure during mask formation, ultraviolet light, KrF laser light, or ArF laser light is suitable. be.

[0160] The channel length (L) of the transistor is defined as the distance between the bottom end of the source or drain electrode 142a and the is determined by the distance between the lower end of the source electrode or drain electrode 142b. When performing exposure so that the channel length (L) is less than 25 nm, the channel length is set to a value of several nm to several tens of nm. and Extreme Ultraviolet with extremely short wavelengths. Exposure to extreme ultraviolet light provides high resolution and a large depth of focus. Design the channel length (L) of the transistor to be formed later to be less than 25 nm. In other words, it is possible to set the channel length (L) to 10 nm or more and 1000 nm or less. This allows the circuit to operate at a high speed. Furthermore, the off-state current is extremely small, so power consumption is This prevents power consumption from increasing.

[0161] In addition, when etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0162] In order to reduce the number of masks used and the number of processes, an exposure method in which the transmitted light has multiple intensities is used. A resist mask is formed using a multi-tone mask, which is a mask, and the etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. This can be further deformed by ashing, resulting in different shapes. It can be used in multiple etching processes to process into a pattern. The mask is used to form resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography can be performed with a reduced cost. The number of graphic processes can also be reduced, simplifying the process.

[0163] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Water and other adhering substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0164] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. Form 4 (see Figure 5(G)).

[0165] The protective insulating layer 144 is formed by, for example, sputtering, which is a method for removing impurities such as water and hydrogen from the protective insulating layer 144. The thickness of the film is at least 1 mm. The protective insulating layer 144 may be made of a material such as silicon oxide or the like. There are silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, the structure is simple. The protective insulating layer 144 may have a layer structure or a stacked structure. The temperature is preferably from room temperature to 300°C, and the atmosphere is a rare gas (typically argon). The atmosphere is a mixture of rare gas (typically argon) and oxygen. It is preferable to

[0166] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized by the hydrogen. As a result, oxygen in the oxide semiconductor layer is extracted, and the back channel side of the oxide semiconductor layer is The resistance of the protective insulating layer 14 may decrease, and a parasitic channel may be formed. It is important that 4 does not contain hydrogen as much as possible, and that hydrogen is not used in the formation method. be.

[0167] In addition, it is preferable to form the protective insulating layer 144 while removing moisture in the treatment chamber. The semiconductor layer 140 and the protective insulating layer 144 contain compounds containing hydrogen or hydroxyl groups or moisture. This is to prevent this from happening.

[0168] In order to remove moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means is a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may be filled with, for example, hydrogen atoms or water (H2O). Since compounds containing hydrogen atoms such as fluorine and fluorine have been removed, the protective insulating layer 1 formed in the film formation chamber is The concentration of impurities contained in 44 can be reduced.

[0169] The sputtering gas used in forming the protective insulating layer 144 contains hydrogen, water, and a hydroxyl group. Impurities such as compounds or hydrides are reduced to 1 ppm or less (preferably 1 ppb or less). It is preferred to use high purity purge gases.

[0170] Then, a second heat treatment (preferably for 20 It is preferable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce the variation in the electrical characteristics of the transistors.

[0171] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment may be performed by maintaining a constant heating temperature or by increasing the temperature from room temperature to 100°C or higher. Repeat heating to a temperature of 200°C or less and cooling from the heating temperature to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. By carrying out the heat treatment under pressure, the heating time can be shortened. This may be carried out in place of the second heat treatment, or may be carried out before or after the second heat treatment.

[0172] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 6(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as fluorine. After that, it is desirable to flatten the surface by a method such as CMP or etching. It is.

[0173] Next, an electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive material is embedded in the opening. A conductive layer 148 is formed (see FIG. 6B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. Thus, it is possible to form the

[0174] Either wet etching or dry etching may be used as the etching method. From the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 148 can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used include molybdenum, titanium, chromium, tantalum, and tungsten. Conductive materials such as zinc, aluminum, copper, neodymium, and scandium, as well as their alloys, Compounds (eg, nitrides) and the like.

[0175] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then the titanium film is removed by the CVD method. After forming a thin titanium nitride film by , a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method serves as an interlayer insulating film. The oxide film at the interface with the edge layer 146 is reduced, and the lower electrode (here, the electrode 136a, the electrode 136 b, electrode 136c, source or drain electrode 142a, source or drain electrode The contact resistance between the electrode 142b and the nitride film formed thereafter is reduced. The titanium film has a barrier function that suppresses the diffusion of conductive materials. Alternatively, after forming a barrier film made of copper or the like, a copper film may be formed by plating.

[0176] After the conductive layer 148 is formed, the conductive layer 148 is etched or CMPed. Electrodes 150a, 150b, and 150c are then removed to expose the interlayer insulating layer 146. 50c, an electrode 150d, and an electrode 150e are formed (see FIG. 6(C)). A part of 148 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming the pole 150e, it is desirable to process it so that the surface is flat. As shown in FIG. 1, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By planarizing the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent steps. It is possible to form an insulating layer, a semiconductor layer, etc.

[0177] Further, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the After forming the conductive layer as described above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a, etc. Therefore, I will omit the details.

[0178] In the case where the transistor 402 is manufactured by the above-described method, the hydrogen concentration in the oxide semiconductor layer 140 is Degree is 5 x 10 19 / cm 3 The off-state current of the transistor 402 at room temperature is Flow is 1×10 -13 The carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 In this way, the hydrogen concentration is sufficiently reduced, oxygen is supplied, and high purity By using the oxide semiconductor layer 140, a transistor 402 with excellent characteristics can be obtained. In addition, a transistor 160 using a material other than an oxide semiconductor can be provided in the lower portion. Since the transistor 402 using an oxide semiconductor is provided in the upper portion, the device has the characteristics of both. It is possible to manufacture a nonvolatile latch circuit having excellent characteristics and a semiconductor device using the same. do.

[0179] Note that in the case where oxygen is supplied to the oxide semiconductor layer 140 immediately after the hydrogen concentration is reduced, Since there is no risk of hydrogen or water being mixed into the oxide semiconductor layer, the oxide has extremely good characteristics. Of course, it is preferable to use an oxide having good characteristics in order to realize a semiconductor layer. If a semiconductor layer can be realized, the hydrogen concentration reduction process and the oxygen supply process should be performed continuously. For example, another process may be included between these processes. These processes may be carried out simultaneously.

[0180] In addition, examples of semiconductor materials that can be compared to oxide semiconductors include silicon carbide (e.g., Oxide semiconductors and 4H-SiC have several things in common. Carrier density is one example. According to the Fermi-Dirac distribution, Number carrier is 1×10 -7 / cm 3 This is estimated to be about the same as in 4H-SiC. 6.7×10 -11 / cm 3 This is an extremely low value, similar to that of the intrinsic carrier density of silicon. Degrees (1.4×10 10 / cm 3 Compared to the degree of I can understand it easily.

[0181] In addition, the energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. In this respect, oxide semiconductors and silicon carbide have in common.

[0182] On the other hand, there is a very big difference between oxide semiconductors and silicon carbide. , the process temperature. Semiconductor processes using silicon carbide are generally performed at 1500°C to 20 Since heat treatment at 00°C is required, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. At such high temperatures, the semiconductor substrate and semiconductor elements will be destroyed. On the other hand, oxide semiconductors can be grown at temperatures between 300 and 500°C (below the glass transition temperature, 7°C at most). It can be fabricated by heat treatment at temperatures of about 100°C, and integrated circuits can be fabricated using other semiconductor materials. After the formation, a semiconductor element can be formed using an oxide semiconductor.

[0183] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, it has the advantage of being possible to heat-treat the silicon carbide. This has the advantage that the energy cost can be significantly lowered compared to the conventional method.

[0184] In addition, in oxide semiconductors, physical properties such as DOS (density of state) Although many studies have been conducted, these studies have focused on the idea of ​​sufficiently reducing the localized levels themselves. In one embodiment of the disclosed invention, water or hydrogen, which may cause a localized level, is not included in an oxide semiconductor. By removing the ions from the body, a highly purified oxide semiconductor is produced. This is based on the idea of ​​reducing the amount of material used. This enables the production of industrial products.

[0185] In addition, oxygen is supplied to the dangling bonds of metals that are generated due to oxygen deficiency, and oxygen vacancies are formed. By reducing the localized levels, a more highly purified (i-type) oxide semiconductor can be obtained. For example, it is possible to form an oxide film containing an excess of oxygen in close proximity to the channel formation region. It is possible to supply oxygen from the oxide film and reduce localized levels due to oxygen defects. be.

[0186] Defects in oxide semiconductors are caused by excess hydrogen at shallow levels 0.1 to 0.2 eV below the conduction band, or by oxidation. These defects are believed to be caused by deep levels due to a lack of elements. The technical idea of ​​thoroughly removing hydrogen and providing a sufficient amount of oxygen is correct. It is possible.

[0187] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type can be achieved by removing water and hydrogen. Rather than creating an i-type by adding a pure substance, it can be said to involve a technological concept that has never been seen before.

[0188] In the above description, the elements included in the nonvolatile latch circuit 400 are made of an oxide semiconductor. The elements other than the transistor 402 are examples in which a material other than an oxide semiconductor is used as a semiconductor material. However, the disclosed invention is not limited to this. Among the elements included in the semiconductor device 100, elements other than the transistor 402 include an oxide semiconductor material. It is also possible to use a semiconductor material.

[0189] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the images reflect the actual situation. The following explanation is merely a consideration. It should be noted that this is merely a modification and does not affect the validity of the invention.

[0190] FIG. 7 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided thereon. An insulating layer is provided to cover the drain electrode (D).

[0191] FIG. 8 shows an energy band diagram (schematic diagram) in the A-A' cross section of FIG. The black circles (●) in 8 represent electrons, and the white circles (○) represent holes, each of which has a charge (-q, +q ) at the drain electrode. D >0), the dashed line shows the gate voltage When no voltage is applied to the pole (V G =0), the solid line indicates a positive voltage (V G >0) When no voltage is applied to the gate electrode, the high potential barrier causes This indicates the off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the on-state in which current flows is established. Indicates the attitude.

[0192] FIG. 9 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 9(A) shows a case where a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source and drain electrodes. FIG. 9B shows a case where a negative voltage (V G <0) is applied. 4 shows the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0193] Figure 10 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E F ) is a band The intrinsic Fermi level (E i ) and is located closer to the conduction band. In oxide semiconductors, some hydrogen becomes a donor, which is one of the factors that causes the semiconductor to become n-type. It is known.

[0194] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that is free from elements (impurity elements) other than the main components of the oxide semiconductor. It is made true (type i) or substantially true by purifying it so that it is not In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By removing the impurities, it is possible to obtain a highly purified i-type semiconductor (intrinsic semiconductor) or a semiconductor close to it. This allows the Fermi level (E F ) is the intrinsic Fermi level (E i ) It can be about that.

[0195] The band gap of oxide semiconductors (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 e V. The work function of titanium (Ti) that constitutes the source and drain electrodes is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, the metal-oxide semiconductor interface In this case, no Schottky barrier is formed for electrons.

[0196] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor layer as shown in FIG. The electrons move near the interface with the oxide semiconductor (the energetically most stable part of the oxide semiconductor).

[0197] Also, as shown in FIG. 9B, when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is essentially zero, the current is close to zero. do.

[0198] In this way, high purity oxide semiconductors are used to minimize the amount of elements (impurity elements) other than the main components of the oxide semiconductor. By optimizing the temperature, the device becomes intrinsic (i-type) or substantially intrinsic, so the boundary with the gate insulating layer is Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, it is necessary to have a device that can generate power frequencies from the VHF band to the microwave band. The insulating layer is made by the CVD method using high density plasma generated by the sputtering method. It is preferable to use an insulating layer manufactured by

[0199] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor is 1×10 4 μm, channel length When (L) is 3 μm, it is 1 × 10 -13 Off-state current less than A, 0.1V / dec. A threshold swing value (S value) of 100 nm (thickness of gate insulating layer) can be realized. do.

[0200] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0201] <Hot-carrier degradation resistance of transistors using oxide semiconductors> Next, the resistance to hot carrier degradation of a transistor including an oxide semiconductor will be described with reference to FIGS. The following description will be given with reference to FIG. 13. In the following description, an ideal situation is assumed for ease of understanding. The following explanations are based on the actual situation and may not reflect the actual situation. I would like to add that this is merely one consideration.

[0202] The main cause of hot carrier degradation is channel hot electron injection (CHE injection). and drain avalanche hot carrier injection (DAHC injection). For simplicity, only electrons are considered.

[0203] CHE injection is an injection into the semiconductor layer that has energy equal to or greater than the barrier of the gate insulating layer. This is the phenomenon in which the electrons that have become electrons are injected into the gate insulating layer, etc. This is achieved by accelerating electrons through a low electric field.

[0204] DAHC injection is a method in which new electrons generated by the collision of electrons accelerated by a high electric field are injected into the gate. The difference between DAHC injection and CHE injection is that the impact ions The question is whether avalanche breakdown occurs due to the breakdown of the semiconductor. To achieve this, electrons with kinetic energy greater than or equal to the band gap are required.

[0205] Figures 11 and 12 show the structure of silicon (Si) and In-Ga-Zn-O oxide semiconductor (I The energy required for various hot carrier injections estimated from the band structure of GZO is shown. In Figures 11 and 12, the left side represents CHE injection and the right side represents DAHC injection.

[0206] In silicon, the degradation caused by DAHC implantation is more severe than that caused by CHE implantation. In the electron, only a very small number of carriers (e.g., electrons) are accelerated without collisions. This is because silicon has a small band gap and is prone to avalanche breakdown. The electrons that can cross the barrier of the gate insulating layer by avalanche breakdown (i.e., the gate insulating layer) This causes a sudden increase in the number of electrons injected into the layer, which leads to degradation.

[0207] In the case of In-Ga-Zn-O oxide semiconductors, the energy required for CHE injection is silicon The probability is low, which is not very different from the case of The required energy is increased by the wider band gap than silicon, Avalanche breakdown itself is unlikely to occur. In other words, the probability of this happening is Both are low, and hot carrier degradation is less likely to occur than with silicon.

[0208] By the way, the band gap of In-Ga-Zn-O oxide semiconductors is This is about the same as that of silicon carbide (SiC), which is attracting attention. The energy required for various hot carrier injections is shown below. For CHE injection, In-Ga -Zn-O-based oxide semiconductors have a slightly higher threshold and are therefore advantageous.

[0209] As mentioned above, the In-Ga-Zn-O oxide semiconductor has a higher hot carrier degradation rate than silicon. It can be seen that the resistance to carbonization and source-drain breakdown is very high. It can be said that the breakdown voltage is comparable to that of silicon.

[0210] <Short-channel effect in transistors using oxide semiconductors> Next, regarding the short-channel effect in a transistor including an oxide semiconductor, FIG. 14 and FIG. In the following explanation, an ideal situation is assumed for ease of understanding. The following explanations are based on the actual situation and may not reflect the actual situation. I would like to add that this is merely one consideration.

[0211] The short channel effect becomes evident as transistors become smaller (as the channel length (L)) The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and S value. Increase in leakage current, etc.

[0212] Here, a structure capable of suppressing the short channel effect is developed using device simulation. Specifically, the carrier concentration and the thickness of the oxide semiconductor layer were varied. We prepared four types of models and confirmed the relationship between channel length (L) and threshold voltage (Vth). A bottom-gate transistor was used as the model, and the oxide semiconductor capacitance was Rear density 1.7×10 -8 / cm 3 , or 1.0 × 10 15 / cm 3 Either The thickness of the oxide semiconductor layer was set to either 1 μm or 30 nm. The substrate is an In-Ga-Zn-O oxide semiconductor, and the gate insulating layer is a 100 nm thick silicon nitride film. The band gap of the oxide semiconductor is 3.15 eV, and the electric field is The electron affinity is 4.3 eV, the relative dielectric constant is 15, and the electron mobility is 10 cm 2 / Vs. Acid The relative dielectric constant of the silicon nitride film was assumed to be 4.0. The simulation software "Atlas" was used.

[0213] There is no significant difference in the calculation results between the top gate structure and the bottom gate structure. The results are shown in Figures 14 and 15. Figure 14 shows the results for a carrier concentration of 1.7 × 10 -8 / cm 3 of In the case of a carrier concentration of 1.0×10 15 / cm 3 This is the case in Fig. 14 and In FIG. 15, a transistor with a channel length (L) of 10 μm is used as a reference. The change in threshold voltage (Vth) when the thickness is changed from 10 μm to 1 μm (ΔVth As shown in Fig. 14, the carrier concentration of the oxide semiconductor is 1.7 × 10 -8 / cm 3 When the thickness of the oxide semiconductor layer is 1 μm, the change in threshold voltage (ΔV th) was −3.6 V. As shown in FIG. 14, the carrier concentration of the oxide semiconductor is 1.7 × 10 -8 / cm 3 When the thickness of the oxide semiconductor layer is 30 nm, the threshold The change in the threshold voltage (ΔVth) was −0.2 V. As shown in FIG. The carrier concentration of the semiconductor is 1.0×10 15 / cm 3 The thickness of the oxide semiconductor layer is 1 μm. In the case of m, the change in threshold voltage (ΔVth) was -3.6 V. As shown in the figure, the carrier concentration of the oxide semiconductor is 1.0×10 15 / cm 3 and the oxide semiconductor When the thickness of the conductor layer is 30 nm, the change in threshold voltage (ΔVth) is -0.2 V. The results show that the thickness of the oxide semiconductor layer in a transistor using an oxide semiconductor This shows that the short channel effect can be suppressed by making the channel thinner. When the channel length (L) is about 1 μm, even in an oxide semiconductor layer with a sufficiently high carrier concentration, If the thickness is set to about 30 nm, the short channel effect can be sufficiently suppressed. is understood.

[0214] The oxide semiconductor according to this embodiment is used as a semiconductor material for forming a channel formation region. The transistor is used in a non-volatile latch circuit as a switching element for a data holding portion. This allows the device to operate stably even at high temperatures, and the stored logic state is maintained even when the power is turned off. A non-volatile latch circuit that does not lose its state or a data holding section with a sufficiently long refresh period It is possible to realize a latch circuit having a built-in latch circuit.

[0215] Data is written by switching transistors, so rewriting is essentially There is no limit to the number of times the data can be written. In addition, the write voltage is approximately the threshold voltage of a transistor, so it is low. In addition, since the potential of the data storage section is directly applied, This allows the variation in the amount of charge held to be kept small, and data can be easily read out. It is possible to do so.

[0216] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0217] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0218] (Embodiment 2) This embodiment describes a structure of an element included in a nonvolatile latch circuit which is one embodiment of the disclosed invention. The structure and manufacturing method thereof will be described with reference to FIGS. 16, 17, and 18. In this embodiment, the configuration of the nonvolatile latch circuit is the same as that in FIG.

[0219] 16 is a cross-sectional view showing an example of the configuration of an element included in a nonvolatile latch circuit. Among the elements included in the nonvolatile latch circuit, the upper transistor using an oxide semiconductor 16 is an example in which the configuration of the upper oxide semiconductor layer 402 is different from that shown in FIG. One example of a case where the transistor 402 using a conductor is a top-gate type transistor. The rest of the configuration (such as the configuration of the lower transistor) is the same as in Figure 3.

[0220] <Configuration of elements in non-volatile latch circuit> FIG. 16 shows a transistor 160 using a material other than an oxide semiconductor in the lower part and an oxide The transistor 402 includes a transistor using a material other than an oxide semiconductor. The transistor 160 used is the first element (D1) 412 and the second element (D2) 413 of the latch section. (D2) 413 can be used as a transistor constituting the transistor. By using the material, high speed operation is possible. The other elements may be configured in the same or similar manner as the transistor 160 .

[0221] In addition, elements such as the capacitor 404 included in the nonvolatile latch circuit are implemented by the transistor 402. Alternatively, the conductive film, the semiconductor film, the insulating film, or the like that constitutes the transistor 160 may be used. It should be noted that the transistor 160 and the transistor 402 are both n-type transistors. Although the transistor 160 will be described as a p-type transistor, a p-type transistor may also be used. It is easy to make it p-type.

[0222] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 are provided so as to sandwich the channel forming region 116. A pure region 120 (collectively referred to as an impurity region) and a channel forming region 11 6, and a gate insulating layer 108a provided on the gate insulating layer 108a. The electrode 110a and the source or drain electrode 111 electrically connected to the impurity region 114 30a, and a source or drain electrode 130b.

[0223] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, A high concentration impurity region 120 is provided, and a metal compound region 124 is provided in contact with the high concentration impurity region 120. In addition, an element isolation insulating layer 106 is formed on the substrate 100 so as to surround the transistor 160. , and an interlayer insulating layer 126 and an interlayer insulating A layer 128 is provided.

[0224] The source or drain electrode 130a and the source or drain electrode 130b are formed on a layer Through the openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128, the metal compound region 12 4. That is, the source electrode or drain electrode 130a, the source The drain electrode 130b is connected to the high concentration impurity region 110 via the metal compound region 124. 20 and the impurity region 114 .

[0225] The transistor 402 includes an oxide semiconductor layer 140 provided over an insulating layer 168 and an oxide semiconductor layer 142. A source electrode provided on the conductor layer 140 and electrically connected to the oxide semiconductor layer 140. Alternatively, the drain electrode 142a, the source electrode or drain electrode 142b, and an oxide semiconductor layer 140, a source or drain electrode 142a, and a source or drain electrode A gate insulating layer 166 is provided to cover the electrode 142b. and a gate electrode 178 provided in a region overlapping the nitride semiconductor layer 140 (FIG. 16). reference).

[0226] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, oxygen is supplied to the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is heated to 3000° C. It is desirable to use highly purified materials. Specifically, secondary ion mass spectrometry (SIM S: Secondary Ion Mass Spectroscopy The hydrogen concentration in the compound semiconductor layer 140 is 5×10 19 / cm 3 Less than 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 The value should be less than 100%.

[0227] Note that the oxide semiconductor layer 14 in which the hydrogen concentration is sufficiently reduced and oxygen is supplied and highly purified is In 0, a typical silicon wafer (a silicon wafer with trace amounts of impurity elements such as phosphorus and boron added) is used. Carrier concentration in silicon wafer (1×10 14 / cm 3 Compared to the degree Small carrier concentration values ​​(e.g., 1×10 12 / cm 3 Less than 1×10 1 1 / cm 3 (Less than)

[0228] In this way, by using an i-type or substantially i-type oxide semiconductor, extremely excellent A transistor 402 having the off-state current characteristic can be obtained. For example, when the drain voltage V D When the gate voltage V G ranges from -5V to -20V The off-state current at room temperature is 1×10 -13 A or less. Therefore, the voltage between the gate and source electrodes is almost The off-state current, or leakage current, in a silicon-based transistor is For example, the leakage current per unit channel width at room temperature is less than 10 aA / μm. become.

[0229] In addition, it is possible to obtain a device with sufficiently low off-current and sufficiently high on-current even at high temperatures. For example, the V of transistor 402 can be G -I D Characteristics range from -25℃ to 150℃ Data has been obtained showing that the on-current, mobility, and S value have little temperature dependence. In addition, the off-state current is 1×10-13 The data is extremely small, below A. This is because the hydrogen concentration is sufficiently reduced and the oxide semiconductor is highly purified. The carrier concentration is sufficiently low, and the material is i-type or substantially i-type. This is thought to be one of the factors.

[0230] In this manner, the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified is used. By reducing the off-state current of the transistor 402, a semiconductor device with a new structure can be realized. It is possible.

[0231] In addition, an interlayer insulating layer 170 and an interlayer insulating layer 172 are provided on the transistor 402. Here, the gate insulating layer 166, the interlayer insulating layer 170, and the interlayer insulating layer 172 are , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, Through the openings, electrodes 154d and 154e are The source electrode or drain electrode 142a and the source electrode or drain electrode 142 b. Similarly to the electrodes 154d and 154e, the gate insulating layer Electrode 1 is inserted through openings provided in interlayer insulating layer 166, interlayer insulating layer 170, and interlayer insulating layer 172. Electrodes 154a, 154b, and 154c are in contact with electrodes 136a, 136b, and 136c. c is formed.

[0232] Moreover, an insulating layer 156 is provided on the interlayer insulating layer 172, and a buried insulating film is formed in the insulating layer 156. Electrodes 158a, 158b, 158c, and 158d are provided so that the electrodes 158a, 158b, 158c, and 158d are inserted into the Here, electrode 158a is in contact with electrode 154a, and electrode 158b is in contact with electrode 154. b, electrode 158c is in contact with electrode 154c and electrode 154d, and electrode 1 58d is in contact with electrode 154e.

[0233] That is, the source or drain electrode 142a of the transistor 402 is connected to the electrode 130c. , other elements (oxidation) through the electrodes 136c, 154c, 158c, and 154d. (e.g., transistors using materials other than solid semiconductors) (see Figure 16) In addition, the source or drain electrode 142b of the transistor 402 is connected to the electrode 15 4e and the electrode 158d are electrically connected to other elements. Structure of electrodes (electrode 130c, electrode 136c, electrode 154c, electrode 158c, electrode 154d, etc.) The configuration is not limited to the above, and additions, omissions, etc. are possible as appropriate.

[0234] <Method for manufacturing elements included in nonvolatile latch circuit> Next, an example of a method for manufacturing an element included in the nonvolatile latch circuit will be described. The elements included in the nonvolatile latch circuit can be manufactured by the manufacturing method shown in The method for manufacturing the transistor 160 is the same as that shown in FIG. A method for manufacturing the transistor 402 will be described with reference to FIGS.

[0235] <How to fabricate the upper transistor> Next, a transistor 402 is formed on the interlayer insulating layer 128 using FIG. 17 or FIG. 17 and 18 show the steps of forming various electrodes on the interlayer insulating layer 128. 4 shows a manufacturing process of the transistor 402, etc. The transistor 160 and other components present in the circuit are omitted.

[0236] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c. On the other hand, the source electrode or drain electrode 130a, the source electrode or drain electrode 130 b and an opening reaching the electrode 130c is formed. Then, the conductive layer is formed by etching or CMP. A part of the layer is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 13 Form 6c (see FIG. 17(A)).

[0237] The insulating layer 132 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating film can be formed using a material containing an inorganic insulating material such as aluminum.

[0238] The openings in the insulating layer 132 can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching method, either wet etching or dry etching may be used. From the viewpoint of fine processing, it is preferable to use dry etching.

[0239] The conductive layer can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used for formation include molybdenum, titanium, chromium, tantalum, and titanium. Conductive materials such as tin, aluminum, copper, neodymium, scandium, and their alloys Examples include gold, compounds (eg, nitrides), and the like.

[0240] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is A bottom electrode (here, a source electrode or a drain electrode 130a, The oxide film that may be formed on the surface of the electrode 130b, electrode 130c, etc. is reduced, and the connection with the lower electrode is established. It has the function of reducing contact resistance.

[0241] In addition, the titanium nitride film formed afterwards has a barrier function that suppresses the diffusion of conductive materials. In addition, after forming a barrier film using titanium or titanium nitride, a copper plating method is used. The method is not limited to the so-called single damascene method, but may be a dual damascene method. etc. may also be applied.

[0242] When the electrodes 136a, 136b, and 136c are formed, CMP or the like is used. In this way, it is desirable to process the insulating layer 132 and the electrode 1 so that the surface is flat. 36a, the electrodes 136b, and the electrodes 136c are planarized, so that the surfaces of the electrodes 136a, 136b, and 136c are planarized in the subsequent process. This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0243] Next, an insulating layer 132 is formed so as to cover the insulating layer 132, the electrodes 136a, 136b, and 136c. Then, an oxide semiconductor layer is formed over the insulating layer 168, and The oxide semiconductor layer is processed by a method such as etching to form an island-shaped oxide semiconductor layer 1 40 is formed (see FIG. 17(B)).

[0244] The insulating layer 168 functions as a base and is formed by using a CVD method, a sputtering method, or the like. The insulating layer 168 can be formed of silicon oxide, silicon nitride, or oxynitride. Silicon, silicon oxide nitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. The insulating layer 168 may have a single layer structure or The thickness of the insulating layer 168 is not particularly limited, but may be, for example, 10 nm or less. The thickness of the insulating layer 168 is not necessarily limited to 500 nm. Therefore, it is possible to adopt a configuration in which the insulating layer 168 is not provided.

[0245] If hydrogen, water, or the like is contained in the insulating layer 168, hydrogen may enter the oxide semiconductor layer, and water may be released from the insulating layer 168. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, which deteriorates the characteristics of the transistor. Therefore, the insulating layer 168 is formed so as to contain as little hydrogen and water as possible. It is desirable.

[0246] For example, when using a sputtering method, the moisture in the processing chamber must be removed before the insulating layer is formed. It is desirable to form a layer 168. In addition, in order to remove moisture from within the processing chamber, Adsorption type vacuum pumps such as ion pumps, titanium sublimation pumps, etc. It is preferable to use a turbo pump with a cold trap. The processing chamber was evacuated using a cryopump, etc., and hydrogen and water were sufficiently removed. Therefore, the concentration of impurities contained in the insulating layer 168 can be reduced.

[0247] In addition, when forming the insulating layer 168, impurities such as hydrogen and water are preferably kept at a level of several ppm or less. It is desirable to use a high purity gas with a purity reduced to 10 ppb or less.

[0248] The oxide semiconductor layer may be a quaternary metal oxide such as In-Sn-Ga-Zn-O. , ternary metal oxides In-Ga-Zn-O, In-Sn-Zn-O, In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O system, binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al-Zn- O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, and single-component metal oxides It can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. Moreover, the above oxide semiconductor may contain SiO2.

[0249] In addition, the oxide semiconductor layer is InMO3(ZnO) m Contains materials represented by (m>0) Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and In addition, Mn, Ga, Co, etc. can be applied.

[0250] In this embodiment, an In-Ga-Zn-O metal oxide target is used as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using a fluorine-containing oxide semiconductor layer. In addition, by adding silicon to the amorphous oxide semiconductor layer, crystallization of the amorphous oxide semiconductor layer can be suppressed. Therefore, for example, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less can be used. An oxide semiconductor layer may be formed.

[0251] As a metal oxide target for forming an oxide semiconductor layer by sputtering, I Metal oxide with a composition ratio of n2O3:Ga2O3:ZnO=1:1:1 [molar ratio] A target of In2O3:Ga2O3:ZnO=1:1 can be used. :2 [molar ratio], or In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] A metal oxide target having a composition ratio may be used. The filling rate is 90% or more and 100% or less, preferably 95% or more (e.g., 99.9%). By using a metal oxide target with a high conversion rate, a dense oxide semiconductor layer is formed. .

[0252] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a fluorine-containing gas atmosphere. Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. In general, impurities such as hydrogen, water, hydroxyl groups, and hydrides should be less than 1 ppm (preferably It is preferable to use a high-purity gas atmosphere in which the concentration of ions is reduced to below 1 ppb.

[0253] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is then increased to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. While removing moisture from within the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced to form a metal oxide. The oxide semiconductor layer is formed by heating the substrate. By forming the oxide semiconductor layer, the concentration of impurities contained in the oxide semiconductor layer can be reduced. This reduces damage to the oxide semiconductor layer caused by sputtering.

[0254] In order to remove moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Alternatively, a turbo pump with a cold trap may be used. In the processing chamber, which is evacuated using a pump, hydrogen and water are removed, and the oxide semiconductor The impurity concentration in the layer can be reduced.

[0255] The oxide semiconductor layer was formed under the following conditions: the distance between the substrate and the target was 100 mm, m, pressure 0.6 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen flow rate 1 00% atmosphere. The use of the oxide semiconductor layer is preferable because it can reduce dust and reduce the film thickness distribution. The thickness is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the oxide semiconductor material and the application of the semiconductor device. The thickness may be selected depending on the material used and the application.

[0256] Note that before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. The deposition on the surface of the insulating layer 168 is removed by reverse sputtering, which generates plasma using the Here, the reverse sputtering is a method of sputtering a sputter target in a normal sputtering process. By bombarding the surface with ions, the surface is deformed by bombarding the surface with ions. The method of modifying the surface by bombarding the surface with ions is called argon bombardment. A method of applying a high-frequency voltage to the processing surface in an atmosphere to generate plasma near the substrate. In addition, an atmosphere of nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. This is also fine.

[0257] Either dry etching or wet etching can be used for etching the oxide semiconductor layer. Of course, both of them can be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. are set appropriately.

[0258] As dry etching, parallel plate type RIE (Reactive Ion Etch) ng) method and ICP (Inductively Coupled Plasma) In this case, the etching conditions are (The amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode Temperature, etc. must be set appropriately.

[0259] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. In addition, gases that contain fluorine (fluorine-based gases For example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoride (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), A gas containing a rare gas such as helium (He) or argon (Ar) may also be used. .

[0260] The etching solution that can be used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Examples include ammonia, water, and hydrogen peroxide. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0261] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. This makes it possible to remove water (including a hydroxyl group), hydrogen, and the like from the oxide semiconductor layer. The temperature of the heat treatment is 300°C or more and 800°C or less, preferably 400°C or more and 700°C or less, more preferably 400°C or more and 700°C or less. More preferably, the temperature is 450° C. or higher and 700° C. or lower, and even more preferably, the temperature is 550° C. or higher and 700° C. or lower. It is possible.

[0262] The temperature of the first heat treatment is set to 350° C. or higher, whereby the oxide semiconductor layer is dehydrated or dehydrated. In addition, the hydrogen concentration in the oxide semiconductor layer can be reduced by the first heat treatment. By setting the temperature to 450° C. or higher, the hydrogen concentration in the oxide semiconductor layer can be further reduced. In addition, by setting the temperature of the first heat treatment to 550° C. or higher, the oxide semiconductor layer For example, the hydrogen concentration in the electric furnace using a resistance heating element can be further reduced. The substrate is introduced, and the oxide semiconductor layer 140 is heated at 450° C. for 1 hour in a nitrogen atmosphere. During this process, the oxide semiconductor layer 140 is not exposed to the air and is not mixed with water or hydrogen. Prevent it from being leaked.

[0263] The heat treatment device is not limited to an electric furnace, and may be heat conducted from a medium such as a heated gas or heat radiation. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) device can be used.

[0264] LRTA devices are available with halogen lamps, metal halide lamps, xenon arc lamps, and car Light emitted from lamps such as Bonn arc lamps, high pressure sodium lamps, and high pressure mercury lamps ( The GRTA device heats the material to be treated by radiating high-temperature gas. The gas used for heat treatment is a rare gas such as argon or nitrogen. In the present embodiment, an inert gas that does not react with the object to be treated by the heat treatment is used.

[0265] For example, the first heat treatment is performed in an inert gas atmosphere heated to a high temperature of 650°C to 700°C. GRTA process in which the substrate is placed in the chamber, heated for a few minutes, and then removed from the inert gas atmosphere. GRTA treatment allows high-temperature heat treatment in a short time. Because this is a long-term heat treatment, it can be applied even under temperature conditions that exceed the heat resistance of the substrate. For example, when using an SOI substrate that includes a substrate with relatively low heat resistance, such as a glass substrate, If the temperature exceeds the thermal temperature (strain point), shrinkage of the substrate becomes an issue, but if the heat treatment is performed for a short period of time, In this case this is not a problem.

[0266] The inert gas atmosphere for the first heat treatment may be nitrogen or a rare gas (helium, An atmosphere that is mainly composed of argon, neon, etc. and does not contain water, hydrogen, etc. For example, nitrogen, helium, neon, and argon are introduced into the heat treatment equipment. The purity of rare gas such as argon is 6N (99.9999%) or more, preferably 7N (99.9 9999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) )

[0267] During the treatment, the inert gas atmosphere may be replaced with an atmosphere containing oxygen. For example, When an electric furnace is used for the first heat treatment, the atmosphere can be switched when the temperature is lowered during the heat treatment. For example, the atmosphere during heat treatment (constant temperature) can be nitrogen or rare gas (helium, neodymium, etc.). The atmosphere is then switched to an inert gas such as benzene or argon, and when the temperature is lowered, the atmosphere is switched to an oxygen-containing atmosphere. The oxygen-containing atmosphere can be oxygen gas or a mixture of oxygen gas and nitrogen gas. The gas may be any suitable gas.

[0268] Even when using an atmosphere containing oxygen, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas and nitrogen gas used should be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., 1 ppm or less, The first heat treatment is preferably performed in an atmosphere containing oxygen. By carrying out the above steps, defects caused by oxygen vacancies can be reduced.

[0269] Depending on the conditions of the first heat treatment or the material constituting the oxide semiconductor layer, the oxide semiconductor layer In some cases, the crystallization rate is 90% or more, and the crystals may become microcrystalline or polycrystalline. In some cases, the oxide semiconductor layer is microcrystalline or has a crystallinity of 80% or more. Alternatively, depending on the material constituting the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide that does not contain a crystalline component. In some cases, it may be a semiconductor layer.

[0270] In addition, microcrystals (grain size of 1 nm or less) are formed in an amorphous oxide semiconductor (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer is a mixture of 20 nm or less (typically 2 nm or more and 4 nm or less). In this way, by mixing and arranging microcrystals in an amorphous material, oxide semiconductors can be obtained. It is also possible to vary the electrical properties of the layer.

[0271] For example, an oxide semiconductor layer is formed using an In-Ga-Zn-O metal oxide target. In this case, the crystal grains of electrically anisotropic In2Ga2ZnO7 are aligned in the microcrystalline region. By forming the above-mentioned region, the electrical characteristics of the oxide semiconductor layer can be changed. The crystalline region is, for example, a region in which the c-axis of the In2Ga2ZnO7 crystal is perpendicular to the surface of the oxide semiconductor layer. It is preferable to have a region oriented in the axial direction.

[0272] By forming a region in which crystal grains are oriented in this manner, It is possible to improve the electrical conductivity in the direction perpendicular to the surface of the oxide semiconductor layer and to improve the insulation in the direction perpendicular to the surface of the oxide semiconductor layer. In addition, such a microcrystalline region can prevent impurities such as water and hydrogen from entering the oxide semiconductor layer. It has the function of suppressing invasion.

[0273] Note that the oxide semiconductor layer having the above-described microcrystalline region is an oxide semiconductor layer formed by GRTA treatment. The Zn content can be reduced by heating the surface of the Zn alloy. By using a sputtering target smaller than the amount of .

[0274] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0275] The first heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, or the like. The hydration and dehydrogenation treatments are carried out by forming the oxide semiconductor layer 140 on a source After stacking the source electrode or drain electrode, a gate insulator is placed on the source electrode or drain electrode. This can be done at any time, such as after the formation of the layer. The hydration treatment and dehydrogenation treatment may be carried out not only once but also multiple times.

[0276] Next, a conductive layer 142 is formed in contact with the oxide semiconductor layer 140. An insulating layer 164 is formed on the insulating layer 164 (see FIG. 17(C)). good.

[0277] The conductive layer 142 is formed by a method such as a PVD method including a sputtering method, a plasma CVD method, etc. The conductive layer 142 can be formed by using a CVD method. , copper, tantalum, titanium, molybdenum, tungsten, or the above-mentioned It can be formed using an alloy containing the element manganese, magnesium, zirconium, etc. Materials containing one or more of arsenic, beryllium, and yttrium may be used. In addition, aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, A material containing one or more elements selected from the group consisting of dimetal and scandium may also be used.

[0278] The conductive layer 142 may be formed using a conductive metal oxide. The materials are indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0279] The conductive layer 142 may have a single-layer structure or a stacked structure of two or more layers. , a single-layer structure of an aluminum film containing silicon, a titanium film laminated on an aluminum film Examples include a two-layer structure and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. Here, a three-layer structure of a titanium film, an aluminum film, and another titanium film is applied.

[0280] Note that an oxide conductor layer may be formed between the oxide semiconductor layer 140 and the conductive layer 142. The oxide conductor layer and the conductive layer 142 can be formed successively (successive film formation). By providing such an oxide conductive layer, the resistance of the source region or the drain region can be reduced. This allows the transistor to operate at high speed.

[0281] The insulating layer 164 can be formed by using a CVD method, a sputtering method, or the like. The insulating layer 164 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, It is preferable to form the film so as to contain aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 164 may have a single-layer structure or a multi-layer structure. The thickness of 164 is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. can.

[0282] The conductive layer 142 and the insulating layer 164 are then selectively etched to form source or drain electrodes. A drain electrode 142a, a source electrode or drain electrode 142b, an insulating layer 164a, an insulating layer 164b is formed (see FIG. 17(D)).

[0283] The exposure to light used in forming the mask used for etching is ultraviolet light, KrF laser light, or ArF laser light. In particular, it is preferable to perform exposure so that the channel length (L) is less than 25 nm. In this case, extreme ultraviolet rays with extremely short wavelengths of several nm to several tens of nm are used. It is preferable to use a raviolet for exposure to form a mask. Light has high resolution and a large depth of focus, so the channel of the transistor that will be formed later can be It is possible to design the channel length (L) to be less than 25 nm. It is also possible to make the channel width 10 nm to 1000 nm. By reducing the length, the operating speed can be improved. Since the off-current of transistors using this material is very small, it is possible to suppress the increase in power consumption due to miniaturization. Can be controlled.

[0284] During etching of the conductive layer 142, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0285] In order to reduce the number of masks used and the number of processes, an exposure method in which the transmitted light has multiple intensities is used. A resist mask is formed using a multi-tone mask, which is a mask, and the etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. This can be further deformed by ashing, resulting in multiple It can be used in the etching process. In other words, at least It is also possible to form resist masks corresponding to two or more different patterns. This reduces the number of exposure masks and the corresponding photolithography steps. This simplifies the process.

[0286] Next, the gate insulating layer 1 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. The gate insulating layer 166 is formed by a CVD method or a sputtering method. The gate insulating layer 166 can be formed by a deposition method or the like. silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide The gate insulating layer 166 is preferably formed so as to contain tantalum oxide or the like. The gate insulating layer 166 may have a single layer structure or a stacked structure. Although not limited thereto, it can be, for example, 10 nm or more and 500 nm or less.

[0287] Note that an oxide semiconductor that has been made i-type or substantially i-type by removing impurities or the like is (Highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, high quality is required for the gate insulating layer 166.

[0288] For example, a high-density plasma CVD method using microwaves (for example, a frequency of 2.45 GHz) This is advantageous in that it allows the formation of a high-quality gate insulating layer 166 that is dense and has a high dielectric strength. The purified oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, so that the interface state This is because it is possible to reduce the interfacial characteristics and improve the interfacial properties.

[0289] Of course, if a good insulating layer can be formed as the gate insulating layer 166, sputtering may be used. It is also possible to apply other methods such as a coating method or a plasma CVD method. An insulating layer may be applied in which the film quality or interface characteristics are modified by treatment. In addition, the quality of the gate insulating layer 166 is good, and the interface state with the oxide semiconductor layer is low. It is sufficient to provide a material that can reduce density and form a good interface.

[0290] In this way, the interface characteristics with the gate insulating layer are improved, and impurities in the oxide semiconductor, particularly By excluding hydrogen and water from the substrate, gate bias and thermal stress tests (BT tests: for example , 85℃, 2×10 6 V / cm, 12 hours, etc.) It is possible to obtain a stable transistor that does not undergo any switching.

[0291] Then, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. is 200°C or more and 400°C or less, preferably 250°C or more and 350°C or less. For example, The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. In this embodiment, the variation in the electrical characteristics of the gate transistor can be reduced. The second heat treatment is performed after the formation of the insulating layer 166. There is no particular limitation as long as it is after the first heat treatment.

[0292] Next, a gate electrode 178 is formed on the gate insulating layer 166 in a region overlapping the oxide semiconductor layer 140. The gate electrode 178 is formed by depositing a conductive layer on the gate insulating layer 166 (see FIG. 18A). After forming the conductive layer, the conductive layer can be selectively patterned. Cut.

[0293] The conductive layer is formed by a method such as PVD (physical vapor deposition) method including sputtering, or plasma CVD method. The conductive layer can be formed by using a VD method. An element selected from the group consisting of niobium, titanium, molybdenum, and tungsten, or a combination of the above elements. The alloy may be made of manganese, magnesium, zirconium, etc. A material containing one or more of: Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, steel A material containing one or more elements selected from candium may be used.

[0294] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium zinc oxide alloy (In2O3-ZnO), or a combination of these metal oxide materials It is possible to use one containing silicon or silicon oxide.

[0295] The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing conductors, and a two-layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and a titanium film are laminated. Here, a conductive layer is formed using a material containing titanium and processed into a gate electrode 178 .

[0296] Next, an interlayer insulating layer 170 and an interlayer insulating film 172 are formed on the gate insulating layer 166 and the gate electrode 178. The edge layer 172 is formed (see FIG. 18(B)). The interlayer insulating layer 170 and the interlayer insulating layer 172 The can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, nitride Silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. The insulating layer 11 can be formed by using a material containing an organic insulating material. The insulating layer 170 and the interlayer insulating layer 172 are laminated together. There is no limitation to the number of layers. It may be a single layer or a laminated structure of three or more layers.

[0297] It is preferable that the interlayer insulating layer 172 is formed so that its surface is flat. By forming the interlayer insulating layer 172 so as to have a flat surface, a conductive layer is formed on the interlayer insulating layer 172. This is because electrodes, wiring, etc. can be formed suitably.

[0298] Next, the electrode 136 is formed on the gate insulating layer 166, the interlayer insulating layer 170, and the interlayer insulating layer 172. a, electrode 136b, electrode 136c, source or drain electrode 142a, source electrode Alternatively, an opening is formed that reaches the drain electrode 142b, and a conductive material is inserted into the opening. Then, a part of the conductive layer is removed by a method such as etching or CMP. The interlayer insulating layer 172 is then removed to expose the electrodes 154a, 154b, 154c, and Then, electrodes 154d and 154e are formed (see FIG. 18(C)).

[0299] The opening can be formed by a method such as etching using a mask. The etching can be performed by a method such as exposure using a photomask. Either wet etching or dry etching may be used for the etching. From this viewpoint, it is preferable to use dry etching.

[0300] The conductive layer can be formed by using a PVD method, a CVD method, or the like. Possible materials include molybdenum, titanium, chromium, tantalum, and tungsten. Conductive materials such as aluminum, copper, neodymium, and scandium, as well as their alloys and compounds Examples of such compounds include nitrides.

[0301] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then the titanium film is removed by the CVD method. After forming a thin titanium nitride film by , a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrodes 136a, 136b, 136c, source electrodes or drain electrodes) Oxides that may form on the surfaces of the electrodes 142a, the source electrode or the drain electrode 142b, etc. This reduces the contact resistance with the lower electrode. Titanium nitride has a barrier function that suppresses the diffusion of conductive materials. After forming a barrier film made of titanium or the like, a copper film may be formed by plating. The method is not limited to the so-called single damascene method, but may be a dual damascene method.

[0302] When removing a portion of the conductive layer, the surface of the interlayer insulating layer 172, the electrode 154a, the The surfaces of the electrodes 154b, 154c, 154d, and 154e are made flat. By flattening the surface in this way, it is possible to improve the quality of the surface in the subsequent processes. This makes it possible to form favorable electrodes, wiring, and the like.

[0303] Thereafter, an insulating layer 156 is further formed, and electrodes 154a, 154b, Openings reaching the electrodes 154c, 154d, and 154e are formed, and the openings are filled with After forming a conductive layer so that it is embedded in the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. The insulating layer 156 is removed to expose the electrodes 158a, 158b, 158c, and 158d is formed (see FIG. 18(D)). This step is performed when forming the electrodes 154a, etc. Since it is similar to the above, the details are omitted.

[0304] In the case where the transistor 402 is manufactured by the above-described method, the hydrogen concentration in the oxide semiconductor layer 140 is Degree is 5 x 10 19 / cm 3 The off-state current of the transistor 402 is 1×10 -13 In this way, the hydrogen concentration is sufficiently reduced, oxygen is supplied, and high purity By using the oxide semiconductor layer 140, a transistor 402 with excellent characteristics can be obtained. It is possible.

[0305] Note that in the case where oxygen is supplied to the oxide semiconductor layer 140 immediately after the hydrogen concentration is reduced, Since there is no risk of hydrogen or water being mixed into the oxide semiconductor layer, the oxide has extremely good characteristics. Of course, it is preferable to use an oxide having good characteristics in order to realize a semiconductor layer. If a semiconductor layer can be realized, the hydrogen concentration reduction process and the oxygen supply process should be performed continuously. For example, another process may be included between these processes. These processes may be carried out simultaneously.

[0306] In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, and an oxide Since the transistor 402 is made of a semiconductor, the device has excellent characteristics that combine the characteristics of both. A volatile latch circuit and a semiconductor device using the same can be manufactured.

[0307] In addition, in oxide semiconductors, physical properties such as DOS (density of state) Although many studies have been conducted, these studies have focused on the idea of ​​sufficiently reducing the localized levels themselves. In one embodiment of the disclosed invention, water or hydrogen, which may cause a localized level, is not included in an oxide semiconductor. By removing the ions from the body, a highly purified oxide semiconductor is produced. This is based on the idea of ​​reducing the amount of material used. This enables the production of industrial products.

[0308] When removing hydrogen and water, oxygen may be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of metals that are generated due to oxygen deficiency, and oxygen vacancies are generated. It is desirable to further purify oxide semiconductors (to make them i-type) by reducing the localized levels. For example, an oxide film containing excess oxygen is formed in close contact with the channel formation region, and then the oxide film is heated at 200°C. By performing heat treatment at a temperature of up to 400°C, typically around 250°C, the oxide film is It is possible to supply oxygen from the second During the first heat treatment, the inert gas may be replaced with a gas containing oxygen. Then, the temperature is lowered in an oxygen atmosphere or an atmosphere from which hydrogen and water have been sufficiently removed. In addition, oxygen can be supplied to the oxide semiconductor.

[0309] The cause of the deterioration of the characteristics of oxide semiconductors is the 0.1 to 0.2 eV lower conduction band caused by excess hydrogen. This is thought to be due to shallow levels of oxygen and deep levels due to oxygen vacancies. The technical idea of ​​thoroughly removing hydrogen and providing a sufficient amount of oxygen to eliminate the defects is correct. It would be something like that.

[0310] Note that an oxide semiconductor is generally an n-type semiconductor. By removing impurities such as i and supplying oxygen, which is a constituent element of oxide semiconductors, In this respect, unlike silicon, which is made i-type by adding impurities, It can be said to contain technological ideas never seen before.

[0311] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewrite operation is performed by switching the data, there is practically no limit to the number of times the data can be rewritten. The input voltage is approximately the threshold voltage of the transistor, so it is possible to operate at a low voltage. The potential of the data storage section is directly applied, so the variation in the amount of charge stored as data is reduced. This can reduce the amount of data transfer and facilitates data reading.

[0312] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0313] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0314] (Embodiment 3) This embodiment describes a configuration and an operation of a nonvolatile latch circuit which is one embodiment of the disclosed invention. This will be described with reference to FIG.

[0315] FIG. 19A shows a latch unit 411 and a data holding unit 401 for holding data from the latch unit. FIG. 19B shows the configuration of a nonvolatile latch circuit 400 having a nonvolatile 2 shows an example of a timing chart of the latch circuit 400.

[0316] FIG. 19A is a specific example of the configuration of the latch unit 411 in FIG. uses an inverter 412 as a first element in the configuration of the latch unit 411 in FIG. In this example, an inverter 413 is used as the second element. It can be the same as the first or second embodiment.

[0317] The latch unit 411 includes an inverter 412 and an inverter 413. 12 is electrically connected to the input of an inverter 413, and the output of the inverter 413 is The latch section 41 has a loop structure electrically connected to the input of the inverter 412. 1 has a switch 431 and a switch 432, and the inverter 431 is connected to the inverter 432 via the switch 432. The output of the inverter 413 is electrically connected to the input of the inverter 412 .

[0318] The input of the inverter 412 is given an input signal of the latch circuit via a switch 431. The output of the inverter 412 is electrically connected to a wiring 414. The input of the inverter 412 is electrically connected to a wiring 415 to which a signal is applied. The node at which the latch circuit is input is called node P. Node P is the node at which the latch circuit is input. The node P is electrically connected to a wiring 414 that is connected to the output of the inverter 413. The potential of the node P is also electrically connected to the input of the inverter 412. The potential is the same as that of

[0319] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistor 402 is used as a switching element. The capacitor 404 is electrically connected to the source electrode or drain electrode of the transistor 02. One of the source and drain electrodes of the transistor 402 is connected to one of the electrodes of the capacitor 404. The other of the source electrode and the drain electrode of the transistor is electrically connected to the latch section. The input of the inverter 412 (node ​​P) is electrically connected to the input of the inverter 412.

[0320] The other of the source electrode and drain electrode of the transistor is connected to an input signal of a latch circuit. The capacitor 404 is electrically connected to the wiring 414 via a switch 431. The other electrode is applied with a potential Vc. The transistor 402 and the capacitor 404 are electrically connected to each other. Let us call the node S.

[0321] The transistor 402 using an oxide semiconductor is a transistor for storing data held in the latch portion 411. The data is written to the capacitor 404 of the data storage unit 401. The data storage unit 401 has a function of storing data written in the capacity 404 of the data storage unit 401. In addition, the transistor 402 is held in the capacitance 404 of the data holding unit 401. The latch unit 411 has a function of reading out the data stored in the latch unit 411.

[0322] The potential of the input signal IN is applied to the wiring 414 from the previous circuit. The switch 431 receives the power of the clock signal φ1 as an output signal OUT. When a high level potential is applied to the clock signal φ1, the switch 431 The potential of the clock signal φ2 is applied to the switch 432. When a high-level potential is applied to φ2, the switch 432 is turned on. The gate of 02 is connected to the control signal φ LS A control signal φ LS High level of electricity When a clock signal is applied, transistor 402 is turned on. The clock signal φ2 has a signal obtained by inverting the clock signal φ1. 1 shows an example in which a transistor or switch is turned on when a clock signal is at a high level.

[0323] The inverter 412 and the inverter 413 of the latch unit 411 are each provided with a high level A power supply voltage VDD at a high level and a power supply voltage VSS at a low level are applied.

[0324] Next, in FIG. 19B, the nonvolatile latch circuit 400 is in an active state (operation period) and in a stopped state. During the stop state period (non-operating period), the input signal IN, the output signal OUT, and the control signal φ LS 1 shows an example of a timing chart of the potentials of the clock signals φ1 and φ2. The node S of the data holding unit 401, the node P of the latch unit 411, and the The potentials of the power supply voltage VDD-L of the inverter 412 and the inverter 413 are also shown. S indicates the potential of one electrode of the capacitor 404. Note that the other electrode of the capacitor 404 has a given A constant potential Vc, for example, ground potential, is applied.

[0325] In FIG. 19B, the latch circuit 400 is in an operating state during periods a, b, d, and e. period c is a period during which the latch circuit 400 is in a stopped state (non-operating period). The periods a and e are normal operation periods of the latch circuit 400, and the clock signal φ1 During period b, a high level or low level potential is alternately applied to the clock signal φ2. Period b is a preparation period before the non-operating period. Period b is also called the down-turn period. Period d is a non-operating period. This is the preparation period after the normal operation period when power is supplied. It is also called the lift-off period.

[0326] During the normal operation period (period a), the clock signal φ1 is at a high level, and the clock signal φ2 When a low-level potential is applied to the switch 432, the switch 432 is turned off and the inverter loop is disconnected. At the same time, the switch 431 is turned on, and the potential of the input signal is input to the inverter 412. The potential of the input signal is inverted by an inverter 412 and output as an output signal OUT to the subsequent stage. When a high-level potential is applied to the clock signal φ1, the input signal If the potential of the clock is high, an output signal having a low potential is obtained. If the potential of the input signal is low when the potential of the signal φ1 is high, , an output signal having a high level potential is obtained.

[0327] When a low level potential is applied to the clock signal φ1 and a high level potential is applied to the clock signal φ2, The switch 431 is turned off and the switch 432 is turned on, forming an inverter loop. The potential of the output signal OUT is held (data is latched). (The logic state of the path is maintained.)

[0328] During normal operation, the control signal φ LS A potential that turns off the transistor 402 is applied to The node S is connected to the previously held potential, and the potential at which the transistor 402 turns on is not applied. The potential is determined by the charge carried by the electrode. Here, the potential is set to an indefinite value.

[0329] Next, in a preparation period (period b) before the non-operation period, the control signal φ LS Transistor 4 When a potential is applied that turns on the transistor 402, the transistor 402 turns on and the latch section The potential of the input (node ​​P) of the inverter 412 is applied to the node S (write). If the potential of the input (node ​​P) of the inverter 412 in the first stage is at a high level, the potential of the node S becomes high level. A charge according to the potential is accumulated in node S.

[0330] Then, the control signal φ LSA potential that turns off the transistor 402 is applied to the The capacitor 402 is turned off, and the node S is in a floating state. The accumulated charge is retained (retained).

[0331] In addition, during period b, the clock signals φ2 and φ1 have the same potential as at the end of period a. Alternatively, the clock signal φ2 may be kept at a high level and the clock signal φ1 may be kept at a low level. It is also possible to fix the signal and latch the data at the end of period a.

[0332] Next, during the non-operating period (period c), the power supply is stopped and the power supply voltage VDD-L is low. The clock signal φ1, clock signal φ2, input signal IN, and output signal OUT are all connected to VDD. Any value between VSS and VSS can be used. During this time, the control signal φ LS The potential of the transformer For example, the resistor 402 is held at a low level so that the resistor 402 is in an off state. During the non-operating period (period c), the transistor 402 is turned off. As a result, the charge stored in node S is retained (retained).

[0333] Next, in the preparation period (period d) before entering the normal operation period after the non-operation period, is supplied, and the clock signals φ2 and φ1 are fixed to a low level. The potential of the node P and the potential of the output signal OUT are the same as those before the power is supplied. In this example, the node P is at a low level and the output signal OUT is at a high level. Let's assume that.

[0334] And the control signal φ LS When a potential that turns on the transistor 402 is applied to the The transistor 402 is turned on, and the potential held at the node S is applied to the latch section 411. Specifically, charge is shared between node S and the input (node ​​P) of inverter 412, A potential corresponding to the charge stored at node S is applied to the input (node ​​P) of inverter 412. Here, the charge stored in the node S is distributed to the latch unit 411, and the inverter The potential at the input of the inverter 412 (node ​​P) rises, and the potential at node S decreases slightly. The potential of the input (node ​​P) of the inverter 412 and the potential of the node S are substantially at a high level. The potential becomes

[0335] The potential of the node P of the latch section is inverted by the inverter 412 and output as the output signal OUT. Here, the potential held at node S and the potential held at node L of the latch are The potential applied to the output terminal P is high, and an output signal having a low potential is obtained. This allows the logic state of the latch circuit to be restored to the logic state before the non-operating period. The state can be restored.

[0336] Then, the control signal φ LS A potential that turns off the transistor 402 is applied to the The capacitor 402 is turned off, and the node S is in a floating state. The accumulated charge is held as is (retained). The charge stored at node S is then signal φ LS The signal is rewritten at the timing when a potential that turns on the transistor 402 is applied. Therefore, the control signal φ LS A potential that turns on the transistor 402 is applied to Until that timing, the charge stored at node S is maintained as is.

[0337] In addition, in the period d, the control signal φ LS A potential that turns on the transistor 402 is applied to the After the clock signal φ2 is turned on, a period during which the clock signal φ2 is turned on may be provided. When a high-level potential is applied to terminal 2, switch 432 is turned on and the inverter loop When the inverter loop is formed, the output signal OUT and the node P are high. A steady or low level potential is applied and held (data is latched).

[0338] As described above, data is read out to the latch section by connecting the node S and the input of the inverter 412 ( This is done by sharing the charge between node S and node P. is stored, the input of inverter 412 before transistor 402 turns on Regardless of the potential of node S (node ​​P), the charge between node S and the input (node ​​P) of inverter 412 The potential of the input (node ​​P) of the inverter 412 after the distribution of (the input potential at which the inverter output is inverted).

[0339] In addition, when a charge corresponding to a low-level potential is stored in the node S, the transistor Regardless of the potential of the input (node ​​P) of the inverter 412 before the inverter 402 is turned on, the potential of the node S After charge sharing between the input of inverter 412 (node ​​P) and the input of inverter 412 (node The potential of the input terminal P) is equal to the threshold voltage of the inverter 412 (the input voltage at which the output of the inverter is inverted). ) lower.

[0340] To achieve this, for example, the capacity of node S is set to be larger than the capacity of node P. In other words, it is preferable that the capacitance value of the capacitor 404 to which the node S is electrically connected is The input capacitance of the inverter 412 to which the node P is electrically connected (the transistor In addition, during the period d, the potential Vc is It is also effective to provide a period in which the voltage is between VDD and VSS. This makes it possible to perform the above steps more stably.

[0341] By doing so, only when the node P is at a low level and the output signal OUT is at a high level, First, when the node P is at a high level and the output signal OUT is at a low level, the latch In addition, a voltage corresponding to a high level potential is applied to the node S. This is not limited to the case where a charge is accumulated, but also applies to the case where a charge corresponding to a low-level potential is accumulated. It is also possible to read data into the latch section.

[0342] Next, the clock signals φ1 and φ2 are alternately switched between high and low levels. is given, and the normal operating state (period e) is entered. At the start of the normal operating period (period e), The clock signals φ1 and φ2 are generated at the end of the previous normal operation period (period a). It may start from the same potential (same state), or it may start from a potential reversed from that at the end of period a (next state). It is acceptable to start from the "no" state.

[0343] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewrite operation is performed by switching the data, there is practically no limit to the number of times the data can be rewritten. The input voltage is approximately the threshold voltage of the transistor, so it is possible to operate at a low voltage. The potential of the data storage section is directly applied, so the variation in the amount of charge stored as data is reduced. This can reduce the amount of data transfer and facilitates data reading.

[0344] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0345] This embodiment mode can be freely combined with other embodiment modes.

[0346] (Embodiment 4) In this embodiment, an operation of a nonvolatile latch circuit according to one embodiment of the disclosed invention will be described with reference to FIG. The configuration of the nonvolatile latch circuit is the same as that shown in FIG. 19B. Therefore, the timing chart shows a different example from that in FIG.

[0347] FIG. 20A shows a period during which the nonvolatile latch circuit 400 is in an active state (operation period) and a period during which the nonvolatile latch circuit 400 is in a stopped state. During the period when the input signal IN is in the inactive state (non-operating period), the input signal IN, the output signal OUT, and the control signal φ LS ,nine 1 shows an example of a timing chart of the potentials of the data lock signal φ1 and the clock signal φ2. The potentials of the node S of the holding unit 401, the node P of the latch unit 411, and the power supply voltage VDD-L are combined. The node S indicates the potential of one electrode of the capacitor 404. One electrode is applied with a potential Vc.

[0348] In FIG. 20A, the latch circuit 400 is in an operating state during periods a, b, d, and e. period c is a period during which the latch circuit 400 is in a stopped state (non-operating period). The periods a and e are normal operation periods of the latch circuit 400, and the clock signal φ1 During period b, a high level or low level potential is alternately applied to the clock signal φ2. Period b is a preparation period before the non-operating period. Period b is also called the down-turn period. Period d is a non-operating period. This is the preparation period after the start-up period until the normal operation period begins. Period d is also called the start-up period. cormorant.

[0349] In FIG. 20A, the operations in periods a, b, and c are similar to those in FIG. 19B. Next, after the non-operating period, power is supplied and there is a preparation period (period d ), the clock signals φ2 and φ1 are fixed to a low level. The potential of the node P and the potential of the output signal OUT are the same as those before the power is supplied. In this example, the node P is at a low level and the output signal OUT is at a high level. Let's assume that.

[0350] And the control signal φ LS When a potential that turns on the transistor 402 is applied to the The transistor 402 is turned on, and the potential held at the node S is applied to the latch section 411. Specifically, charge is shared between node S and the input (node ​​P) of inverter 412, A potential corresponding to the charge stored at node S is applied to the input (node ​​P) of inverter 412. Here, the charge stored in the node S is distributed to the latch unit 411, and the inverter The potential at the input of the inverter 412 (node ​​P) rises, and the potential at node S decreases slightly.

[0351] As a result, the potential at the input of the inverter 412 (node ​​P) and the potential at node S are substantially The potential of the node P of the latch section is inverted by the inverter 412. The output signal OUT is sent to the next circuit. The potential applied to the node P of the latch section is high level, and the potential applied to the node P of the latch section is low level. This shows an example in which an output signal having a logic state of a latch circuit can be obtained. The logic state before the operation period can be restored.

[0352] Next, the control signal φ LS With the potential at which the transistor 402 is turned on being applied to When the clock signal φ2 is at a high level, a high level potential is applied to the clock signal φ2. When a potential is applied, switch 432 turns on and an inverter loop is formed. When the inverter loop is formed, the output signal OUT and the node P are at high or low level. A level potential is applied and held (data is latched).

[0353] In particular, the charge sharing between node S and the input of inverter 412 (node ​​P) results in The input of the inverter 412 (node ​​P) is at a potential slightly different from the high or low level. Even if the voltage is high or low, the voltage is supplied again. The potential of node P is applied to node S. As a result, node S becomes high level or low level. Even if the potential is slightly different from the high or low level, As a result, the potential of the node S is returned to the state before the change (also called rewriting). It is possible to do so.

[0354] Then, the control signal φ LS A potential that turns off the transistor 402 is applied to the The capacitor 402 is turned off, and the node S is in a floating state. The accumulated charge is held as is (retained). The charge stored at node S is then signal φ LS The signal is rewritten at the timing when a potential that turns on the transistor 402 is applied. Therefore, the control signal φ LS A potential that turns on the transistor 402 is applied to Until that timing, the charge stored at node S is maintained as is.

[0355] As described above, data is read out to the latch section by connecting the node S and the input of the inverter 412 ( This is done by sharing the charge between node S and node P. is stored, the input of inverter 412 before transistor 402 turns on Regardless of the potential of node S (node ​​P), the charge between node S and the input (node ​​P) of inverter 412 The potential of the input (node ​​P) of the inverter 412 after the distribution of (the input potential at which the inverter output is inverted).

[0356] In addition, when a charge corresponding to a low-level potential is stored in the node S, the transistor Regardless of the potential of the input (node ​​P) of the inverter 412 before the inverter 402 is turned on, the potential of the node S After charge sharing between the input of inverter 412 (node ​​P) and the input of inverter 412 (node The potential of the input terminal P) is equal to the threshold voltage of the inverter 412 (the input voltage at which the output of the inverter is inverted). ) lower.

[0357] To achieve this, for example, the capacity of node S is set to be larger than the capacity of node P. In other words, it is preferable that the capacitance value of the capacitor 404 to which the node S is electrically connected is The input capacitance of the inverter 412 to which the node P is electrically connected (the transistor In addition, during the period d, the potential Vc is It is also effective to provide a period in which the voltage is between VDD and VSS. This makes it possible to perform the above steps more stably.

[0358] By doing so, only when the node P is at a low level and the output signal OUT is at a high level, First, when the node P is at a high level and the output signal OUT is at a low level, the latch In addition, a voltage corresponding to a high level potential is applied to the node S. This is not limited to the case where a charge is accumulated, but also applies to the case where a charge corresponding to a low-level potential is accumulated. It is also possible to read data into the latch section.

[0359] Next, the clock signals φ1 and φ2 are alternately switched between high and low levels. is given, and the normal operating state (period e) is entered. At the start of the normal operating period (period e), The clock signals φ1 and φ2 are generated at the end of the previous normal operation period (period a). It may start from the same potential (same state), or it may start from a potential reversed from that at the end of period a (next state). It is acceptable to start from the "no" state.

[0360] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough A latch circuit incorporating a holding section can be realized.

[0361] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and also makes it easier to read out data. It can be done easily.

[0362] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0363] This embodiment mode can be freely combined with other embodiment modes.

[0364] (Embodiment 5) In this embodiment, an operation of a nonvolatile latch circuit according to one embodiment of the disclosed invention will be described with reference to FIG. The configuration of the nonvolatile latch circuit is the same as that shown in FIG. Therefore, the timing chart shows an example different from those in FIG. 19(B) and FIG. 20(A).

[0365] FIG. 20B shows a period during which the nonvolatile latch circuit 400 is in an active state (operation period) and a period during which the nonvolatile latch circuit 400 is in a stopped state. During the period when the input signal IN is in the inactive state (non-operating period), the input signal IN, the output signal OUT, and the control signal φ LS ,nine 1 shows an example of a timing chart of the potentials of the data lock signal φ1 and the clock signal φ2. Node S of the holding unit 401, node P of the latch unit 411, the potential of the power supply voltage VDD-L, and capacitance The potential Vc of the other electrode of the capacitor 404 is also shown. This indicates the rank.

[0366] In FIG. 20B, the latch circuit 400 is in an operating state during periods a, b, d, and e. period c is a period during which the latch circuit 400 is in a stopped state (non-operating period). The periods a and e are normal operation periods of the latch circuit 400, and the clock signal φ1 During period b, a high level or low level potential is alternately applied to the clock signal φ2. Period b is a preparation period before the non-operating period. Period b is also called the down-turn period. Period d is a non-operating period. This is the preparation period after the normal operation period when power is supplied. It is also called the lift-off period.

[0367] In FIG. 20B, the operations in the periods a, b, and c are similar to those in FIG. 19B. Next, in the preparation period (period d) before entering the normal operation period after the non-operation period, is supplied, and the clock signals φ2 and φ1 are fixed to a low level. The potential of the node P and the potential of the output signal OUT are the same as those before the power is supplied. In this example, the node P is at a low level and the output signal OUT is at a high level. Let's assume that.

[0368] And the control signal φ LS When a potential that turns on the transistor 402 is applied to the The transistor 402 is turned on, and the potential held at the node S is applied to the latch section 411. Specifically, charge is shared between node S and the input (node ​​P) of inverter 412. And the control signal φ LS The timing at which the transistor 402 is turned on is given to A predetermined potential is applied to the potential Vc of the other electrode of the capacitor. The potential Vc is a low level potential. The potential is raised from the low level to a potential between the high level and the low level.

[0369] As a result, the input (node ​​P) of the inverter 412 is charged by the charge sharing with the node S. The potential is determined by adding the increment of the potential Vc of the other electrode of the capacitance to the potential determined by the capacitance. In this case, the charge stored in the node S is distributed to the latch section 411 and the potential Vc is By applying a constant potential, the potential of the input (node ​​P) of the inverter 412 rises, and The potential of node S decreases slightly. As a result, the potential of the input (node ​​P) of inverter 412 and The potential of the node S becomes substantially high level.

[0370] The potential of the node P of the latch section is inverted by the inverter 412 and output as the output signal OUT. This allows the logic state of the latch circuit to be kept constant before entering the non-operating period. Then, the potential Vc of the other electrode of the capacitance is returned to the low level. The potential of the filter is set to

[0371] Next, the control signal φ LS With the potential at which the transistor 402 is turned on being applied to When the clock signal φ2 is at a high level, a high level potential is applied to the clock signal φ2. When a potential is applied, switch 432 turns on and an inverter loop is formed. When a inverter loop is formed, the output signal OUT and the node P are at a high or low level. The potential of the bell is applied and held (data is latched).

[0372] In particular, the charge sharing between node S and the input of inverter 412 (node ​​P) results in The input of the inverter 412 (node ​​P) is at a potential slightly different from the high or low level. Even if the voltage is high or low, the voltage is supplied again. The potential of node P is applied to node S. As a result, node S becomes high level or low level. Even if the potential is slightly different from the normal level, it can be set to high or low again. As a result, the potential of the node S is returned to the state before the change (also called rewriting). It is possible to do so.

[0373] Then, the control signal φ LS A potential that turns off the transistor 402 is applied to the The capacitor 402 is turned off, and the node S is in a floating state. The accumulated charge is held as is (retained). The charge stored at node S is then signal φ LS The signal is rewritten at the timing when a potential that turns on the transistor 402 is applied. Therefore, the control signal φ LS A potential that turns on the transistor 402 is applied to Until that timing, the charge stored at node S is maintained as is.

[0374] As described above, data is read out to the latch section by connecting the node S and the input of the inverter 412 ( This is done by sharing the charge with node P and controlling the potential Vc. When a charge corresponding to the potential is stored, the inverter before the transistor 402 is turned on is turned on. Regardless of the potential of the input (node ​​P) of the inverter 412, the potential of the node S and the input (node The potential of the input (node ​​P) of the inverter 412 after the charge sharing with the inverter The input potential is set to be higher than the threshold value of 412 (the input potential at which the inverter output is inverted).

[0375] In addition, when a charge corresponding to a low-level potential is stored in the node S, the transistor Regardless of the potential of the input (node ​​P) of the inverter 412 before the inverter 402 is turned on, the potential of the node S After charge sharing between the input of inverter 412 (node ​​P) and the input of inverter 412 (node The potential of the input terminal P) is equal to the threshold voltage of the inverter 412 (the input voltage at which the output of the inverter is inverted). ) lower.

[0376] To achieve this, for example, the capacity of node S is set to be larger than the capacity of node P. In other words, it is preferable that the capacitance value of the capacitor 404 to which the node S is electrically connected is The input capacitance of the inverter 412 to which the node P is electrically connected (the transistor In addition, during the period d, the potential Vc is It is also effective to provide a period in which the voltage is between VDD and VSS. This makes it possible to perform the above steps more stably.

[0377] By doing so, only when the node P is at a low level and the output signal OUT is at a high level, First, when the node P is at a high level and the output signal OUT is at a low level, the latch In addition, a voltage corresponding to a high level potential is applied to the node S. This is not limited to the case where a charge is accumulated, but also applies to the case where a charge corresponding to a low-level potential is accumulated. It is also possible to read data into the latch section.

[0378] In particular, as described in this embodiment, the control signal φ LS Then, transistor 402 turns on. At the timing when the potential is applied to the other electrode of the capacitor, a predetermined potential is applied to the potential Vc of the other electrode of the capacitor. This allows for more stable reading.

[0379] For example, when the capacitance value of the capacitor 404 is small or when the period during which the power supply is stopped is long, After the charge is shared, the potential of the input (node ​​P) of the inverter 412 and the potential of the It becomes difficult to maintain a relationship with the threshold voltage (the input voltage at which the inverter output is inverted). , the read stability may decrease.

[0380] Even in such a case, by applying a predetermined potential to the potential Vc of the other electrode of the capacitance, The magnitude relationship of the potentials described above is maintained, and the potential difference is controlled to be kept as large as possible. As a result, stable reading is possible. This allows operation with a capacitance of a small value, making it possible to reduce the size of the device. Longer holding periods are possible.

[0381] The timing at which the potential Vc of the other electrode of the capacitor is returned to the low level is The control signal φ2 may be turned on after a high-level potential is applied to the control signal φ LS To Trang The potential can be returned to a low level before the potential that turns off the transistor 402 is applied.

[0382] Next, the clock signals φ1 and φ2 are alternately switched between high and low levels. is given, and the normal operating state (period e) is entered. At the start of the normal operating period (period e), The clock signals φ1 and φ2 are generated at the end of the previous normal operation period (period a). It may start from the same potential (same state), or it may start from a potential reversed from that at the end of period a (next state). It is acceptable to start from the "no" state.

[0383] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough A latch circuit incorporating a holding section can be realized.

[0384] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and also makes it easier to read out data. In addition, the capacitance of the data storage section can be made smaller. This makes it possible to reduce the size.

[0385] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0386] This embodiment mode can be freely combined with other embodiment modes.

[0387] (Embodiment 6) This embodiment relates to a logic circuit having a plurality of nonvolatile latch circuits, which is one embodiment of the disclosed invention. The configuration of the path will be described with reference to FIG.

[0388] FIG. 21 shows a configuration of a latch unit 411 and a data holding unit 401 that holds data from the latch unit. The configuration of a logic circuit having two nonvolatile latch circuits 400 is shown. is called a D-FF and is used, for example, as a register in CPUs and various logic circuits.

[0389] The configuration of the data holding unit 401 is the same as that of FIG. 1. The configuration of the latch unit 411 is the same as that of FIG. In the configuration of the switch unit 411, a NAND is used as the first element and a clock is used as the second element. This is an example using a quadrature inverter.

[0390] The latch unit 411 includes a NAND 412 and a clocked inverter 413. The output of the ND412 is electrically connected to the input of the clocked inverter 413, The output of the inverter 413 is electrically connected to the input of the NAND 412. The latch unit 411 also has an analog switch 431.

[0391] One of the inputs of the NAND 412 is connected to the input of the latch circuit 400 via an analog switch 431. The output of the NAND 412 is electrically connected to a wiring 414 to which an input signal is applied. The NAND gate 400 is electrically connected to a wiring 415 to which an output signal of the NAND gate 400 is applied. The other input of 412 is electrically connected to a wiring to which the signal RSTB is applied. The analog switch 431 is supplied with a clock signal and an inverted signal of the clock signal. The clocked inverter 413 is provided with a clock signal and an inverted signal of the clock signal.

[0392] The logic circuit shown in FIG. 21 is a nonvolatile latch circuit 400. The nonvolatile latch circuit 400a and the nonvolatile latch circuit 400b are 00a is electrically connected to a wiring 414 to which a potential of an input signal is applied from a previous circuit. The wiring 415 to which the potential of the output signal of the nonvolatile latch circuit 400a is applied is The latch circuit 400b is electrically connected to a wiring 414 to which a potential of an input signal is applied. The nonvolatile latch circuit 400b outputs the nonvolatile latch circuit 400b to a subsequent circuit. It is electrically connected to a wiring 415 that provides the potential of a force signal.

[0393] The analog switch 431 of the nonvolatile latch circuit 400a receives the clock signal φ1 and An inverted signal φ1b of the clock signal is applied to the clocked inverter 413. A clock signal φ2 and an inverted clock signal φ2b are applied to the nonvolatile latch circuit 40. The analog switch 431 of the 0b receives the clock signal φ2 and the inverted signal φ 2b is applied to the clocked inverter 413, which receives the clock signal φ1 and the inverse of the clock signal φ1. A rotation signal φ1b is applied.

[0394] The oxide semiconductor according to this embodiment is used as a semiconductor material for forming a channel formation region. The transistor is used in a non-volatile latch circuit as a switching element for a data holding portion. This allows the device to operate stably even at high temperatures, and the stored logic state is maintained even when the power is turned off. A non-volatile latch circuit that does not lose its state or a data holding section with a sufficiently long refresh period It is possible to realize a latch circuit having a built-in latch circuit.

[0395] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and also makes it easier to read out data. It can be done easily.

[0396] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0397] This embodiment mode can be freely combined with other embodiment modes.

[0398] (Embodiment 7) In this embodiment, a configuration of a nonvolatile latch circuit which is one embodiment of the disclosed invention will be described with reference to FIG. 22. FIG. 22 shows an example different from FIG. 1. FIG. 22 shows a latch A non-volatile latch circuit having a data holding unit for holding data of the latch unit. 4 shows the configuration of a switching circuit 400.

[0399] In the nonvolatile latch circuit 400 shown in FIG. 22, the output of the first element (D1) 412 is The output of the second element (D2) 413 is electrically connected to the input of the first element (D3) 413. A latch unit 411 having a loop structure electrically connected to the input of the element (D1) 412; and a data holding unit 401 for holding data from the latch unit.

[0400] The input of the first element (D1) 412 is connected to a wiring 414 to which an input signal of the latch circuit is applied. The output of the first element (D1) 412 is electrically connected to the output of the latch circuit. The wiring 415 is electrically connected to the wiring 415.

[0401] If the first element (D1) 412 has multiple inputs, one of them is used as the input signal of the latch circuit. The second element (D2) 413 can be electrically connected to a wiring 414 to which a signal is applied. If there are multiple inputs, one of them is electrically connected to the output of the first element (D1) 412. It can continue.

[0402] The first element (D1) 412 uses an element that outputs an inverted version of the input signal. For example, the first element (D1) 412 may include an inverter, a NAND (NAND gate), ), NOR, clocked inverter, etc. can be used. (D2) 413 can be an element in which the inverted input signal is the output. For example, the second element (D2) 413 includes an inverter, a NAND, a NOR (NOR), a clocked inverter, etc. can be used.

[0403] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistors 402a and 402b are used as switching elements. In addition, a capacitor electrically connected to the source electrode or the drain electrode of the transistor 402a A capacitor 404a and a source electrode or a drain electrode of the transistor 402b are electrically connected to the capacitor 404a. The capacitor 404b has a capacitance 404b.

[0404] The source electrode and drain electrode of the transistor 402a are connected to the electrode of the capacitor 404a. One of the electrodes is electrically connected to one of the source electrode and drain electrode of the transistor 402b. One of the electrodes of the capacitor 404b is electrically connected to the source voltage of the transistor 402a. The other of the two electrodes is connected to the input of the first element (D1) 412 or the input signal of the latch circuit. The source electrode of the transistor 402b is electrically connected to a wiring 414 to which a voltage is applied. The other of the drain electrodes is connected to the output of the first element (D1) 412 or the output signal of the latch circuit. The other electrode of the capacitor 404a and the The other electrode 404b is applied with a potential Vc.

[0405] The transistor 402a and the transistor 402b using this oxide semiconductor are The data held in the data storage unit 11 is written to the capacity 404a and the capacity 404b of the data storage unit 401. The transistors 402a and 402b have a function of writing data. The data storage unit 401 has a function of storing the written data in the capacity 404a and the capacity 404b. The transistors 402a and 402b are connected to the data storage unit 401. A function of reading out data held in the capacitance 404a and the capacitance 404b to the latch unit 411. It has.

[0406] The data held in the latch unit 411 is written to the data holding unit 401, held, and decoded. The data is read from the data holding unit 401 to the latch unit 411, and the data is rewritten. First, the gate electrodes of the transistors 402a and 402b are A potential is supplied to each of the transistors 402a and 402b so that the transistors 402a and 402b are turned on. The switch 402b is turned on.

[0407] As a result, the data held in the latch section, i.e., the first The potential of the input of the element (D1) 412 is applied to one electrode of the capacitance 404a, and the latch portion The held output potential of the first element (D1) 412 is applied to one electrode of the capacitor 404b. As a result, the input of the first element (D1) 412 is connected to one electrode of the capacitance 404a. A charge corresponding to the potential of the first element (D1) 4 is accumulated in one electrode of the capacitor 404b. A charge according to the potential of the output of 12 is accumulated (write).

[0408] After that, the potentials of the gate electrodes of the transistors 402a and 402b are The transistor 402a and the transistor 402 b is turned off, the charge stored in one electrode of the capacitor 404a or 404b is The charge is retained (retention).

[0409] In addition, the gate electrodes of the transistors 402a and 402b are connected to the respective transistors. A potential is supplied to turn on the transistors 402a and 402b. By turning on the capacitor 404a, one electrode of the capacitor 404a and the input terminal of the first element (D1) 412 are connected to each other. The charge is distributed between one electrode of the capacitance 404b and the first element (D1) 412. As a result, the charge is shared between the input and output of the first element (D1) 412. A potential corresponding to the charge stored in one electrode of the capacitor 404a and the capacitor 404b is applied. As a result, data can be read (read). Data can be rewritten by The data writing and storage can be performed in the same manner as described above.

[0410] The oxide semiconductor according to this embodiment is used as a semiconductor material for forming a channel formation region. The transistor is used in a non-volatile latch circuit as a switching element for a data holding portion. This allows the device to operate stably even at high temperatures, and the stored logic state is maintained even when the power is turned off. A non-volatile latch circuit that does not lose its state or a data holding section with a sufficiently long refresh period It is possible to realize a latch circuit having a built-in latch circuit.

[0411] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and also makes it easier to read out data. It can be done easily.

[0412] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0413] This embodiment mode can be freely combined with other embodiment modes.

[0414] (Embodiment 8) This embodiment describes a configuration and an operation of a nonvolatile latch circuit which is one embodiment of the disclosed invention. This will be described with reference to FIG. 23 and FIG.

[0415] FIG. 23 shows a configuration of a latch unit 411 and a data holding unit 401 that holds data from the latch unit. FIG. 24 shows the configuration of the nonvolatile latch circuit 400. 1 shows an example of a timing chart for 00.

[0416] FIG. 23 is a specific example of the configuration of the latch unit 411 in FIG. In the configuration of the latch unit 411, an inverter 412 is used as the first element, and In this example, an inverter 413 is used as a transistor. The configuration of 2b can be the same as that of the first or second embodiment.

[0417] The latch unit 411 includes an inverter 412 and an inverter 413. 12 is electrically connected to the input of an inverter 413, and the output of the inverter 413 is The latch section 41 has a loop structure electrically connected to the input of the inverter 412. 1 has a switch 431 and a switch 432, and the inverter 431 is connected to the inverter 432 via the switch 432. The output of the inverter 413 is electrically connected to the input of the inverter 412 .

[0418] The input of the inverter 412 is given an input signal of the latch circuit via a switch 431. The output of the inverter 412 is electrically connected to a wiring 414. The input of the inverter 412 is electrically connected to a wiring 415 to which a signal is applied. The node at which the latch circuit is input is called node P. Node P is the node at which the latch circuit is input. The node P is electrically connected to a wiring 414 that is connected to the output of the inverter 413. The potential of the node P is also electrically connected to the input of the inverter 412. The potential is the same as that of

[0419] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistors 402a and 402b are used as switching elements. In addition, a capacitor electrically connected to the source electrode or the drain electrode of the transistor 402a A capacitor 404a and a source electrode or a drain electrode of the transistor 402b are electrically connected to the capacitor 404a. The capacitor 404b has a capacitance 404b.

[0420] The source electrode and drain electrode of the transistor 402a are connected to the electrode of the capacitor 404a. One of the electrodes is electrically connected to one of the source electrode and drain electrode of the transistor 402b. One of the electrodes of the capacitor 404b is electrically connected to the source voltage of the transistor 402a. The other of the electrode and drain electrode is connected to a wiring 414 to which an input signal of the latch circuit is given and a latch section The input of the inverter 412 (node ​​P) is electrically connected to the input of the inverter 412.

[0421] The other of the source electrode and the drain electrode of the transistor 402b is connected to a The signal is electrically connected to a wiring 415 to be applied and the output of the inverter 412 of the latch portion. A potential Vc is applied to the other electrode of the capacitor 404a and the other electrode of the capacitor 404b. The transistor 402a and the capacitor 404a, and the transistor 402b and the capacitor 404b, The electrically connected nodes are referred to as node S1 and node S2.

[0422] The transistor 402a and the transistor 402b using this oxide semiconductor are The data held in the data storage unit 11 is written to the capacity 404a and the capacity 404b of the data storage unit 401. The transistors 402a and 402b have a function of writing data. The data storage unit 401 has a function of storing the written data in the capacity 404a and the capacity 404b. The transistors 402a and 402b are connected to the data storage unit 401. A function of reading out data held in the capacitance 404a and the capacitance 404b to the latch unit 411. It has.

[0423] The potential of the input signal IN is applied to the wiring 414 from the previous circuit. The switch 431 receives the power of the clock signal φ1 as an output signal OUT. When a high level potential is applied to the clock signal φ1, the switch 431 The potential of the clock signal φ2 is applied to the switch 432. When a high-level potential is applied to φ2, the switch 432 is turned on. The gates of the transistors 402a and 402b are connected to a control signal φ LS The potential is given .

[0424] Control signal φ LS When a high-level potential is applied to each transistor, the transistors turn on. During normal operation, the clock signal φ2 has the inverted version of the clock signal φ1. Here, when the control signal and clock signal are at a high level, the transistors and switches 13 shows an example in which the switch is turned on.

[0425] The inverter 412 and the inverter 413 of the latch unit 411 are each provided with a high level A power supply voltage VDD at a high level and a power supply voltage VSS at a low level are applied.

[0426] Next, in FIG. 24(A) and FIG. 24(B), the nonvolatile latch circuit 400 is in an operating state ( The input signal IN, output signal OUT, Control signal φ LS , an example of a timing chart of the potentials of the clock signal φ1 and the clock signal φ2 Also, the node S1 and node S2 of the data holding unit 401 and the node P of the latch unit 411 are shown. The power supply voltage VDD-L of the inverter 412 and the inverter 413 of the latch unit 411 The potential is also shown.

[0427] The node S1 indicates the potential of one electrode of the capacitor 404a. The potential of one electrode of the capacitor 404a and the other electrode of the capacitor 404b is shown. are each given a predetermined potential Vc, for example, the ground potential.

[0428] First, FIG. 24(A) will be described. In FIG. 24(A), period a, period b, period d, The period e is a period during which the latch circuit 400 is in an operating state (operating period), and the period c is a period during which the latch circuit 4 Periods a and e are periods during which the latch circuit 400 is in a normal state. This is the operation period when the clock signal φ1 and the clock signal φ2 are alternately at high or low level. The potential of the bell is given. Period b is a preparation period before the non-operating period. Period d is the preparation period after the non-operating period until the normal operating period begins. Period d is also called the start-up period.

[0429] During the normal operation period (period a), the clock signal φ1 is at a high level, and the clock signal φ2 When a low-level potential is applied to the switch 432, the switch 432 is turned off and the inverter loop is disconnected. At the same time, the switch 431 is turned on, and the potential of the input signal is input to the inverter 412. The potential of the input signal is inverted by an inverter 412 and output as an output signal OUT to the subsequent stage. When a high-level potential is applied to the clock signal φ1, the input signal If the potential of the clock is high, an output signal having a low potential is obtained. If the potential of the input signal is low when the potential of the signal φ1 is high, , an output signal having a high level potential is obtained.

[0430] When a low level potential is applied to the clock signal φ1 and a high level potential is applied to the clock signal φ2, The switch 431 is turned off and the switch 432 is turned on, forming an inverter loop. The potential of the output signal OUT is held (data is latched). The logic state of the path is maintained.

[0431] During normal operation, the control signal φ LS The transistor 402a and the transistor 40 A potential is applied to turn off the transistor 402a and the transistor 402b. The potential at the node S1 and the node S2 is not given to the node S2 in response to the charge that was previously held. The potential is set to an indefinite value here.

[0432] Next, in a preparation period (period b) before the non-operation period, the control signal φ LS Transistor 4 When a potential is applied to turn on the transistors 402a and 402b, the transistors 402a and 402b are turned on. This causes the input of the inverter 412 in the latch section to The potential of the node P is applied to one electrode (node ​​S1) of the capacitance 404a, and the potential of the latch portion The potential of the output of the inverter 412 (or the wiring 415 to which the output signal is applied) is b is applied to one electrode (node ​​S2).

[0433] As a result, the capacitance 404a is connected to the potential of the input (node ​​P) of the inverter 412 of the latch section. The capacitor 404b stores a charge according to the output of the inverter 412 of the latch unit (or An electric charge corresponding to the potential of the wiring 415 to which the output signal is applied is accumulated (written). For example, the control signal φ LS The potential at which the transistor 402a and the transistor 402b are turned on is At the timing given, the potential of the input (node ​​P) of the inverter 412 of the latch section becomes high. If the potential of the node S1 is at a high level, the potential of the inverter 412 of the latch section becomes high level. If the potential of the output of the node S (or the wiring 415 to which the output signal is applied) is at a low level, The potential of 2 becomes low level.

[0434] Then, the control signal φ LS At this time, the transistor 402a and the transistor 402b are turned off. When a voltage is applied, each transistor is turned off, and the nodes S1 and S2 flow As a result, the charges stored at nodes S1 and S2 are Retained (retained).

[0435] In addition, during period b, the clock signals φ2 and φ1 have the same potential as at the end of period a. Alternatively, the clock signal φ2 may be kept at a high level and the clock signal φ1 may be kept at a low level. It is also possible to fix the signal and latch the data at the end of period a.

[0436] Next, in the non-operating period (period c), the power supply is stopped, and the The power supply voltage VDD-L of the inverter 412 and the inverter 413 drops. 1. The potential of the clock signal φ2, the input signal IN, the output signal OUT, and the node P is VDD-VS Any value may be taken between S. During this time, the control signal φ LS The potential of the transistor For example, the resistors 402a and 402b are held at a low level so that the resistors 402a and 402b are in an off state. During the non-operating period (period c), the transistors 402a and 402b are held at a potential By turning off the nodes S1 and S2, the charges stored in the nodes S1 and S2 are held (retained).

[0437] Next, after the non-operational period, a preparation period (period d) is entered before entering the normal operation period. (A) shows the control signal φ LS Then, the transistor 402a and the transistor 402b are turned on. When the potential of the node P and the output signal OUT is at a low level at the timing when the potential is applied, An example of this case is shown below.

[0438] During a period d, the inverter 412 and the inverter 413 of the latch unit 411 are powered on. Before being supplied, the clock signal φ2 is fixed at a high level and the clock signal φ1 is fixed at a low level. In this state, the control signal φ LS Then, the transistor 402a and the transistor 402b When an on potential is applied, each transistor is turned on, and the nodes S1 and S2 The potentials held in the nodes S2 are applied to the latch sections 411, respectively.

[0439] Specifically, charge is shared between node S1 and the input (node ​​P) of inverter 412, and A potential corresponding to the charge stored at node S1 is applied to the input (node ​​P) of inverter 412. Here, the potential at the input (node ​​P) of the inverter 412 rises, and the potential at node S1 The potential of decreases slightly.

[0440] In addition, the node S2 and the output of the inverter 412 (or the wiring 415 to which the output signal is applied) The charge is distributed between the output of the inverter 412 (or the wiring 415 to which the output signal is provided). ) is given a potential according to the charge stored in node S2. The potential of the input of 412 (node ​​P) and the potential of node S2 remain at low level.

[0441] In this state, when power is supplied to the inverter 412 and the inverter 413, the inverter 41 2. Inverter 413 The inverters in the latch section are connected to each other by the potential difference between their inputs and outputs. The input (node ​​P) of the inverter 412 is at a high level, and the output (or output signal) of the inverter 412 is at a high level. The line 415 to which this signal is applied becomes low level.

[0442] As a result, the data in the data holding section is read out to the latch section, and the logic state of the latch circuit is changed to The logic state before the non-operating period can be restored. A potential difference is generated between the input and output of each of the inverters 412 and 413. This allows the latch circuit to be used as a differential amplifier. This allows for more stable reading.

[0443] When power is supplied and an inverter loop is formed, the node P and the output signal OU A high or low level potential is applied to the potential of T and held (data is wrapped). Then, the potentials of the node P and the output signal OUT are applied to the nodes S1 and S2, respectively. This causes nodes S1 and S2 to be set to high or low again. As a result, the potentials of the nodes S1 and S2 are restored to their pre-change states. It can be reverted (also called rewritten).

[0444] Then, the control signal φ LS At this time, the transistor 402a and the transistor 402b are turned off. When a voltage is applied, each transistor is turned off, and the nodes S1 and S2 flow As a result, the charges stored at nodes S1 and S2 are The charges stored at the nodes S1 and S2 are then held in the control signal φ LS At the timing when a potential is applied to turn on the transistor 402a and the transistor 402b, Therefore, the control signal φ LS Transistor 402a, transistor Until the timing when the potential that turns on the transistor 402b is applied, the nodes S1 and S2 The accumulated charge is retained.

[0445] As described above, data is read out to the latch section by connecting the node S1 and the input of the inverter 412. (node ​​P), and the charge sharing between node S2 and the output of inverter 412 (or output This is done by sharing charge with the wiring 415 to which the signal is applied. A charge corresponding to the potential of the bell is accumulated at node S1, and a charge corresponding to the potential of the low level is accumulated at node S2. If the transistors 402a and 402b are turned on, the inverter 412 Depending on the potential of the input (node ​​P) and the output (or the wiring 415 to which the output signal is applied), First, the potential of the input (node ​​P) of the inverter 412 after the charge sharing is higher than the potential of the output of the inverter 412 (or the wiring 415 to which the output signal is applied). to.

[0446] In addition, a charge corresponding to a low-level potential is accumulated at node S1, and a high-level potential is accumulated at node S2. When a charge corresponding to the potential of the transistor 402a is stored, the transistors 402a and 402b are turned on. The input (node ​​P) and output (or output signal) of the inverter 412 before Regardless of the potential of the wiring 415, the voltage of the input (node ​​P) of the inverter 412 after the charge distribution The potential is the output of the inverter 412 after the charge distribution (or the wiring 415 to which the output signal is applied). ) is lower than the potential of the input (node) of the inverter 412 after the charge distribution. The potential of the output terminal P and the output (or the wiring 415 to which the output signal is applied) are both too low. For example, the threshold voltage of the transistors that make up the inverter must not be lower than Try not to get sick.

[0447] To achieve this, the capacity of node S1 must be greater than the capacity of node P. In other words, it is preferable that the capacitance value of the capacitor 404a to which the node S1 is electrically connected is The input capacitance of the inverter 412 to which P is electrically connected (the transistor It is preferable that the potential Vc is larger than the capacitance value of the gate capacitance (gate capacitance). It is also effective to set a period in which the value is between DD and VSS. This allows for more stable operation.

[0448] By doing so, only when the node P is at a low level and the output signal OUT is at a high level, First, when the node P is at a high level and the output signal OUT is at a low level, the latch In addition, the node S1 is set to a high level potential. This is not limited to the case where electric charge is accumulated, but also applies to the case where electric charge corresponding to a low level potential is accumulated. Even if the latch section is turned off, data can still be read out from the latch section.

[0449] Next, the clock signals φ1 and φ2 are alternately switched between high and low levels. is given, and the normal operating state (period e) is entered. At the start of the normal operating period (period e), The clock signals φ1 and φ2 are generated at the end of the previous normal operation period (period a). It may start from the same potential (same state), or it may start from a potential reversed from that at the end of period a (next state). It is acceptable to start from the "no" state.

[0450] Next, FIG. 24B will be described. In FIG. 24B, the period a, the period b, and the period c The operation is the same as in FIG.

[0451] Next, after the non-operational period, a preparation period (period d) is entered before entering the normal operation period. (B) shows the control signal φ LS Then, the transistor 402a and the transistor 402b are turned on. When the potential of the node P and the output signal OUT is at a high level at the timing when the potential is applied, An example of this case is shown below.

[0452] During a period d, the inverter 412 and the inverter 413 of the latch unit 411 are powered on. Before being supplied, the clock signal φ2 is fixed at a high level and the clock signal φ1 is fixed at a low level. In this state, the control signal φ LS Then, the transistor 402a and the transistor 402b When an on potential is applied, each transistor is turned on, and the nodes S1 and S2 The potentials held in the nodes S2 are applied to the latch sections 411, respectively.

[0453] Specifically, charge is shared between node S1 and the input (node ​​P) of inverter 412, and A potential corresponding to the charge stored at node S1 is applied to the input (node ​​P) of inverter 412. Here, the potential of the input (node ​​P) of the inverter 412 and the potential of the node S1 are It will remain at a high level.

[0454] In addition, the node S2 and the output of the inverter 412 (or the wiring 415 to which the output signal is applied) The charge is distributed between the output of the inverter 412 (or the wiring 415 to which the output signal is provided). ) is given a potential according to the charge stored in node S2. The potential of the output of 412 (output signal OUT) decreases, and the potential of node S2 increases slightly.

[0455] In this state, when power is supplied to the inverter 412 and the inverter 413, the inverter 41 2. Inverter 413 The inverters in the latch section are connected to each other by the potential difference between their inputs and outputs. The input (node ​​P) of the inverter 412 is at a high level, and the output (or output signal) of the inverter 412 is at a high level. The line 415 to which this signal is applied becomes low level.

[0456] As a result, the data in the data holding section is read out to the latch section, and the logic state of the latch circuit is changed to The logic state before the non-operating period can be restored. A potential difference is generated between the input and output of each of the inverters 412 and 413. This allows the latch circuit to be used as a differential amplifier. This allows for more stable reading.

[0457] When power is supplied and an inverter loop is formed, the node P and the output signal OU A high or low level potential is applied to the potential of T and held (data is wrapped). Then, the potentials of the node P and the output signal OUT are applied to the nodes S1 and S2. This causes nodes S1 and S2 to be set to high or low again. As a result, the potentials of the nodes S1 and S2 are restored to their pre-change states. It can be reverted (also called rewritten).

[0458] Then, the control signal φ LS At this time, the transistor 402a and the transistor 402b are turned off. When a voltage is applied, each transistor is turned off, and the nodes S1 and S2 flow As a result, the charges stored at nodes S1 and S2 are The charges stored at the nodes S1 and S2 are then held in the control signal φ LS At the timing when a potential is applied to turn on the transistor 402a and the transistor 402b, Therefore, the control signal φ LS Transistor 402a, transistor Until the timing when the potential that turns on the transistor 402b is applied, the nodes S1 and S2 The accumulated charge is retained.

[0459] Next, the clock signals φ1 and φ2 are alternately switched between high and low levels. is given, and the normal operating state (period e) is entered. At the start of the normal operating period (period e), The clock signals φ1 and φ2 are generated at the end of the previous normal operation period (period a). It may start from the same potential (same state), or it may start from a potential reversed from that at the end of period a (next state). It is acceptable to start from the "no" state.

[0460] Before the power is supplied, the inverters 412 and 413 are Although an example in which a potential difference is generated between the input and the output has been shown, the non-volatile memory shown in this embodiment In the configuration of the switch circuit (FIG. 23), a timing chart similar to that of FIG. 19(B) is used. It is also possible to operate it.

[0461] During the period d, it is also possible to provide a period in which the potential Vc is set to a value between VDD and VSS. This makes it possible to perform the read operation more stably.

[0462] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough A latch circuit incorporating a holding section can be realized.

[0463] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and also makes it easier to read out data. In addition, when the latch circuit is used as a differential amplifier, a more stable readout can be achieved. It becomes possible to extract

[0464] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0465] This embodiment mode can be freely combined with other embodiment modes.

[0466] (Embodiment 9) In this embodiment, an operation of a nonvolatile latch circuit according to one embodiment of the disclosed invention will be described with reference to FIG. The configuration of the nonvolatile latch circuit is the same as that of FIG. The graph shows an example different from those in FIG. 24(A) and FIG. 24(B).

[0467] FIG. 25 shows a period during which the nonvolatile latch circuit 400 is in an active state (operation period) and a period during which the nonvolatile latch circuit 400 is in a stopped state. During the non-operating period, the input signal IN, the output signal OUT, and the control signal φ LS ,clock 1 shows an example of a timing chart of the potentials of the signal φ1 and the clock signal φ2. Node S1 and node S2 of 401, node P of latch unit 411, The potential of the power supply voltage VDD-L of the inverter 412 and the inverter 413, the capacitance 404a, the capacitance The potential Vc of the other electrode of the capacitor 404b is also shown. A node S2 represents the potential of one electrode of the capacitor 404b.

[0468] In FIG. 25, periods a, b, d, and e are periods during which the latch circuit 400 is in an operating state. (operation period), and period c is a period during which the latch circuit 400 is in a stopped state (non-operation period). The periods a and e are normal operation periods of the latch circuit 400. A high level potential or a low level potential is alternately applied to the clock signal φ2. This is the preparation period before the operating period. Period b is also called the shutdown period. Period d is the non-operating period. This is the preparation period before entering the normal operation period. Period d is also called the start-up period.

[0469] In FIG. 25, the operation during periods a and b is the same as that in FIG. 24. During period c), the power supply is stopped, and the inverter 412 and the inverter 413 of the latch unit 411 are turned on. The power supply voltage VDD-L of the inverter 413 drops. During this time, the input signal IN can take any value between VDD and VSS. No.φ LS The potential is set to a low level so that the transistors 402a and 402b are turned off. For example, it may be held at ground potential.

[0470] During the non-operating period (period c), the transistors 402a and 402b are turned off. As a result, the charges stored at the nodes S1 and S2 are held (held). The signal OUT is held at a low level, and the potential of the node P gradually decreases.

[0471] Next, after the non-operating period, a preparation period (period d) is entered before entering the normal operating period. In the latch unit 411, power is supplied to the inverter 412 and the inverter 413. Before this, the clock signal φ2 is fixed at a high level and the clock signal φ1 is fixed at a low level. In this state, the control signal φ LS Then, the transistor 402a and the transistor 402b are turned on. When a potential is applied to the node S1 and the node S2, the transistors are turned on. The potentials held in the latch circuits 411 are then applied to the latch circuits 411.

[0472] Specifically, charge is shared between node S1 and the input of inverter 412 (node ​​P). And the control signal φ LS The timing at which a potential is applied to turn on the transistor 402a A predetermined potential is applied to the potential Vc of the other electrode of the capacitor 404a. The potential is raised from the bell potential to a potential between the low and high levels. The input of the inverter 412 (node ​​P) is at a potential determined by the charge sharing with node S1. A potential is applied that takes into account the increment of the potential Vc of the other electrode of the capacitor 404a. The potential at the input (node ​​P) of the inverter 412 rises, and the potential at node S1 decreases slightly. .

[0473] In addition, the node S2 and the output of the inverter 412 (or the wiring 415 to which the output signal is applied) The charge is shared between the control signal φ LS The voltage at which transistor 402b turns on is At the timing when the potential is applied, a predetermined potential is applied to the potential Vc of the other electrode of the capacitor 404b. The potential Vc is raised from the low level potential to a potential between the low level and the high level. do.

[0474] As a result, the output of the inverter 412 (or the wiring 415 to which the output signal is applied) The potential Vc of the other electrode of the capacitor 404b is determined by the charge sharing with the node S2. Here, the output of the inverter 412 (or the output signal The wiring 415 to which the signal is applied and the node S2 are connected to the potential Vc of the other electrode of the capacitor 404b. The potential increases slightly with the application of

[0475] In this state, when power is supplied to the inverter 412 and the inverter 413, the inverter 41 2. Inverter 413 The inverters in the latch section are connected to each other by the potential difference between their inputs and outputs. The input (node ​​P) of the inverter 412 is at a high level, and the output (or output signal) of the inverter 412 is at a high level. The line 415 to which this signal is applied becomes low level.

[0476] As a result, the data in the data holding section is read out to the latch section, and the logic state of the latch circuit is changed to The logic state before the non-operating period can be restored. A potential difference is generated between the input and output of each of the inverters 412 and 413. This allows the latch circuit to be used as a differential amplifier. This allows for more stable reading.

[0477] When power is supplied and an inverter loop is formed, the node P and the output signal OU A high or low level potential is applied to the potential of T and held (data is wrapped). Then, the potentials of the node P and the output signal OUT are applied to the nodes S1 and S2, respectively. This causes nodes S1 and S2 to be set to high or low again. As a result, the potentials of the nodes S1 and S2 are restored to their pre-change states. It can be reverted (also called rewritten).

[0478] Thereafter, the potential Vc of the other electrode of the capacitor is returned to a low level potential.

[0479] Then, the control signal φ LS At this time, the transistor 402a and the transistor 402b are turned off. When a voltage is applied, each transistor is turned off, and the nodes S1 and S2 flow As a result, the charges stored at nodes S1 and S2 are Retained (retained).

[0480] The charges stored at the nodes S1 and S2 are then applied with the control signal φ LS Transistor 402 a) is rewritten at the timing when a potential that turns on the transistor 402b is applied. Therefore, next, the control signal φ LS Then, the transistor 402a and the transistor 402b are turned on. The charges stored in the nodes S1 and S2 are not changed until the timing at which the potential is applied. The data is retained as is.

[0481] As described above, data is read out to the latch section by connecting the node S1 and the input of the inverter 412. (node ​​P), and the charge sharing between node S2 and the output of inverter 412 (or output This is done by sharing charge with the wiring 415 to which the signal is applied. A charge corresponding to the potential of the bell is accumulated at node S1, and a charge corresponding to the potential of the low level is accumulated at node S2. If the transistors 402a and 402b are turned on, the inverter 412 Depending on the potential of the input (node ​​P) and the output (or the wiring 415 to which the output signal is applied), First, the potential of the input (node ​​P) of the inverter 412 after the charge sharing is 412 (or the wiring 415 to which the output signal is applied) to.

[0482] In addition, a charge corresponding to a low-level potential is accumulated at node S1, and a high-level potential is accumulated at node S2. When a charge corresponding to the potential of the transistor 402a is stored, the transistors 402a and 402b are turned on. The input (node ​​P) and output (or output signal) of the inverter 412 before Regardless of the potential of the wiring 415, the voltage of the input (node ​​P) of the inverter 412 after the charge distribution The potential is the output of the inverter 412 after the charge distribution (or the wiring 415 to which the output signal is applied). ) is lower than the potential of the input (node) of the inverter 412 after the charge distribution. If both the potential of the output terminal P and the potential of the output (or the wiring 415 to which the output signal is applied) are too low, For example, the threshold voltage of the transistors that make up the inverter must not be lower than Try not to get sick.

[0483] To achieve this, the capacity of node S1 must be greater than the capacity of node P. In other words, it is preferable that the capacitance value of the capacitor 404a to which the node S1 is electrically connected is The input capacitance of the inverter 412 to which P is electrically connected (the transistor It is preferable that the potential Vc is larger than the capacitance value of the gate capacitance (gate capacitance). It is also effective to set a period in which the value is between DD and VSS. This allows for more stable operation.

[0484] By doing so, only when the node P is at a low level and the output signal OUT is at a high level, First, when the node P is at a high level and the output signal OUT is at a low level, the latch In addition, the node S1 is set to a high level potential. This is not limited to the case where electric charge is accumulated, but also applies to the case where electric charge corresponding to a low level potential is accumulated. Even if the latch section is turned off, data can still be read out from the latch section.

[0485] In particular, as described in this embodiment, the control signal φ LS The transistors 402a and 402 At the timing when a potential is applied to turn on b, a predetermined voltage is applied to the potential Vc of the other electrode of the capacitor. By providing a position, it becomes possible to perform reading more stably.

[0486] For example, when the capacitance values ​​of the capacitors 404a and 404b are small or the period during which the power supply is stopped is long, In the case where the charge is not distributed, the input (node ​​P) and output (or It becomes difficult to maintain the potential difference of the wiring 415) to which the power signal is applied, or after the charge is distributed The input (node ​​P) and output (or the wiring 415 to which the output signal is applied) of the inverter 412 This may result in a decrease in the potential of the readout region and a decrease in readout stability.

[0487] Even in such a case, the potential Vc of the other electrode of the capacitor 404a and the capacitor 404b is set to a predetermined value. By applying the potential of Alternatively, the potential of the wiring 415 to which the output signal is applied can be controlled to an appropriate potential. As a result, stable readout is possible. This allows operation in a wide range of environments, making it possible to miniaturize the device. Alternatively, the data retention period can be extended. It is possible to do so.

[0488] Next, the clock signals φ1 and φ2 are alternately switched between high and low levels. is given, and the normal operating state (period e) is entered. At the start of the normal operating period (period e), The clock signals φ1 and φ2 are generated at the end of the previous normal operation period (period a). It may start from the same potential (same state), or it may start from a potential reversed from that at the end of period a (next state). It is acceptable to start from the "no" state.

[0489] Before the power is supplied, the inverters 412 and 413 are Although an example in which a potential difference is generated between the input and the output has been shown, the non-volatile memory shown in this embodiment In the configuration of the switch circuit (FIG. 23), a timing chart similar to that of FIG. 19(B) is used. It is also possible to operate it.

[0490] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough A latch circuit incorporating a holding section can be realized.

[0491] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and makes it easier to read out data. In addition, the capacitance of the data storage section can be made smaller. This makes it possible to reduce the size.

[0492] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0493] This embodiment mode can be freely combined with other embodiment modes.

[0494] (Embodiment 10) This embodiment relates to a logic circuit having a plurality of nonvolatile latch circuits, which is one embodiment of the disclosed invention. The configuration of the path will be described with reference to FIG.

[0495] FIG. 26 shows a configuration of a latch unit 411 and a data holding unit 401 that holds data from the latch unit. The configuration of a logic circuit having two nonvolatile latch circuits 400 is shown. is called a D-FF and is used, for example, as a register in CPUs and various logic circuits.

[0496] The configuration of the data holding unit 401 is the same as that shown in FIG. 22. The configuration of the latch unit 411 is as follows. In the configuration of the latch unit 411 in FIG. 22, a NAND is used as the first element, and This is an example in which a clocked inverter is used as a transistor.

[0497] The latch unit 411 includes a NAND 412 and a clocked inverter 413. The output of the ND412 is electrically connected to the input of the clocked inverter 413, The output of the inverter 413 is electrically connected to the input of the NAND 412. The latch unit 411 also has an analog switch 431.

[0498] One of the inputs of the NAND 412 is connected to the input of the latch circuit 400 via an analog switch 431. The output of the NAND 412 is electrically connected to a wiring 414 to which an input signal is applied. The NAND gate 400 is electrically connected to a wiring 415 to which an output signal of the NAND gate 400 is applied. Another input of 412 is electrically connected to a wiring through which the signal RSTB is applied. The analog switch 431 is supplied with a clock signal and an inverted signal of the clock signal. A clock signal and an inverted signal of the clock signal are applied to locked inverter 413 .

[0499] The logic circuit shown in FIG. 26 is a nonvolatile latch circuit 400. The nonvolatile latch circuit 400a and the nonvolatile latch circuit 400b are 00a is electrically connected to a wiring 414 to which a potential of an input signal is applied from a previous circuit. The wiring 415 to which the potential of the output signal of the nonvolatile latch circuit 400a is applied is The latch circuit 400b is electrically connected to a wiring 414 to which a potential of an input signal is applied. The nonvolatile latch circuit 400b outputs the nonvolatile latch circuit 400b to a subsequent circuit. It is electrically connected to a wiring 415 that provides the potential of a force signal.

[0500] The analog switch 431 of the nonvolatile latch circuit 400a receives the clock signal φ1 and An inverted signal φ1b of the clock signal is applied to the clocked inverter 413. A clock signal φ2 and an inverted clock signal φ2b are applied to the nonvolatile latch circuit 40. The analog switch 431 of the 0b receives the clock signal φ2 and the inverted signal φ 2b is applied to the clocked inverter 413, which receives the clock signal φ1 and the inverted clock signal φ2. A rotation signal φ1b is applied.

[0501] According to this embodiment, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. A non-volatile latch circuit using a transistor as a switching element for data storage By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data refresh period that is long enough A latch circuit incorporating a holding section can be realized.

[0502] In addition, since data is written by switching transistors, There is no limit to the number of times it can be rewritten. In addition, the write voltage is approximately the threshold voltage of a transistor. This allows operation at a low voltage. In addition, the potential of the data storage section is directly applied, so the data This allows the variation in the amount of charge held as a charge to be kept small, and makes it easier to read out data. It can be done easily.

[0503] By using the non-volatile latch circuit, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible.

[0504] This embodiment mode can be freely combined with other embodiment modes.

[0505] (Embodiment 11) Next, the transistor 402 in the previous embodiment (Embodiment 1, Embodiment 2, etc.) Another example of a method for manufacturing a transistor including an oxide semiconductor that can be used as a This will be described with reference to FIG. 27. In this embodiment, a highly purified oxide semiconductor ( In particular, the case where a top gate electrode is used (amorphous structure) will be described in detail. The following description will be given taking a top-gate transistor as an example. There is no need to.

[0506] First, an insulating layer 202 is formed on a lower substrate 200. Then, an oxide layer is formed on the insulating layer 202. A semiconductor layer 206 is formed (see FIG. 27(A)).

[0507] Here, the lower layer substrate 200 is a substrate in which the lower transistor 160 and the like in the previous embodiment are formed. The above embodiment can be referred to for details. It is preferable that the surface of the lower substrate 200 is as flat as possible. By chemical mechanical polishing (CMP) or the like, the height difference of the surface is reduced to 5 nm or less, preferably 1 nm or less, or the root sum square (RMS) of the surface roughness is 2 nm or less, preferably 0 It is recommended to keep it below .4nm.

[0508] The insulating layer 202 functions as a base, and is different from the insulating layer 168 in the previous embodiment. It can be formed in the same manner as the protective insulating layer 144. For details, see the previous embodiment. Note that the insulating layer 202 is formed so as not to contain hydrogen or water as much as possible. It is desirable to do so.

[0509] The oxide semiconductor layer 206 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O or a ternary The In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides. The material can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. .

[0510] Among them, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. Since it is possible to sufficiently reduce the field current and the field effect mobility is high, It is suitable as a semiconductor material for use in devices.

[0511] A representative example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) mThere are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M is Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn The above composition is derived from the crystal structure. It should be noted that the above is merely an example.

[0512] In this embodiment, the oxide semiconductor layer 206 having an amorphous structure is formed using an In-Ga-Zn-O based metal oxide. The layer is formed by sputtering using a metal oxide target.

[0513] As a metal oxide target for forming the oxide semiconductor layer 206 by a sputtering method For example, the composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] is Alternatively, a metal oxide target such as In2O3:Ga2O3:ZnO may be used. Metal oxide targets with a composition ratio of In2O3:Ga = 1:1:2 [mol ratio] A metal oxide target with a composition ratio of 2O3:ZnO=1:1:4 [molar ratio] was used. It is also possible.

[0514] The relative density of the oxide semiconductor in the metal oxide target is 80% or more, preferably 95% or more. More preferably, the relative density is 99.9% or more. This makes it possible to form the oxide semiconductor layer 206 with a dense structure.

[0515] The oxide semiconductor layer 206 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about several ppm. It is preferable to use a high-purity gas atmosphere in which the concentration is reduced to about several ppb. be.

[0516] When the oxide semiconductor layer 206 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The temperature of the substrate is maintained at 100° C. or higher and 550° C. or lower, preferably 200° C. or higher and 400° C. or lower. The substrate is heated so that the moisture in the processing chamber is removed, and hydrogen, water, etc. are removed. The oxide semiconductor layer 206 is formed by using the above target. The oxide semiconductor layer 206 is formed while the substrate is heated. It is possible to reduce the impurity concentration in the material and to reduce damage caused by sputtering. To remove moisture from inside the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferable. In addition, a turbo pump with a cold trap can be used. Hydrogen, water, etc. can be removed from the processing chamber by evacuating it using a cryopump. Therefore, the impurity concentration in the oxide semiconductor layer 206 can be reduced.

[0517] The oxide semiconductor layer 206 is formed under the following conditions: the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen flow rate ratio 100%) atmosphere, or argon (argon flow ratio 100%) atmosphere, or acid The conditions that can be applied are a mixture of nitrogen and argon. By using a DC power supply, dust (powdery material formed during film formation) can be reduced, and the thickness distribution can be improved. The thickness of the oxide semiconductor layer 206 is preferably 2 nm to 200 nm. However, the thickness is preferably 5 nm to 30 nm depending on the oxide semiconductor material and The appropriate thickness varies depending on the application of the semiconductor device, and the thickness is determined based on the material and application used. The selection can be made depending on the situation.

[0518] Note that before the oxide semiconductor layer 206 is formed by a sputtering method, argon gas is Then, a reverse sputtering process is performed by introducing a gas into the insulating layer 202 to generate plasma, and deposits on the surface of the insulating layer 202 are removed. Here, the reverse sputtering is a method similar to the conventional sputtering. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of modifying the surface is to bombard the surface with ions. A high-frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon. May be applied.

[0519] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 206a is formed.

[0520] The oxide semiconductor layer 206 can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching temperature) are adjusted according to the material so that the layer can be etched into the desired shape. The gas, etching solution, etching time, temperature, etc. are set appropriately. For details, see The oxide semiconductor layer 206 is etched in the same manner as in the above embodiment. The etching of the oxide semiconductor layer can be performed in the same manner as in the etching of the oxide semiconductor layer in the embodiment. The above embodiment may be referred to.

[0521] After that, the oxide semiconductor layer 206a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or a hydroxyl group) from the oxide semiconductor layer 206a. The structure of the oxide semiconductor layer 206a is adjusted, and defects in the oxide semiconductor layer 206a are removed. The temperature of the first heat treatment is, for example, 300° C. or more and 550° C. or less. or 400°C or higher and 550°C or lower.

[0522] The heat treatment is carried out, for example, by placing the lower substrate 200 in an electric furnace using a resistance heating element or the like and heating the lower substrate 200 in a nitrogen atmosphere. The heat treatment can be performed under the conditions of air at 450° C. for one hour. During this time, the oxide semiconductor layer 206a Do not expose to air and prevent contamination with water or hydrogen.

[0523] The heat treatment device is not limited to an electric furnace, and may be any type of heat treatment device, such as heat conduction from a medium such as a heated gas, or A device that heats the workpiece by thermal radiation may be used. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0524] For example, in the first heat treatment, the substrate is placed in an inert gas atmosphere and heated for several minutes. A GRTA process may be performed to remove the substrate from the inert gas atmosphere. This allows high-temperature heat treatment in a short time. It can be applied even under temperature conditions exceeding thermal temperatures.

[0525] During the treatment, the inert gas atmosphere may be switched to an atmosphere containing oxygen. By performing the first heat treatment in an atmosphere containing oxygen, defects due to oxygen vacancies can be reduced. This is because it is possible.

[0526] For example, when an electric furnace is used for the first heat treatment, the atmosphere is changed when the temperature of the heat treatment is decreased. For example, the atmosphere during the heat treatment (constant temperature) can be nitrogen or rare gas (helium). The atmosphere is an inert gas such as fluorine, neon, argon, etc., and when the temperature is lowered, it is switched to an atmosphere containing oxygen. The oxygen-containing atmosphere can be oxygen gas or oxygen gas and nitrogen gas. A gas mixture of the above can be used.

[0527] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing 1,2-dichloroethane (CO), which is the main component, and does not contain water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into heat treatment equipment Purity should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0528] In any case, the first heat treatment reduces impurities and makes the semiconductor i-type or substantially i-type. By forming the oxide semiconductor layer 206a, a transistor with excellent characteristics can be realized. It is possible.

[0529] Note that the first heat treatment is performed on the oxide semiconductor layer 2 before it is processed into the island-shaped oxide semiconductor layer 206a. In that case, the lower substrate 20 is removed from the heating device after the first heat treatment. 0 and undergoes a photolithography process.

[0530] The first heat treatment has the effect of removing hydrogen and water, so the first heat treatment is also called dehydration treatment or dehydration treatment. The dehydration or dehydrogenation treatment may be called hydrogenation treatment or the like. After the formation of the oxide semiconductor layer 206a, a source electrode or a drain electrode is stacked on the oxide semiconductor layer 206a. In addition, such dehydration treatment and dehydrogenation can be performed at the following timing. The chemical treatment may be carried out not only once but also multiple times.

[0531] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. By selectively etching the source or drain electrode 208a, the source or drain The source electrode 208b is formed (see FIG. 27(B)). The process is similar to that for the electrode 142a, drain electrode 142b, etc. The embodiments can be referred to.

[0532] Next, the gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (FIG. 27). (See (C)). For details, please refer to the description of the gate insulating layer in the previous embodiment. It is possible.

[0533] After the gate insulating layer 212 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0 and 350°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. In addition, when the gate insulating layer 212 contains oxygen, the oxide semiconductor layer 206 By supplying oxygen to the oxide semiconductor layer 206a, oxygen vacancies in the oxide semiconductor layer 206a are reduced, and the oxide semiconductor layer 206a is turned into an i-type (intrinsic semiconductor ) or an oxide semiconductor layer that is as close to i-type as possible.

[0534] In this embodiment, the second heat treatment is performed immediately after the formation of the gate insulating layer 212. However, the timing of the second heat treatment is not particularly limited to this.

[0535] Next, a gate electrode 21 is formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a. 27(D) . The gate electrode 214 is formed on the gate insulating layer 212 by a conductive film. After forming a layer, the conductive layer is selectively patterned to form the insulating layer. For details, the description of the gate electrode in the previous embodiment can be referred to. Cut.

[0536] Next, an interlayer insulating layer 216 and an interlayer insulating film 217 are formed on the gate insulating layer 212 and the gate electrode 214. The edge layer 218 is formed (see FIG. 27(E)). The interlayer insulating layer 216 and the interlayer insulating layer 218 are The can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, oxynitride, etc. Inorganic materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The insulating film can be formed using a material containing an insulating material. However, one embodiment of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers.

[0537] It is preferable that the interlayer insulating layer 218 is formed so that its surface is flat. By forming the interlayer insulating layer 218 so as to have a flat surface, a conductive layer is formed on the interlayer insulating layer 218. This is because electrodes, wiring, etc. can be formed suitably.

[0538] Through the above steps, the transistor 250 including the highly purified oxide semiconductor layer 206a is completed. do.

[0539] The transistor 250 shown in FIG. 27(E) is disposed on the lower substrate 200 via the insulating layer 202. The oxide semiconductor layer 206a is electrically connected to the source A source or drain electrode 208a, a source or drain electrode 208b, and an oxide semiconductor A conductor layer 206a, a source electrode or a drain electrode 208a, a source electrode or a drain electrode a gate insulating layer 212 covering the electrode 208b; and a gate electrode 214 on the gate insulating layer 212. An interlayer insulating layer 216 on the gate insulating layer 212 and the gate electrode 214; and an interlayer insulating layer 218.

[0540] In the transistor 250 described in this embodiment, the oxide semiconductor layer 206a is highly purified. Therefore, the hydrogen concentration is 5×10 19 / cm 3 Less than 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 The carrier density of the oxide semiconductor layer 206a is less than that of general silicon. Carrier density in the silicon wafer (1×10 14 / cm 3 A sufficiently low value compared to the (For example, 1×10 12 / cm 3 Less than 1×10 11 / cm 3 (Less than) This makes the off-state current sufficiently small. For example, when the drain voltage V D +1 V or +10V, and the gate voltage V G In the range of -5V to -20V, The off-state current at room temperature is 1×10 -13 In addition, the transistor is normally Therefore, the voltage between the gate and source electrodes is almost zero. The off-state current, i.e., leakage current, is lower than that of a silicon transistor. For example, the leakage current per unit channel width at room temperature is 10 aA / μm or less.

[0541] By using the oxide semiconductor layer 206a which has been highly purified and made intrinsic, Therefore, the off-state current of the transistor can be sufficiently reduced.

[0542] Note that in this embodiment, a transistor However, the disclosed invention should not be construed as being limited to this example. For example, by sufficiently improving the electrical properties of oxide semiconductors, It is also possible to use an oxide semiconductor for all the transistors, including the transistor. In such a case, it is not necessary to have a laminated structure as shown in the above embodiment. For example, a semiconductor device can be formed using a substrate such as a glass substrate.

[0543] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0544] (Embodiment 12) Next, the transistor 402 in the previous embodiment (Embodiment 1, Embodiment 2, etc.) Another example of a method for manufacturing a transistor including an oxide semiconductor that can be used as a This will be described with reference to FIG. 28. In this embodiment, a crystalline region is used as the oxide semiconductor layer. a first oxide semiconductor layer having a crystalline region; and The case where the second oxide semiconductor layer is used will be described in detail. The following description will be given taking a top-gate transistor as an example. It doesn't have to be limited to a type.

[0545] First, an insulating layer 302 is formed on a lower substrate 300. Then, a first An oxide semiconductor layer is formed, and at least a surface of the first oxide semiconductor layer is subjected to a first heat treatment. The region containing the oxide semiconductor layer is crystallized to form a first oxide semiconductor layer 304 (see FIG. 28A). ).

[0546] Here, the lower layer substrate 300 is a substrate in which the lower transistor 160 and the like in the previous embodiment are formed. For details thereof, the above embodiments can be referred to. In this embodiment, the flatness of the surface of the lower substrate 300 is of particular importance. This is because surface flatness is an essential factor for uniform crystal growth. In order to obtain an oxide semiconductor layer with favorable crystallinity, the height difference on the surface is preferably 1 nm or less. 0.2 nm or less, or the root sum of squares (RMS) of the surface roughness is 0.5 nm or less, Preferably, it is 0.1 nm or less.

[0547] The insulating layer 302 functions as a base, and is the same as the insulating layer 168 in the previous embodiment. It can be formed in the same manner as the protective insulating layer 144. For details, see the previous embodiment. Note that the insulating layer 302 is formed so as not to contain hydrogen or water as much as possible. It is desirable to do so.

[0548] The first oxide semiconductor layer 304 is formed in the same manner as the oxide semiconductor layer 206 in the above embodiment. The details of the first oxide semiconductor layer 304 and a method for forming the first oxide semiconductor layer 304 will be described below. The above embodiment may be referred to. However, in this embodiment, In order to intentionally crystallize the first oxide semiconductor layer, a metal oxide substrate that is prone to crystallization is used. It is preferable to form the first oxide semiconductor layer 304 using a target such as ZnO. In addition, even in the case of an In-Ga-Zn-O oxide, for example, the concentration of Zn is The higher the concentration, the easier it is to crystallize, and the ratio of Zn to the total metal elements (In, Ga, Zn) is 60%. The above is preferable for this purpose. The thickness is preferably 3 nm or more and 15 nm or less. However, the thickness may be appropriately determined depending on the oxide semiconductor material and the application of the semiconductor device. The thickness varies depending on the material and the application.

[0549] The temperature of the first heat treatment is 450° C. or higher and 850° C. or lower, preferably 550° C. or higher and 750° C. or lower. The heat treatment time should be between 1 minute and 24 hours. The time varies depending on the type and composition of the oxide semiconductor. It is preferable to use an atmosphere that does not contain oxygen or water. For example, a nitrogen atmosphere with water thoroughly removed is preferable. The atmosphere may be nitrogen, oxygen, or a rare gas (helium, neon, argon, etc.).

[0550] Heat treatment equipment includes electric furnaces, as well as equipment that uses heat conduction from a medium such as heated gas or heat radiation. For example, a GRTA (Gas Ra pid Thermal Anneal) equipment, LRTA (Lamp Rapid Th RTA (Rapid Thermal Anneal) equipment l) Equipment can be used. LRTA equipment includes halogen lamps, metal halide lamps, etc. xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp It is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as benzene or nitrogen. is used.

[0551] By the above-mentioned first heat treatment, at least a region including a surface of the first oxide semiconductor layer is crystallized. The crystalline region extends from the surface of the first oxide semiconductor layer to the inside of the first oxide semiconductor layer. The crystal growth proceeds toward the crystal region. The crystal region may contain plate-like crystals with an average thickness of 2 nm to 10 nm. The oxide semiconductor layer has an ab-plane that is approximately parallel to the surface of the oxide semiconductor layer, and a c-axis that is approximately perpendicular to the surface. In this case, the term "approximately parallel" refers to a state within ±10° of the parallel direction. "Approximately vertical" refers to a state in which the angle is within ±10° from the vertical direction.

[0552] In addition, the first heat treatment forms a crystalline region and removes hydrogen from the first oxide semiconductor layer. It is desirable to remove hydrogen and other substances (including water and hydroxyl groups). Nitrogen and oxygen with a purity of 6N (99.9999%) or more (i.e. impurity concentration of 1ppm or less) The first heat treatment is preferably performed in a nitrogen or rare gas (helium, neon, argon, etc.) atmosphere. More preferably, the purity is 7N (99.99999%) or more (i.e., the concentration of impurities is 0.1 ppm or less). In addition, it is preferable to use ultra-dry air with H2O of 20 ppm or less. Alternatively, the first heat treatment may be performed in ultra-dry air with an H2O concentration of 1 ppm or less.

[0553] In addition, the first heat treatment is performed to form a crystalline region and to supply oxygen to the first oxide semiconductor layer. For example, by changing the heat treatment atmosphere to an oxygen atmosphere, Oxygen can be supplied to the oxide semiconductor layer 1.

[0554] In this embodiment, the first heat treatment is performed in a nitrogen atmosphere at 700° C. for 1 hour. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere is switched to an oxygen atmosphere. The first heat treatment is performed mainly to supply oxygen to the inside of the first oxide semiconductor layer. Since this is a process for forming a region, the removal of hydrogen and other substances and the treatment for the purpose of supplying oxygen must be carried out separately. For example, after heat treatment to remove hydrogen, etc., or treatment to supply oxygen, In addition, it is possible to carry out a heat treatment for crystallization.

[0555] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. Thus, the first oxide semiconductor layer 304 to which oxygen is supplied is obtained.

[0556] Next, a first oxide semiconductor layer 304 having a crystalline region at least in a region including a surface thereof is formed with A second oxide semiconductor layer 305 is formed (see FIG. 28B).

[0557] The second oxide semiconductor layer 305 is formed in the same manner as the oxide semiconductor layer 206 in the above embodiment. The details of the second oxide semiconductor layer 305 and a method for forming the second oxide semiconductor layer 305 will be described below. The above embodiment may be referred to. Note that the second oxide semiconductor layer 305 is It is preferable that the first oxide semiconductor layer 304 is formed thicker than the first oxide semiconductor layer 304. The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are formed so that the sum of their thicknesses is 3 nm to 50 nm. It is preferable to form the oxide semiconductor layer 305 of the second oxide semiconductor material. The appropriate thickness varies depending on the material and application of the semiconductor device. The method may be selected depending on the purpose.

[0558] The second oxide semiconductor layer 305 is made of a material having the same main component as the first oxide semiconductor layer 304. Furthermore, materials with similar lattice constants after crystallization (lattice constant mismatch of 1% or less) are used. In the case where materials having the same main component are used, the bonding of the second oxide semiconductor layer 305 is preferably In the crystallization, crystal growth is likely to proceed using the crystalline regions of the first oxide semiconductor layer 304 as seeds. Furthermore, when the main components are the same, the interface properties and electrical properties are also good. become.

[0559] In addition, when a desired film quality can be obtained by crystallization, the material of the first oxide semiconductor layer 304 may be The second oxide semiconductor layer 305 may be formed using a material whose main component is different from that of the oxide semiconductor layer 302.

[0560] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystalline region is used as a seed for crystal growth to form a second oxide semiconductor layer 306 (FIG. 28). (C))).

[0561] The temperature of the second heat treatment is 450° C. or higher and 850° C. or lower, preferably 600° C. or higher and 700° C. or lower. The heating time of the second heat treatment is from 1 minute to 100 hours, preferably from 5 hours to 100 hours. The heat treatment time is set to 20 hours or less, typically 10 hours. It is preferable that the atmosphere during the process does not contain hydrogen, water, etc.

[0562] The details of the atmosphere and the effects of the second heat treatment are the same as those of the first heat treatment. The heat treatment apparatus that can be used for the first heat treatment is the same as that for the first heat treatment. For example, The inside of the furnace is filled with nitrogen when heating and with oxygen when cooling. Hydrogen and the like can be removed in a nitrogen atmosphere, and oxygen can be supplied in an oxygen atmosphere.

[0563] By performing the above-described second heat treatment, the oxide semiconductor layer 304 is formed. The crystal growth is caused to proceed from the crystalline region to the entire second oxide semiconductor layer 305, so that the second oxide semiconductor A conductor layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like are removed. In addition, the second oxide semiconductor layer 306 to which oxygen is supplied can be formed. The heat treatment can improve the orientation of the crystalline region of the first oxide semiconductor layer 304. be.

[0564] For example, an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 306. In this case, the second oxide semiconductor layer 306 is InGaO3(ZnO). m (m>0 and In2Ga2ZnO7 (In:Ga:Zn:O=2:2 Such crystals may include crystals represented by the formula: The c-axis is oriented so as to be substantially perpendicular to the surface of the second oxide semiconductor layer 306 .

[0565] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be considered as a laminated structure of multiple layers parallel to the a-axis. Specifically, the above crystal is composed of a layer containing In and a layer not containing In ( The layer has a structure in which a Ga or Zn-containing layer is stacked in the c-axis direction.

[0566] In the In-Ga-Zn-O oxide semiconductor crystal, the layer containing In, i.e., The electrical conductivity in the directions parallel to the a-axis and b-axis is good. In the oxide semiconductor crystal of this system, the electrical conduction is mainly controlled by In, and The In 5s orbital of the In has overlap with the adjacent In 5s orbital, which improves the carrier distribution. This is due to the formation of a gap.

[0567] In addition, the first oxide semiconductor layer 304 may have an amorphous region at the interface with the insulating layer 302. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region toward the bottom of the first oxide semiconductor layer, and the In some cases, the amorphous region may be crystallized. Depending on the conditions, the amorphous region may remain.

[0568] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are made of oxide semiconductors having the same main component. In the case where a dielectric material is used, as shown in FIG. 28C, a first oxide semiconductor layer 304 and a second oxide semiconductor layer 305 are formed. In some cases, the oxide semiconductor layer 306 may have the same crystal structure as the oxide semiconductor layer 306 in FIG. In FIG. 3C, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are shown by dotted lines. The boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable. In some cases they may be considered to be the same layer.

[0569] Next, the first oxide semiconductor layer 304 and the The second oxide semiconductor layer 306 is processed into an island-shaped first oxide semiconductor layer 304a and a second oxide semiconductor layer 304b. An oxide semiconductor layer 306a is formed (see FIG. 28D).

[0570] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are etched using a dry etching method. Either etching or wet etching may be used. Of course, a combination of both may also be used. In order to etch the oxide semiconductor layer into a desired shape, a material Etching conditions (etching gas, etching solution, etching time, temperature, etc.) The etching temperature of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is set appropriately. The etching can be performed in a manner similar to the etching of the oxide semiconductor layer in the above embodiment. For details, please refer to the above embodiment.

[0571] Note that a region to be a channel formation region in the oxide semiconductor layer has a flat surface. For example, it is preferable that the height difference of the surface of the second oxide semiconductor layer is such that the second oxide semiconductor layer overlaps with the gate electrode. In the region (channel formation region), the thickness is 1 nm or less (preferably 0.2 nm or less). This is preferable.

[0572] Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. The conductive layer is selectively etched to form the source or drain electrode 308a, The source or drain electrode 308b is formed (see FIG. 28(D)). The electrode 308a and the source or drain electrode 308b are the same as those in the previous embodiment. The source or drain electrode 142a has a shape similar to that of the source or drain electrode 142b. For details, the above embodiment may be referred to.

[0573] In the step shown in FIG. 28D, the first oxide semiconductor layer 304a and the second oxide semiconductor layer On the side of the conductor layer 306a, a source electrode or drain electrode 308a, Alternatively, the crystal layer in contact with the drain electrode 308b may become amorphous.

[0574] Next, a gate insulating layer 312 is formed in contact with a part of the second oxide semiconductor layer 306a. The gate insulating layer 312 can be formed by using a CVD method, a sputtering method, or the like. After that, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b on the gate insulating layer 312 are A gate electrode 314 is formed in a region overlapping with the layer 306a. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed on the gate electrode 314 (FIG. 28(E)). A gate insulating layer 312, a gate electrode 314, an interlayer insulating layer 316 and a layer The interlayer insulating layer 318 can be formed in the same manner as the gate insulating layer in the previous embodiment. For details, please refer to the above embodiment.

[0575] After the gate insulating layer 312 is formed, a third heat treatment is per...

Claims

1. A first transistor, a second transistor, and a capacitor element, one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the capacitive element, a first semiconductor layer having a channel formation region of the first transistor; a first conductive layer disposed above the first semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer disposed above the first conductive layer; a second conductive layer disposed above the first insulating layer and functioning as a gate electrode of the second transistor; a third conductive layer disposed in the same layer as the second conductive layer and electrically connected to the first semiconductor layer; a second semiconductor layer disposed above the second conductive layer and having a channel formation region of the second transistor; a second insulating layer disposed above the second semiconductor layer; a fourth conductive layer disposed above the second insulating layer and electrically connected to the second semiconductor layer; a fifth conductive layer disposed above the second insulating layer; having the first semiconductor layer comprises silicon; the second semiconductor layer includes an oxide semiconductor; The third conductive layer is electrically connected to the fifth conductive layer.

2. A first transistor, a second transistor, and a capacitor element, one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the capacitive element, a first semiconductor layer having a channel formation region of the first transistor; a first conductive layer disposed above the first semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer disposed above the first conductive layer; a second conductive layer disposed above the first insulating layer and functioning as a gate electrode of the second transistor; a third conductive layer disposed in the same layer as the second conductive layer and electrically connected to the first semiconductor layer; a second semiconductor layer disposed above the second conductive layer and having a channel formation region of the second transistor; a second insulating layer disposed above the second semiconductor layer; a fourth conductive layer disposed above the second insulating layer and electrically connected to the second semiconductor layer; a fifth conductive layer disposed above the second insulating layer; having the first semiconductor layer comprises silicon; the second semiconductor layer includes an oxide semiconductor; the fifth conductive layer is disposed in the same layer as the fourth conductive layer, The third conductive layer is electrically connected to the fifth conductive layer.

3. In claim 1 or 2, The fourth conductive layer comprises at least one of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium.

4. In any one of claims 1 to 3, a third transistor and a second capacitance element; the third transistor includes an oxide semiconductor in a channel formation region; a gate electrode of the third transistor is electrically connected to a gate electrode of the second transistor; a third transistor having a source and a drain electrically connected to the second capacitor;

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