Wireless communication circuit

Abstract

A wireless communication circuit (1) comprises an antenna (10), a transmission circuit (2) including an output amplifier (4) that outputs a transmission signal (STx) to the antenna (10), a reception circuit (6) including an LNA (8) to which a reception signal (SRx) is input from the antenna (10), and a matching circuit (7) provided between the antenna (10) and an input of the LNA (8). The LNA (8) includes a MOS input transistor (81) receiving, at the gate, a reception signal (SRx) received from the antenna (10) via the matching circuit (7) and includes a variable capacitor (C2) disposed between the gate and the source of the input transistor (81), the capacitance value of the variable capacitor (C2) being changed between transmission and reception.

Description

[Technical field]

[0001] The present invention relates to a wireless communication circuit using a CMOS process. [Background technology]

[0002] There is a need to use CMOS processes in wireless communication circuits from the viewpoint of cost benefits. In wireless communication circuits, when a transmitting circuit and a receiving circuit are connected to an antenna, loss occurs due to signal leakage from the transmitting circuit to the receiving circuit during transmission. In particular, when a CMOS process is used, the parasitic capacitance of the LNA (Low Noise Amplifier) ​​provided in the receiving circuit tends to be large, resulting in large loss. To prevent this, an antenna switch may be provided between the transmitting circuit and the receiving circuit, but this increases the number of circuit elements, which in turn increases costs.

[0003] In response to this, Patent Document 1 discloses a technique that uses a λ / 4 strip line and a switching diode, controls the switching diode to be on during signal transmission, and sets the receiving side to a high impedance, thereby suppressing attenuation of the transmission output. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-72475 A Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, the loss from the transmitting circuit to the receiving circuit is suppressed without providing an antenna switch, but there is a problem that the cost of providing a strip line increases. For example, when transmitting a 1 GHz signal on a printed circuit board with a relative dielectric constant of 4.9, a transmission line of about 3.4 cm is required, which increases the board size.

[0006] An object of the present disclosure is to solve the above-mentioned problems and to provide a wireless communication circuit capable of suppressing attenuation of transmitted and received signals without providing a switch or a stripline. [Means for solving the problem]

[0007] A wireless communication circuit in one embodiment of the present disclosure comprises an antenna, a transmitting circuit having an output amplifier that outputs a transmitting signal to the antenna, a receiving circuit having an LNA (Low Noise Amplifier) ​​to which a receiving signal from the antenna is input, and a matching circuit provided between the antenna and the input of the LNA, wherein the LNA has a MOS type input transistor that receives at its gate a receiving signal received from the antenna via the matching circuit, and a variable capacitance is provided between the gate and source of the input transistor, the capacitance value of which changes between a transmitting time when the transmitting signal is output and a receiving time when the receiving signal is received. Effect of the Invention

[0008] In the present disclosure, by providing a variable capacitance on the receiving circuit side, whose capacitance value changes between transmission and reception, it is possible to suppress attenuation of the transmitted signal and the received signal with less circuitry than when a switch or stripline is provided. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a wireless communication circuit according to an embodiment of the present invention; [Diagram 2] Circuit diagram showing an example of a variable capacitance [Diagram 3] 1 is a schematic diagram of a wireless communication circuit according to an embodiment of the present invention; [Figure 4] Circuit diagram showing an example of an LNA configuration [Diagram 5] FIG. 13 is a diagram showing the relationship between the capacitance value of a variable capacitor and the strength of a transmitted signal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described. Note that specific numerical values ​​and the like shown in the following embodiment are merely examples for facilitating understanding of the invention, and are not intended to limit the scope of the invention.

[0011] As shown in Fig. 1, the wireless communication circuit 1 includes an antenna 10 for transmitting and receiving a wireless signal, a transmission circuit 2 that outputs a transmission signal STx to the antenna 10, and a reception circuit 6 to which a reception signal SRx from the antenna 10 is input. That is, the antenna 10 is connected to the output of the transmission circuit 2 and the input of the reception circuit 6 by a common signal line N1. The reception circuit 6 includes a matching circuit 7 connected to the antenna 10, and an LNA (Low Noise Amplifier) ​​to which a reception signal is input via the matching circuit 7. In Fig. 1, for example, a transmission processing circuit 3, an output amplifier 4, an LNA 8, and a reception processing circuit 9 are built into an IC (Integrated Circuit), and the other circuits are mounted outside the IC (for example, on a board).

[0012] The wireless communication circuit 1 of the present disclosure is characterized in that a variable capacitance C2 is provided between the gate and source of an input transistor 81 (see FIG. 4) of an LNA 8 described later, the capacitance value of which changes between when a transmission signal is sent from the antenna 10 (hereinafter simply referred to as "when transmitting") and when a reception signal is received from the antenna 10 (hereinafter simply referred to as "when receiving"). More specifically, when transmitting, the variable capacitance C2 and a matching circuit 7 change the capacitance value of the variable capacitance C2. Transmitted signal The capacitance value is set so that a parallel resonant circuit 11 that resonates in parallel at a frequency of 100 MHz is formed. As a result, during transmission, it is possible to reduce the load on the receiving circuit 6 side with respect to the output amplifier 4 of the transmitting circuit 2, which will be described later. That is, the provision of the variable capacitance C2 acts to suppress attenuation of the transmitting signal. On the other hand, the variable capacitance C2 is set so that the capacitance value is substantially 0 (zero) during reception. As a result, there is a feature that during reception, it acts to prevent attenuation of the receiving signal due to the variable capacitance C2.

[0013] A detailed description will be given below with reference to a specific circuit configuration example.

[0014] <Transmitting circuit> As shown in FIG. 1, the transmission circuit 2 includes a transmission processing circuit 3, an output amplifier 4 that amplifies the output of the transmission processing circuit 3, and a load circuit 5 provided between the output amplifier 4 and an antenna 10.

[0015] The transmission processing circuit 3 includes all the circuits necessary for transmitting the transmission signal STx sent from the antenna 10 in a desired format. The design of the transmission processing circuit 3 can be changed according to the format and frequency band of the signal to be transmitted as the transmission signal, the interface standard to which it conforms, etc. As the specific circuit configuration can employ a conventionally known configuration, a detailed description thereof will be omitted here.

[0016] The output amplifier 4 is, for example, a class E amplifier. The configuration of the class E amplifier is not particularly limited, and a wide range of conventionally known circuit configurations can be applied. By using a class E amplifier as the output amplifier 4, the frequency band of the transmission signal STx can be set or changed by the drive frequency of a switch (not shown) inside the output amplifier 4 and the circuit constant of the load circuit 5.

[0017] Fig. 3 shows a more detailed configuration example of the wireless communication circuit 1. In the example of Fig. 3, in addition to the configuration of Fig. 1, an example is shown in which a harmonic suppression circuit 13 is provided between the load circuit 5 and the antenna 10. In the following description, the signal line connecting the output amplifier 4 and the load circuit 5 is designated by N21, and the signal line connecting the load circuit 5 and the harmonic suppression circuit 13 is designated by N22.

[0018] The load circuit 5 includes load inductors L51 and L52 and load capacitances C51 and C52. The load inductor L51 is provided between a power supply VDD and a signal line N21. The load capacitance C51 is provided between the signal line N21 and ground. The load inductor L52 and the load capacitance C52 are connected in series and provided between the signal line N21 and the signal line N22. As described above, the frequency band of the transmission signal STx can be set or changed by the circuit constants of the load inductors L51 and L52 and the load capacitances C51 and C52.

[0019] Note that a configuration other than the class E amplifier (for example, a linear amplifier) ​​may be used as the output amplifier 4. In that case, the configuration of the load circuit 5 is also changed in accordance with the configuration of the output amplifier 4.

[0020] The harmonic suppression circuit 13 is provided between the transmitting circuit 2 and the receiving circuit 6 and the antenna 10, and is a circuit for removing components other than the fundamental wave of the transmission signal STx during transmission. FIG. 3 shows an example of a configuration in which a π-type LC circuit and an L-type LC circuit are combined as the harmonic suppression circuit 13. Note that the harmonic suppression circuit 13 may have other configurations. Also, the harmonic suppression circuit 13 shown in FIG. 1 does not need to be provided.

[0021] <Receiving circuit> The receiving circuit 6 includes a matching circuit 7, a coupling capacitor C1, an LNA 8, and a receiving processing circuit 9.

[0022] The matching circuit 7 is a circuit for transmitting the power of the reception signal SRx to the LNA 8 without loss by converting the impedance of the antenna 10, 50 [Ω], into the complex conjugate of the input impedance of the LNA 8.

[0023] As shown in Fig. 1, the matching circuit 7 includes a capacitance C71 and an inductor L71. The capacitance C71 and the coupling capacitance C1 are connected in series between the signal line N1 and the input of the LNA8. The inductor L71 is provided between the signal line N71, which connects the capacitance C71 and the coupling capacitance C1, and the ground. As a result, the reception signal SRx received by the antenna 10 is input to the LNA8 via the signal line N1, the capacitance C71, and the coupling capacitance C1. The coupling capacitance C1 is a capacitance for cutting the DC component of the reception signal SRx.

[0024] -LNA circuit- FIG. 4 shows an example of the circuit configuration of the LNA 8.

[0025] The LNA 8 includes a MOS input transistor 81 that receives at its gate a reception signal SRx received from the antenna 10 via the matching circuit 7 .

[0026] 4, the input transistor 81 is an N-type transistor, with its gate connected to the input terminal P81 of the LNA 8 and its source connected to ground. In the following description, the signal line connecting the input terminal P81 of the LNA 8 and the gate of the input transistor 81 is designated by the symbol N81.

[0027] The drain of the input transistor 81 is connected to an output terminal P82 of the LNA 8 via a cascode transistor 82. A resistor 83 is connected between a power supply and the output terminal P82. A bias voltage Vb is applied to the gate of the cascode transistor 82. An input bias circuit 84, in which a resistor and a bias power supply are connected in series, is provided between the signal line N81 and ground.

[0028] 1 and 3, the input capacitance of the input transistor 81 formed between the input terminal P81 and the ground is indicated by a dashed line and is labeled C3.

[0029] Furthermore, a variable capacitance C2 is provided between the gate and source of the input transistor 81. In other words, the variable capacitance C2 is provided between the input terminal P81 and ground so as to be in parallel with the input capacitance C3 of the input transistor 81. The capacitance value of the variable capacitance C2 changes between transmission and reception.

[0030] (When sending) As described above, during transmission, the capacitance value of the variable capacitance C2 is set to a capacitance value such that the variable capacitance C2 and the matching circuit 7 form the parallel resonant circuit 11 that resonates in parallel at the transmission frequency ftx of the transmission signal STx.

[0031] Fig. 2 shows an example of the circuit configuration of the variable capacitance C2. In the example of Fig. 2, a plurality of circuit parts, each of which has a capacitance C21 and a MOS transistor T21 as a switch connected in series, are connected in parallel between the signal line N81 and ground. The capacitance value is changed in stages by controlling the on / off of the MOS transistor T21 using a variable capacitance control signal. In this way, by making it possible to change the capacitance value of the variable capacitance C2 in stages, it is possible to accommodate transmission signals STx having different transmission frequencies ftx.

[0032] Here, when the resonant frequency of the parallel resonant circuit 11 is set to the transmission frequency ftx, the transmission frequency is expressed by the following formula (1). In the following formula, the same symbol is given to the sign of the capacitance and the capacitance value, and the same symbol is given to the sign of the inductor and the inductance value. For example, C1 in the formula is the capacitance value of the coupling capacitance C1.

[0033]

number

[0034] Here, if the capacitance value C1 is sufficiently large compared to the capacitance values ​​C2 and C3, the capacitance value C2 of the variable capacitance C2 is expressed by the following equation (2).

[0035]

number

[0036] By setting the variable capacitance control signal to the capacitance value C2 shown in this equation, the input impedance of the LNA can be increased, reducing the load on the receiving circuit side, and suppressing output load losses, thereby maximizing the transmission output.

[0037] Figure 5 shows the results of a simulation in which the capacitance value of the variable capacitance C2 in the circuit of Figure 3 is changed and the change in the transmission signal STx sent from the antenna 10 is plotted. In Figure 5, the transmission frequency is set to 920 [MHz], the capacitance value of the coupling capacitance C1 is set to 1000 [pF], and the capacitance value of the variable capacitance C2 is changed.

[0038] As shown in Fig. 5, when the capacitance value of the variable capacitance C2 is set to 0.4 [pF] by the variable capacitance control signal, the loss due to the input capacitance C3 of the LNA 8 in the receiving circuit 6 is minimized, and as a result, the transmission output of the transmission signal STx is maximized (see the arrow labeled "resonance point" in Fig. 5). More specifically, compared to the case where the variable capacitance C2 is not provided (the capacitance value of the variable capacitance C2 is 0 (zero)), the transmission output of the transmission signal STx is increased by 0.6 [dB].

[0039] (When receiving) As described above, during reception, the capacitance value of the variable capacitance C2 is set so that the capacitance value is substantially 0 (zero). When the variable capacitance C2 is configured as in FIG. 2, all MOS transistors T21 are controlled to be off (a low signal is applied in the case of N-type) by the variable capacitance control signal. This prevents attenuation of the received signal SRx due to the addition of the variable capacitance C2 during reception. Note that, although it is preferable that the capacitance value of the variable capacitance C2 is substantially 0 (zero) during reception, it may be set to another capacitance value smaller than that during transmission.

[0040] As described above, the wireless communication circuit 1 of this embodiment includes the antenna 10, the transmitting circuit 2 including the output amplifier 4 that outputs the transmitting signal STx to the antenna 10, the receiving circuit 6 including the LNA 8 to which the receiving signal SRx from the antenna 10 is input, and the matching circuit 7 provided between the antenna 10 and the input of the LNA 8. The LNA 8 has a MOS type input transistor 81 that receives at its gate the receiving signal SRx received from the antenna 10 via the matching circuit 7, and includes a variable capacitance C2 between the gate and source of the input transistor 81, the capacitance value of which changes between the time of transmission when the transmitting signal STx is output and the time of reception when the receiving signal is received.

[0041] The variable capacitance C2 is preferably set to a capacitance value larger during transmission than during reception. More preferably, the variable capacitance C2 is set so that the variable capacitance C2 and the matching circuit 7 form a parallel resonant circuit 11 that resonates in parallel at the transmission frequency ftx of the transmission signal STx during transmission, and is set to substantially zero during reception.

[0042] As a result, without providing a switch or a stripline as in the prior art between the transmitting circuit and the receiving circuit, the input impedance of the LNA can be increased during transmission, reducing the load on the receiving circuit 6 side for the output amplifier 4 of the transmitting circuit 2, and attenuation of the receiving signal SRx can be prevented during reception. That is, even when the transmitting circuit 2 and the receiving circuit 6 are connected by a common signal line N1 without a switch or stripline from the antenna 10, attenuation of the transmitting signal STx and the receiving signal SRx can be suppressed. That is, without providing a switch or stripline, it is possible to achieve the desired characteristics with a smaller amount of circuitry than if a switch or stripline were provided. [Industrial Applicability]

[0043] The wireless communication circuit of the present disclosure is extremely useful because it can suppress attenuation of transmitted and received signals without providing switches or striplines. [Explanation of symbols]

[0044] 1 Wireless communication circuit 2. Transmitting circuit 4 Output Amplifier 6 Receiving circuit 7 Matching circuit 8 LNA 10 Antennas 81 Input transistor STx Transmit signal SRx Received Signal

Claims

1. The antenna, a transmission circuit including an output amplifier for outputting a transmission signal to the antenna; a receiving circuit including an LNA (Low Noise Amplifier) ​​to which a received signal from the antenna is input; a matching circuit provided between the antenna and an input of the LNA; the LNA has a MOS input transistor which receives at its gate a signal received from the antenna via the matching circuit, a variable capacitance having a capacitance value that is changed between a transmission time when the transmission signal is output and a reception time when the reception signal is received, between the gate and the source of the input transistor; 23. A wireless communication circuit comprising:

2. 2. The wireless communication circuit according to claim 1, The capacitance value of the variable capacitance is set to zero upon receiving the signal.

23. A wireless communication circuit comprising:

3. 2. The wireless communication circuit according to claim 1, a capacitance value of the variable capacitor is changed according to a transmission frequency of a transmission signal during the transmission; 23. A wireless communication circuit comprising:

4. 2. The wireless communication circuit according to claim 1, The variable capacitance includes a circuit in which a plurality of series circuits of a capacitance and a switch are connected in parallel.

23. A wireless communication circuit comprising:

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