Semiconductor Device

Abstract

To improve the performance of semiconductor devices.SOLUTION: A semiconductor device has a field plate section 16 having a high concentration p-type semiconductor region 17, a low concentration p-type semiconductor region 18 with a lower impurity concentration than the high concentration p-type semiconductor region 17, and a high concentration n-type semiconductor region 19. The high concentration p-type semiconductor region 17 is electrically connected to the source region 21, while the high concentration n-type semiconductor region 19 is electrically connected to the drain region 20.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a laterally diffused MOSFET (LDMOSFET: Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor). [Background technology]

[0002] Non-Patent Document 1 describes research into improving the performance of LDMOSFETs. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Author: Tomoyuki Miyoshi, Tohoku University Research Paper "Research on High Performance Lateral Diffused MOSFET for High Voltage Integrated Circuits", Tohoku University Institutional Repository, Degree Award Number "11301-16629" Summary of the Invention [Problem to be solved by the invention]

[0004] In an LDMOSFET, there is a trade-off between increasing the breakdown voltage and reducing the on-resistance. For example, in order to increase the breakdown voltage of an LDMOSFET, it is necessary to lower the impurity concentration of the drift layer. However, lowering the impurity concentration of the drift layer increases the on-resistance. Conversely, if the impurity concentration of the drift layer is increased to reduce the on-resistance, the depletion layer becomes less likely to extend between the source and drain regions. As a result, the distance between the equipotential lines narrows in the drift layer near the source region, increasing the electric field strength, and decreasing the breakdown voltage of the LDMOSFET. Therefore, there is a need for a method to achieve both increasing the breakdown voltage and reducing the on-resistance, which are in a trade-off relationship. [Means for solving the problem]

[0005] In one embodiment, a semiconductor device is provided with a field plate portion having a first semiconductor region of a second conductivity type different from the first conductivity type and a second semiconductor region of the first conductivity type, the first semiconductor region being electrically connected to a source region, while the second semiconductor region being electrically connected to a drain region. Effect of the Invention

[0006] According to one embodiment, the performance of a semiconductor device can be improved. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view illustrating a device structure of a semiconductor device according to an embodiment. [Diagram 2] FIG. 1 is a diagram illustrating a planar layout configuration of a semiconductor device. [Diagram 3] 1 is a double logarithmic graph showing the relationship between breakdown voltage and normalized on-resistance. [Figure 4] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device in the embodiment. [Diagram 5] 5 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 4. [Figure 6] 6 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 7. [Figure 9] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device in the embodiment. [Figure 10] 10 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 11] 11 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 11. [Figure 13]13 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 15. [Figure 17] 17 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 16. [Figure 18] 18 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 17. [Figure 19] 19 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 18. [Figure 20] FIG. 2 is a schematic diagram showing a structural portion of an LDMOSFET in which a special feature has been implemented to improve the breakdown voltage, specifically, a structural portion in a field plate portion in which a special feature has been implemented to improve the breakdown voltage. [Figure 21] FIG. 1A is a schematic diagram illustrating how the equipotential line distribution becomes dense in a configuration that does not adopt the first design point, and FIG. 1B is a schematic diagram illustrating how the equipotential line distribution is less likely to become dense in a configuration that adopts the first design point. [Figure 22] 1A is a schematic diagram illustrating how the equipotential line distribution becomes dense in a configuration that does not adopt the second ingenuity point, and FIG. 1B is a schematic diagram illustrating how the equipotential line distribution is less likely to become dense in a configuration that adopts the second ingenuity point. [Diagram 23] 1 is a graph showing the relationship between the thickness of an insulating film and the breakdown voltage of an LDMOSFET. [Figure 24] FIG. 2 is a diagram showing a schematic distribution of equipotential lines in an insulating film. [Diagram 25] FIG. 13 is a diagram illustrating a schematic distribution of equipotential lines when an insulating film is thin. [Figure 26] FIG. 13 is a diagram illustrating a schematic distribution of equipotential lines when the insulating film is thick. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0009] <Description of Related Art> The related art referred to in this specification is not a publicly known art, but is a technology having a problem that the present inventor has found, and is a technology that is a premise for the present invention.

[0010] For example, as a device structure of an LDMOSFET, there is a technology of providing a drift layer between the source region and the drain region with a lower concentration than the drain region in order to ensure a breakdown voltage between the source region and the drain region. Then, based on this device structure, there is a technology of providing a thick (about 200 nm) LOCOS structure on the surface of the drift layer to ensure the breakdown voltage. In this specification, this technology will be called the first related technology. There is also a technology of providing a groove in the drift layer and providing an STI structure in which an insulating film is embedded in the groove to ensure the breakdown voltage. In this specification, this technology will be called the second related technology. The idea underlying such first related technology and second related technology is the idea of ​​improving the breakdown voltage by alleviating the electric field with the insulating film constituting the LOCOS structure or STI structure, and in order to realize this idea, it is necessary to increase the film thickness of the insulating film constituting the LOCOS structure or STI structure. Therefore, in the first related technology and the second related technology, the manufacturing cost of the LDMOSFET increases.

[0011] However, the more important point is that the idea of ​​improving the breakdown voltage by providing a LOCOS structure or an STI structure in the drift layer is insufficient to achieve a good balance between the improvement of the breakdown voltage and the reduction of the on-resistance, which are in a trade-off relationship. That is, the present inventor has acquired new knowledge that in order to improve the performance of LDMOSFETs, it is necessary to break away from the ideas underlying the first related technology and the second related technology described above. In this way, in order to achieve a good balance between the improvement of the breakdown voltage and the reduction of the on-resistance, which are in a trade-off relationship, a novel idea that is completely different from the ideas underlying the first related technology and the second related technology is required. Then, the present inventor has diligently studied and found that a novel basic idea can achieve a good balance between the improvement of the breakdown voltage and the reduction of the on-resistance, which are in a trade-off relationship, and this point will be described.

[0012] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is not an idea of ​​alleviating the electric field by a thick insulating film such as the LOCOS structure or STI structure, but an idea of ​​preventing the formation of a dense region in the equipotential lines in the drift layer even if the impurity concentration of the drift layer is somewhat increased by utilizing a field plate portion provided above the drift layer. That is, the basic idea of ​​this embodiment is an idea of ​​utilizing the fact that an equipotential line distribution smoothly connected to the uniform equipotential line distribution is induced in the drift layer by forming a uniform equipotential line distribution in which there is no dense region in the field plate portion. As a result, according to the basic idea, even if the impurity concentration of the drift layer is somewhat increased, the formation of a dense region in the drift layer can be suppressed, so that the breakdown voltage can be ensured. That is, according to the basic idea of ​​this embodiment, it is possible to achieve a good balance between the improvement of the breakdown voltage and the reduction of the on-resistance, which are in a trade-off relationship with each other.

[0013] In particular, in the basic idea of this embodiment, by forming a wide depletion layer in the field plate portion, a uniform equipotential line distribution without a dense region is formed in the depletion layer of the field plate portion, and the equipotential line distribution smoothly connected to this uniform equipotential distribution is induced in the depletion layer formed in the drift layer, utilizing such a mechanism.

[0014] An important point in this mechanism is the charge balance between the field plate portion and the drift layer. This is because by appropriately setting the charge balance between the field plate portion and the drift layer, a uniform equipotential line distribution without a dense region can be formed in the depletion layer of the field plate portion, and an equipotential line distribution smoothly connected to this uniform equipotential distribution can be induced in the depletion layer formed in the drift layer.

[0015] Therefore, the basic idea in this embodiment can be said to be the idea of achieving electric field relaxation through the charge balance between the drift layer and the field plate portion provided above the drift layer. That is, the basic idea is the idea of appropriately setting the charge balance between the drift layer and the field plate portion to balance the improvement of breakdown voltage and the reduction of on-resistance, which are in a trade-off relationship with each other. Hereinafter, specific embodiments embodying the basic idea based on such a mechanism will be described.

[0016] <Device Structure of LDMOSFET> FIG. 1 is a cross-sectional view for explaining the device structure of the semiconductor device in this embodiment.

[0017] In FIG. 1, an element isolation region 10 is formed in the semiconductor substrate 1, and an LDMOSFET is formed in the active region surrounded by this element isolation region 10. The LDMOSFET has a drift layer 11 which is an n-type semiconductor layer formed in the semiconductor substrate 1, and a p-type body region 12 which is a p-type semiconductor region in contact with this drift layer 11.

[0018] A gate electrode 14 is formed on the semiconductor substrate 1 via a gate insulating film 13. A field plate portion 16 is formed on the semiconductor substrate 1 via an insulating film 15. The field plate portion 16 is made of a semiconductor region, and is made of a high-concentration p-type semiconductor region 17, a low-concentration p-type semiconductor region 18 having a lower impurity concentration than the high-concentration p-type semiconductor region 17, and a high-concentration n-type semiconductor region 19. The low-concentration p-type semiconductor region 18 is disposed so as to be sandwiched between the high-concentration p-type semiconductor region 17 and the high-concentration n-type semiconductor region 19. Therefore, the field plate portion 16 has a pn junction formed at the junction surface between the low-concentration p-type semiconductor region 18 and the high-concentration n-type semiconductor region 19. Here, the gate electrode 14 is made of, for example, an n-type polysilicon film which is an n-type semiconductor film, and the impurity concentration of the field plate portion 16 is lower than the impurity concentration of the gate electrode 14. The field plate portion 16 is made of, for example, an amorphous semiconductor film such as an amorphous silicon film, or a single crystal semiconductor film such as a single crystal silicon film.

[0019] The thickness of the insulating film 15 is thicker than that of the gate insulating film 13. For example, the thickness of the insulating film 15 is about twice that of the gate insulating film 13. However, the thickness of the insulating film 15 does not necessarily need to be thicker than that of the gate insulating film 13. For example, the thickness of the insulating film 15 may be equal to that of the gate insulating film 13.

[0020] A drain region 20 made of a high-concentration n-type semiconductor region is formed in the drift layer 11. Meanwhile, a source region 21 made of a high-concentration n-type semiconductor region and a p-type body contact region 22 made of a high-concentration p-type semiconductor region are formed in the p-type body region 12.

[0021] An interlayer insulating film 23 is formed so as to cover the LDMOSFET configured in this manner, and a plurality of plugs 24 are formed in the interlayer insulating film 23, penetrating the interlayer insulating film 23. The plurality of plugs 24 include a "plug 24A" electrically connected to the p-type body contact region 22, a "plug 24B" electrically connected to the source region 21, a "plug 24C" electrically connected to the high-concentration p-type semiconductor region 17 of the field plate portion 16, a "plug 24D" electrically connected to the high-concentration n-type semiconductor region 19 of the field plate portion 16, and a "plug 24E" electrically connected to the drain region 20.

[0022] 1, a wiring 25A and a wiring 25B are formed on the interlayer insulating film 23 on which the multiple plugs 24 are formed. The wiring 25A is connected to "plug 24A", "plug 24B" and "plug 24C". On the other hand, the wiring 25B is electrically connected to "plug 24D" and "plug 24E".

[0023] 1, the high-concentration p-type semiconductor region 17 of the field plate portion 16 is electrically connected to the source region 21 and the p-type body contact region 22. On the other hand, the high-concentration n-type semiconductor region 19 of the field plate portion 16 is electrically connected to the drain region 20.

[0024] Here, for example, a ground potential (0V) is applied to the source region 21 and the p-type body contact region 22. Therefore, "0V" is applied to the high-concentration p-type semiconductor region 17 of the field plate portion 16 and the low-concentration p-type semiconductor region 18 electrically connected to the high-concentration p-type semiconductor region 17. In contrast, for example, a positive potential of 80V or more is applied to the drain region 20. Therefore, a "positive potential of 80V or more" is applied to the high-concentration n-type semiconductor region 19 of the field plate portion 16.

[0025] At this time, when "0 V" (the first potential) is supplied to the source region 21 and a positive potential (the second potential) higher than "0 V" is supplied to the drain region 20, the field plate portion 16 includes a depleted region. Specifically, the low-concentration p-type semiconductor region 18 is depleted.

[0026] <Operation of LDMOSFET> Subsequently, with reference to FIG. 1, the operation of the LDMOSFET will be described.

[0027] First, the on-operation of the LDMOSFET will be described. In FIG. 1, for example, with "0 V" applied to the source region 21 and a positive potential of "80 V or more" applied to the drain region 20, a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 14. As a result, a channel composed of an n-type inversion layer is formed on the surface of the p-type body region 12 located below the gate electrode 14 through the gate insulating film 13. Thereby, electrons flow through the path of source region 21 → channel (n-type inversion layer) → drift layer 11 → drain region 20. In other words, current flows through the path opposite to the above-described path. Thereby, the LDMOSFET is turned on.

[0028] Next, the off operation of the LDMOSFET will be described. In FIG. 1, a gate voltage smaller than the threshold voltage is applied to the gate electrode 14 while a current is flowing through the LDMOSFET. As a result, the channel (n-type inversion layer) formed on the surface of the p-type body region 12 disappears. This blocks the path through which electrons flow from the source region 21 to the drain region 20, and the LDMOSFET turns off. At this time, since the source region 21, the p-type body contact region 22, and the p-type body region 12 are electrically connected, "0 V" is also applied to the p-type body region 12. On the other hand, since the drift layer 11 is electrically connected to the drain region 20, "a positive potential of 80 V or more" is applied to the drift layer 11. This means that a reverse bias is applied to the pn junction formed on the boundary surface between the p-type body region 12 and the drift layer 11. As a result, a depletion layer extends from the pn junction surface to both the p-type body region 12 and the drift layer 11, and this depletion layer ensures the breakdown voltage between the source region 21 and the drain region 20.

[0029] However, if the impurity concentration of the drift layer 11 is increased in order to reduce the on-resistance, the extension of the depletion layer is suppressed, and the electric field strength in the depletion layer increases, making it difficult to ensure the breakdown voltage. However, if the impurity concentration of the drift layer 11 is reduced, an increase in the on-resistance when the LDMOSFET is turned on becomes apparent.

[0030] In this regard, in this embodiment, the above-mentioned basic idea is adopted in order to achieve both the improvement of breakdown voltage and the reduction of on-resistance, which are in a trade-off relationship, at a high level. Specifically, as shown in FIG. 1, the high-concentration p-type semiconductor region 17 of the field plate portion 16 is electrically connected to the source region 21. On the other hand, the high-concentration n-type semiconductor region 19 of the field plate portion 16 is electrically connected to the drain region. This means that a reverse bias is applied to the pn junction formed at the junction surface between the low-concentration p-type semiconductor region 18 and the high-concentration n-type semiconductor region 19 in the field plate portion 16. As a result, a wide depletion layer is formed in the low-concentration p-type semiconductor region 18. As explained in the above-mentioned basic idea, a uniform equipotential distribution without a dense region can be formed in the depletion layer of the field plate portion, and an equipotential distribution smoothly connected to the uniform equipotential distribution is induced in the depletion layer formed in the drift layer. Therefore, even if the impurity concentration of drift layer 11 is somewhat increased, it is possible to prevent the formation of a region where equipotential lines are dense in drift layer 11, thereby ensuring the breakdown voltage. In other words, when the basic idea of ​​this embodiment is applied to the device structure of an LDMOSFET, it is possible to achieve a good balance between improved breakdown voltage and reduced on-resistance, which are in a trade-off relationship with each other.

[0031] <Layout configuration> FIG. 2 is a diagram illustrating a schematic planar layout configuration of the semiconductor device.

[0032] The cross-sectional view taken along line AA in Fig. 2 corresponds to Fig. 1. In Fig. 2, components with the same reference numerals as in Fig. 1 correspond to the components shown in Fig. 1.

[0033] 2, in plan view, the wiring 25A includes a "first protruding portion" protruding from the "plug 24C" toward the wiring 25B. Similarly, in plan view, the wiring 25B includes a "second protruding portion" protruding from the "plug 24D" toward the wiring 25A.

[0034] Here, the width L1 of the "first protruding portion" shown in Figures 1 and 2 is greater than "0". This allows for electric field relaxation at the end of the high-concentration p-type semiconductor region 17. Similarly, the width L2 of the "second protruding portion" shown in Figures 1 and 2 is also greater than "0". This allows for electric field relaxation at the end of the high-concentration n-type semiconductor region 19.

[0035] From the viewpoint of alleviating the electric field at the end of the high-concentration p-type semiconductor region 17, it is desirable that the width L1 of the "first protruding portion" is large, and from the viewpoint of alleviating the electric field at the end of the high-concentration n-type semiconductor region 19, it is desirable that the width L2 of the "second protruding portion" is also large. However, if the widths L1 and L2 are made too large, the distance between the wiring 25A and the wiring 25B becomes narrow, and as a result, the distance between the equipotential lines formed between the wiring 25A and the wiring 25B becomes narrow, and the breakdown voltage of the semiconductor device decreases. For this reason, for example, it is desirable that the width L1 of the "first protruding portion" and the width L2 of the "second protruding portion" are each 0.4 μm or more and 1.0 μm or less.

[0036] <Features of this embodiment> Next, features of this embodiment will be described.

[0037] The feature of this embodiment is that, for example, in FIG. 1, the LDMOSFET is configured so that a wide depletion layer is formed in the field plate section 16 provided above the drift layer 11 when a potential difference is provided between the source region 21 and the drain region 20. Specifically, as shown in FIG. 1, the field plate section 16 is configured from a high-concentration p-type semiconductor region 17, a low-concentration p-type semiconductor region 18, and a high-concentration n-type semiconductor region 19, and the low-concentration p-type semiconductor region 18 is sandwiched between the high-concentration p-type semiconductor region 17 and the high-concentration n-type semiconductor region 19. The high-concentration p-type semiconductor region 17 and the source region 21 are electrically connected, and the high-concentration n-type semiconductor region 19 and the drain region 20 are electrically connected. As a result, a reverse bias is applied to the pn junction formed by the low-concentration p-type semiconductor region 18 and the high-concentration n-type semiconductor region 19, so that the low-concentration p-type semiconductor region 18 is depleted.

[0038] This makes it possible to form a uniform equipotential distribution without any dense regions in the depletion layer of field plate portion 16, and as a result, an equipotential distribution smoothly connected to this uniform equipotential distribution is induced in the depletion layer formed in drift layer 11. Therefore, even if the impurity concentration of drift layer 11 is somewhat increased, it is possible to suppress the formation of a region where the equipotential lines are dense in drift layer 11, and therefore it is possible to ensure the withstand voltage. In other words, according to the feature of this embodiment, it is possible to achieve a good balance between an improvement in withstand voltage and a reduction in on-resistance, which are in a trade-off relationship with each other.

[0039] In particular, in this embodiment, it is important that the direction in which the depletion layer in the field plate portion 16 extends is opposite to the direction in which the depletion layer in the drift layer 11 extends in Fig. 1. That is, in the field plate portion 16, the depletion layer extends in a direction (leftward in Fig. 1) from the junction surface between the low-concentration p-type semiconductor region 18 and the high-concentration n-type semiconductor region 19 toward the inside of the low-concentration p-type semiconductor region 18. On the other hand, in the drift layer 11, the depletion layer extends in a direction (rightward in Fig. 1) from the junction surface between the drift layer 11 and the p-type body region 12 toward the inside of the drift layer 11. This makes it easier for the equipotential lines in the depletion layer formed in the field plate portion 16 and the equipotential lines in the depletion layer formed in the drift layer 11 to be smoothly connected. In other words, due to the configuration in which the depletion layer extends in the reverse direction, the uniform equipotential line distribution in the depletion layer formed in the field plate portion 16 makes it easier to induce in the drift layer 11 a distribution of equipotential lines that are smoothly connected so that no areas where the equipotential lines are dense are formed.

[0040] Furthermore, it is important to uniform the equipotential line distribution in the depletion layer formed in the field plate portion 16, and from this viewpoint, it is desirable to configure the field plate portion 16 from an amorphous semiconductor film, such as an amorphous silicon film, or a single crystal semiconductor film, such as a single crystal silicon film, rather than a polycrystalline semiconductor film, such as a polycrystalline silicon film. This is because, in a polycrystalline semiconductor film, grain boundaries of non-uniform size exist, making it difficult to progress depletion uniformly, which means that it is difficult to generate a uniform equipotential line distribution in the depletion layer.

[0041] Next, a description will be given of simulation results that support the superiority of the LDMOSFET in this embodiment. Fig. 3 is a double logarithmic graph showing the relationship between the breakdown voltage (BVDSS) and the normalized on-resistance (relative value). In Fig. 3, "Graph A" is a graph representing the first related technology, and "Graph B" is a graph representing the second related technology. Meanwhile, "Graph C" is a graph representing this embodiment.

[0042] For example, LDMOSFETs are used as transistors for controlling power. In this case, it is important to improve the breakdown voltage between the source region and the drain region and to reduce the on-resistance. In this regard, as shown in FIG. 3, in the first related technology and the second related technology, in a breakdown voltage region exceeding 80 V, the trade-off relationship between the breakdown voltage between the source region and the drain region and the on-resistance is different from the slope of a low breakdown voltage less than 80 V, and it is found that it becomes even more difficult to achieve both an improvement in breakdown voltage and a reduction in on-resistance.

[0043] In contrast, as shown in Fig. 3, in this embodiment, a remarkable effect of reducing the on-resistance can be obtained even in a withstand voltage region exceeding 90 V while maintaining the withstand voltage. Specifically, according to this embodiment, an effect of reducing the on-resistance by about 20% compared to the second related technology can be obtained while obtaining a withstand voltage of 90 V. Thus, the LDMOSFET in this embodiment can be said to be extremely excellent in that it can achieve both an improvement in withstand voltage and a reduction in on-resistance at a high level.

[0044] Next, further advantages of this embodiment will be described.

[0045] For example, the first and second related techniques are techniques for improving the breakdown voltage by alleviating the electric field with an insulating film disposed below a field plate portion, such as a LOCOS structure or an STI structure, and therefore require the insulating film to be thick, which means that the manufacturing costs of semiconductor devices including LDMOSFETs will increase.

[0046] In contrast, the present embodiment has a technical idea of ​​preventing dense regions from being formed in the equipotential distribution formed in the depletion layer of the drift layer 11 based on the uniform equipotential distribution formed in the depletion layer of the field plate portion 16. In other words, the technical idea of ​​the present embodiment can be said to be an idea of ​​alleviating the electric field by the charge balance between the field plate portion 16 and the drift layer 11. For this reason, the present embodiment does not require an extremely thick insulating film, and an insulating film having a thickness of, for example, about the gate insulating film 13 may be used. This means that the LDMOSFET embodying the technical idea of ​​the present embodiment can reduce the manufacturing cost. In other words, the present embodiment is very excellent in that it not only provides the performance advantage of being able to achieve both improved breakdown voltage and reduced on-resistance, but also provides the advantage of reducing the manufacturing cost.

[0047] Furthermore, in this embodiment, since the charge balance between the field plate portion 16 and the drift layer 11 is achieved to facilitate depletion, depletion can be caused quickly even if the drain voltage applied to the drain region 20 is low. Therefore, the feedback capacitance (Crss) between the gate electrode 14 and the drain region 20 can be reduced. Since the larger the feedback capacitance, the slower the switching speed and the larger the switching loss, the LDMOSFET in this embodiment, which can reduce the feedback capacitance, has the advantage of reducing the risk of power loss and erroneous turn-on.

[0048] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0049] Here, as described above, from the viewpoint of generating a uniform equipotential distribution in the depletion layer formed in field plate portion 16, it is desirable to configure field plate portion 16 from an amorphous semiconductor film or a single crystal semiconductor film rather than a polycrystalline semiconductor film.

[0050] Therefore, a method for manufacturing a semiconductor device in which field plate portion 16 is made of an amorphous silicon film will be described as a "first semiconductor device manufacturing method," while a method for manufacturing a semiconductor device in which field plate portion 16 is made of a single crystal silicon film will be described as a "second semiconductor device manufacturing method."

[0051] <<First manufacturing method for semiconductor device>> First, as shown in FIG. 4, an element isolation region 10 is formed in a semiconductor substrate 1, and then, for example, by using a photolithography technique and an ion implantation method, a drift layer 11 and a p-type body region 12 are formed inside the semiconductor substrate 1. The drift layer 11 is formed by introducing phosphorus, which is an n-type impurity (donor), into the semiconductor substrate 1. On the other hand, the p-type body region 12 is formed by introducing boron, which is a p-type impurity (acceptor), into the semiconductor substrate 1. Thereafter, for example, by using a thermal oxidation method, a gate insulating film 13 made of a silicon oxide film is formed in a first region on the surface of the semiconductor substrate 1, and an insulating film 15 made of a silicon oxide film is formed in a second region on the surface of the semiconductor substrate 1. This insulating film 15 is formed to have a thickness larger than that of the gate insulating film 13.

[0052] 5, for example, by using a CVD (Chemical Vapor Deposition) method, an amorphous silicon film 30 is formed on the gate insulating film 13 and the insulating film 15. Then, by using an ion implantation method, boron, which is a p-type impurity, is introduced into the amorphous silicon film 30.

[0053] 6, photolithography and ion implantation are used to introduce phosphorus, which is an n-type impurity, into the amorphous silicon film 30 formed in the first region of the semiconductor substrate 1. At this time, the amorphous silicon film 30 may be converted into polysilicon in the region of the amorphous silicon film 30 into which phosphorus, which is an n-type impurity, is introduced. In this way, the amorphous silicon film 30 formed in the first region becomes an n-type amorphous silicon film or an n-type polysilicon film, while the amorphous silicon film 30 formed in the second region becomes a p-type amorphous silicon film.

[0054] 7, the amorphous silicon film 30 is patterned using photolithography and etching techniques. As a result, the gate electrode 14 can be formed on the gate insulating film 13, and the field plate portion 16 can be formed on the insulating film 15. At this stage, the field plate portion 16 is composed of a low-concentration p-type semiconductor region 18.

[0055] Next, as shown in Fig. 8, photolithography and ion implantation are used to form a high-concentration p-type semiconductor region 17 and a high-concentration n-type semiconductor region 19 in the field plate portion 16. The high-concentration p-type semiconductor region 17 can be formed by introducing boron, which is a p-type impurity, into the field plate portion 16. On the other hand, the high-concentration n-type semiconductor region 19 can be formed by introducing phosphorus, which is an n-type impurity, into the field plate portion 16. As a result, the field plate portion 16 is composed of the high-concentration p-type semiconductor region 17, the low-concentration p-type semiconductor region 18, and the high-concentration n-type semiconductor region 19.

[0056] Then, by using photolithography and ion implantation, a drain region 20 is formed in the drift layer 11, and a source region 21 and a p-type body contact region 22 are formed in the p-type body region 12. The drain region 20 and the source region 21 can be formed by introducing phosphorus, which is an n-type impurity, while the p-type body contact region 22 can be formed by introducing boron, which is a p-type impurity.

[0057] After the LDMOSFET is formed in this manner, a wiring process is carried out. Specifically, as shown in Fig. 1, an interlayer insulating film 23 is formed so as to cover the LDMOSFET. Then, a plurality of contact holes are formed in the interlayer insulating film 23 by using photolithography and etching techniques, and then a conductor film is embedded in each of the plurality of contact holes to form a plurality of plugs 24. Next, a wiring 25A and a wiring 25B are formed on the interlayer insulating film 23 in which the plurality of plugs 24 have been formed.

[0058] 1, high-concentration p-type semiconductor region 17 of field plate portion 16 is electrically connected to source region 21 and p-type body contact region 22 by plugs 24A-24C and wiring 25A. Meanwhile, high-concentration n-type semiconductor region 19 of field plate portion 16 is electrically connected to drain region 20 by plugs 24D-24E and wiring 25B. In this manner, an LDMOSFET having the field plate structure of this embodiment can be manufactured.

[0059] <<Second manufacturing method of semiconductor device>> First, as shown in FIG. 9, an SOI substrate 1A having a support substrate 40, an insulating film 15 formed on the support substrate 40, and a single crystal silicon layer 50 formed on the insulating film 15 is prepared.

[0060] Next, as shown in FIG. 10, by using photolithography and etching techniques, element isolation trenches 60 are formed in the SOI substrate 1A.

[0061] Then, as shown in FIG. 11, an insulating film is embedded in the element isolation trenches 60 to form element isolation regions 10 in the SOI substrate 1A.

[0062] 12, a drift layer 11 and a p-type body region 12 are formed inside the SOI substrate 1A by using a photolithography technique and an ion implantation method. The drift layer 11 is formed by introducing phosphorus, which is an n-type impurity (donor), into the SOI substrate 1A. On the other hand, the p-type body region 12 is formed by introducing boron, which is a p-type impurity (acceptor), into the SOI substrate 1A.

[0063] Thereafter, as shown in FIG. 13, boron, which is a p-type impurity, is introduced into the single crystal silicon layer 50 by using photolithography and ion implantation.

[0064] Next, as shown in Fig. 14, the surface of the element isolation region 10 is recessed by using photolithography and etching techniques. Thereafter, as shown in Fig. 15, the single crystal silicon layer 50 is patterned by using photolithography and etching techniques. This allows the field plate portion 16 to be formed on the insulating film 15. At this stage, the field plate portion 16 is composed of a low-concentration p-type semiconductor region 18.

[0065] Next, for example, by using an etch-back technique, the insulating film 15 exposed from the field plate portion 16 is removed as shown in Fig. 16. Then, for example, by using a thermal oxidation method, a gate insulating film 13 is formed in the region from which the insulating film 15 has been removed as shown in Fig. 17. Furthermore, for example, by using a CVD method, a polysilicon film is formed so as to cover the SOI substrate 1A, and the polysilicon film is patterned by using a photolithography technique and an etching technique. As a result, a gate electrode 14 can be formed on the gate insulating film 13.

[0066] Next, as shown in Fig. 18, photolithography and ion implantation are used to form a high-concentration p-type semiconductor region 17 and a high-concentration n-type semiconductor region 19 in the field plate portion 16. The high-concentration p-type semiconductor region 17 can be formed by introducing boron, which is a p-type impurity, into the field plate portion 16. On the other hand, the high-concentration n-type semiconductor region 19 can be formed by introducing phosphorus, which is an n-type impurity, into the field plate portion 16. As a result, the field plate portion 16 is composed of the high-concentration p-type semiconductor region 17, the low-concentration p-type semiconductor region 18, and the high-concentration n-type semiconductor region 19.

[0067] Then, by using photolithography and ion implantation, a drain region 20 is formed in the drift layer 11, and a source region 21 and a p-type body contact region 22 are formed in the p-type body region 12. The drain region 20 and the source region 21 can be formed by introducing phosphorus, which is an n-type impurity, while the p-type body contact region 22 can be formed by introducing boron, which is a p-type impurity.

[0068] After the LDMOSFET is formed in this manner, a wiring process is carried out. Specifically, as shown in Fig. 19, an interlayer insulating film 23 is formed so as to cover the LDMOSFET. Then, a plurality of contact holes are formed in the interlayer insulating film 23 by using photolithography and etching techniques, and then a conductor film is embedded in each of the plurality of contact holes to form a plurality of plugs 24. Next, a wiring 25A and a wiring 25B are formed on the interlayer insulating film 23 in which the plurality of plugs 24 have been formed.

[0069] 19, high-concentration p-type semiconductor region 17 of field plate portion 16 is electrically connected to source region 21 and p-type body contact region 22 by plugs 24A-24C and wiring 25A. Meanwhile, high-concentration n-type semiconductor region 19 of field plate portion 16 is electrically connected to drain region 20 by plugs 24D-24E and wiring 25B. In this manner, an LDMOSFET having the field plate structure of this embodiment can be manufactured.

[0070] <Further ideas for improving pressure resistance> As a result of extensive research into further improving the breakdown voltage of LDMOSFETs, the present inventors have come up with several ideas for making it difficult for regions where equipotential lines are dense to be formed, as described below. These ideas will now be described.

[0071] FIG. 20 is a schematic diagram showing a structural portion of an LDMOSFET in which improvements have been made to improve the breakdown voltage. Specifically, it is a schematic diagram showing a structural portion in field plate portion 16 in which improvements have been made to improve the breakdown voltage.

[0072] 20, the devised point regarding the high-concentration p-type semiconductor region 17 surrounded by "circle A" is the "first devised point," and the devised point regarding the high-concentration n-type semiconductor region 19 surrounded by "circle B" is the "second devised point." Furthermore, the devised point regarding the insulating film 15 surrounded by "circle C" is the "third devised point." Each of the above three devised points will be described below.

[0073] <<First improvement point>> 20, the first ingenuity is that while low-concentration p-type semiconductor region 18 of field plate portion 16 contacts insulating film 15, a part of low-concentration p-type semiconductor region 18 is interposed between the bottom of high-concentration p-type semiconductor region 17 and insulating film 15. In other words, the first ingenuity is that the thickness of high-concentration p-type semiconductor region 17 is smaller than the thickness of field plate portion 16, and high-concentration p-type semiconductor region 17 is not in contact with insulating film 15.

[0074] This makes it difficult for a region where the equipotential lines are densely distributed to be formed on the source end side (left side) of the field plate portion 16, thereby improving the breakdown voltage of the LDMOSFET.

[0075] The qualitative reasons for this will be explained below.

[0076] Fig. 21 is a diagram illustrating how the first ingenuity point makes it difficult for dense regions to form in the equipotential line distribution. In particular, Fig. 21(a) is a schematic diagram illustrating how the equipotential line distribution becomes dense in a configuration that does not employ the first ingenuity point, and Fig. 21(b) is a schematic diagram illustrating how the equipotential line distribution becomes difficult to become dense in a configuration that employs the first ingenuity point.

[0077] Specifically, in Fig. 21(a), the high-concentration p-type semiconductor region 17 reaches the insulating film 15. In this case, the impurity concentration of the high-concentration p-type semiconductor region 17 is high, and considering that the equipotential lines do not enter the high-concentration p-type semiconductor region 17, the equipotential line distribution shown by the thick lines becomes dense. That is, in Fig. 21(a), the equipotential line interval becomes narrow, resulting in electric field concentration and making the breakdown voltage of the LDMOSFET more likely to decrease.

[0078] 21(b), the high-concentration p-type semiconductor region 17 does not reach the insulating film 15. In this case, the impurity concentration of the high-concentration p-type semiconductor region 17 is high, and considering that the equipotential lines do not enter the high-concentration p-type semiconductor region 17, the equipotential line distribution shown by the thick lines is less likely to be dense than in FIG. 21(a). That is, in FIG. 21(b), the equipotential line intervals are wider, which suppresses electric field concentration and improves the breakdown voltage of the LDMOSFET.

[0079] As shown in FIGS. 21(a) and 21(b), the first improvement point makes it difficult for a region where the equipotential lines are dense to be formed, and as a result, it is possible to improve the breakdown voltage of the LDMOSFET.

[0080] <<Second point of improvement>> 20, the second ingenuity is that the low-concentration p-type semiconductor region 18 of the field plate portion 16 is in contact with the insulating film 15, and the bottom of the high-concentration n-type semiconductor region 19 is also in contact with the insulating film 15. In other words, the second ingenuity is that the thickness of the high-concentration n-type semiconductor region 19 is equal to the thickness of the field plate portion 16, and the high-concentration n-type semiconductor region 19 reaches the insulating film 15.

[0081] This makes it difficult for a region where the equipotential lines are densely distributed to be formed on the drain end side (right side) of the field plate portion 16, thereby improving the breakdown voltage of the LDMOSFET.

[0082] The qualitative reasons for this will be explained below.

[0083] For example, considering that the first improvement point described above makes it difficult for a region where the equipotential lines are dense to be formed on the source end side, it can be thought that by adopting a configuration similar to the first improvement point on the drain end side, it is possible to make it difficult for a region where the equipotential lines are dense to be formed on the drain end side of field plate portion 16, thereby improving the breakdown voltage of the LDMOSFET.

[0084] However, due to the presence of drain region 20 composed of a high-concentration n-type semiconductor region below high-concentration n-type semiconductor region 19 on the drain end side of field plate portion 16, adopting the above-mentioned second design point rather than the first design point makes it less likely that a region with a dense equipotential line distribution will be formed on the drain end side of field plate portion 16, and the breakdown voltage of the LDMOSFET can be improved.

[0085] The qualitative reasons for this will be explained below.

[0086] Fig. 22 is a diagram illustrating how the second ingenuity point makes it difficult for dense regions to form in the equipotential line distribution. In particular, Fig. 22(a) is a schematic diagram illustrating how the equipotential line distribution becomes dense in a configuration that does not employ the second ingenuity point, and Fig. 22(b) is a schematic diagram illustrating how the equipotential line distribution becomes difficult to become dense in a configuration that employs the second ingenuity point.

[0087] Specifically, in FIG. 22(a), the high-concentration n-type semiconductor region 19 does not reach the insulating film 15. In this case, the impurity concentration of the high-concentration n-type semiconductor region 19 and the impurity concentration of the drain region 20 are high, and considering that the equipotential lines do not enter the high-concentration n-type semiconductor region 19 and the drain region 20, the equipotential line distribution is bent. As a result, the equipotential lines enter between the high-concentration n-type semiconductor region 19 and the drain region 20, forming a region where the equipotential line distribution is dense. As a result, electric field concentration occurs, and the breakdown voltage of the LDMOSFET is likely to decrease.

[0088] 22(b), the high-concentration n-type semiconductor region 19 reaches the insulating film 15. In this case, the equipotential lines do not enter between the high-concentration n-type semiconductor region 19 and the drain region 20, so the equipotential line distribution is less likely to become dense than in FIG. 22(a). That is, in FIG. 22(b), the equipotential lines do not enter between the high-concentration n-type semiconductor region 19 and the drain region 20, so that a region where the equipotential line distribution becomes dense is not formed, so that electric field concentration is suppressed and the breakdown voltage of the LDMOSFET can be improved.

[0089] In this manner, as shown in FIGS. 22(a) and 22(b), according to the second improvement point, it is difficult to form an area where the equipotential lines are densely distributed, and as a result, it is understood that the breakdown voltage of the LDMOSFET can be improved.

[0090] <<Third point>> FIG. 23 is a graph showing the relationship between the thickness (TOX) of the insulating film 15 and the breakdown voltage (BVDSS) of the LDMOSFET. The thickness of the gate insulating film 13 is, for example, 25 nm. In this case, as shown in FIG. 23, it is found that the thickness of the insulating film 15 is about 50 nm, which is thicker than the gate insulating film, is optimal from the viewpoint of improving the breakdown voltage. For example, since it is desirable for the gate insulating film 13 to be thin from the viewpoint of reducing channel resistance, it is found that satisfying the relationship of thickness of the gate insulating film 13<thickness of the insulating film 15 is advantageous for achieving both an improvement in the breakdown voltage and a reduction in the on-resistance. Specifically, it is found that setting the thickness of the insulating film 15 to about twice the thickness of the gate insulating film 13 is useful for achieving both an improvement in the breakdown voltage and a reduction in the on-resistance, which are in a trade-off relationship, at a high level.

[0091] Here, from the graph shown in FIG. 23, the reason why the withstand voltage decreases when the thickness of the insulating film 15 is too thin, while the withstand voltage decreases when the thickness of the insulating film 15 is too thick, will be described.

[0092] Fig. 24 is a diagram showing a schematic distribution of equipotential lines in the insulating film 15. As shown in Fig. 24, the equipotential lines are inclined straight lines inside the insulating film 15. On the basis of this, the reason why the breakdown voltage decreases when the insulating film 15 is too thin, while the breakdown voltage also decreases when the insulating film 15 is too thick, will be described with reference to Figs. 25 and 26.

[0093] Fig. 25 is a diagram showing a schematic view of the equipotential line distribution when the insulating film 15 is thin. It can be seen qualitatively from Fig. 25 that as the thickness of the insulating film 15 becomes thinner, the equipotential line distribution shifts toward the source side, and as a result, the equipotential lines become denser on the source side, making electric field concentration more likely to occur. In other words, if the insulating film 15 is too thin, electric field concentration is more likely to occur on the source side, and a decrease in breakdown voltage caused by this electric field concentration becomes apparent.

[0094] In contrast, Fig. 26 is a diagram showing a schematic view of the equipotential line distribution when the insulating film 15 is thick. Qualitatively, Fig. 26 shows that as the insulating film 15 becomes thicker, the equipotential line distribution shifts toward the drain side, and as a result, the equipotential lines become denser on the drain side, making electric field concentration more likely to occur. In other words, if the insulating film 15 is too thick, electric field concentration is more likely to occur on the drain side, and a decrease in breakdown voltage caused by this electric field concentration becomes apparent.

[0095] From the above, it can be understood that if the thickness of the insulating film 15 is too thin, the breakdown voltage will decrease, and if the thickness of the insulating film 15 is too thick, the breakdown voltage will also decrease. This makes it possible to understand the characteristics of the graph shown in FIG. 23. Therefore, it can be seen that from the viewpoint of improving the breakdown voltage, it is desirable that the thickness of the insulating film 15 is not too thin, but also not too thick. As described above, the thickness of the insulating film 15 is desirably about twice the thickness of the gate insulating film 13.

[0096] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0097] The above embodiment includes the following aspects.

[0098] (Appendix 1) (a) forming a first insulating film in a first region of a semiconductor substrate; (b) forming a second insulating film in a second region of the semiconductor substrate; (c) forming a gate electrode on the first insulating film; (d) forming a field plate portion on the second insulating film; (e) forming a first semiconductor region of a second conductivity type in the field plate portion; (f) forming a second semiconductor region of the first conductivity type in the field plate portion; (g) forming a source region of the first conductivity type in the semiconductor substrate; (h) forming a drain region of the first conductivity type in the semiconductor substrate; (i) electrically connecting the first semiconductor region and the source region; (j) electrically connecting the second semiconductor region and the drain region; A manufacturing method of a semiconductor device comprising:

[0099] (Appendix 2) 2. The method for manufacturing a semiconductor device according to claim 1, The step (d) comprises: (d1) forming an amorphous semiconductor film on at least the second insulating film; (d2) patterning the amorphous semiconductor film; The method for manufacturing a semiconductor device comprising the steps of:

[0100] (Appendix 3) (a) preparing an SOI substrate having a support substrate, a second insulating film formed on the support substrate, and a semiconductor layer formed on the second insulating film; (b) processing the semiconductor layer to form the field plate portion on the second insulating film formed in a second region of the SOI substrate; (c) removing the second insulating film formed in the first region of the SOI substrate; (d) forming a first insulating film in the first region; (e) forming a gate electrode on the first insulating film; (f) forming a first semiconductor region of a second conductivity type in the field plate portion; (g) forming a second semiconductor region of the first conductivity type in the field plate portion; (h) forming a source region of the first conductivity type in the SOI substrate; (i) forming a drain region of the first conductivity type in the SOI substrate; (j) electrically connecting the first semiconductor region and the source region; (k) electrically connecting the second semiconductor region and the drain region; A manufacturing method of a semiconductor device comprising:

[0101] (Appendix 4) In the method for manufacturing a semiconductor device according to claim 3, The method for manufacturing a semiconductor device, wherein the semiconductor layer is a single crystal semiconductor layer. [Explanation of symbols]

[0102] 1. Semiconductor substrate 13 Gate insulating film 14 Gate electrode 15 Insulating film 16 Field plate section 17 Highly-concentrated p-type semiconductor region 18 Low concentration p-type semiconductor region 19 Highly-doped n-type semiconductor region 20 Drain Region 21 Source Area 24 Plug 24A plug 24B plug 24C Plug 24D Plug 24E plug

Claims

1. A semiconductor substrate; a first insulating film formed on a first region of the semiconductor substrate; a second insulating film formed on a second region of the semiconductor substrate; a gate electrode formed on the first insulating film; a field plate portion formed on the second insulating film; a source region of a first conductivity type formed in the semiconductor substrate; a drain region of the first conductivity type formed in the semiconductor substrate; A semiconductor device comprising: The field plate portion is a first semiconductor region of a second conductivity type different from the first conductivity type; a second semiconductor region of the first conductivity type; having The first semiconductor region is A first high concentration semiconductor region; a first low concentration semiconductor region having an impurity concentration lower than that of the first high concentration semiconductor region; Including, In a plan view, the first lightly doped semiconductor region is disposed so as to be sandwiched between the first heavily doped semiconductor region and the second semiconductor region; the first high concentration semiconductor region is electrically connected to the source region; the second semiconductor region is electrically connected to the drain region; The first lightly doped semiconductor region is in contact with the second insulating film, a portion of the first low concentration semiconductor region is interposed between a bottom of the first high concentration semiconductor region and the second insulating film.

2. 2. The semiconductor device according to claim 1, The field plate portion has a pn junction formed by the first semiconductor region and the second semiconductor region.

3. 2. The semiconductor device according to claim 1, the gate electrode is made of a semiconductor film of the first conductivity type, an impurity concentration of the field plate portion is lower than an impurity concentration of the gate electrode.

4. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the second insulating film has a thickness greater than a thickness of the first insulating film.

5. 5. The semiconductor device according to claim 4, A semiconductor device, wherein the second insulating film has a thickness twice as large as the first insulating film.

6. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the second insulating film has a thickness equal to that of the first insulating film.

7. 2. The semiconductor device according to claim 1, The semiconductor device includes: a first plug electrically connected to the first high concentration semiconductor region; a second plug electrically connected to the second semiconductor region; a first wiring electrically connected to the first plug; a second wiring electrically connected to the second plug; having In a plan view, the first wiring includes a first protruding portion protruding from the first plug toward the second wiring, In a plan view, the second wiring includes a second protruding portion protruding from the second plug toward the first wiring.

8. 8. The semiconductor device according to claim 7, a first width of the first protruding portion is equal to or greater than 0.4 μm and equal to or less than 1.0 μm; The second width of the second protruding portion is also not less than 0.4 μm and not more than 1.0 μm.

9. 2. The semiconductor device according to claim 1, The second semiconductor region is in contact with the second insulating film.

10. 2. The semiconductor device according to claim 1, The field plate portion is made of an amorphous semiconductor film.

11. 2. The semiconductor device according to claim 1, The field plate portion is made of a single crystal semiconductor film.

12. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the field plate portion includes a region that is depleted when a first potential is supplied to the source region and a second potential higher than the first potential is supplied to the drain region.

13. 2. The semiconductor device according to claim 1, A semiconductor device, wherein when a first potential is supplied to the source region and a second potential higher than the first potential is supplied to the drain region, the first lightly doped semiconductor region is depleted.

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