DEPFET transistor and method for manufacturing the same

Abstract

The present invention relates to a DEPFET, the DEPFET comprising a semiconductor substrate (100) of a first conductivity type, the semiconductor substrate (100) having a first major surface (101) and a second major surface (102) opposite to each other, the DEPFET further comprising a source terminal region (1s) of a second conductivity type on the first major surface (101), a drain terminal region (1d) of the second conductivity type, a channel region (10) disposed between the source terminal region (1s) and the drain terminal region (1d), and a gate insulator (6) separated from the channel region (10). The device comprises an electrode (11), a rear activation region (104) of a second conductivity type formed on the second main surface (102), and a substrate doping increase region (2) of a first conductivity type formed at least below the source terminal region (1s) and below the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conductivity type below the gate electrode (11), in which the effective doping dose in the signal charge control region is higher than that in other portions of the substrate doping increase region (2) below the gate electrode.

Description

[Technical field]

[0001] The present invention relates to a DEPFET transistor and a method for fabricating a DEPFET transistor. [Background technology]

[0002] The DEPFET transistor was already described in 1987 in the paper "New Detector Concepts" by J. Kemmer and G. Lutz (Nuclear Instruments and Methods A253 (1987) p. 365). Here, the name DEPFET comes from DEPleted Field Effect Transistor and stands for a fully depleted field effect transistor on a lightly doped semiconductor substrate. The basic structure of such a detector is described below on the basis of FIG. 4, which is taken from the above paper.

[0003] As shown in the left half of FIG. 4, a highly ohmic n-silicon substrate 200 has a first (front) major surface 101 and a second (back) major surface 102. A highly doped p backside contact region 204 is located on the second (back) major surface 102 of the semiconductor substrate 200. A highly doped p source connection region 201s and a highly doped p drain connection region 201d of an (enhancement mode) MOSFET are located on the first (front) major surface 101. The gate structure comprises a gate electrode 211 and a gate insulator 206. The semiconductor substrate located between the source connection region 201s and the drain connection region 201d below the gate insulator 206 forms a channel region 210 of the depletion mode MOSFET shown.

[0004] When a reverse voltage is applied between the backside contact region 204 and the semiconductor substrate contact region 220 and the potentials of the source connection region 201s and the backside contact region 204 are appropriately adjusted, a potential distribution can be created in the depleted semiconductor substrate such that an electron potential minimum is below the transistor channel (see the right half of FIG. 4). When signal electrons generated in the semiconductor by radiation accumulate in this potential minimum, they can control the current in the channel from there, which is why the potential minimum is also called the "inner gate" of the field effect transistor. In the left half of FIG. 4, such an "inner gate" is shown diagrammatically and is assigned the reference number 20.

[0005] The signal-to-noise ratio achievable by a detector system is influenced in particular by the input capacitance of the amplifier directly connected to the detector (the so-called "front-end" amplifier). Roughly speaking, the better the signal-to-noise ratio, the smaller the input capacitance. Here, the DEPFET detector has a great advantage due to its construction, since the internal gate capacitance is small and in particular there are no stray capacitances, which would be generated when the detector signal is transferred to the amplifier.

[0006] In the above paper, the following relationship is derived regarding the correlation between the signal charge and the change in the drain current of a transistor:

[0007] dl D =g m Q / C eff (1) In the formula, dl D is the change in drain current produced by the signal (electron) charge Q, and g m is the transconductance of the transistor, and C eff represents the capacitance between the internal gate and the transistor channel.

[0008] In a field-effect transistor, the transconductance g mSince is proportional to the ratio of the gate width W to the gate length L, which follows from the above formula, a high signal can be realized especially with short channel transistors. Based on this consideration, a DEPFET detector with a short gate length should enable a particularly high signal-to-noise ratio. In particular, it should thereby even be possible to detect a single signal electron. However, the inventors have noticed by simulation that when the gate length of a DEPFET transistor is shortened, not only the short channel effect known from conventional field effect transistors occurs, but also further effects occur that limit the increase in the signal-to-noise ratio. Summary of the Invention [Problem to be solved by the invention]

[0009] It is therefore an object of the present invention to provide a DEPFET transistor which has a high signal-to-noise ratio, in particular a high amplification of the signal charge. [Means for solving the problem]

[0010] This object is achieved by a DEPFET transistor according to claims 1 and 4 as well as by a method for manufacturing a DEPFET transistor according to claim 10. Further developments of the invention are defined in the dependent claims.

[0011] The DEPFET transistor according to the present invention comprises: a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first major surface and a second major surface opposed to each other, the DEPFET transistor further comprising: a field effect transistor portion formed on the first major surface, the field effect transistor portion comprising a source connection region of a second conductivity type, a drain connection region of a second conductivity type, a channel region disposed between the source connection region and the drain connection region, and a gate electrode above the channel region and separated from the channel region by a gate insulator, the DEPFET transistor further comprising: a backside control region of a second conductivity type formed on the second major surface; a substrate doping enhancement region of a first conductivity type formed in the first major surface at least below the source connection region and below the channel region; The substrate doping enhancement region comprises a signal charge control region of the first conductivity type below the gate electrode, in which the effective doping dose has a higher value than at other positions of the substrate doping enhancement region below the gate electrode, such that the extension of the signal charge control region between the source connection region and the drain connection region is smaller than the extension of the gate electrode above it, between the source connection region and the drain connection region.

[0012] The semiconductor substrate is, for example, a high ohmic silicon substrate having a sheet resistance of 1 kΩ-cm or more and preferably less than 15 kΩ-cm (meaning, for example, 2 kΩ-cm or more and / or 5 kΩ-cm or less).

[0013] The substrate doping enhanced region is located near the first main surface, but is located far enough away from the first main surface that its doping dose (which is at least two orders of magnitude lower than the respective doping doses of the drain connection region and the source connection region) cannot be compensated for by the respective doping doses of the drain connection region and the source connection region. The substrate doping enhanced region preferably extends below the channel region and the source connection region, but may also be located below part or the entire drain connection region.

[0014] The drain and source connection regions may comprise the complete drain and source regions, respectively, of the field effect transistor portion. In that case, the drain and source connection regions are directly adjacent to the gate electrode. However, in some embodiments, the drain and source connection regions may simply be regions that serve to provide an ohmic contact to a metal contact for connecting the source or drain, respectively. In the latter case, the drain and source connection regions, respectively, will be surrounded by regions of the same conductivity type, but with a smaller doping dose than the drain and source connection regions, respectively.

[0015] The effective doping dose in the signal charge control region, and therefore the number of dopants per unit area, preferably exceeds the average effective doping dose in the substrate doping enhanced region below the gate electrode by about 50% or more. Moreover, a lower percentage can also achieve advantageous effects, which are further described below. However, as a rule, the degree to which the effective doping dose is higher than that of the substrate doping enhanced region should be 1.5-5 times, preferably 2-2.5 times. The reason we refer here to the effective doping dose is that some of the dopants may be compensated by dopants of the opposite conductivity type, e.g., if the donor concentration dominates, some of the donors may have been compensated by acceptors, and vice versa.

[0016] When the DEPFET transistor operates as a sensor element for electromagnetic or particle radiation (e.g. a pixel element of a DEPFET pixel detector having a matrix array of DEPFETs), the signal charge induced by this radiation during operation accumulates, at least for a while, in the signal charge control region. When the DEPFET transistor is used as an amplifier for another detector (e.g. a semiconductor drift chamber), the signal charge from the other detector is transferred to the signal charge control region, i.e. the "inner gate", of the DEPFET.

[0017] Preferably, the complete gate region and the signal charge control region, respectively, have the described characteristics. However, the advantageous effects of the present invention can already be realized if at least the gate portion (meaning a part of the DEPFET) has the described characteristics. Therefore, the field effect transistor portion is further described above.

[0018] Between the source and drain connection regions, the extension of the signal charge control region is smaller than the extension of the gate electrode above it, so that the gate length of the "internal gate" is smaller than the gate length of the external gate (extension of the gate electrode between the source and drain connection regions). This means that the gate length of the internal gate can be chosen small for high signal charge amplification and high signal-to-noise ratio, without having to accept adverse short channel effects due to the concomitant shortening of the gate length of the external gate.

[0019] Finally, it should be mentioned that in the field effect transistor section, there is preferably only one gate electrode in the direction of the gate length, and thus between the source and drain connection regions, so that there are not several MOS sections in the direction of the gate length to which different voltages can be applied.

[0020] Preferably, in an orthogonal projection onto the plane of the first main surface, the signal charge control region is spaced apart from the drain connection region. The signal charge control region is located below the channel region of the transistor and is therefore deeper (relative to the first main surface) than the drain connection region. Since it is the horizontal distance between the signal charge control region and the drain connection region that is of concern, the best way to characterize this fact is to project the signal charge control region and the drain connection region in an orthogonal projection onto the plane of the first main surface and refer to this distance in this plane.

[0021] The distance of the signal charge control region from the drain connection region provides a smaller electric field strength at the boundary region between the signal charge control region and the drain connection region. As the gate length is shortened, this can reduce the probability of avalanche occurrence in this area, which adversely affects the signal to noise ratio.

[0022] More preferably, in an orthogonal projection onto the plane of the first main surface, a resistive region in the form of a doped region of a second conductivity type may be formed between the drain connection region and the signal charge control region (20), the doping dose of the doped region being smaller than the doping dose of the drain connection region.

[0023] The presence of the resistive region reduces the strength of the electric field at the drain end of the signal charge control region, which, when the gate length is reduced, can reduce the probability of avalanching in this region, which adversely affects the signal-to-noise ratio.

[0024] A further DEPFET transistor according to the invention comprises a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first major surface and a second major surface opposed to each other, the DEPFET transistor further comprising: a field effect transistor portion formed on the first major surface, the field effect transistor portion comprising a source connection region of a second conductivity type, a drain connection region of a second conductivity type, a channel region disposed between the source connection region and the drain connection region, and a gate electrode above the channel region and separated from the channel region by a gate insulator, the DEPFET transistor further comprising: a backside control region of a second conductivity type formed on the second major surface; a substrate doping enhancement region of a first conductivity type formed in the first major surface at least below the source connection region and below the channel region; the substrate doping enhancement region comprises a signal charge control region of the first conductivity type below the gate electrode, in which an effective doping dose in the signal charge control region is higher than in other locations of the substrate doping enhancement region; In an orthogonal projection onto the plane of the first main surface, a resistive region in the form of a doped region of a second conductivity type is formed between the drain connection region and the signal charge control region, the doping dose of the doped region being smaller than the doping dose of the drain connection region.

[0025] The semiconductor substrate is, for example, a high ohmic silicon substrate having a sheet resistance of 1 kΩ-cm or more and preferably less than 15 kΩ-cm, thus, for example, 2 kΩ-cm or more and / or 5 kΩ-cm or less. The substrate doping enhancement region is located near the first main surface, but is spaced from the first main surface by such an amount that its doping dose (at least two orders of magnitude lower than the respective doping doses of the drain connection region and the source connection region) cannot be compensated by the respective doping doses of the drain connection region and the source connection region. Preferably, the substrate doping enhancement region not only extends below the channel region and the source connection region, but may also extend below a part or the entire drain connection region. The drain connection region and the source connection region may respectively comprise the complete drain region and source region of the field effect transistor part. In such a case, the drain connection region and the source connection region, respectively, are directly adjacent to the gate electrode. However, in some embodiments, the drain connection region and the source connection region may only be the region that serves to generate an ohmic contact to a metal contact for connecting the source or the drain, respectively. In the latter case, the drain and source connection regions will each be surrounded by a region of the same conductivity type but having a smaller doping dose than the respective drain and source connection regions.

[0026] When the DEPFET transistor operates as a sensor element for electromagnetic or particle radiation, the signal charge induced by this radiation during operation accumulates, at least for a time, in the signal charge control region. When the DEPFET transistor is used as an amplifier for another detector (e.g. a semiconductor drift chamber), the signal charge from the other detector is transferred to the signal charge control region, or "inner gate", of the DEPFET.

[0027] Preferably, the complete gate region and the signal charge control region, respectively, have the described characteristics, but the advantageous effects of the invention can already be realized if at least the gate portion (meaning part of the DEPFET) has the described characteristics, which is why the field effect transistor portion is further described above.

[0028] Here, the resistive region is a region formed by separate doping and extends from the first major surface to a depth such that during operation of the DEPFET, the region is in series connection with the transistor channel above the signal charge control region.

[0029] The presence of the resistive region allows to reduce the strength of the electric field at the drain end of the signal charge control region. If the gate length is reduced, this can reduce the probability of avalanche generation in this region, which has a negative effect on the signal-to-noise ratio. Thus, such a DEPFET design allows to obtain in a particularly advantageous manner a short channel length, which is favorable for high signal charge amplification and a high signal-to-noise ratio.

[0030] Preferably, in a further DEPFET transistor according to the invention, the signal charge control region (20) is located below the entire gate electrode (11). Due to the presence of a resistive region, the potential difference in the transistor channel above the signal charge control region is reduced, thereby attenuating short channel effects even when the gate lengths of the outer gate and the "inner gate" are the same (when the signal charge control region is located below the entire gate electrode).

[0031] More preferably, in a further DEPFET transistor according to the invention, the resistive region comprises a region of the second conductivity type having a doping concentration smaller than a doping concentration of the drain connection region (1d), said region being located between the drain connection region (1d) and the gate electrode (11) in an orthogonal projection onto the plane of the first main surface (101).

[0032] Here, the resistance region is at least partially or completely arranged outside the region below the gate electrode. Since it is completely arranged outside the region below the gate electrode, the gate configuration is simplified, so that a particularly short channel length can be more easily realized. Since the doping dose of the resistance region is smaller than that of the drain connection region, the electric field strength at the drain side end of the signal charge control region is small, so that the probability of avalanche occurrence is not too high even with a short channel length.

[0033] More preferably, in a further DEPFET transistor according to the invention, the resistive region comprises a drain side channel region (15) which is a doped region of a second conductivity type at a drain side end of the channel region (10) below the gate electrode (11), the doping dose of the drain side channel region (15) being smaller than the doping dose of the drain connection region (1d).

[0034] In this realization of the DEPFET detector according to the invention, the resistive region is located at least partially or completely below the gate electrode. In operation, the drain side channel region does not play the role of a transistor channel, but rather a resistor connected in series with the transistor channel. For this, the doping dose is set such that a conductive resistive region is always present independent of the potentials used to turn the transistor on and off. In other words, the gate voltage cannot deplete the drain side channel region, because gate breakdown would occur before such a state is realized. Furthermore, the drain side channel region is formed such that the dopants of the drain side channel region partially, but not completely, compensate for the doping of the substrate doping enhanced region. Preferably, the doping dose of the drain boundary region is between 1·10 12 / cm 2 Above and / or 5·10 12 / cm 2 It is selected to be:

[0035] Instead of or in addition to the drain-side channel region, a source-side channel region may be formed at the source-side end of the channel region below the gate electrode. Such a source-side channel region likewise partially, but not completely, compensates for the doping of the substrate doping enhanced region. What has been said about the drain-side channel region also applies to the doping parameters of the source-side channel region.

[0036] More preferably, in the DEPFET transistor according to the present invention, a signal charge overflow region (21) further exists below at least a part of the source connection region (1s).

[0037] The signal charge control region can be considered as a potential pocket that cannot absorb all the signal charge when a large amount of signal charge is present. By suitable selection of the doping doses of the signal charge control region and the substrate doping enhancement region, if such a potential pocket is designed so that when the signal charge is large, the excess signal charge is collected in a controlled manner in the signal charge overflow region, a DEPFET with a large dynamic range can be realized, in which a small amount of signal charge is detected with high measurement sensitivity, but does not exceed the measurement range even when the signal charge is large. For this reason, the signal charge overflow region is directly adjacent to the signal charge control region.

[0038] More preferably, in an orthogonal projection onto the plane of the first main surface, the extension of the gate electrode between the source connection region and the drain connection region is greater than 300 nm and / or less than 4.5 μm. The specified values ​​of gate length can be realized by the means of the present invention.

[0039] The method of manufacturing a DEPFET transistor of the present invention comprises the steps of: The method includes providing a semiconductor substrate of a first conductivity type, the semiconductor substrate having opposing first and second major surfaces, the method further comprising: forming a field effect transistor portion on the first major surface; a dopant of a second conductivity type is introduced into the semiconductor substrate at a high doping dose to form a source connection region; A dopant of a second conductivity type is introduced into the semiconductor substrate at a high doping dose to form a drain connection region; A gate insulator and a gate electrode disposed on the gate insulator are formed on the first major surface and between the source connection region and the drain connection region, the method further comprising: forming a backside control region by introducing a dopant of a second conductivity type at a high doping dose into the second major surface; forming a substrate doping enhancement region of a first conductivity type in the first major surface at least below the source connection region and below the gate insulator; forming a signal charge control region of the first conductivity type below the gate electrode, in which an effective doping dose has a higher value than at other locations of the substrate doping enhancement region below the gate electrode, such that the extension of the signal charge control region between the source connection region and the drain connection region is smaller than the extension of the gate electrode above it, between the source connection region and the drain connection region.

[0040] Preferably, in the method, the signal charge control region is formed by further introducing a dopant of a first conductivity type into the substrate doping enhanced region. By further introducing the dopant into the substrate doping enhanced region, a complementary doping region with an increased doping dose is generated, thereby defining the position of the signal charge control region. The additional introduction of the dopant can be performed, for example, by implantation at substantially the same energy as that for forming the substrate doping enhanced region.

[0041] More preferably, in the method, a resistive region is formed by introducing dopants of the second conductivity type with a doping dose smaller than that of the drain connection region, the resistive region being located between the drain connection region and the signal charge control region in an orthogonal projection onto the plane of the first main surface, the doping dose being set such that a conductive resistive region always exists independently of the potential at the gate for turning the transistor on and off. In particular, by means of these dopants the doping of the substrate doping enhancement region is partially, but not completely, compensated.

[0042] More preferably, in the method of forming the resistor region, dopants of a second conductivity type are introduced into the drain side end of the channel region below the gate electrode, preferably by implantation at an angle greater than 30° and / or less than 80° relative to normal to the first major surface, to form the resistor region.

[0043] This oblique implantation allows for a simplification of the manufacturing process. The preferred angle at which the dopants are implanted relative to the perpendicular to the major surface is greater than or equal to 40° and / or less than or equal to 60°.

[0044] Further features and advantages of the invention will emerge from the description of the embodiments based on the attached drawings. [Brief description of the drawings]

[0045] [Figure 1] 1 is a schematic cross-sectional view of a portion of a DEPFET transistor according to a first embodiment; [Diagram 2] FIG. 13 is a schematic cross-sectional view of a portion of a DEPFET transistor according to a second embodiment. [Diagram 3] FIG. 13 is a schematic cross-sectional view of a portion of a DEPFET transistor according to a third embodiment. [Figure 4] FIG. 1 shows a schematic diagram of the structure of a known DEPFET transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] First embodiment FIG. 1 is a schematic diagram of a cut perpendicular to the main surface of a DEPFET transistor of a first embodiment. In this cut, a semiconductor substrate 100 (e.g., a high ohmic n silicon substrate) is shown having a first main surface 101 (chip front side and chip top side, respectively). A second main surface 102 (chip back side and chip bottom side, respectively) of the substrate 100 faces the first main surface. FIG. 1 shows a highly doped (in this example, p +doped) source connection region 1s and highly doped (in this example, p + One can see a source connection region 1s and a drain connection region 1d, both of which are adjacent to a gate electrode 11 disposed therebetween, with a gate insulator 6 (e.g., a SiO2 layer) disposed between the gate electrode 11 and the semiconductor substrate 100. The semiconductor substrate below the gate insulator 6 and between the source connection region 1s and the drain connection region 1d forms the channel region 10 of the illustrated enhancement mode MOSFET, and is configured to increase the threshold voltage V T The doping of the semiconductor substrate may be varied in this channel region to adjust

[0047] Furthermore, in Fig. 1 there is seen a substrate doping-enhanced region 2 below the transistor and close to the first main face 101. The substrate doping-enhanced region 2 may be present only below the source connection region 1s and below the part of the channel region 10 adjacent thereto. However, preferably the substrate doping-enhanced region 2 reaches below the drain connection region. Compared to the semiconductor substrate 100, this substrate doping-enhanced region 2 has a high n-doping. The p-doping in the second main face 102 is + The presence of the substrate doping enhanced region 2 can prevent punch-through between the source connection region 1s and the backside contact 104 when the semiconductor substrate 100 is fully depleted by applying a high reverse voltage between the backside contact or backside control region 104 and the substrate connection contact (not shown). Here, it was assumed that the source connection region 1s has a potential substantially at the substrate connection contact or at least a potential negative with respect to the substrate connection contact that is much smaller (at least 10-100 times smaller) than the negative potential of the backside contact 104. Furthermore, the substrate doping enhanced region 2 realizes a deepening of the potential minimum of the signal charges (electrons in this example) near the first main surface 101.

[0048] As can be seen in FIG. 1, below the part of the channel adjacent to the source connection region 1s and at a certain horizontal distance to the drain connection region 1d, there is a complementary doped region 9. This complementary doped region 9 is formed by an additional local n-doping, the doping dose of which is higher than that of the substrate doping enhanced region 2. More precisely, with reference to the plane of the first semiconductor face 101, the doping dose of donors not compensated by acceptors, and therefore the effective doping dose, is higher in the complementary doped region 9 than in the substrate doping enhanced region 2. This local increase in the effective doping dose has the effect that when the semiconductor substrate 100 is depleted, the potential minimum of the signal charges (electrons in this example) assumes a lower value in the complementary doped region 9 than in the substrate doping enhanced region 2. Since the doping dose of the complementary doped region 9 is partly compensated by the dopants of the source connection region 1s, the potential minimum is located below the channel region. The regions are therefore referred to as the signal charge control region 20 and the internal gate, respectively. This is because the signal charge in this region can control the current in the channel region 10 .

[0049] 1, it can be seen that there is no signal charge control region 20 below the drain side portion of the channel region. As a result, the gate length of the internal gate, i.e., the lateral dimension of the signal charge control region 20 in FIG. 1, is smaller than the lateral dimension of the gate electrode 11 (meaning the gate length of the external gate).

[0050] The configuration shown in Fig. 1 allows high amplification with high signal-to-noise ratio. As a consequence of equation (1), the change in drain current generated by signal charge increases when the capacitance between the internal gate and the transistor channel decreases. According to this embodiment, since the complementary doping region 9 is at a distance to the drain connection region 1d, the signal charge control region 20 is also at a distance to the drain connection region 1d, and the size of the internal gate of the DEPFET corresponding to the signal charge control region 20 is reduced, so the capacitance between the internal gate and the transistor channel is reduced, resulting in a larger amplification (change in drain current).

[0051] Furthermore, the first embodiment makes it possible in particular to achieve channel lengths of less than 4.5 μm. As already explained above, the transconductance g m corresponds to the inverse of the channel length L. Thus, a further possibility of achieving high amplification is provided in that the above configuration is used for transistors with short channel lengths (see formula (1)). The inventors assume that in conventional DEPFET transistors realized with short channel lengths L, the increase in the signal-to-noise ratio is limited by the fact that avalanche generation occurs at the boundary between the drain connection region 1d and the semiconductor substrate (particularly the internal gate) due to the high electric field strength in short channel transistors. However, according to the first embodiment, since the complementary doping region 9 is at a certain distance to the drain connection region 1d, the electric field strength occurring in this configuration is not very high, which has a positive effect on the signal-to-noise ratio. By introducing additional donors in the complementary doping region 9, the potential minimum of the signal charge is deepened especially at this position, so that the doping of the substrate doping enhancement region 2 can generally be lower, since not only the substrate doping enhancement region 2 has to be provided to deepen the potential minimum. On the other hand, a lower doping of the substrate doping enhanced region 2 close to the drain connection region 1d leads to a lower electric field strength at this location and therefore a lower probability of avalanche occurrence.

[0052] It should still be mentioned that although in FIG. 1 the complementary doped region 9 reaches below the source connection region 1c, the described advantages can also be achieved if the complementary doped region 9 is laterally spaced apart from the source connection region 1c.

[0053] Second embodiment FIG. 2 shows a second embodiment, which differs from the first embodiment only in two aspects, as can be seen in the drawing: On the one hand, in the second embodiment, the explicit complementary doped region 9 for forming the signal charge control region 20 is omitted. On the other hand, in FIG. 2, the drain side channel region 15 and the source side channel region 16 are visible. These two regions are p-doped regions at the drain side end and the source side end of the channel below the gate insulator 6, respectively. The doping dose in these regions is smaller than the doping dose in the source connection region 1c and the drain connection region 1d. Even if FIG. 2 shows the source side channel region 16, this can also be omitted. The advantageous behavior of the DEPFET transistor can be realized even without such a source side channel region 16.

[0054] Due to the presence of the drain side channel region 15 and possibly the source side channel region 16, the doping dose in the underlying substrate doping enhanced region 2 is lowered. As a result, a signal charge control region 20 is formed which has a higher effective doping dose than the remaining substrate doping enhanced region 2 below the channel 10 (or gate electrode 11) and is laterally spaced apart from the drain connection region 1d (and possibly the source connection region 1c). As a result, it can be seen that the second embodiment achieves the same advantages as the first embodiment. Only the manner in which the signal charge control region 20 is provided by compensating the doping of the substrate doping enhanced region 2 instead of introducing a specific dopant is different.

[0055] Third embodiment 3 shows a third embodiment which differs from the second embodiment in that there is neither a drain side channel region 15 nor a source side channel region 16. However, the drain connection region 1d is laterally spaced away from the gate electrode 11 and a drain resistor region 17 is arranged on the first main surface 101 between the drain connection region 1d and the gate electrode 11. The drain resistor region 17 is a p-doped region having a doping dose smaller than the doping dose of the drain connection region 1d.

[0056] Due to the presence of the drain resistance region 17, the doping dose in the substrate doping enhanced region 2 is partially compensated. As a result, the part of the substrate doping enhanced region 2 with the highest effective doping dose (and therefore the signal charge control region 20) is laterally spaced away from the drain connection region 1d, even if it extends below the entire channel. Thus, as in the first embodiment, the electric field strength at the drain side end of the signal charge control region 20 is not very high, which has a positive effect on the signal-to-noise ratio. Thus, this configuration is also suitable for transistors with short channel lengths and resulting small capacitances of the internal gate. At the same time, the drain resistance region 17 has the effect that the voltage applied to the channel is smaller than the voltage between the drain connection region 1d and the source connection region 1c. This also contributes to limiting the probability of avalanche occurrence at the drain side end of the signal charge control region 20, even with a short channel length L.

[0057] The following outlines the steps for fabricating a DEPFET transistor according to the present invention, where steps not explicitly mentioned are the same or similar to those used in the fabrication of DEPFET transistors known in the prior art.

[0058] To form the backside control region 104, at the second main face 102, a high dose of acceptors (e.g. boron) is introduced into the semiconductor substrate, which is usually highly ohmic (e.g. 2 k / Ω-cm). At the opposite first main face 101, the source connection region 1s and the drain connection region 1d are formed by introducing acceptors (e.g. boron) at a high dose. In both cases the introduction is preferably by implantation (e.g. energy of 10-15 keV). The dose should be high enough to allow the formation of ohmic junctions with the contacts (depending on the metallization used). As a rule, the dose for this is between 10 and 15 keV. 14 / cm 2 ~10 16 / cm 2 It is.

[0059] For example, at high energies (e.g., about 300-600 keV, about 0.5-2·10 12 / cm 2 ) to form the substrate doping enhanced region 2, where the energy and dose should be set such that the doping dose below the source and drain connection regions 1s and 1d is not fully compensated by the dopants in the source and drain connection regions.

[0060] For example, the drain side channel region 15 or the source side channel region 16 can be introduced by implantation of boron at an angle of more than 30° and / or less than 80°, preferably more than 40° and / or less than 60°, relative to the normal to the first major surface (101), where the implantation angle is about 1-5·10 (depending on the doping depth and dose of the substrate doping enhancement region). 12 / cm 2 An energy of about 150-500 keV of boron ions at a dose of 0.1 can be selected.

[0061] The complementary doped regions 9 can be formed like the substrate doping enhanced regions 2, but with a dose 1.5 to 5 times, preferably 2 to 2.5 times, higher than the dose of the substrate doping enhanced regions 2. Implantation at an angle with respect to being perpendicular to the first main surface (101) can also be selected to form the complementary doped regions 9, especially in the case where the complementary doped regions 9 are only formed below the gate electrode and not below the source connection region.

[0062] The designs of the above embodiments, with all respective possible variations, can also be combined with each other. Thus, a DEPFET may, for example, comprise a complementary doping region 9 and at the same time comprise a drain side channel region 15. Likewise, for example, a DEPFET having a drain side channel region 15 and / or a complementary doping region 9 can be provided with a drain resistor region 17.

[0063] Furthermore, in all the embodiments, the n region can be replaced with a p region, and the p region can be replaced with an n region. In other words, all the embodiments can be realized in a p-type conductive semiconductor substrate as well. Furthermore, the MOS field effect transistor portion can be either enhancement mode or depletion mode.

[0064] The described DEPFET transistor can be used as a detector for particle radiation or electromagnetic radiation, in particular as a pixel of a pixel detector. In particular, it is also conceivable to use the DEPFET transistor as an amplifier for another detector (for example a semiconductor drift chamber).

[0065] During sensor operation for detection of radiation induced signal charge, the described DEPFET transistor is substantially operated such that a reverse voltage is applied between the backside control region 104 and the semiconductor substrate connection region for full depletion of the semiconductor substrate 100, and suitable voltages are applied between the source connection region 1s and the drain connection region 1d and between the gate electrode 11 and the source connection region 1s to form a conductive channel. Signal charge present in the signal charge control region 20 can be removed by applying a signal (for positive signal electrons) to the semiconductor substrate connection region for a short period of time.

Claims

1. A DEPFET transistor, The DEPFET transistor comprises a semiconductor substrate (100) of a first conductivity type, the semiconductor substrate (100) having a first major surface (101) and a second major surface (102) opposed to each other, the DEPFET transistor further comprising: a field effect transistor portion formed on said first major surface (101), said field effect transistor portion comprising a source connection region (1s) of a second conductivity type, a drain connection region (1d) of a second conductivity type, a channel region (10) disposed between said source connection region (1s) and said drain connection region (1d), and a gate electrode (11) above said channel region (10) and separated from said channel region (10) by a gate insulator (6); said DEPFET transistor further comprising: a backside control region (104) of a second conductivity type formed on the second major surface (102); a substrate doping enhancement region (2) of a first conductivity type formed on the first main surface at least below the source connection region (1s) and below the channel region (10); 1. A DEPFET transistor, wherein the substrate doping enhancement region (2) comprises a signal charge control region (20) of the first conductivity type below the gate electrode (11), in which the effective doping dose has a higher value than at other positions of the substrate doping enhancement region (2) below the gate electrode, such that the extension of the signal charge control region (20) between the source connection region (1s) and the drain connection region (1d) is smaller than the extension of the gate electrode above it, between the source connection region (1s) and the drain connection region (1d).

2. 2. A DEPFET transistor according to claim 1, wherein in an orthogonal projection onto the plane of said first main surface (101), said signal charge control region (20) is spaced apart from said drain connection region (1d).

3. 3. A DEPFET transistor according to claim 1 or 2, wherein in an orthogonal projection onto the plane of said first main surface (101) a resistive region in the form of a doped region of a second conductivity type is formed between said drain connection region (1 d) and said signal charge control region (20), the doping dose of said doped region being smaller than the doping dose of said drain connection region (1 d).

4. A DEPFET transistor, The DEPFET transistor comprises a semiconductor substrate (100) of a first conductivity type, the semiconductor substrate (100) having a first major surface (101) and a second major surface (102) opposed to each other, the DEPFET transistor further comprising: a field effect transistor portion formed on said first major surface (101), said field effect transistor portion comprising a source connection region (1s) of a second conductivity type, a drain connection region (1d) of a second conductivity type, a channel region (10) disposed between said source connection region (1s) and said drain connection region (1d), and a gate electrode (11) above said channel region (10) and separated from said channel region (10) by a gate insulator (6); said DEPFET transistor further comprising: a backside control region (104) of a second conductivity type formed on the second major surface (102); a substrate doping enhancement region (2) of a first conductivity type formed on the first main surface at least below the source connection region (1s) and below the channel region (10); a substrate doping enhancement region (2) comprising a signal charge control region (20) of the first conductivity type below the gate electrode (11), in which the effective doping dose has a higher value than at other positions of the substrate doping enhancement region (2); and in an orthogonal projection onto the plane of the first main surface (101), a resistive region in the form of a doped region of a second conductivity type is formed between the drain connection region (1d) and the signal charge control region (20), the doping dose of which is smaller than the doping dose of the drain connection region (1d).

5. A DEPFET transistor according to claim 4, wherein said signal charge control region (20) is located below the entire gate electrode (11).

6. 5. A DEPFET transistor according to claim 3, wherein the resistor region comprises a region of a second conductivity type having a doping concentration smaller than a doping concentration of the drain connection region (1d), said region being located between the drain connection region (1d) and the gate electrode (11) in an orthogonal projection onto the plane of the first main surface (101).

7. 7. A DEPFET transistor according to claim 3, 4 or 6, wherein the resistor region comprises a drain side channel region (15) which is a doped region of a second conductivity type at a drain side end of the channel region (10) below the gate electrode (11), the doping dose of the drain side channel region (15) being smaller than the doping dose of the drain connection region (1d).

8. A DEPFET transistor according to claim 1 or 4, further comprising a signal charge overflow region (21) below at least a portion of said source connection region (1s).

9. 5. A DEPFET transistor according to claim 1 or 4, wherein in an orthogonal projection onto the plane of the first main surface (101), the extension of the gate electrode (11) between the source connection region (1s) and the drain connection region (1d) is greater than 300 nm and / or less than 4.5 μm.

10. A method for manufacturing a DEPFET transistor according to claim 1 or 4, comprising the steps of: The method includes providing a semiconductor substrate (100) of a first conductivity type, the semiconductor substrate (100) having a first major surface (101) and a second major surface (102) opposed to each other, the method further comprising: forming a field effect transistor portion on the first major surface; A dopant of a second conductivity type is introduced into the semiconductor substrate (100) at a high doping dose to form a source connection region (1s); A dopant of a second conductivity type is introduced into the semiconductor substrate (100) at a high doping dose to form a drain connection region (1d); A gate insulator (6) and a gate electrode (11) arranged on the gate insulator are formed on the first main surface (101) and between the source connection region (1s) and the drain connection region (1d), and the method further comprises: forming a backside control region (104) by introducing a dopant of a second conductivity type at a high doping dose into said second major surface (102); forming a substrate doping enhancement region (2) of a first conductivity type on said first major surface (101) at least below said source connection region (1s) and below said gate insulator (6); forming a signal charge control region (20) of the first conductivity type below the gate electrode (11), in which the effective doping dose has a higher value than at other positions of the substrate doping enhancement region (2) below the gate electrode (11), such that the extension of the signal charge control region (20) between the source connection region (1s) and the drain connection region (1d) is smaller than the extension of the gate electrode above it, between the source connection region (1s) and the drain connection region (1d).

11. 11. The method of claim 10, wherein the signal charge control region (20) is formed by further introducing a dopant of a first conductivity type into the substrate doping enhancement region (2).

12. 11. The method of claim 10, wherein a resistor region is formed by introducing a dopant of the second conductivity type with a doping dose smaller than a doping dose of the drain connection region (1d), the resistor region being located between the drain connection region (1d) and the signal charge control region (20) in an orthogonal projection onto the plane of the first main surface (101).

13. The method described in claim 12, wherein the channel region has a drain side end, and a dopant of a second conductivity type is introduced into the drain side end of the channel region (10) below the gate electrode (11) to form the resistance region.

14. The method of claim 13, wherein the dopant of a second conductivity type is introduced into the drain side end of the channel region (10) below the gate electrode (11) by implantation at an angle greater than 30° and / or less than 80° relative to perpendicular to the first major surface (101).

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