Tunneling-based selectors incorporating van der Waals (vdW) materials

Abstract

To provide a selector and a device based on a tunneling effect.SOLUTION: A selector 200a includes a multilayer barrier structure 120a formed between a first electrode 110 and a second electrode 130. The multilayer barrier structure includes a first layer 121 of a first van der Waals (vdW) material, a second layer 223a of a second vdW material, and a third layer of a third vdW material 225a. The first layer of the first vdW material is formed between the second layer of the second vdW material and the third layer of the third vdW material. The electron affinity of the first layer of the first vdW material is lower than the second electron affinity of the second layer of the second vdW material and the electron affinity of the third layer of the vdW material.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] Implementations of the present disclosure relate generally to selector devices, and more specifically to tunneling-based selectors incorporating van der Waals (vdW) materials. [Background technology]

[0002] High density memories and computing devices such as crossbar circuits that include circuit structures with interconnect conductive lines sandwiching resistive switching material at their cross points require that each memory cell be paired with a selector device to enable reading and writing of the selected memory cell. For example, a crossbar circuit may utilize a one selector one register (1S1R) structure that includes a selector device (e.g., a transistor) connected in series with the memory cells to select a particular memory cell to perform a read or write operation and suppress unwanted leakage current through unselected memristors. Summary of the Invention [Problem to be solved by the invention]

[0003] The following is a brief summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure, nor to delineate the scope of particular implementations of the disclosure or the scope of the claims. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later. [Means for solving the problem]

[0004] According to some embodiments of the present disclosure, a selector based on the tunneling effect is provided. The selector includes a multi-layer barrier structure formed between a first electrode and a second electrode. The multi-layer barrier structure includes a first layer of a first van der Waals (vdW) material, a second layer of a second vdW material, and a third layer of a third vdW material. The first layer of the first vdW material is formed between the second layer of the second vdW material and the third layer of the third vdW material. The electron affinity of the first layer of the first vdW material is lower than the second electron affinity of the second layer of the second vdW material and the electron affinity of the third layer of vdW material.

[0005] In some embodiments, a first layer including a first vdW material is formed between a second layer including a second vdW material and a third layer including a third vdW material.

[0006] In some embodiments, the first vdW material includes h-BN. The second vdW material includes MoS 2 , W.S. 2 , or WSe 2 The third vdW material includes at least one of MoS 2 , W.S. 2 , or WSe 2 It includes at least one of the following.

[0007] In some embodiments, the first vdW material is WSe 2 The second vdW material is MoSe 2 , MoS 2 , or HfS 2 The third vdW material includes at least one of MoSe 2 , MoS 2 , or HfS 2 It includes at least one of the following.

[0008] In some embodiments, the multi-layer barrier structure further comprises a fourth layer of a fourth vdW material. The second electron affinity of the second vdW material is lower than the fourth electron affinity of the fourth vdW material.

[0009] In some embodiments, a fourth layer of a fourth vdW material is formed between a second layer including a second vdW material and the first electrode.

[0010] In some embodiments, the multi-layer barrier structure further comprises a fifth layer of a fifth vdW material. The third electron affinity of the third layer of the third vdW material is lower than the fifth electron affinity of the fifth layer of the fifth vdW material.

[0011] In some embodiments, a fifth layer of a fifth vdW material is formed between the third layer including the third vdW material and the second electrode.

[0012] In some embodiments, the multi-layer barrier structure comprises (2n+1) layers of vdW material, where n is a positive integer.

[0013] In some embodiments, the multi-layer barrier structure forms a stepped tunnel barrier that approximates a triangular tunnel barrier. The multi-layer structure may or may not be symmetric about the central layer.

[0014] In some embodiments, the ratio of the first current passing through the selector in response to the first voltage to the second current passing through the selector in response to the second voltage is 10 2 or more, the second voltage is half the first voltage.

[0015] In some embodiments, this ratio is 10 5 That's all.

[0016] In some embodiments, this ratio is 10 7 That's all.

[0017] In some embodiments, the selector has a stepped tunnel barrier that approximates a triangular tunnel barrier.

[0018] According to one or more aspects of the present disclosure, an apparatus is provided, the apparatus including a selector and a memory device serially coupled to the selector.

[0019] In some embodiments, the memory device comprises a switching oxide layer including at least one of HfOx or TaOy, where x≦2.0 and y≦2.5.

[0020] In some embodiments, the memory device includes at least one of a memristor, a resistive random access memory (RRAM), a phase change memory (PCM), a floating gate, a spintronic device, a dynamic random access memory (DRAM), a ferroelectric random access memory (FeRAM), or a static random access memory (SRAM).

[0021] In some embodiments, the device further comprises a first electrode and a second electrode. [Brief description of the drawings]

[0022] The present disclosure will be better understood from the detailed description set forth below and from the accompanying drawings of various embodiments of the present disclosure, which should not, however, be construed as limiting the disclosure to specific embodiments, but are for illustration and understanding purposes. [Figure 1] 1A-1C are schematic diagrams illustrating cross-sectional views of example selectors according to some embodiments of the present disclosure. [Figure 2A] 1A-1C are schematic diagrams illustrating cross-sectional views of example selectors according to some embodiments of the present disclosure. [Figure 2B] 1A-1C are schematic diagrams illustrating cross-sectional views of example selectors according to some embodiments of the present disclosure. [Figure 2C] 1A-1C are schematic diagrams illustrating cross-sectional views of example selectors according to some embodiments of the present disclosure. [Figure 3A] FIG. 2 is a schematic diagram illustrating an example of a crossbar circuit according to some embodiments of the present disclosure. [Figure 3B] FIG. 2 is a schematic diagram illustrating an example cross point device according to some embodiments of the present disclosure. [Figure 4] FIG. 2 illustrates the band gap and electron affinity of example van der Waals materials according to some embodiments of the present disclosure. [Diagram 5] FIG. 2 illustrates current-voltage (IV) characteristics of a selector according to some embodiments of the present disclosure. [Figure 6] FIG. 2 illustrates the non-linearity of a selector according to some embodiments of the present disclosure. [Figure 7A] FIG. 1 illustrates an example energy barrier according to some embodiments of the present disclosure. [Figure 7B] FIG. 1 illustrates an example energy barrier according to some embodiments of the present disclosure. [Figure 8A] 1A and 1B are schematic diagrams illustrating cross-sectional views of example 1S1R structures according to some embodiments of the present disclosure. [Figure 8B] 1A and 1B are schematic diagrams illustrating cross-sectional views of example 1S1R structures according to some embodiments of the present disclosure. [Figure 9] 1 is a flow diagram illustrating an example method for constructing a selector and a device including a 1S1R structure according to some embodiments of the present disclosure. [Figure 10] 1 is a flow diagram illustrating an example method for constructing a selector and a device including a 1S1R structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] In an aspect of the present disclosure, a mechanism is provided for constructing a tunneling-based selector incorporating van der Waals (vdW) materials. As used herein, vdW materials may refer to two-dimensional (2D) materials with van der Waals heterostructures. vdW materials may include strongly bonded 2D layers (one-atom-thick sheets) that can be stacked together and exfoliated into thin 2D free-standing layers via van der Waals interactions. An example of a vdW material is SnS 2 (Tin sulfide), ZrS 2 (zirconium sulfide), SnSe 2 (Tin Selenide), HfS 2 (Hafnium disulfide), MoS 2 (Molybdenum disulfide), MoSe 2 (Molybdenum diselenide), MoTe 2 (Molybdenum ditelluride), WS 2(Tungsten disulfide), WSe 2 (tungsten diselenide), graphene (Gr), h-BN (hexagonal boron nitride), etc.

[0024] Memory and computing devices such as memristor-based crossbar arrays may require selector devices to select specific memory and / or computing elements and suppress unwanted leakage currents passing through some selected or unselected memory and / or computing elements. Although transistors are widely used as selectors in crossbar arrays, selectors based on three-terminal transistors are not ideal for crossbar arrays because their large footprint can limit array density and increase cost. Therefore, it may be desirable to use two-terminal selectors that can be horizontally scaled and stacked vertically with memory cells (e.g., memristors) to implement crossbar arrays. However, conventional two-terminal selectors do not have certain desirable properties necessary to implement computing and / or memory applications similar to crossbar arrays, such as high nonlinearity, high ruggedness, sufficient current density, and small device-to-device variation.

[0025] The present disclosure provides a tunneling-based selector with multiple stepped tunneling barriers that approximate a desired triangular tunneling barrier, which may be used in memory and computing applications such as in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, etc.

[0026] According to one or more aspects of the present disclosure, a selector may include a first electrode, a second electrode, and a multi-layer barrier structure constructed between the first electrode and the second electrode. The first electrode and the second electrode may include graphene or any other material with suitable electrical conductivity.

[0027] The multilayer barrier may include multiple layers of van der Waals (vdW) materials to form a stepped tunneling barrier that approximates a triangular tunneling barrier. The multilayer barrier structure may include a central layer of a first VDW material sandwiched between layers of a VDW material having a higher electron affinity than the first VDW material. The multilayer barrier structure may include any suitable number of layers of vdW material (e.g., 2n+1 layers, where n is a positive integer), in which the inner layers of the multilayer barrier structure have a lower electron affinity than the adjacent outer layers, and the inner layers are closer to the central layer than the outer layers. By way of example, the multilayer barrier structure may include MoS 2 As another example, the multi-layer barrier structure may include a layer of h-BN sandwiched between two layers of WS 2 As a further example, the multi-layer barrier structure may include a layer of h-BN sandwiched between two layers of WSe 2 The first layer of WSe 2 The multi-layer barrier structure may further include a layer of h-BN sandwiched between a second layer of WSe 2 The MoS is constructed between the first layer and the first electrode. 2 The first layer of WSe 2 The second layer of MoS is constructed between the second electrode and the 2 and a second layer of

[0028] The multi-layer barrier structure may approximate a triangular tunnel barrier with a height peak at the center of the energy barrier. The electric field may reduce the peak barrier height of the triangular tunnel barrier compared to the case of a triangular or uniform tunnel barrier where the barrier width may be reduced. However, the barrier height does not decrease due to the external voltage provided by many existing selector devices based on tunneling. Therefore, the tunneling current in the triangular tunnel barrier changes suddenly in response to an electric field applied to the selector, resulting in high nonlinearity of the selector. The nonlinearity of the selector may be measured by the nonlinearity coefficient, which represents the ratio of the current passing through the selector at the threshold voltage to switch the selector into a conductive state to the current passing through the selector at half the threshold voltage. The nonlinearity coefficient of the selector may be in the range of 10 in some embodiments. 7 It can exceed.

[0029] The selectors described herein have high durability (e.g., a read or write voltage of at least 10 8 The selector also exhibits sufficient drive current density (e.g., 10 to 200 MHz) to implement many memory or computing applications. 6 μA / cm 2 The selectors described herein can thus enable high density memory and / or computing applications requiring high device uniformity and selectivity.

[0030] 1 is a schematic diagram illustrating a cross-sectional view of an example of a selector 100 according to some embodiments of the present disclosure. The selector 100 is a two-terminal device having exactly two terminals and may have a multi-layer tunnel barrier structure that approximates a triangular tunnel barrier.

[0031] As shown, the selector 100 may include a first electrode 110, a multi-layer barrier structure 120, and a second electrode 130. The first electrode 110 and the second electrode 130 may include any suitable conductive material, such as graphene.

[0032] A multi-layer barrier structure 120 may be constructed on the first electrode 110. The multi-layer barrier structure 120 may include multiple layers of vdW material forming a stepped tunnel barrier that may approximate a triangular tunnel barrier. As shown in FIG. 1, the multi-layer barrier structure 120 includes (2n+1) layers, where "1" represents the layer of vdM material at the center of the tunnel barrier ("central layer 121"), and n is a positive integer (e.g., 1, 2, 3, ...) representing the number of layers of vdM material between the central layer 121 and the first electrode 110, or the number of layers between the central layer 121 and the second electrode 130.

[0033] For example, the multilayer barrier structure 120 may include a central layer 121 constructed between the first electrode 110 and the second electrode 130. The central layer 121 may include a first vdW material. The multilayer barrier structure 120 may further include one or more layers 123 constructed between the first electrode 110 and the central layer 121, and one or more layers 125 constructed between the central layer 121 and the second electrode 130. Thus, the central layer 121 is sandwiched between n layers 123 and n layers 125. Each layer 123 and / or 125 may include a different vdW material than the first vdW material.

[0034] The selector 100 and multi-layer barrier structure 120 may have a stepped energy barrier that may approximate a desired triangular energy barrier (e.g., the stepped energy barrier 700b described with respect to FIG. 7B). The multi-layer barrier structure 120 may include a suitable number of layers of vdW material to form a stepped energy barrier. A selector with more layers of vdW material may form a finer stepped tunnel barrier to approximate a triangular tunnel barrier than a selector with fewer layers of vdW.

[0035] The vdW materials of the various layers of the multi-layer barrier structure 120 may have different electron affinities. The electron affinity of a material may refer to the amount of energy released when an electron of that material is added to a neutral atom to form a negatively charged ion. As will be discussed in more detail with respect to FIG. 4, different vdW materials may have different electron affinities. For example, SnS 2 , ZrS 2 , SnSe 2 , HfS 2 , MoS 2 , MoSe 2 , MoTe 2 , W.S. 2 , WSe 2, graphene (Gr), and h-BN have low electron affinities. The vdW material in the central layer may have the lowest electron affinity of the vdW materials in the multilayer barrier structure 120. The electron affinity of the n-layer vdM material disposed between the central layer 121 and the first electrode 110 may have an increasing electron affinity from the layer closest to the central layer 121 (i.e., layer 123a) to the layer closest to the first electrode 110 (i.e., layer 123n). The electron affinity of the n-layer vdM material disposed between the central layer 121 and the second electrode 130 may have an increasing electron affinity from the layer closest to the central layer 121 (i.e., layer 125a) to the layer closest to the second electrode 130 (i.e., layer 125n). The electron affinity of the layers 123a-n and the electrode affinity of the layers 125a-n may increase symmetrically or asymmetrically. For example, the electron affinity of layers 123a and 125a may or may not be the same, and the electron affinity of layers 123n and 125n may or may not be the same.

[0036] More specifically, for example, the electron affinity of central layer 121 is lower than the electron affinity of each of layers 123 and / or 125. The electron affinity of the inner layers of multilayer barrier structure 120 is lower than that of the adjacent outer layers, the inner layers being closer to central layer 121 than the outer layers. For example, layer 123a has a lower electron affinity than layer 123b. The electron affinity of layer 123n-1 is lower than that of layer 123n. As another example, the electron affinity of layer 125a is lower than that of layer 125b. The electron affinity of layer 125n-1 is lower than that of layer 125n.

[0037] The multi-layer barrier structure 120 may include one or more of the multi-layer barrier structures 120a, 120b, 120c described below with respect to Figures 2A-2C.

[0038] 5, when the voltage applied to the selector 100 is less than half (+V / 2 or −V / 2) of the threshold voltage V, the selector 100 can be in a high resistance state (OFF state). When the voltage applied to the selector 100 reaches or exceeds the threshold voltage V, the selector 100 is conductive and in an ON state.

[0039] 2A-2C are schematic cross-sectional views of example selectors 200a, 200b, and 200c according to some embodiments of the present disclosure.

[0040] As shown in Figure 2A, the selector 200a may include the first electrode 110 and the second electrode 130 described with respect to Figure 2. The selector 200a may further include a multi-layer barrier structure 120a including multiple layers of vdW material as an example of a (2n+1) multi-layer barrier structure, where n=1.

[0041] The multi-layer barrier structure 120a may include a central layer 121 of a first vdW material (also referred to as a "first layer of first vdW material"), a second layer 223a of a second vdW material, and a third layer 225a of a third vdW material. The electron affinity (also referred to as a "first electron affinity") of the central layer 121 and / or the first vdW material is lower than the electron affinity (also referred to as a "second electron affinity") of the second layer 223 and / or the second vdW material, and lower than the electron affinity (also referred to as a "third electron affinity") of the third layer 225 and / or the third vdW material. By way of example, the first vdW material may be h-BN. The second and third materials may be MoS 2 , W.S. 2 , WSe 2 The first electron affinity may be and / or may include any suitable vdW material having a higher electron affinity than the first electron affinity, such as, for example, ZnO, HfO, etc. In one implementation, the central layer 121, the second layer 223a, and the third layer 225a are layers of h-BN, MoS, etc. 2 layer, MoS 2 In another implementation, the central layer 121, the second layer 223a, and the third layer 225a may be layers of h-BN, WS 2 layer, WS 2 In another implementation, the central layer 121, the second layer 223a, and the third layer 225a may be layers of h-BN, WSe 2 layer, WSe 2 The layer may be

[0042] As another example, the first vdW material may be WSe 2 The second and third vdW materials can be WSe 2As a more specific example, the central layer 121, the second layer 223a, and the third layer 225a may each be made of WSe. 2 layer, MoSe 2 layer, and MoSe 2 The layer may include and / or be:

[0043] As shown in Figure 2B, the selector 200b may include the first electrode 110 and the second electrode 130 described with respect to Figure 1. The selector 200b may further include a multi-layer barrier structure 120b including multiple layers of vdW material. The multi-layer barrier structure 120n is an example of a (2n+1) multi-layer barrier structure, where n=2.

[0044] The multilayer barrier structure 120b may include a first layer 121 including a first vdW material, a second layer 223a of a second vdW material, and a third layer 225a of a third vdW material. The multilayer barrier structure 120b may further include a fourth layer 223b of a fourth vdW material constructed between the second layer 223a of the second vdW material and the first electrode 110. The multilayer barrier structure 120b may further include a fifth layer 225b of a fifth vdW material constructed between the third layer 225a of the third vdW material and the second electrode 130. The electron affinity of the second vdW material (second electron affinity) is lower than the electron affinity of the fourth vdW material (also referred to as "fourth electron affinity"). The third vdW material has a lower electron affinity (third electron affinity) than the fifth vdW material (also called the fifth electron affinity). As an example, the first vdW material can be h-BN. The second vdW material and the third material can be WSe 2 The fourth and fifth vdW materials may be MoS 2 As another example, the first vdW material can be WSe 2 The second material dvW and the third material vdW can be MoSe 2 The fourth and fifth vdW materials may be MoS 2 It could be.

[0045] Referring to FIG. 2C, the selector 200c may include the first electrode 110 and the second electrode 130 described with respect to FIG. 1. The selector 200c may further include a multi-layer barrier structure 120c including multiple layers of vdW materials. The multi-layer structure 120c is an example of a (2n+1) multi-layer barrier structure with n=3. The multi-layer barrier structure 120c may include layers 121, 223a, 223b, 225a, 225b as described above with respect to FIG. 2B. The multi-layer barrier structure 120c may further include a sixth layer 223c of a sixth vdW material and a seventh layer 225c of a seventh vdW material. The sixth layer 223c is constructed between the fourth layer 223b and the first electrode 110. The seventh layer 225c is constructed between the fifth layer 225b and the second electrode 130. The electron affinity of the fourth vdW material (fourth electron affinity) is lower than the electron affinity of the sixth vdW material (also called the sixth electron affinity). The electron affinity of the fifth vdW material (fifth electron affinity) is lower than the electron affinity of the seventh vdW material (also called the seventh electron affinity). For example, the first vdW material is WSe 2 The second vdW material and the third vdW material can be MoSe 2 The fourth and fifth vdW materials may be MoS 2 The sixth and seventh vdW materials can be HfS. 2 It could be.

[0046] 3A is a schematic diagram illustrating an example crossbar circuit 300 according to some embodiments of the present disclosure. As shown, the crossbar circuit 300 may include a plurality of interconnecting conductive wires, such as one or more bit lines 311a,...,311i,...,311n and word lines 313a,...,311j,...,311m, for an n-row by m-column crossbar array. The crossbar circuit 300 may further include cross point devices 320a, 320b,...,320z, etc. Each of the cross point devices may be connected to a bit line and a word line. For example, cross point device 320ij may connect bit line 311i and word line 313j.

[0047] In some embodiments, the crossbar circuitry 300 may further include digital-to-analog converters (DACs, not shown), analog-to-digital converters (ADCs, not shown), switches (not shown), and / or other suitable circuit components for implementing a crossbar-based device. The number of word lines 313a-m and the number of bit lines 311a-n may or may not be the same.

[0048] The bitlines 311 may include a first bitline 311a, a second bitline 311i, ..., and an nth bitline 311n. Each of the bitlines 311a,...,311n may be and / or include a suitable conductive material. In some embodiments, each bitline 311a-n may be a metal wire.

[0049] The word lines 313 may include a first word line 313a, a second word line 313j, ..., and an m-th word line 313m. Each of the word lines 313a-m may be and / or include a suitable conductive material. In some embodiments, each word line 313a-m may be a metal wire.

[0050] Each cross point device 320 may be and / or include a selector and one or more memory devices, such as memristors, resistive random access memory (RRAM), phase change memory (PCM), floating gate, spintronic devices, dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), static random access memory (SRAM), etc. Each of the cross point devices 320 may include one or more components, as described below with respect to FIG. 3B. In some embodiments, one or more of the cross point devices 320 may also include a selector that is serially connected to multiple memristor devices (also referred to as a 1SnR structure).

[0051] One or more of the cross point devices 320 may be selected to perform an operation (e.g., a read operation, a write operation, etc.). For example, to select a cross point device 320ij, an appropriate programming voltage equal to a selector threshold voltage V may be applied to the cross point device 320ij. More specifically, for example, a voltage of +V / 2 and a voltage of -V / 2 may be applied to the selected word line 313j and the selected bit line 311i, respectively. Thus, the voltage at the cross point device 320ij is the full voltage V. Thus, the cross point device changes to an ON state. The other cross point devices connected to the word line 313j and the other cross point devices connected to the bit line 311i are considered half-selected devices, since each of these devices receives either a voltage of +V / 2 or a voltage of -V / 2. The half-selected devices remain in an OFF state. The cross point devices that are not connected to either the word line 313j or the bit line 311i are unselected devices and may also remain in an OFF state. The on / off state of the cross point device corresponds to the on / off state of the selector. That is, when the voltage applied to the selector is higher than the threshold voltage V, the cross point device and the selector are in the on state, and when the voltage applied to the selector is lower than half the threshold voltage, +V / 2 or -V / 2, the cross point device and the selector are in the off state. In a 1S1R configuration in which one selector device is connected in series with one memory device, the resistance of the selector in the off state is much higher than that of the memory device. Therefore, according to the voltage division rule, the selector generates a voltage drop that is significantly larger than the voltage drop generated in the memory device. The voltage applied to the cross point device is dropped across the selector to turn the selector to the on state. According to the voltage division rule, when the selector is turned on (e.g., conductive), the voltage applied to the cross point device is dropped across the memory device for the operation of the memory device. When the selector is turned on, the memory device connected to the selector is selected.As discussed in more detail below, by applying appropriate programming signals to the memory devices, the memory devices can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS), such that the memory devices can have an on / off state or memory state that is independent of the on / off state of the cross point devices.

[0052] The crossbar circuit 300 may perform parallel voltage-weighted multiplication and current-weighted summation. For example, an input voltage may be applied to one or more rows (e.g., one or more selected rows) of the crossbar circuit 300. An input signal may flow to the crosspoint devices of the row of the crossbar circuit 300. The conductivity of the crosspoint devices may be adjusted to a particular value (also called "weighting"). According to Ohm's law, the input voltage is multiplied by the crosspoint conductivity to obtain a current from the crosspoint device. According to Kirchhoff's law, the currents passing through the devices in each column are summed to obtain a current as an output signal, which may be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array is expressed as I=VG, where I represents the output signal matrix as a current, V represents the input signal matrix as a voltage, and G represents the conductivity matrix of the crosspoint device. Thus, the input signals are weighted at each of the crosspoint devices according to Ohm's law. The weighted currents can be output through each word line and accumulated according to Kirchhoff's current law, which enables in-memory computing (IMC) via parallel multiplications and additions performed in a crossbar array.

[0053] 3B is a schematic diagram illustrating an example cross-point device 320 according to some embodiments of the present disclosure. As shown, the cross-point device 320 may include a memory device 321 and a selector 325 connected in series to the memory device 321.

[0054] The memory device 321 may include a switching oxide layer constructed between the top and bottom electrodes. The switching oxide layer may include one or more transition metal oxides, such as at least one of HfOx or TaOx, where x is used to indicate that the oxide is oxygen deficient compared to the complete (or final) oxide, and the value of x is x≦2.0 for HfOx (HfO 2 is a complete oxide), and for TaOx it is ≦2.5 (Ta 2 O 5 8A and 8B, the memory device 321 and the selector 325 may be stacked vertically such that they may share the same electrode as the top electrode of one device and the bottom electrode of the other device.

[0055] By applying appropriate programming signals to the RRAM device, the resistance of the memory device 321 can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS). For example, the RRAM device can be in an initial or virgin state and have an initial high resistance before undergoing electrical simulation (e.g., voltage or current signals applied to the RRAM device). The memory device 321 can be changed from a low resistance state to a virgin state through a formation process, or from HRS to LRS through a set process. A formation process can refer to programming of the device starting from a virgin state. A set process can refer to programming of the device starting from a HRS.

[0056] As described above with respect to Figures 1-2C, the selector 325 may be and / or include the selectors 100, 200a, 200b, and / or 200c. The selector 325 is a two-terminal device that acts as a bipolar switch to control the current in the memory device 321. The current through the selector varies nonlinearly with the voltage applied to the selector. When the voltage applied to the selector 325 is less than half the threshold voltage (+V / 2 or -V / 2), the selector 325 may be in a high resistance state. When the voltage applied to the selector 325 reaches or exceeds the threshold voltage V, the selector 325 becomes conductive and the memory device 321 connected to the selector is selected to operate. An appropriate programming voltage (a voltage equal to or greater than the threshold voltage) may be applied to the cross point device 320 to program the memory device 321 to a desired conductivity.

[0057] FIG. 4 illustrates the band gaps and electron affinities of example vdW materials according to some embodiments of the present disclosure. As shown, each vdW material is associated with a particular energy band Eg (the rectangular bar represents the band gap of the selected vdW material, which corresponds to the difference between the minimum energy of the conduction band (Ec) and the maximum energy of the valence band (Ev)). As shown in FIG. 4, different vdW materials can have a variety of electron affinities. For example, as shown in FIG. 4, SnS 2 , ZrS 2 , HfS 2 , MoS 2 , MoTe 2 , WSe 2 , graphene (Gr), and h-BN have low electron affinities.

[0058] FIG. 5 illustrates the current-voltage (I-V) characteristics of a selector according to some embodiments of the present disclosure. As illustrated, the selector exhibits current-voltage nonlinearity. That is, the current passing through the selector varies nonlinearly with the voltage applied to the selector. The nonlinearity of the selector may be measured by a nonlinearity coefficient K, which corresponds to the ratio of the current at a full voltage V (e.g., current 501 corresponding to voltage 511 shown in FIG. 5) to the current at half the full voltage (V / 2) (e.g., current 503 corresponding to voltage 513 shown in FIG. 5). The full voltage V may be a threshold voltage that may switch the selector into a conductive state. That is, when the voltage applied to the selector reaches or exceeds the full voltage V, the selector is conductive and the memory or computing cell controlled by the selector is selected. As shown in FIG. 6, the value of K is about 10 7 or 10 7 Therefore, the selector disclosed herein exhibits high non-linearity.

[0059] 6 is a diagram illustrating the nonlinearity of a selector according to some embodiments of the present disclosure. As shown, the nonlinearity coefficient K of the selector is 10 7 The value of K is 10 for various applications. 2 , 10 5 etc. Thus, the selector has a desirable high degree of non-linearity.

[0060] 7A is a band diagram of an example tunnel barrier 700a of a selector according to some embodiments of the present disclosure. The energy barrier 700a has an E 0 The tunnel barrier 700a is also called a triangular tunnel barrier. The total width of the barrier is 2a (-a to +a on the X-axis). The external voltage V applied Without it, E 0 Electrons with lower energy (represented by arrow 750a) must tunnel through the energy barrier. Therefore, the current through the selector is low and the selector is in the off state. appliedWhen a voltage is applied to the selector, the energy barrier is lowered, as shown by dotted line 711a. Electrons, represented by arrow 750a, are free to move across the barrier. Therefore, the current through the selector is high and the selector is in the on (conducting) state.

[0061] 7B is a band diagram of an example energy barrier 700b of a selector according to some embodiments of the present disclosure. The energy barrier 700b may be referred to as a stepped energy barrier and may approximate the triangular tunnel barrier 700a of FIG. 7A. As shown, the energy barrier 700b has a stepped shape defined by lines 701b, 702b, 703b, 704b, 705b, 706b, and 707b, with a barrier height E at the center of the barrier. 0 The total width of the barrier is 2a (-a to +a on the X-axis). This may be an example of the (2n+1) layers with n=1 shown in FIG. 2A, with central layer 121 sandwiched between layers 223a and 225a. Energy barrier 700b is symmetric about the Y-axis, which represents energy, but this is for illustrative purposes only. In some embodiments, energy barrier 700 is not symmetric about the Y-axis.

[0062] External voltage V applied Without it, E 0 Electrons with lower energy (represented by arrow 750b) must tunnel through the energy barrier. Therefore, the current through the selector is low and the selector is in the off state. The external voltage V applied When a voltage is applied to the selector, the energy barrier is lowered, as shown by dotted line 711b. Electrons, represented by arrow 750b, are free to move across the barrier. Thus, the current through the selector is high and the selector is in the on (conducting) state. A selector with more layers of vdW material has a step-like energy barrier with finer steps, and therefore may more closely resemble a triangular tunnel barrier 700a than a selector with fewer layers of vdW material.

[0063] 8A and 8B are schematic diagrams illustrating cross-sectional states of an example of a 1S1R structure according to some embodiments of the present disclosure.

[0064] As shown in FIG. 8A, the 1S1R structure 800a may include a first electrode 110, a multi-layer barrier 120 built on the first electrode 110, and a second electrode 130 built on the multi-layer barrier structure 120 to complete the selector 805. A memory device 810 may be built on the second electrode 130 of the selector 805. The memory device 810 may have its own device stack including a bottom electrode, a switching oxide, and a top electrode. In some embodiments, the memory device 810 may share one or more electrodes with the selector 805 (e.g., by using the second electrode 130 as a bottom electrode). The first electrode 110, the multi-layer barrier structure 120, and the second electrode 130 may correspond to the equivalents described above with respect to FIGS. 1-2C. In this implementation, the memory device 810 is built above the second electrode 130 of the selector 805.

[0065] The memory device 810 may be and / or include any suitable material with programmable conductivity, such as a memristor, RRAM, PCM, floating gate, spintronic device, DRAM, FeRAM, SRAM, etc. In some embodiments, the memory device 810 may be a HfO x , TaO x , TiO x , NbO x , ZrO x In some embodiments, the switching oxide layer may include one or more transition metal oxides such as HfO. x Or TaO x where x is used to refer to an oxide that is oxygen deficient compared to the complete (or final) oxide, and for HfOx, x≦2.0 (HfO 2 is a complete oxide), and for TaOx, x≦2.5 (Ta 2 O 5 The value of x can vary from the oxygen-metal atomic ratio of the complete oxide stoichiometry, such as x being the complete oxide.

[0066] As shown in FIG. 8B, the 1S1R structure 800b may include a memory device 810 and a selector 805. In this implementation, the selector 805 is built on the memory device 810. The first electrode 110, the multi-layer barrier structure 120, and the second electrode 130 may be built in sequence above the memory device 810 as described above. The memory device 810 may have a unique device stack including a bottom electrode, a switching electrode, a top electrode, etc. The multi-layer barrier structure 120 is built on the first electrode 110, and the second electrode 130 is built on the multi-layer barrier structure 120.

[0067] Although certain layers are shown in Figures 1, 2A-2C, and 8A-8B, they are for illustrative purposes only. The selectors and 1S1R structures described herein may also include components and / or layers suitable for implementing memory and computing applications. For example, memory device 810 may include one or more interface layers (not shown) of one or more materials that are more chemically stable than the transition metal oxide of the switching oxide layer.

[0068] 9 is a flow diagram illustrating an example method 900 for constructing a selector and / or a 1S1R structure according to some embodiments of the present disclosure. The 1S1R structure may be the 1S1R structure 800a described with respect to FIG. 8A.

[0069] In block 910, a first electrode 110 may be constructed. The first electrode may include the second electrode 110 described with respect to Figure 1 above. Construction of the first electrode may involve depositing a layer of a suitable conductive material.

[0070] In block 920, a multi-layer barrier structure may be constructed on the first electrode. The multi-layer barrier structure may include multiple layers of vdW materials. The multi-layer barrier structure may be and / or may include the multi-layer barrier structures 120, 120a, 120b, and / or 120c described with respect to FIGS. 1-2C. The construction of the multi-layer barrier structure may include constructing a layer 123n on the first electrode, constructing a central layer 121, and constructing a layer 125n. The construction of the multi-layer barrier structure may further include constructing one or more layers 123i between layers 123a and 123n, and one or more layers 123j between layers 125a and 125n. Each of the layers of vdW materials may be grown by various ultra-thin film deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). In some embodiments, a multi-layer barrier structure may be constructed using a suitable layer transfer technique, for example by transferring one or more layers of vdW material to a first electrode and / or by transferring one or more other vdW layers of the multi-layer barrier structure to construct a selector.

[0071] At block 930, a second electrode may be constructed over the multi-layer barrier structure. The second electrode may include second electrode 130 described above with respect to Figure 1. Construction of the second electrode may involve depositing a layer of a suitable conductive material in the memory device.

[0072] At block 940, a memory device may be constructed over the second electrode of the selector device. Construction of the memory device may involve constructing a bottom electrode, a switching oxide layer, a top electrode, etc. The switching oxide layer may be TaO x , HfO x , TiO x , NbO x , ZrO x The switching oxide layer may include one or more transition metal oxides such as. The switching oxide layer may be deposited using PVD, CVD, ALD, and / or other suitable deposition techniques. In some embodiments, the second electrode of the selector device may be used as a bottom electrode of the memory device.

[0073] 10 is a flow diagram illustrating an example method 1000 for constructing a selector and a 1S1R device according to some embodiments of the present disclosure. The 1S1R structure may be the 1S1R structure 800b described with respect to FIG. 8B.

[0074] In block 1010, a memory device can be constructed. The memory device can be the memory device 810 described with respect to FIG. 8B with a unique device stack including a bottom electrode, a switching oxide, a top electrode, etc. The construction of the memory device can be performed using TaO x , HfO x , TiO x , NbO x , ZrO x The switching oxide layer may include constructing a switching oxide layer including one or more transition metal oxides such as, for example, a SiO 2 layer ...

[0075] In block 1020, a first electrode 110 may be constructed over the memory device 810. In some embodiments, the top electrode of the memory device 810 may also be used as the first electrode 110 of the selector device.

[0076] In block 1030, a multi-layer barrier structure may be constructed over the first electrode 110. For example, one or more of the operations described with respect to block 920 of Figure 9 may be performed to construct the multi-layer barrier structure.

[0077] At block 1040, a second electrode may be constructed on the multi-layer barrier structure. The second electrode may include second electrode 130 described above with respect to Figure 1. Construction of the second electrode may involve depositing a layer of a suitable conductive material on the memory device.

[0078] For simplicity of explanation, the methods of the present disclosure have been shown and described as a series of operations. However, operations according to the present disclosure may be performed in various orders and / or in parallel, and with other operations not shown and described herein. Moreover, not all illustrated operations are required to implement a methodology in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states via a state diagram or events.

[0079] The terms "approximately," "about," and "substantially" may be used in some embodiments to mean within ±20% of a target dimension, in some embodiments within ±10% of a target dimension, in some embodiments within ±5% of a target dimension, and even in some embodiments within ±2% of a target dimension. The terms "approximately" and "about" may be inclusive of the target dimension.

[0080] In the preceding description, numerous details are set forth. It will be apparent, however, that the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the disclosure.

[0081] The words "first," "second," "third," "fourth," etc., as used herein, are meant as labels distinguishing between different elements and do not necessarily have an ordinal meaning in accordance with numerical designations.

[0082] The word "example" or "exemplary" is used herein to mean serving as an example, illustration, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word "example" or "exemplary" is intended to present a concept in a concrete manner. As used in this application, the word "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A, X includes B, or X includes both A and B, then "X includes A or B" is satisfied in any of the above cases. In addition, the articles "a" and "an" as used in this specification and the appended claims should generally be construed to mean "one or more," unless otherwise specified or clear from the context that it is in the singular. References throughout this specification to "an implementation" or "one implementation" mean that a particular feature, structure, or characteristic described with respect to an implementation is included in at least one implementation. Thus, the appearances of the phrase "an implementation" or "one implementation" in various places throughout this specification are not necessarily all referring to the same implementation.

[0083] As used herein, when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or layers present.

[0084] Although many variations and modifications of the present disclosure will no doubt become apparent to those skilled in the art after reading the preceding description, it should be understood that the specific embodiments shown and described by way of illustration are not intended to be considered in any way limiting. Therefore, reference to details of various embodiments is not intended to limit the scope of the claims, which themselves recite only those features that are deemed to be disclosed. [Explanation of symbols]

[0085] 100 Selector 110 1st electrode 120, 120a, 120b, 120c Multi-layer barrier structure 121 Central layer / 1st layer 123a,123b,...,123n-1,123n layers 125a,125b,...,125n-1,125n layers 130 2nd electrode 200a, 200b, 200c selector 223a 2nd layer 223b 4th layer 223c 6th layer 225a 3rd layer 225b 5th layer 225c 7th layer 300 Crossbar Circuit 311a, 311i, 311n bit lines 313a, 313j, 313m word lines 320;320a,320b,320ij,320z Crosspoint Device 321 Memory Devices 325 Selector 501 Current 503 Current 511 Voltage 513 Voltage 700a,b Energy Barrier 701a, 701b Symmetry lines 702b line 703a, 703b Symmetry lines 704b line 705b line 706b line 707b line 711a,b dotted line 750a,b Arrow 800a,b 1S1R structure 805 Selector 810 Memory Devices 900 Example method 1000 Method Examples E 0 Barrier height

Claims

1. A selector comprising a multi-layer barrier structure formed between a first electrode and a second electrode, The multi-layer barrier structure comprises: a plurality of layers of van der Waals (vdW) material; The layers of van der Waals (vdW) material include a first layer having a first van der Waals (vdW) material; a second layer having a second vdW material; a third layer having a third vdW material; and Equipped with a first electron affinity of the first layer having the first vdW material is lower than a second electron affinity of the second layer having the second vdW material and a third electron affinity of the third layer having the third vdW material; the first vdW material has the lowest electron affinity of the van der Waals (vdW) materials of the multi-layer barrier structure; the first vdW material comprises WSe 2 ; the second vdW material comprises at least one of MoSe2, MoS2, or HfS2; selector.

2. the first layer having the first vdW material is formed between the second layer having the second vdW material and the third layer having the third vdW material. The selector of claim 1.

3. the first vdW material comprises h-BN; The second vdW material is MoS ２ , W.S. ２ , or WSe ２ At least one of The selector of claim 1.

4. The third vdW material is MoS ２ , W.S. ２ , or WSe ２ At least one of The selector of claim 3.

5. the multi-layer barrier structure further comprising a fourth layer of a fourth vdW material; the second electron affinity of the second vdW material is lower than the fourth electron affinity of the fourth vdW material; The selector of claim 1.

6. the fourth layer of the fourth vdW material is formed between the second layer of the second vdW material and the first electrode. The selector of claim 5.

7. the multi-layer barrier structure further comprising a fifth layer of a fifth vdW material; the third electron affinity of the third layer of the third vdW material is lower than a fifth electron affinity of the fifth layer of the fifth vdW material; The selector of claim 5.

8. the fifth layer of the fifth vdW material is formed between the third layer having the third vdW material and the second electrode. The selector of claim 7.

9. the multi-layer barrier structure includes (2n+1) layers of vdW material; n is a positive integer; The selector of claim 1.

10. The selector of claim 1 , wherein the multi-layer barrier structure forms a stepped tunnel barrier that approximates a triangular tunnel barrier.

11. The ratio of a first current passing through the selector in response to a first voltage to a second current passing through the selector in response to a second voltage is 10 ２ That's all. the second voltage is half the first voltage; The selector of claim 1.

12. 1. An apparatus having a selector and a memory device connected in series to the selector, the selector comprises a multi-layer barrier structure formed between a first electrode and a second electrode; The multi-layer barrier structure comprises: a plurality of layers of van der Waals (vdW) material; The layers of van der Waals (vdW) material include a first layer having a first van der Waals (vdW) material; a second layer having a second vdW material; a third layer having a third vdW material; and Preparation, a first electron affinity of the first layer having the first vdW material is lower than a second electron affinity of the second layer having the second vdW material and a third electron affinity of the third layer having the third vdW material; the first vdW material has the lowest electron affinity of the van der Waals (vdW) materials of the multi-layer barrier structure; the multi-layer barrier structure further comprising a fourth layer of a fourth vdW material; the second electron affinity of the second vdW material is lower than the fourth electron affinity of the fourth vdW material; Device.

13. The memory device comprises: including at least one of a memristor, a resistive random access memory (RRAM), a phase change memory (PCM), a floating gate, a spintronics device, a dynamic random access memory (DRAM), a ferroelectric random access memory (FeRAM), or a static random access memory (SRAM); 13. The apparatus of claim 12.

14. the first vdW material comprises h-BN; The second vdW material is MoS ２ , W.S. ２ , or WSe ２ At least one of 13. The apparatus of claim 12.

15. The third vdW material is MoS ２ , W.S. ２ , or WSe ２ At least one of 15. The apparatus of claim 14.

16. The first vdW material is WSe ２ having The second vdW material is MoSe ２ , MoS ２ , or HfS ２ At least one of 13. The apparatus of claim 12.

17. The device further comprises the first electrode and the second electrode.

13. The apparatus of claim 12.

18. the selector has a stepped tunnel barrier approximating a triangular tunnel barrier; 13. The apparatus of claim 12.

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