Carrier substrate for SOI structures and associated manufacturing method - Patents.com

Abstract

The present invention relates to a carrier substrate (10) made of monocrystalline silicon having a front surface (10a) and a back surface (10b), wherein the surface region (1) extends from the front surface (10a) to a depth of 800 nm to 2 microns, where less than 10 crystal-origin particles (COPs) are detected by examining the surface using dark-field microscopy, and the surface region (1) extends from the front surface (10a) downward to a depth of a few microns to 40 microns, where the surface region (1) has a conductivity of 7.5E17 Oi / cm 3 an upper region (2) having an interstitial oxygen (Oi) content of less than or equal to 100 Ωcm and a resistivity higher than 500 Ωcm; and a lower region (10b) extending between the upper region (2) and the rear surface (10b) having a resistivity of 1E8 / cm 3 and a lower region (3) having a black matrix defect (BMD) concentration of at least 1000 nm.

Description

[Technical field]

[0001] FIELD OF THEINVENTION The field of the invention is that of semiconductors and microelectronics. The invention relates to a carrier substrate made of silicon for silicon-on-insulator (SOI) structures, in particular for fully depleted silicon-on-insulator (FD-SOI) structures suitable for logic and radio frequency applications. The invention also relates to a method for manufacturing such a carrier substrate. Description of the Prior Art

[0002] (Technical Background of the Invention) The advantages of FD-SOI technology have already been widely demonstrated for radio frequency and low power logic applications.

[0003] To meet the stringent specifications of these applications, FD-SOI structures must meet several criteria.

[0004] Firstly, the very thin functional layer made of silicon (typically around 20 nm) must exhibit excellent thickness uniformity and high crystal quality. To achieve this, this functional layer must be able to undergo, especially during its manufacture, long treatments at high temperatures, which are required to smooth its free surface and repair the crystal defects present in this layer. This includes that the carrier substrate of the SOI structure must be resistant to slip line failure modes, and in particular exhibit a sufficient and uniform density of microdefects throughout (BMD, short for bulk microdefects). These microdefects are usually present in sufficient quantities in substrates with a high interstitial oxygen content ("high Oi" substrates), typically exceeding 1E18 / cm. 3 Accommodates higher Oi concentrations than (ASTM'79 standard): These high Oi carrier substrates are particularly robust against slip line defects.

[0005] Secondly, the SOI structure must be compatible with very low inspection thresholds to allow the detection of defects on and / or in the functional layer smaller than 50 nm in size. High-Oi carrier substrates are known to contain defects called "crystal-origin particles" (COPs) that limit the inspectability of the functional layer of the SOI structure; specifically, COP defects located in the surface zone of the carrier substrate are detected with very thorough detection thresholds during the inspection of the functional layer, even if those defects remain below the buried oxide layer of the SOI structure, due to the penetration of the inspection signal probing slightly below the buried oxide layer. Therefore, high-Oi carrier substrates are not compatible as such for such applications.

[0006] Finally, to meet the radio frequency requirements, the carrier substrate of the SOI structure must exhibit a stable high resistivity (higher than 500 Ωcm, higher than 1000 Ωcm, or even higher than 5000 Ωcm). To obtain these properties, it is necessary to use high resistivity carrier substrates with low Oi content ("low Oi" substrates, typically 8E17 Oi / cm), since carrier substrates with high Oi content exhibit resistivity instability with depth, especially due to the smoothing heat treatment required for the functional layers. 3 It is common to use low Oi carrier substrates (corresponding to Oi concentrations below 100 nm). Unfortunately, low Oi carrier substrates are extremely sensitive to long treatments at high temperatures and subsequently exhibit a high density of slip lines that are detrimental to the SOI structure. Summary of the Invention

[0007] (Subject of the Invention) The present invention provides a solution that overcomes all or some of the aforementioned drawbacks. In particular, the present invention relates to a carrier substrate that is compatible with the thermal processes imposed on SOI structures and with the stringent specifications of logic and radio frequency applications. The present invention also relates to a method for manufacturing such a carrier substrate.

[0008] BRIEF DESCRIPTION OF THE DRAWINGS The present invention provides a carrier substrate made of monocrystalline silicon having a front surface and a back surface, a surface region from 800 nm to 2 microns deep from the front surface, where less than 10 crystal-origin particles (COPs) are detected by examining the surface using dark field microscopy; The upper region extending from the front surface to a depth of a few microns to 40 microns has a surface area of ​​7.5E17Oi / cm 3 an upper region having an interstitial oxygen (Oi) content equal to or less than 500 Ω cm and a resistivity greater than 500 Ω cm; Extends between the top region and the back, 1E8 / cm 3 a lower region having a black matrix defect (BMD) concentration equal to or greater than the The present invention relates to a carrier substrate comprising:

[0009] According to some advantageous features of the present invention, taken alone or in any feasible combination, The resistivity of the upper region is 750 Ω cm or more, or 1000 Ω cm or more; the upper region extending downward to a depth of between 10 microns and 30 microns; The density of micro defects (BMD) in the lower region is 1E8 / cm 3 ~3E10 / cm 3 , preferably 1E9 / cm 3 ~2E10 / cm 3 It is.

[0010] The invention also relates to an SOI structure comprising a functional layer arranged on a dielectric layer, which is itself arranged on a carrier substrate as described above. The functional layer may have a thickness of less than 50 nm, preferably between 4 nm and 25 nm, and the dielectric layer may have a thickness of between 10 nm and 150 nm.

[0011] The invention also relates to an electronic component for radio frequency and low power logic applications comprising at least one transistor arranged on and / or in a functional layer of an SOI structure as described above.

[0012] Finally, the invention relates to a method for manufacturing a carrier substrate as described above, the manufacturing method comprising the following steps: a) 12E17Oi / cm 3 ~16E17Oi / cm 3 providing an initial substrate made of monocrystalline silicon having an interstitial oxygen content of 0.01% and a resistivity higher than 500 Ω cm, the initial substrate being intended to form a carrier substrate after the subsequent steps b) and c), b) subjecting the first heat treatment at a temperature between 1150° C. and 1250° C. in a neutral or reducing atmosphere for a duration of at least 30 minutes to form a surface region and a top region; c) performing a second heat treatment, including a first sequence of annealing at a temperature between 600°C and 900°C and a second sequence of annealing at a temperature between 950°C and 1100°C, to form a lower region of the carrier substrate; Includes.

[0013] Advantageously, the first sequence of the second heat treatment comprises two temperature plateaus, the first being between 650°C and 700°C and the second being around 800°C.

[0014] Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 shows a carrier substrate according to the present invention. [Diagram 2] 1 shows a SOI structure with a carrier substrate according to the present invention; [Figure 3a] 3A-3D illustrate steps of a method for manufacturing a carrier substrate according to the invention; [Figure 3b] 3A-3D illustrate steps of a method for manufacturing a carrier substrate according to the invention; [Figure 3c] 3A-3D illustrate steps of a method for manufacturing a carrier substrate according to the invention; [Figure 4]2 shows two maps obtained from surface inspection using dark field microscopy of the surface of an initial substrate (a) not treated with the manufacturing method according to the invention, and of an intermediate substrate (b) after the first heat treatment of the manufacturing method according to the invention. [Diagram 5] FIG. 2 shows an edge of a carrier substrate according to the invention after chemical activation of BMD type micro-defects. [Figure 6] FIG. 2 shows a resistivity versus depth curve for a carrier substrate according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Detailed Description of the Invention In the drawings, the same reference numbers may be used for elements of the same nature.

[0017] The figures are schematic representations and are not drawn to scale for ease of reading, in particular the layer thicknesses along the z-axis are not drawn to scale relative to the lateral dimensions along the x- and y-axes.

[0018] The invention relates to a monocrystalline silicon carrier substrate 10 having a front surface 10a and a rear surface 10b substantially parallel to a main surface (x,y). The carrier substrate is advantageously in the form of a circular wafer having a diameter between 200 mm and 450 mm. The total thickness of the carrier substrate along a z-axis perpendicular to the main surface (x,y) may range from a few hundred microns to 1000 microns.

[0019] The carrier substrate 10 comprises a surface region 1 from the front surface 10a to a depth of about 1 micron, typically 800 nm to 2 microns. This surface region 1 exhibits the particularity of a very low density of crystal-origin particles (COPs). A direct means of detecting these COPs is to use surface inspection equipment based on dark-field microscopy, which is usually implemented to measure surface defect densities. It is possible to use, for example, an instrument such as the KLA-Tencor Surfscan SP2®, known from the field of microelectronics. In oblique incidence mode (narrow oblique channel) and a detection threshold of 44 nm, less than 10 COPs are detected on the front surface 10a of the carrier substrate 10 according to the invention.

[0020] The carrier substrate 10 comprises a top region 2 extending from a front surface 10a to a depth of a few microns to 40 microns, preferably to a depth of 10 microns to 30 microns.

[0021] Upper region 2 is 7.5E17Oi / cm 3 The upper region 2 has an interstitial oxygen (Oi) content of 0.1 to 1.0 ppma (corresponding to a content of 0.1 to 15 ppma (according to the ASTM '79 standard)). Moreover, the upper region 2 has a resistivity higher than 500 Ω cm, corresponding to a low concentration of p-type dopant (boron). Advantageously, the resistivity is 750 Ω cm or higher, or even 1000 Ω cm or higher. The level of resistivity is defined depending on the targeted application and the electronic components that will be subsequently manufactured on the carrier substrate 10. The resistivity range of the upper region 2 is particularly suitable for radio frequency components targeted for applications in the 30 to 300 GHz band, including millimeter wave ("mmWave"), and is of particular note for supporting 5G networks for the next generation of mobile phones.

[0022] The carrier substrate 10 finally comprises a lower region 3 extending between the upper region 2 and the rear surface 10b, the thickness of which is of the order of a few hundred microns. 3The lower region 3 preferably has a BMD concentration of 1E8 / cm or more, which provides the lower region 3 with high mechanical robustness against heat treatment at high temperatures. 3 ~3E10 / cm 3 and more preferably 1E9 / cm 3 ~2E10 / cm 3 It is.

[0023] The lower region 3 has a potentially variable resistivity, typically above 250 Ωcm, but this does not have a substantial impact on future radio frequency components, since the electromagnetic fields generated by said components do not or only slightly reach the lower region 3. Only the resistivity of the upper region 2 must exhibit a stable and sufficiently high value.

[0024] To enable the production of the components, the functional layers on or in which said components are to be arranged must be transferred onto the carrier substrate 10 .

[0025] The present invention therefore also relates to a silicon-on-insulator (SOI) structure 100 comprising a functional layer 30 arranged on a dielectric layer 20, which is itself arranged on the above-mentioned carrier substrate 10 (Figure 2).

[0026] The functional layer 30 is made of high quality monocrystalline silicon and has a thickness of less than 50 nm, preferably between 4 nm and 25 nm. This thickness range is particularly suitable for electronic components based on FD-SOI architecture and technology. The dielectric layer 20 itself, made of, for example, silicon oxide, has a thickness of between 10 nm and 150 nm.

[0027] The presence of a surface region 1 of the carrier substrate 10 exhibiting a very low density of crystal-origin particles (COPs) provides excellent inspectability of the SOI substrate 100, with a very low detection threshold (<50 nm). Thus, the quality of the functional layer 30 can be precisely and reliably controlled, without disturbances and / or false detections due to the presence of COPs on the surface of the carrier substrate 10.

[0028] The invention also relates to electronic components for radio frequency and low power logic applications. Such components include, in particular, at least one transistor arranged on and / or in the functional layer 30 of the SOI structure 100. The properties of the upper region 2 of the carrier substrate 10, namely the resistivity and the low Oi concentration, give this region very good insulating performance: in particular, in addition to being at a high level, the resistivity is also stable in this region 2 since it does not undergo variations due to oxygen thermal donors that counteract the initial p-type doping and excessively high Oi concentrations that may generate micro-BMDs. Thus, the upper region 2 does not undergo any decrease or substantial variations in resistivity during the thermal treatment at high temperatures (>1100° C.) to which the SOI structure 100 is subjected. In addition, the high density of micro-defects (BMDs) in the lower region 3 of the carrier substrate 10 gives this substrate excellent mechanical strength and insensitivity to slip line defects during said thermal treatment.

[0029] The invention further relates to a method for manufacturing a carrier substrate 10 as described above.

[0030] The manufacturing method is 12E17Oi / cm 3 ~16E17Oi / cm 3 The method comprises a step a) of providing an initial substrate 10' made of monocrystalline silicon having an interstitial oxygen content of 10 ...

[0031] The initial substrate 10' has a resistivity higher than 500 Ωcm, i.e. 2.6E13 / cm 3It has a concentration of p-type dopant (boron) of 0.1 to 1.0 μm. After going through the subsequent steps b) and c) of the method, it is intended to form a carrier substrate 10. The resistivity of the initial substrate 10' is therefore selected to have a value required for the upper region 2 of the carrier substrate 10 depending on the intended application. Advantageously, the resistivity of the initial substrate 10' is greater than or equal to 750 Ωcm, or even greater than or equal to 1000 Ωcm.

[0032] During a next step b) of the method, the initial substrate 10' is subjected to a first heat treatment in a neutral or reducing atmosphere at a temperature between 1150° C. and 1250° C. The duration of this treatment is greater than or equal to 30 minutes, for example between 5 hours and 10 hours.

[0033] The role of this first heat treatment is to dissolve the crystal grains (COPs) in the surface area of ​​the initial substrate 10' over a depth of 800 nm to 2 microns, thereby forming the surface area 1 of the future carrier substrate 10.

[0034] The COP can be dissolved, for example, by rapid thermal annealing (RTA) at temperatures around 1250° C. for 10 seconds with rapid up- and down-ramp (50° C. / min) under a neutral (argon) or reducing (argon and hydrogen) atmosphere. Alternatively, the COP in surface region 1 can also be dissolved by annealing in a conventional oven, for example at 1200° C. for 30 minutes or 1 hour, also under a neutral or reducing atmosphere.

[0035] An additional role of the first heat treatment is to outdiffuse interstitial oxygen (Oi) and deplete the initial substrate 10' of Oi in a region from the front surface 10a to a more or less certain depth, depending on the duration of the heat treatment. Typically, for a treatment temperature of 1200° C. and a duration of 10 hours, the substrate is depleted of Oi over a depth of the order of 20 microns. This forms the upper region 2 of the future carrier substrate 10.

[0036] The first thermal treatment can therefore consist of either a single anneal or a series of anneals, in the same or different equipment, that fulfill both of the above mentioned roles, allowing the dissolution of the COP and the sequential out-diffusion of the interstitial oxygen.

[0037] At the end of the first thermal treatment, an intermediate substrate 10'' is obtained, which comprises a surface region 1 from 800 nm to a depth of 2 microns from the front surface 10a. This surface region 1, as shown in FIG. 4(b), shows a very low density of crystal-origin particles (COPs) compared to FIG. 4(a) corresponding to the initial substrate 10' before any treatment. The map in FIG. 4 was generated with an apparatus such as a KLA-Tencor SP2, in oblique incidence mode, on a wafer with a diameter of 300 mm, with a detection threshold of 44 nm: more than 1000 COPs are detected on the front surface 10a of the initial substrate 10' prepared in step a) of the method, whereas after the first thermal treatment of step b), less than 10 COPs, or even less than 5 COPs, are detected on the front surface 10a of the intermediate substrate 10'' (only one COP in the example of FIG. 4(b)).

[0038] It is observed that after removing about 1 micron of material from the front side 10a of the intermediate substrate 10'', the number of detected COPs remains very low, still less than 10. This allows the thickness of the surface region 1 with low COP density to be assessed.

[0039] The intermediate substrate 10'' also includes an upper region 2 extending from the front surface 10a to a depth of a few microns to 40 microns, preferably to a depth of 10 microns to 30 microns. The upper region 2 is depleted by the first heat treatment with respect to the Oi content of the initial substrate 10', to 7.5E17 Oi / cm 3 The upper region 2 has an interstitial oxygen (Oi) content of 0.1 to 1.0 μm, the resistivity of which is higher than that of the initial substrate 10', i.e. 500 Ωcm. This upper region 2 can be compared to silicon with a low Oi content ("low Oi" silicon), which gives it a good stability in terms of resistivity, even when the substrate is exposed to very high temperatures.

[0040] The manufacturing method then comprises a step c) in which a second heat treatment is applied to the intermediate substrate 10''. This treatment comprises a first sequence of annealing at a temperature between 600°C and 900°C and a second sequence of annealing at a temperature between 950°C and 1100°C.

[0041] The first annealing sequence comprises two temperature plateaus: a first plateau at 650°C to 700°C, lasting for 30 minutes to 10 hours, in a neutral atmosphere or with a low oxygen flow (typically about 0.075 standard liters per minute (slm) O2 and about 0.015 slm O2 in an oven for 300 mm wafers and an oven for 200 mm wafers, respectively). The role of this first plateau is to promote the nucleation of "nuclear" defects of small size (typically less than 10 nm, or even less than 5 nm), especially in the lower region of the intermediate substrate 10'' (below the upper region 2), which contains a high Oi concentration. These nuclei are small SiO x Precipitations can occur either heterogeneously, i.e. on pre-existing defects (vacancies) in the material, or homogeneously, i.e. by migration of oxygen atoms and formation of SiO2 bonds and SiO x These precipitates do not form, or do not form significantly, in the upper region 2 where Oi is depleted. Moreover, even if a few nuclei are formed in the upper region 2, due to the low amount of Oi, these nuclei cannot grow in the second sequence of the second heat treatment (described below) and therefore dissolve.

[0042] A second plateau around 800° C., lasting 30 min to 10 h, in a neutral atmosphere or with a low oxygen flow rate: the second plateau initiates a second stage of nucleation forming other nuclei between the first ones in the lower region of the intermediate substrate 10″, thus increasing the density of nuclei. It is noted that an oxidizing atmosphere (wet or dry) can be used, preferably after half or three-quarters of the duration of the second plateau has elapsed.

[0043] Thereafter, a second sequence of a second heat treatment lasting from 5 to 20 hours results in the diffusion of the interstitial oxygen Oi and its precipitation on the numerous nuclei present in the lower region of the substrate 10'', which causes the interstitial oxygen Oi to grow and become stabilized in the material. The microdefects thus created are known as BMDs, short for bulk microdefects.

[0044] A lower region 3 of the carrier substrate 10 rich in BMD microdefects is thus formed (FIG. 3c). 3 ~3E10 / cm 3 , preferably 1E9 / cm 3 ~2E10 / cm 3 A BMD concentration in the lower region 3 of a few 1E9 / cm is achieved. Figure 5 corresponds to an optical microscope image of the edge of the carrier substrate 10 after chemical etching to reveal the BMD micro-defects: a defect-free zone is observed in the upper region 2 over a thickness of the order of 20-25 microns. In contrast, the lower region 3 has a BMD concentration of a few 1E9 / cm 3 Typically, in this example, 2E9 / cm 3 ~5E9 / cm 3 Contains a high density of BMD defects.

[0045] Figure 6 shows the resistivity versus depth curve of a carrier substrate 10 according to the invention. The initial substrate 10' had a resistivity of the order of 3500 Ωcm and a high Oi content. After the manufacturing method of the invention, the carrier substrate 10 has a resistivity of more than 3000 Ωcm, which is stable over the first 30 microns (top region 2). The bottom region 3 has a very high and fluctuating resistivity due to the high density of interstitial oxygen. It is noted that the top region 2 maintains its resistivity level and its low COP content (surface region 1), although this resistivity may still change during the process for manufacturing SOI structures and microelectronic components.

[0046] Such a carrier substrate 10 can be used in a process for manufacturing an SOI structure 100 as shown in FIG. 2. The manufacturing of the SOI structure 100 is preferably based on a thin film transfer process known as the Smart Cut™ process. A monocrystalline silicon donor substrate is implanted through its front side, thereby defining a buried weakened plane that delimits the transferred thin layer 30, 20 substantially parallel to the front side. The implantation is usually carried out with light species such as hydrogen or helium ions or a combination of these two species. The weakened plane is so named because it contains lenticular nanocracks generated by the implanted light species.

[0047] According to one preferred option, the transferred thin layer 30, 20 comprises, from the front surface of the donor substrate to the buried weakened surface, a dielectric layer 20 and a silicon layer 30, which respectively form the buried dielectric layer 20 and the silicon functional layer 30 of the SOI structure 100. It will therefore be understood that the implantation energy of the light species is selected and adjusted so as to form a buried weakened surface (more or less localized at the implantation peak) at a depth corresponding to the desired thickness of said layer 30, taking into account the finishing steps (described below) that consume part of the material of the functional layer 30.

[0048] The donor substrate and the carrier substrate 10 are then bonded by direct bonding between the front faces of said substrates to form a bonded assembly. To obtain good bonding quality, the substrates can be subjected to surface cleaning and / or activation before bonding, which are well known in the field of bonding by molecular adhesion. Bonding in a controlled atmosphere is also possible.

[0049] The separation at the buried weakened surface is preferably performed by a heat treatment at moderate temperatures, typically 350° C. to 500° C., in order to grow microcracks by coalescence and pressurization of gas species. Alternatively, or in combination, the separation may be brought about by applying mechanical stress to the bonded assembly. This separation results in an intermediate SOI structure on the one hand and the remainder of the donor structure on the other hand. A finishing sequence, including cleaning, surface treatments (etching, polishing, etc.) and / or heat treatments, is usually applied to the intermediate SOI structure, aimed at removing part of the material of the transferred functional layer 30. This allows to restore to the silicon functional layer 30 a good surface state (defect density and roughness) as well as a good crystal quality. After this, the SOI structure 100 is available.

[0050] The above-mentioned finishing heat treatments are typically carried out at temperatures between 900°C and 1250°C: the robustness of the lower region 3 of the carrier substrate 10 against defects such as slip lines and other plastic deformations is an important advantage during these treatments, making it possible to maintain a very good integrity of the SOI structure 100.

[0051] Although the fabrication of SOI structure 100 is described herein with reference to the Smart-Cut process, such structures may also be prepared by other thin layer transfer processes known in the art.

[0052] RF (e.g. "mmWave") electronic components can then be manufactured on or in the functional layer 30, in particular based on at least one CMOS (Complementary Metal-Oxide-Semiconductor) transistor. Again, the properties of the carrier substrate 10 of the SOI structure 100 are advantageous in that: Inspectability of the structure 100 at various steps for manufacturing the part due to the presence of a surface region 1 having a very low density of COPs. Manufacturability of all or some of the components in the surface region 1 for hybrid SOI / bulk Si integration. Mechanical strength of the structure 100 during multiple sequences of high temperature heat treatments carried out in CMOS technology for manufacturing components due to a high density of BMD micro-defects in the lower region 3 of the carrier substrate 10 (said region 3 corresponds to the majority of the thickness of said substrate 10). 1E9 / cm 3 ~2E10 / cm 3 Advantageously, by targeting a BMD density of 0.1 μm, slip lines and / or other plastic deformations of the carrier substrate 10 that lead to alignment (“overlay”) problems at various levels of lithography are avoided or significantly minimized. RF performance of the component due to the high and stable resistivity of the upper region 2 of the carrier substrate 10: the low Oi content in this region ensures a high stability of its resistivity despite multiple heat treatments, and its thickness is adapted to the penetration of the electromagnetic fields generated by the RF component, preventing them from reaching the lower region 3 where the resistivity is not well controlled, potentially at levels that are too low for the targeted application.

[0053] The electronic components may consist of RF switches, power amplifiers (PAs), low noise amplifiers (LNAs), transmitters / receivers, among others.

[0054] Of course, the invention is not limited to the described embodiments and variations of implementation can be applied thereto without departing from the scope of the invention as defined by the claims.

[0055] In particular, while the functional layer 30 used to fabricate the component has been described in the context of an SOI structure and is thus composed of silicon, it is fully contemplated that the functional layer 30 may comprise other types of materials, which may or may not be semiconducting. Similarly, the dielectric layer 20 may comprise various types of electrically insulating materials.

Claims

1. A carrier substrate (10) made of monocrystalline silicon having a front surface (10a) and a back surface (10b), a surface region (1) from said front surface (10a) to a depth of 800 nm to 2 microns, said surface region (1) having less than 10 crystallite particles (COPs) detected by surface inspection using dark field microscopy; Extending downward from said front surface (10a) to a depth of several microns to 40 microns, ３ an upper region (2) having an interstitial oxygen (Oi) content of less than or equal to 1000 Ω cm and a resistivity of more than 500 Ω cm; Extending between said upper region (2) and said rear surface (10b), ３ a lower region (3) having a BMD concentration of at least A carrier substrate (10).

2. The carrier substrate (10) according to claim 1, wherein the resistivity of the upper region (2) is 750 Ωcm or more, or 1000 Ωcm or more.

3. The carrier substrate (10) according to claim 1 or 2, wherein the upper region (2) extends downwards to a depth of between 10 microns and 30 microns.

4. The concentration of micro defects (BMD) in the lower region (3) is 1E8 / cm ３ The carrier substrate (10) according to any one of claims 1 to 3, wherein the density of the carrier substrate (10) is ≦3E10 / cm3.

5. An SOI structure (100) comprising a functional layer (30) arranged on a dielectric layer (20), the dielectric layer (20) itself being arranged on a carrier substrate (10) according to any one of claims 1 to 4.

6. The SOI structure (100) of claim 5, wherein the functional layer (30) has a thickness of less than 50 nm.

7. The SOI structure (100) of claim 5 or 6, wherein the dielectric layer (20) has a thickness between 10 nm and 150 nm.

8. An electronic component for radio frequency and low power logic applications comprising at least one transistor arranged on and / or in the functional layer (30) of an SOI structure (100) according to any one of claims 5 to 7.

9. A method for manufacturing a carrier substrate (10) according to any one of claims 1 to 4, said method comprising the steps of: a) 12E17Oi / cm ３ ~16E17Oi / cm ３ providing an initial substrate (10') made of monocrystalline silicon having an interstitial oxygen content of 0.1 μm and a resistivity higher than 500 Ω cm, said initial substrate (10') intended to form said carrier substrate (10) after the subsequent steps b) and c), b) subjecting the substrate to a first heat treatment at a temperature between 1150° C. and 1250° C. in a neutral or reducing atmosphere for a duration of at least 30 minutes to form said surface region (1) and said top region (2); c) subjecting the carrier substrate (10) to a second heat treatment comprising a first sequence of annealing at a temperature between 600°C and 900°C and a second sequence of annealing at a temperature between 950°C and 1100°C to form the lower region (3); A method comprising:

10. 10. The method of claim 9, wherein the first sequence of the second heat treatment comprises two temperature plateaus, a first plateau between 650°C and 700°C and a second plateau around 800°C.

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