Semiconductor device, display device, and method for manufacturing the semiconductor device

Abstract

To suitably realize a CMOS structure using an n-type oxide semiconductor TFT and a p-type oxide semiconductor TFT (or transparent semiconductor TFT).SOLUTION: A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode. The first gate insulating layer includes a first layer and a second layer provided on the first layer. The second layer of the first gate insulating layer and the second gate insulating layer are provided in the same layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a display device, and also to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, it has been proposed to use oxide semiconductors as materials for the active layers of thin film transistors (hereinafter referred to as "TFTs") instead of amorphous silicon or polycrystalline silicon. A TFT having an oxide semiconductor film as its active layer is called an "oxide semiconductor TFT." Patent Document 1 discloses an active matrix substrate that uses an In-Ga-Zn-O based semiconductor film as the active layer of the TFT.

[0003] Oxide semiconductors have a higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs. In addition, oxide semiconductor films can be formed in a simpler process than polycrystalline silicon films, so they can be used in devices that require a large area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-134475 A Summary of the Invention [Problem to be solved by the invention]

[0005] Currently, most oxide semiconductors that are put to practical use as active layer materials for TFTs are n-type (n-channel type), but recently, p-type (p-channel type) oxide semiconductors have begun to be proposed. Among oxide semiconductors, some are known to have a wide band gap and are transparent. In addition, p-type transparent semiconductors with high mobility that are not oxides have also been proposed. In the following, a TFT having a transparent semiconductor film as an active layer is referred to as a "transparent semiconductor TFT." The oxide semiconductor TFT may also be referred to as a transparent semiconductor TFT. It is believed that a circuit with a CMOS (Complementary Metal-Oxide Semiconductor) structure formed by configuring an n-type oxide semiconductor TFT and a p-type oxide semiconductor TFT (or transparent semiconductor TFT) in a complementary manner can be used to reduce voltage and power consumption.

[0006] However, a suitable configuration for a CMOS structure using an n-type oxide semiconductor TFT and a p-type oxide semiconductor TFT (or a transparent semiconductor TFT) has not yet been established.

[0007] The embodiments of the present invention have been made in consideration of the above problems, and their purpose is to preferably realize a CMOS structure using an n-type oxide semiconductor TFT and a p-type oxide semiconductor TFT (or a transparent semiconductor TFT). [Means for solving the problem]

[0008] This specification discloses a semiconductor device, a display device, and a method for manufacturing a semiconductor device as described in the following items.

[0009] [Item 1] A substrate; a first thin film transistor of a first conductivity type supported by the substrate; a second thin film transistor of a second conductivity type different from the first conductivity type supported by the substrate; A complementary semiconductor device comprising: The first thin film transistor is a first semiconductor layer formed from an oxide semiconductor material of the first conductivity type, the first semiconductor layer including a first channel region, and a first source region and a first drain region located on both sides of the first channel region; a first gate insulating layer provided on the first semiconductor layer; a first gate electrode provided to face the first channel region via the first gate insulating layer; a first source electrode electrically connected to the first source region; having The second thin film transistor is A second semiconductor layer formed from the second conductive type oxide semiconductor material or transparent semiconductor material, the second semiconductor layer including a second channel region, and a second source region and a second drain region located on both sides of the second channel region; a second gate insulating layer provided on the second semiconductor layer; a second gate electrode provided to face the second channel region via the second gate insulating layer; a second source electrode electrically connected to the second source region; having the first gate insulating layer includes a first layer and a second layer provided on the first layer; The second layer of the first gate insulating layer and the second gate insulating layer are formed in the same layer.

[0010] [Item 2] the first gate electrode and the second gate electrode are formed in the same layer, 2. The semiconductor device according to item 1, wherein the first source electrode and the second source electrode are formed in the same layer.

[0011] [Item 3] an insulating layer formed in the same layer as the first layer of the first gate insulating layer; 3. The semiconductor device according to claim 1, wherein the second semiconductor layer is provided on the insulating layer.

[0012] [Item 4] the first thin film transistor has a first drain electrode electrically connected to the first drain region; the second thin film transistor has a second drain electrode electrically connected to the second drain region; 4. The semiconductor device according to any one of items 1 to 3, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed in the same layer.

[0013] [Item 5] an interlayer insulating layer provided so as to cover the first gate electrode and the second gate electrode; 5. The semiconductor device according to item 4, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are provided on the interlayer insulating layer.

[0014] [Item 6] 6. The semiconductor device according to any one of items 1 to 5, wherein the first conductivity type is n-type and the second conductivity type is p-type.

[0015] [Item 7] 7. The semiconductor device according to claim 6, wherein the first semiconductor layer includes an In-Ga-Zn-O based semiconductor.

[0016] [Item 8] 6. The semiconductor device according to any one of items 1 to 5, wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0017] [Item 9] Item 9. The semiconductor device according to item 8, wherein the second semiconductor layer includes an In-Ga-Zn-O based semiconductor.

[0018] [Item 10] a first capacitance electrode extending from the first semiconductor layer; a second capacitance electrode extending from the second semiconductor layer; a capacitance insulating layer provided between the first capacitance electrode and the second capacitance electrode and formed in the same layer as the first layer of the first gate insulating layer; 10. The semiconductor device according to any one of items 1 to 9, comprising a capacitive element comprising:

[0019] [Item 11] 11. The semiconductor device according to any one of items 1 to 10, which is an active matrix substrate for a display device having a display area defined by a plurality of pixel areas and a peripheral area located around the display area.

[0020] [Item 12] a gate driver circuit formed in the peripheral region; Item 12. The semiconductor device of item 11, wherein the gate driver circuit includes the first thin film transistor and the second thin film transistor.

[0021] [Item 13] a demultiplexer circuit formed in the peripheral region; Item 12. The semiconductor device of item 11, wherein the demultiplexer circuit includes the first thin film transistor and the second thin film transistor.

[0022] [Item 14] 14. A display device comprising the semiconductor device according to any one of items 11 to 13 as the active matrix substrate.

[0023] [Item 15] Item 15. The display device according to item 14, which is a liquid crystal display device.

[0024] [Item 16] Item 15. The display device according to item 14, which is an organic electroluminescence (EL) display device.

[0025] [Item 17] A substrate; a first thin film transistor of a first conductivity type supported by the substrate; a second thin film transistor of a second conductivity type different from the first conductivity type supported by the substrate; Equipped with The first thin film transistor is a first semiconductor layer formed from an oxide semiconductor material of the first conductivity type, the first semiconductor layer including a first channel region, and a first source region and a first drain region located on both sides of the first channel region; a first gate insulating layer provided on the first semiconductor layer; a first gate electrode provided to face the first channel region via the first gate insulating layer; a first source electrode electrically connected to the first source region; having The second thin film transistor is A second semiconductor layer formed from the second conductive type oxide semiconductor material or transparent semiconductor material, the second semiconductor layer including a second channel region, and a second source region and a second drain region located on both sides of the second channel region; a second gate insulating layer provided on the second semiconductor layer; a second gate electrode provided to face the second channel region via the second gate insulating layer; a second source electrode electrically connected to the second source region; having A method for manufacturing a complementary semiconductor device, comprising the steps of: (A) depositing a first semiconductor film on the substrate and then patterning the first semiconductor film to form the first semiconductor layer; (B) after the step (A), depositing a first insulating film including a region that will become a first layer that is a part of the first gate insulating layer so as to cover the first semiconductor layer; (C) after step (B), depositing a second semiconductor film and then patterning the second semiconductor film to form the second semiconductor layer; (D) after the step (C), depositing a second insulating film including a region that will become a second layer, which is another part of the first gate insulating layer, and a region that will become the second gate insulating layer; (E) after the step (D), depositing a first conductive film and then patterning the first conductive film to form the first gate electrode and the second gate electrode; (F) after the step (E), forming an interlayer insulating layer to cover the first gate electrode and the second gate electrode; (G) after the step (F), depositing a second conductive film on the interlayer insulating layer, and then patterning the second conductive film to form the first source electrode and the second source electrode; The present invention relates to a method for manufacturing a semiconductor device.

[0026] [Item 18] the first thin film transistor has a first drain electrode electrically connected to the first drain region; the second thin film transistor has a second drain electrode electrically connected to the second drain region; Item 18. The method for manufacturing a semiconductor device according to item 17, wherein in the step (G), the first drain electrode and the second drain electrode are formed together with the first source electrode and the second source electrode.

[0027] [Item 19] Item 19. The method for manufacturing a semiconductor device according to item 17 or 18, wherein the first conductivity type is n-type and the second conductivity type is p-type.

[0028] [Item 20] Item 19. The method for manufacturing a semiconductor device according to item 17 or 18, wherein the first conductivity type is p-type and the second conductivity type is n-type. Effect of the Invention

[0029] According to the embodiment of the present invention, it is possible to suitably realize a CMOS structure using an n-type oxide semiconductor TFT and a p-type oxide semiconductor TFT (or a transparent semiconductor TFT). [Brief description of the drawings]

[0030] [Figure 1] 1 is a cross-sectional view that diagrammatically illustrates a semiconductor device 100 according to an embodiment of the present invention. [Figure 2A]1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2B] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2C] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2D] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2E] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2F] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2G] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2H] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2I] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2J] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 2K] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method of the semiconductor device 100. [Figure 3A] 1 is a cross-sectional view that typically illustrates a semiconductor device 100. FIG. [Figure 3B] 1 is a cross-sectional view that typically illustrates a semiconductor device 100. FIG. [Figure 4] 1 is a cross-sectional view that illustrates a schematic diagram of another semiconductor device 100A according to an embodiment of the present invention. [Diagram 5] 11 is a cross-sectional view that diagrammatically illustrates a semiconductor device 100B according to another embodiment of the present invention. FIG. [Figure 6] FIG. 11 is a cross-sectional view that illustrates a schematic diagram of a semiconductor device 200 according to an embodiment of the present invention. [Figure 7A] 1 is a cross-sectional view that illustrates a semiconductor device 200. FIG. [Figure 7B] 1 is a cross-sectional view that illustrates a semiconductor device 200. FIG. [Figure 8]11 is a cross-sectional view that illustrates a schematic diagram of a semiconductor device 200A according to an embodiment of the present invention. [Figure 9] 11 is a cross-sectional view that diagrammatically illustrates a semiconductor device 200B according to an embodiment of the present invention. FIG. [Figure 10] FIG. 1 is a plan view illustrating an active matrix substrate 1000. [Figure 11] 1 is an equivalent circuit diagram of a plurality of pixels PIX included in a liquid crystal display device 1100. FIG. [Figure 12] 12 is an equivalent circuit diagram of one pixel PIX of an organic EL display device 1200. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the following embodiment. In the drawings referred to below, components having substantially the same functions are indicated by common reference symbols, and their description may be omitted. In addition, for ease of understanding of the description, in the drawings referred to below, the configuration is simplified or illustrated in a schematic manner, or some components are omitted. The dimensional ratio between components shown in each drawing does not necessarily indicate the actual dimensional ratio.

[0032] [Embodiment 1] A complementary semiconductor device 100 of this embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the semiconductor device 100 in schematic form.

[0033] 1, the semiconductor device 100 includes a substrate 1, a first thin film transistor (hereinafter "first TFT") 10A of a first conductivity type, and a second thin film transistor (hereinafter "second TFT") 20A of a second conductivity type different from the first conductivity type. In this embodiment, the first TFT 10A is an n-type, and the second TFT 20A is a p-type. The first TFT 10A is an oxide semiconductor TFT, and the second TFT 20A is an oxide semiconductor TFT or a transparent semiconductor TFT.

[0034] The substrate 1 has insulating properties and is typically transparent, and is, for example, a glass substrate or a plastic substrate.

[0035] The first TFT 10A is supported by the substrate 1 and has a top-gate structure. The first TFT 10A has a first semiconductor layer 11N, a first gate insulating layer 12, a first gate electrode 13, a first source electrode 14, and a first drain electrode 15.

[0036] The first semiconductor layer 11N is made of an n-type oxide semiconductor material and includes a channel region 11a, and a source region 11b and a drain region 11c located on either side of the channel region 11a.

[0037] The first gate insulating layer 12 is provided on the first semiconductor layer 11N. The first gate insulating layer 12 includes a first layer (lower layer) 12a in contact with the first semiconductor layer 11N, and a second layer (upper layer) 12b provided on the first layer 12a. In other words, the first gate insulating layer 12 has a laminated structure.

[0038] The first gate electrode 13 is provided to face the channel region 11a of the first semiconductor layer 11N via the first gate insulating layer 12. The first source electrode 14 is electrically connected to the source region 11b of the first semiconductor layer 11N, and the first drain electrode 15 is electrically connected to the drain region 11c of the first semiconductor layer 11N.

[0039] The second TFT 20A, like the first TFT 10A, is supported by the substrate 1 and has a top-gate structure. The second TFT 20A has a second semiconductor layer 21P, a second gate insulating layer 22, a second gate electrode 23, a second source electrode 24, and a second drain electrode 25.

[0040] The second semiconductor layer 21P is made of a p-type oxide semiconductor material or a transparent semiconductor material. The second semiconductor layer 21P includes a channel region 21a, and a source region 21b and a drain region 21c located on both sides of the channel region 21a. The second semiconductor layer 21P is provided on an insulating layer 2 formed in the same layer as the first layer 12a of the first gate insulating layer 12 (i.e., formed together with the first layer 12a in the step of forming the first layer 12a).

[0041] The second gate insulating layer 22 is provided on the second semiconductor layer 21P and is in contact with the second semiconductor layer 21P. The second gate insulating layer 22 is formed in the same layer as the second layer (upper layer) 12b of the first gate insulating layer 12 (i.e., together with the second layer 12b in the step of forming the second layer 12b).

[0042] The second gate electrode 23 is provided to face the channel region 21a of the second semiconductor layer 21P via the second gate insulating layer 22. The second gate electrode 23 is formed in the same layer as the first gate electrode 13 (i.e., together with the first gate electrode 13 in the process of forming the first gate electrode 13).

[0043] The second source electrode 24 is electrically connected to the source region 21b of the second semiconductor layer 21P. The second drain electrode 25 is electrically connected to the drain region 21c of the second semiconductor layer 21P. The second source electrode 24 and the second drain electrode 25 are formed in the same layer as the first source electrode 14 and the first drain electrode 15 (i.e., together with the first source electrode 14 and the first drain electrode 15 in the process of forming the first source electrode 14 and the first drain electrode 15).

[0044] An interlayer insulating layer 3 is provided so as to cover the first gate electrode 13, the second gate electrode 23, and the like. The first source electrode 14, the first drain electrode 15, the second source electrode 24, and the second drain electrode 25 are provided on the interlayer insulating layer 3. The interlayer insulating layer 3 is provided with a first contact hole 3a, a second contact hole 3b, a third contact hole 3c, and a fourth contact hole 3d. The first source electrode 14 is connected to the source region 11b of the first semiconductor layer 11N through the first contact hole 3a, and the first drain electrode 15 is connected to the drain region 11c of the first semiconductor layer 11N through the second contact hole 3b. The second source electrode 24 is connected to the source region 21b of the second semiconductor layer 21P through the third contact hole 3c, and the second drain electrode 25 is electrically connected to the drain region 21c of the second semiconductor layer 21P through the fourth contact hole 3d.

[0045] 2A to 2K, a method for manufacturing the semiconductor device 100 in this embodiment will be described. 2A to 2K are cross-sectional views for explaining the manufacturing method of the semiconductor device 100.

[0046] 2A, an n-type first semiconductor layer 11N is formed on a substrate 1. Specifically, a first semiconductor film (thickness: for example, 15 nm or more and 200 nm or less) is deposited on the substrate 1, and then the first semiconductor film is patterned, thereby forming the first semiconductor layer 11N.

[0047] As the substrate 1, for example, a glass substrate, a silicon substrate, a heat-resistant plastic substrate (resin substrate), or the like can be used.

[0048] The deposition of the first semiconductor film can be performed by, for example, a sputtering method, and the patterning of the first semiconductor film can be performed by, for example, wet etching. The material of the first semiconductor film is not particularly limited, but is, for example, an In-Ga-Zn-O based semiconductor.

[0049] 2B, a first insulating film IF1 (thickness: for example, 20 nm to 150 nm) is deposited so as to cover the first semiconductor layer 11N. The first insulating film IF1 includes a region 12a' that will become the first layer 12a (part of the first gate insulating layer 12) of the first gate insulating layer 12, and a region 2' that will become the insulating layer 2 interposed between the second semiconductor layer 21P and the substrate 1.

[0050] The first insulating film IF1 can be deposited by, for example, a CVD method. As a material for the first insulating film IF1, silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy;x>y), silicon nitride oxide (SiNxOy;x>y), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), etc. can be appropriately used. The first insulating film IF1 may have a laminated structure.

[0051] 2C, a p-type second semiconductor layer 21P is formed on the first insulating film IF1. Specifically, a second semiconductor film (thickness: for example, 20 nm or more and 200 nm or less) is deposited on the first insulating film IF1, and then the second semiconductor film is patterned, thereby forming the second semiconductor layer 21P.

[0052] The deposition of the second semiconductor film can be performed by, for example, a sputtering method, and the patterning of the second semiconductor film can be performed by, for example, wet etching. The material of the second semiconductor film is not particularly limited, but is, for example, SnO.

[0053] Thereafter, the second layer 12b of the first gate insulating layer 12, the second gate insulating layer 22, the first gate electrode 13 and the second gate electrode 23 are formed.

[0054] 2D, a second insulating film IF2 (thickness: for example, 80 nm or more and 250 nm or less) is deposited on the first insulating film IF1 and the second semiconductor layer 21P. The second insulating film IF2 includes a region 12b' that will become the second layer 12b of the first gate insulating layer 12 (another part of the first gate insulating layer 12) and a region 22' that will become the second gate insulating layer 22.

[0055] The deposition of the second insulating film IF2 can be performed by, for example, a CVD method. As a material for the second insulating film IF2, aluminum oxide (Al2O3), tantalum oxide (Ta2O5), silicon oxide (SiO2), silicon oxynitride (SiOxNy;x>y), etc. can be appropriately used. The second insulating film IF2 may have a laminated structure.

[0056] Next, as shown in FIG. 2E, a first conductive film (conductive film for gate) CF1 (thickness: for example, 50 nm or more and 500 nm or less) is deposited on the second insulating film IF2. The deposition of the first conductive film CF1 can be performed by, for example, a sputtering method. The material of the first conductive film CF1 can be, for example, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy material containing these elements. The first conductive film CF1 may have a laminated structure. The laminated structure can be, for example, a three-layer structure of a titanium layer-aluminum layer-titanium layer or a three-layer structure of a molybdenum layer-aluminum layer-molybdenum layer. Of course, it is not limited to a three-layer structure, and may be a two-layer structure or a four-layer or more laminate structure.

[0057] 2F, the first conductive film CF1 is patterned to form the first gate electrode 13 and the second gate electrode 23. The first conductive film CF1 can be patterned by, for example, wet etching or dry etching.

[0058] Thereafter, as shown in Fig. 2G, the second insulating film IF2 is patterned to form the second layer 12b of the first gate insulating layer 12 and the second gate insulating layer 22. The patterning of the second insulating film IF2 can be performed by, for example, dry etching. In the example shown in Fig. 2G, at this time, the first insulating film IF1 is also patterned to separate into the first layer 12a of the first gate insulating layer 12 and the insulating layer 2.

[0059] Next, the first semiconductor layer 11N and the second semiconductor layer 21P are subjected to a resistance reduction process using the first gate electrode 13 and the second gate electrode 23 as a mask. The resistance reduction process is, for example, a plasma process. As a result, as shown in FIG. 2H, the region of the first semiconductor layer 11N that does not overlap with the first gate electrode 13 becomes a low-resistance region (source region 11b and drain region 11c) having a lower resistivity than the region (channel region 11a) that overlaps with the first gate electrode 13. Also, the region of the second semiconductor layer 21P that does not overlap with the second gate electrode 23 becomes a low-resistance region (source region 21b and drain region 21c) having a lower resistivity than the region (channel region 21a) that overlaps with the second gate electrode 23.

[0060] Subsequently, as shown in FIG. 2I, an interlayer insulating layer 3 (thickness: for example, 100 nm to 500 nm) is formed so as to cover the first gate electrode 13 and the second gate electrode 23. The interlayer insulating layer 3 can be formed, for example, by a CVD method. For example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used as the material of the interlayer insulating layer 3. The interlayer insulating layer 3 may have a laminated structure.

[0061] 2J, a first contact hole 3a and a second contact hole 3b are formed in the interlayer insulating layer 3 so as to expose a part of the source region 11b and a part of the drain region 11c of the first semiconductor layer 11N, and a third contact hole 3c and a fourth contact hole 3d are formed so as to expose a part of the source region 21b and a part of the drain region 21c of the second semiconductor layer 21P. The first, second, third and fourth contact holes 3a, 3b, 3c and 3d can be formed by a photolithography process (including, for example, a dry etching process).

[0062] 2K, a second conductive film (conductive film for source) CF2 (thickness: for example, 50 nm or more and 500 nm or less) is deposited on the interlayer insulating layer 3. The second conductive film CF2 can be deposited by, for example, a sputtering method. For example, the materials exemplified as the materials of the first conductive film CF1 can be used as the material of the second conductive film CF2. The second conductive film CF2 may have a laminated structure, similar to the first conductive film CF1.

[0063] Thereafter, the second conductive film CF2 is patterned to form the first source electrode 14, the first drain electrode 15, the second source electrode 24, and the second drain electrode 25. The second conductive film CF2 can be patterned by, for example, wet etching or dry etching. In this manner, the semiconductor device 100 shown in FIG. 1 is obtained.

[0064] Here, an example has been shown in which the first insulating film IF1 is also patterned and separated into the first layer 12a of the first gate insulating layer 12 and the insulating layer 2 when the second insulating film IF2 is patterned, but as shown in FIG. 3A, in the completed semiconductor device 100, the first layer 12a of the first gate insulating layer 12 and the insulating layer 2 may be continuous. Depending on the materials and patterning methods of the first insulating film IF1 and the second insulating film IF2, the first insulating film IF1 may not be separated into the first layer 12a of the first gate insulating layer 12 and the insulating layer 2 when the second insulating film IF2 is patterned. For example, when the first insulating film IF1 is a silicon oxide film and the second insulating film IF2 has a laminated structure with an aluminum oxide layer as a lower layer and a silicon oxide layer as an upper layer, the first insulating film IF1 may not be separated into the first layer 12a of the first gate insulating layer 12 and the insulating layer 2.

[0065] Alternatively, as shown in FIG. 3B, both the first insulating film IF1 and the second insulating film IF2 may be unpatterned, the first layer 12a of the first gate insulating layer 12 may be continuous with the insulating layer 2, and the second layer 12b of the first gate insulating layer 12 may be continuous with the second gate insulating layer 22.

[0066] As described above, the semiconductor device 100 of the present embodiment includes the first TFT 10A, which is an n-type oxide semiconductor TFT, and the second TFT 20A, which is a p-type oxide semiconductor TFT (or a transparent semiconductor TFT), and by using these to form a CMOS structure circuit, it is possible to achieve low voltage and low power consumption. In addition, since both the first TFT 10A and the second TFT 20A have a top gate structure, the TFT characteristics and reliability are superior to those of a case in which an n-type TFT with a bottom gate structure and a p-type TFT with a bottom gate structure are used. Furthermore, since the portion (first layer) 12a of the first gate insulating layer 12 that contacts the first semiconductor layer 11N and the second gate insulating layer 22 that contacts the second semiconductor layer 21P are formed in separate layers, the gate insulating films that contact the semiconductor layers of the n-type oxide semiconductor TFT and the p-type oxide semiconductor TFT (or transparent semiconductor TFT) can be formed from different materials, that is, from materials suitable for each gate insulating film.

[0067] Furthermore, the semiconductor device 100 of this embodiment can be manufactured using a relatively small number of masks, which reduces manufacturing costs. For example, the manufacturing method illustrated with reference to Figures 2A to 2K requires five masks. In contrast, when forming a CMOS structure using n-type TFTs and p-type TFTs having an LTPS (low temperature polysilicon) layer as the active layer, the number of masks required to complete the process of separating the source electrode and the drain electrode is generally eight.

[0068] Furthermore, in the semiconductor device 100 of this embodiment, the first gate insulating layer 12 has a laminated structure including the first layer 12a and the second layer 12b, whereas the second gate insulating layer 22 is formed in the same layer as the second layer 12b of the first gate insulating layer 12, so that the second gate insulating layer 22 can be made thinner than the first gate insulating layer 12. This is advantageous in that it increases the on-current of the second TFT 20, which is a p-type oxide semiconductor TFT (or a transparent semiconductor TFT) with a relatively low mobility.

[0069] Another semiconductor device 100A according to the present embodiment is shown in Fig. 4. As shown in Fig. 4, the semiconductor device 100A differs from the semiconductor device 100 shown in Fig. 3 in that the semiconductor device 100A includes a capacitive element 30.

[0070] The capacitive element 30 includes a first capacitive electrode 31 , a second capacitive electrode 32 , and a capacitive insulating layer 33 provided between the first capacitive electrode 31 and the second capacitive electrode 32 .

[0071] The first capacitance electrode 31 extends from the first semiconductor layer 11N. In the illustrated example, the first capacitance electrode 31 extends from the drain region 11c of the first semiconductor layer 11N, and can be said to be electrically connected to the drain region 11c. The first capacitance electrode 31 is made to have a low resistance (conductivity) like the drain region 11c.

[0072] The second capacitance electrode 32 extends from the second semiconductor layer 21P. In the illustrated example, the second capacitance electrode 32 extends from the source region 21b of the second semiconductor layer 21P, and can be said to be electrically connected to the source region 21b. The second capacitance electrode 32 is made to have a low resistance (conductivity) like the source region 21b.

[0073] The capacitive insulating layer 33 is formed in the same layer as the first layer 12a of the first gate insulating layer 12. In the illustrated example, the capacitive insulating layer 33 is continuous with the first layer 12a of the first gate insulating layer 12 and the insulating layer 2.

[0074] When the semiconductor device is used as an active matrix substrate for an organic EL display device as described later, a capacitive element is provided in each pixel region. As in the semiconductor device 100A shown in Fig. 4, a capacitive element 30 can be formed using a portion (first capacitive electrode 31) extending from the first semiconductor layer 11N and a portion (second capacitive electrode 32) extending from the second semiconductor layer 21P.

[0075] Note that, although an example has been shown here in which the first capacitance electrode 31 extends from the drain region 11c of the first semiconductor layer 11N and the second capacitance electrode 32 extends from the source region 21b of the second semiconductor layer 21P, the first capacitance electrode 31 may extend from the source region 11b of the first semiconductor layer 11N, and the second capacitance electrode 32 may extend from the drain region 21c of the second semiconductor layer 21P.

[0076] Fig. 5 shows yet another semiconductor device 100B according to the present embodiment. As shown in Fig. 5, the semiconductor device 100B differs from the semiconductor device 100 shown in Fig. 1 in that the semiconductor device 100B includes a first light-shielding layer 4A, a second light-shielding layer 4B, and a lower insulating layer 5.

[0077] The first light-shielding layer 4A and the second light-shielding layer 4B are provided on a substrate 1. A lower insulating layer 5 is provided so as to cover the first light-shielding layer 4A and the second light-shielding layer 4B. A first TFT 10A and a second TFT 20A are formed on the lower insulating layer 5.

[0078] The first light-shielding layer 4A overlaps the channel region 11a of the first semiconductor layer 11N via the lower insulating layer 5. The second light-shielding layer 4B overlaps the channel region 21a of the second semiconductor layer 21P via the lower insulating layer 5. Here, the first light-shielding layer 4A and the second light-shielding layer 4B are formed of a conductive material.

[0079] When the semiconductor device is used as an active matrix substrate for a liquid crystal display device, by providing a first light-shielding layer 4A and a second light-shielding layer 4B as in the semiconductor device 100B shown in FIG. 5, it is possible to prevent light from a backlight (illumination device) from entering the channel regions 11a and 21a.

[0080] The first light-shielding layer 4A and the second light-shielding layer 4B can be formed by forming a conductive film for the light-shielding layer (thickness: for example, 50 nm to 500 nm) by a sputtering method or the like, and then patterning the conductive film for the light-shielding layer. As the material for the conductive film for the light-shielding layer, for example, those exemplified as the material for the first conductive film CF1 can be used.

[0081] The lower insulating layer 5 can be formed by, for example, a CVD method. The thickness of the lower insulating layer 5 is, for example, 200 nm or more and 500 nm or less. As the material of the lower insulating layer 5, for example, those exemplified as the material of the first insulating film IF1 can be used.

[0082] The first light-shielding layer 4A and the second light-shielding layer 4B may be in an electrically floating state (floating) or may be given a predetermined potential. By giving a predetermined potential (fixed potential) to the first light-shielding layer 4A and the second light-shielding layer 4B, the TFT characteristics can be improved. In addition, the first light-shielding layer 4A may be made to function as a lower gate electrode by giving substantially the same potential as the first gate electrode 13 to the first light-shielding layer 4A, and the first TFT 10A may have a double-gate structure. Similarly, the second light-shielding layer 4B may be made to function as a lower gate electrode by giving substantially the same potential as the second gate electrode 23 to the second light-shielding layer 4B, and the second TFT 20A may have a double-gate structure.

[0083] [N-type oxide semiconductors] The oxide semiconductor contained in the n-type semiconductor layer may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor whose c-axis is oriented approximately perpendicular to the layer surface.

[0084] The n-type semiconductor layer may have a laminated structure of two or more layers. The semiconductor layer having a laminated structure may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer, or may include a plurality of crystalline oxide semiconductor layers having different crystal structures. The semiconductor layer having a laminated structure may also include a plurality of amorphous oxide semiconductor layers. When the semiconductor layer has a two-layer structure including an upper layer and a lower layer, it is preferable that the energy gap of the oxide semiconductor included in the lower layer is larger than that of the oxide semiconductor included in the upper layer. However, when the difference in energy gap between these layers is relatively small, the energy gap of the oxide semiconductor of the upper layer may be larger than that of the oxide semiconductor of the lower layer.

[0085] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a laminated structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described in, for example, JP 2014-007399 A. For reference, the entire disclosure of JP 2014-007399 A is incorporated herein by reference.

[0086] The n-type semiconductor layer may contain at least one metal element selected from, for example, In, Ga, and Zn. In this embodiment, the n-type semiconductor layer contains, for example, an In-Ga-Zn-O-based semiconductor (for example, indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such a semiconductor layer may be formed from an oxide semiconductor film containing an In-Ga-Zn-O-based semiconductor.

[0087] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline. As the crystalline In-Ga-Zn-O based semiconductor, a crystalline In-Ga-Zn-O based semiconductor in which the c-axis is oriented approximately perpendicular to the layer surface is preferable.

[0088] The crystal structure of the crystalline In-Ga-Zn-O-based semiconductor is disclosed in, for example, the above-mentioned JP 2014-007399 A, JP 2012-134475 A, JP 2014-209727 A, etc. For reference, the disclosures of JP 2012-134475 A and JP 2014-209727 A are incorporated herein by reference in their entirety. A TFT having an In-Ga-Zn-O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than 1 / 100 that of an a-Si TFT).

[0089] The n-type semiconductor layer may contain other oxide semiconductors instead of In-Ga-Zn-O-based semiconductors. For example, it may contain In-Sn-Zn-O-based semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O-based semiconductors are ternary oxides of In (indium), Sn (tin) and Zn (zinc). Alternatively, the n-type semiconductor layer may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, or the like.

[0090] [About p-type oxide semiconductors and transparent semiconductors] The oxide semiconductor contained in the p-type semiconductor layer may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. The p-type semiconductor layer may have a laminated structure of two or more layers.

[0091] The p-type semiconductor layer may contain, for example, SnO (tin oxide), Cu2O (copper oxide), NiO (nickel oxide), etc. The p-type semiconductor layer may also contain a transparent semiconductor other than an oxide (for example, CuI (copper iodide)).

[0092] [Embodiment 2] A complementary semiconductor device 200 of the present embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view showing a schematic view of the semiconductor device 200. The following description will focus on the differences between the semiconductor device 200 and the semiconductor device 100 of the first embodiment.

[0093] 6, the semiconductor device 200 includes a substrate 1, a first TFT 10B of a first conductivity type, and a second TFT 20B of a second conductivity type different from the first conductivity type. In this embodiment, the first TFT 10B is a p-type, and a first semiconductor layer 11P of the first TFT 10B is made of a p-type oxide semiconductor material or a transparent semiconductor material. The second TFT 20B is an n-type, and a second semiconductor layer 21N of the second TFT 20B is made of an n-type oxide semiconductor material.

[0094] The semiconductor device 200 can be manufactured in a manner similar to that of the semiconductor device 100 in the first embodiment. As the material of the first semiconductor layer 11P, the materials exemplified as the materials of the second semiconductor layer 21P of the semiconductor device 100 can be used, and as the material of the second semiconductor layer 21N, the materials exemplified as the materials of the first semiconductor layer 11N of the semiconductor device 100 can be used. As the material of the insulating film (first insulating film) for forming the first layer 12a of the first gate insulating layer 12 and the insulating layer 2, the materials exemplified as the materials of the second insulating film IF2 shown in FIG. 2D and the like can be used. As the material of the insulating film (second insulating film) for forming the second layer 12b of the first gate insulating layer 12 and the second gate insulating layer 22, the materials exemplified as the materials of the first insulating film IF1 shown in FIG. 2B and the like can be used.

[0095] 6 shows an example in which the first layer 12a of the first gate insulating layer 12 and the insulating layer 2 are separated, but as shown in FIG. 7A, the first layer 12a of the first gate insulating layer 12 and the insulating layer 2 may be continuous. Depending on the materials and patterning method of the first and second insulating films, the first insulating film may not be separated into the first layer 12a of the first gate insulating layer 12 and the insulating layer 2 when the second insulating film is patterned. For example, when the first insulating film is an aluminum oxide film and the second insulating film is a silicon oxide film, the first insulating film may not be separated into the first layer 12a of the first gate insulating layer 12 and the insulating layer 2.

[0096] Alternatively, as shown in FIG. 7B, both the first insulating film and the second insulating film may be unpatterned, and the first layer 12a of the first gate insulating layer 12 may be continuous with the insulating layer 2, while the second layer 12b of the first gate insulating layer 12 may be continuous with the second gate insulating layer 22.

[0097] As described above, the semiconductor device 200 of this embodiment includes the first TFT 10B, which is a p-type oxide semiconductor TFT (or a transparent semiconductor TFT), and the second TFT 20B, which is an n-type oxide semiconductor TFT. By using these to form a CMOS circuit, it is possible to reduce the voltage and power consumption. In addition, since both the first TFT 10B and the second TFT 20B have a top gate structure, they have excellent TFT characteristics and reliability. Furthermore, since the portion (first layer) 12a of the first gate insulating layer 12 that contacts the first semiconductor layer 11P and the second gate insulating layer 22 that contacts the second semiconductor layer 21N are formed in separate layers, the gate insulating films that contact the semiconductor layers of the n-type oxide semiconductor TFT and the p-type oxide semiconductor TFT (or the transparent semiconductor TFT) can be formed from different materials, that is, from materials suitable for the respective gate insulating films. In addition, since the semiconductor device 200 of this embodiment can be manufactured using a relatively small number of masks, it is also possible to reduce the manufacturing cost.

[0098] Furthermore, in the semiconductor device 200 of this embodiment, the first gate insulating layer 12 has a laminated structure including the first layer 12a and the second layer 12b. This makes it easy to ensure the dielectric strength of the first TFT 10B, which is a p-type oxide semiconductor TFT (or a transparent semiconductor TFT). For example, when an aluminum oxide film is used as the insulating film (the first layer 12a of the first gate insulating layer 12) in contact with the p-type first semiconductor layer 11P, the aluminum oxide film is deposited by atomic layer deposition (ALD), but the atomic layer deposition method generally has a slow film formation speed and is not suitable for depositing a thick film. Since the first gate insulating layer 12 has a laminated structure including the first layer 12a and the second layer 12b, even if the first layer 12a is thin, the dielectric strength can be ensured as long as the first gate insulating layer 12 has a certain thickness as a whole.

[0099] Another semiconductor device 200A according to the present embodiment is shown in Fig. 8. As shown in Fig. 8, the semiconductor device 200A differs from the semiconductor device 200 shown in Fig. 7 in that the semiconductor device 200A includes a capacitive element 30.

[0100] The capacitive element 30 includes a first capacitive electrode 31 , a second capacitive electrode 32 , and a capacitive insulating layer 33 provided between the first capacitive electrode 31 and the second capacitive electrode 32 .

[0101] The first capacitance electrode 31 extends from the first semiconductor layer 11P. In the illustrated example, the first capacitance electrode 31 extends from the drain region 11c of the first semiconductor layer 11P, and can be said to be electrically connected to the drain region 11c. The first capacitance electrode 31 is made to have a low resistance (conductivity) like the drain region 11c.

[0102] The second capacitance electrode 32 extends from the second semiconductor layer 21N. In the illustrated example, the second capacitance electrode 32 extends from the source region 21b of the second semiconductor layer 21N, and can be said to be electrically connected to the source region 21b. The second capacitance electrode 32 is made to have a low resistance (conductivity) like the source region 21b.

[0103] The capacitive insulating layer 33 is formed in the same layer as the first layer 12a of the first gate insulating layer 12. In the illustrated example, the capacitive insulating layer 33 is continuous with the first layer 12a of the first gate insulating layer 12 and the insulating layer 2.

[0104] When the semiconductor device is used as an active matrix substrate for an organic EL display device as described later, a capacitive element is provided in each pixel region. As in the semiconductor device 200A shown in Fig. 8, a capacitive element 30 can be formed using a portion (first capacitive electrode 31) extending from the first semiconductor layer 11P and a portion (second capacitive electrode 32) extending from the second semiconductor layer 21N.

[0105] Among the materials exemplified for the insulating film (first insulating film) for forming the first layer 12a of the first gate insulating layer 12, there is a material (e.g., aluminum oxide) having a higher dielectric constant than silicon oxide, etc., and the use of such a material can reduce the area of ​​the capacitive element 30.

[0106] Note that, although an example has been shown here in which the first capacitance electrode 31 extends from the drain region 11c of the first semiconductor layer 11P and the second capacitance electrode 32 extends from the source region 21b of the second semiconductor layer 21N, the first capacitance electrode 31 may extend from the source region 11b of the first semiconductor layer 11P, and the second capacitance electrode 32 may extend from the drain region 21c of the second semiconductor layer 21N.

[0107] Fig. 9 shows yet another semiconductor device 200B according to the present embodiment. As shown in Fig. 9, the semiconductor device 200B differs from the semiconductor device 200 shown in Fig. 6 in that the semiconductor device 200B includes a first light-shielding layer 4A, a second light-shielding layer 4B, and a lower insulating layer 5.

[0108] The first light-shielding layer 4A and the second light-shielding layer 4B are provided on a substrate 1. A lower insulating layer 5 is provided so as to cover the first light-shielding layer 4A and the second light-shielding layer 4B. A first TFT 10B and a second TFT 20B are formed on the lower insulating layer 5.

[0109] The first light-shielding layer 4A overlaps the channel region 11a of the first semiconductor layer 11P via the lower insulating layer 5. The second light-shielding layer 4B overlaps the channel region 21a of the second semiconductor layer 21N via the lower insulating layer 5. Here, the first light-shielding layer 4A and the second light-shielding layer 4B are formed of a conductive material.

[0110] When the semiconductor device is used as an active matrix substrate for a liquid crystal display device, by providing a first light-shielding layer 4A and a second light-shielding layer 4B as in the semiconductor device 200B shown in FIG. 9, it is possible to prevent light from a backlight (illumination device) from entering the channel regions 11a and 21a.

[0111] The first light-shielding layer 4A and the second light-shielding layer 4B may be in an electrically floating state (floating) or may be given a predetermined potential. By giving a predetermined potential (fixed potential) to the first light-shielding layer 4A and the second light-shielding layer 4B, the TFT characteristics can be improved. In addition, the first light-shielding layer 4A may be made to function as a lower gate electrode by giving substantially the same potential as the first gate electrode 13 to the first light-shielding layer 4A, and the first TFT 10B may have a double-gate structure. Similarly, the second light-shielding layer 4B may be made to function as a lower gate electrode by giving substantially the same potential as the second gate electrode 23 to the second light-shielding layer 4B, and the second TFT 20B may have a double-gate structure.

[0112] [Active matrix substrate] The semiconductor device according to the embodiment of the present invention is suitably used, for example, as an active matrix substrate for a display device. The configuration of an active matrix substrate 1000 will be described with reference to FIG.

[0113] The active matrix substrate 1000 may be, for example, any one of the above-mentioned semiconductor devices 100, 100A, 100B, 200, 200A, and 200B. As shown in Fig. 10, the active matrix substrate 1000 has a display region DR and a peripheral region FR.

[0114] The display region DR includes a plurality of pixel regions PIX. The pixel regions PIX correspond to pixels of the display device. Hereinafter, the pixel regions PIX may be simply referred to as "pixels." The plurality of pixel regions PIX are arranged in a matrix including a plurality of rows and a plurality of columns. The display region DR is defined by the plurality of pixel regions PIX arranged in a matrix.

[0115] The peripheral region FR is located around the display region DR. The peripheral region FR is a region that does not contribute to display, and is also called a "non-display region" or a "frame region."

[0116] A plurality of gate bus lines (scanning lines) GL and a plurality of source bus lines (signal lines) SL are provided on the substrate 1. The plurality of gate bus lines GL extend along the row direction. The plurality of source bus lines SL extend along the column direction. In FIG. 10, the gate bus lines GL in the first row, the second row, . . . the xth row are denoted as "GL1", "GL2", . . . "GLx", and the source bus lines SL in the first column, the second column, . . . the yth column are denoted as "SL1", "SL2", . . . "SLy". Typically, a region surrounded by two adjacent gate bus lines GL and two adjacent source bus lines SL is a pixel region PIX.

[0117] In the peripheral region FR, there are arranged gate driver circuits 41A and 41B for driving the gate bus lines GL, a source driver circuit 42 for driving the source bus lines SL, and a demultiplexer (DEMUX) circuit 43. The DEMUX circuit 43 functions as an SSD circuit for driving the source bus lines SL in a time-division manner. Here, the gate driver circuits 41A and 41B are integrally (monolithically) formed on the substrate 1 (hereinafter, also referred to as a GDM (Gate Driver Monolithic) circuit). Similarly to the gate driver circuits 41A and 41B, the DEMUX circuit 43 is monolithically formed on the substrate 1, and the source driver circuit 42 is mounted on the substrate 1 (for example, COG mounting).

[0118] In the illustrated example, a gate driver circuit 41A for driving odd-numbered gate bus lines GL is disposed on the left side of the display area DR, and a gate driver circuit 41B for driving even-numbered gate bus lines GL is disposed on the right side of the display area DR. The odd-numbered gate bus lines GL are connected to a plurality of output terminals (not shown) of the gate driver circuit 41A. The even-numbered gate bus lines GL are connected to a plurality of output terminals (not shown) of the gate driver circuit 41B.

[0119] A source driver circuit 42 is disposed below the display area DR, and a DEMUX circuit 43 is disposed between the source driver circuit 42 and the display area DR. The source driver circuit 42 includes a plurality of output terminals (not shown). A plurality of signal output lines (video signal lines) VL are provided in an area located between the source driver circuit 42 and the DEMUX circuit 43. Each of the plurality of signal output lines VL is connected to a corresponding one of the plurality of output terminals of the source driver circuit 42. In FIG. 10, the first, second, ..., zth signal output lines VL are denoted as "VL1", "VL2", ..., "VLz".

[0120] The DEMUX circuit 43 distributes a display signal supplied from one signal output line VL to two or more source bus lines SL.

[0121] In the active matrix substrate 1000, it is possible to reduce power consumption by including a circuit having a CMOS structure using the first TFT 10A and the second TFT 20A (or the first TFT 10B and the second TFT 20B) in the GDM circuits 41A and 41B. Also, it is possible to reduce power consumption and improve reliability by lowering the voltage of the switching signal by including a circuit having a CMOS structure using the first TFT 10A and the second TFT 20A (or the first TFT 10B and the second TFT 20B) in the DEMUX circuit 43.

[0122] The active matrix substrate 1000 can be used in various display devices, and is preferably used in, for example, a liquid crystal display device or an organic EL display device.

[0123] 11 is an example of an equivalent circuit diagram of a plurality of pixels PIX included in a liquid crystal display device 1100. Although not shown here, the liquid crystal display device 1100 includes an active matrix substrate 1000, a counter substrate facing the active matrix substrate 1000, and a liquid crystal layer provided between the active matrix substrate 1000 and the counter substrate.

[0124] 11, a pixel TFT 51 and a pixel electrode 52 are arranged in each pixel P of the liquid crystal display device 1100. The gate electrode, source electrode, and drain electrode of the pixel TFT 51 are electrically connected to the gate bus line GL, the source bus line SL, and the pixel electrode 52, respectively. An n-type oxide semiconductor TFT (first TFT 10A or second TFT 20B) can be suitably used as the pixel TFT 51.

[0125] 12 is an example of an equivalent circuit diagram of one pixel PIX of an organic EL display device 1200. Although not shown here, the organic EL display device 1200 includes at least an active matrix substrate 1000.

[0126] Each pixel PIX of the organic EL display device 1200 is provided with a driving TFT 61, a selection TFT 62, a capacitance element (storage capacitance) 63, and an OLED (organic light emitting diode) 64. Although not shown here, the OLED 64 is composed of a pixel electrode (e.g., an anode), an organic EL layer provided on the pixel electrode, and a common electrode (e.g., a cathode) provided on the organic EL layer.

[0127] The gate electrode and source electrode of the selection TFT 62 are electrically connected to the gate bus line GL and the source bus line SL, respectively. The drain electrode of the selection TFT 62 is electrically connected to the gate electrode of the driving TFT 61 and the capacitive element 63. The drain electrode of the driving TFT 61 is electrically connected to the power supply line CL. The source electrode of the driving TFT 61 is electrically connected to the OLED 64, more specifically, to the pixel electrode of the OLED 64.

[0128] A p-type oxide semiconductor TFT or a transparent semiconductor TFT (the second TFT 20A or the first TFT 10B) can be suitably used as the driving TFT 61. An n-type oxide semiconductor TFT (the first TFT 10A or the second TFT 20B) can be suitably used as the selection TFT 62.

[0129] In the above-described oxide semiconductor TFT (or transparent semiconductor TFT), the drain electrode may be omitted. For example, the drain electrode of the pixel TFT 51 of the liquid crystal display device 1100 may be omitted, and the pixel electrode 52 may be directly connected to the drain region of the semiconductor layer of the pixel TFT 51. [Industrial Applicability]

[0130] According to the embodiment of the present invention, it is possible to preferably realize a CMOS structure using an n-type oxide semiconductor TFT and a p-type oxide semiconductor TFT (or a transparent semiconductor TFT). The semiconductor device according to the embodiment of the present invention is used as an active matrix substrate for various display devices, and is preferably used as an active matrix substrate for, for example, a liquid crystal display device or an organic EL display device. [Explanation of symbols]

[0131] 1 Board 2. Insulation layer 3 Interlayer insulation layer 3a First Contact Hole 3b 2nd contact hole 3c 3rd Contact Hole 3d 4th Contact Hole 4A 1st light shielding layer 4B 2nd light shielding layer 5 Lower insulating layer 10A, 10B First thin film transistor 11N, 11P First semiconductor layer 11a Channel Region 11b Source area 11c Drain region 12 First gate insulating layer 12a 1st layer (lower layer) 12b 2nd layer (upper layer) 13 First gate electrode 14 First source electrode 15 First drain electrode 20A, 20B Second thin film transistor 21P, 21N Second semiconductor layer 21a Channel Region 21b Source area 21c Drain region 22 Second gate insulating layer 23 Second gate electrode 24 Second source electrode 25 Second drain electrode 30 Capacitive element 31 1st capacitor electrode 32 Second capacitor electrode 33 Capacitive insulating layer 41A, 41B Gate driver circuit 42 Source driver circuit 43 Demultiplexer circuit 51 pixel TFT 52 Pixel electrode 61 Driving TFT 62 Selection TFT 63 Capacitive element 64 OLED 100, 100A, 100B, 200, 200A, 200B Semiconductor device 1000 Active matrix substrate 1100 LCD display device 1200 Organic EL display device DR display area FR peripheral area PIX Pixel area GL Gate Bus Line SL Source bus line VL signal output line

Claims

1. A substrate; a first thin film transistor of a first conductivity type supported by the substrate; a second thin film transistor having a second conductivity type different from the first conductivity type supported by the substrate; A complementary semiconductor device comprising: The first thin film transistor is A first semiconductor layer formed from an oxide semiconductor material of the first conductivity type, the first semiconductor layer including a first channel region, and a first source region and a first drain region located on both sides of the first channel region; a first gate insulating layer provided on the first semiconductor layer; a first gate electrode provided to face the first channel region via the first gate insulating layer; a first source electrode electrically connected to the first source region; having The second thin film transistor is A second semiconductor layer formed from the second conductive type oxide semiconductor material or transparent semiconductor material, the second semiconductor layer including a second channel region, and a second source region and a second drain region located on both sides of the second channel region; a second gate insulating layer provided on the second semiconductor layer; a second gate electrode provided to face the second channel region via the second gate insulating layer; a second source electrode electrically connected to the second source region; having the first gate insulating layer includes a first layer and a second layer provided on the first layer; the second layer of the first gate insulating layer and the second gate insulating layer are formed in the same layer, the semiconductor device includes an insulating layer formed in the same layer as the first layer of the first gate insulating layer, The second semiconductor layer is provided on the insulating layer, the first layer of the first gate insulating layer and the insulating layer are formed to be continuous with each other; the second layer of the first gate insulating layer and the second gate insulating layer are formed so as to be continuous with each other.

2. the first gate electrode and the second gate electrode are formed in the same layer, The semiconductor device according to claim 1 , wherein the first source electrode and the second source electrode are formed in the same layer.

3. the first thin film transistor has a first drain electrode electrically connected to the first drain region; the second thin film transistor has a second drain electrode electrically connected to the second drain region; 3. The semiconductor device according to claim 1, wherein the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed in the same layer.

4. an interlayer insulating layer provided so as to cover the first gate electrode and the second gate electrode; 4. The semiconductor device according to claim 3, wherein the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are provided on the interlayer insulating layer.

5. 3. The semiconductor device according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

6. 6. The semiconductor device according to claim 5, wherein the first semiconductor layer includes an In--Ga--Zn--O based semiconductor.

7. 3. The semiconductor device according to claim 1, wherein the first conductivity type is a p-type, and the second conductivity type is an n-type.

8. 8. The semiconductor device according to claim 7, wherein the second semiconductor layer includes an In--Ga--Zn--O based semiconductor.

9. a first capacitance electrode extending from the first semiconductor layer; a second capacitance electrode extending from the second semiconductor layer; a capacitance insulating layer provided between the first capacitance electrode and the second capacitance electrode and formed in the same layer as the first layer of the first gate insulating layer; The semiconductor device according to claim 1 , further comprising a capacitive element comprising:

10. 3. The semiconductor device according to claim 1, wherein the semiconductor device is an active matrix substrate for a display device, the active matrix substrate having a display area defined by a plurality of pixel areas and a peripheral area located around the display area.

11. a gate driver circuit formed in the peripheral region; The semiconductor device according to claim 10 , wherein the gate driver circuit includes the first thin film transistor and the second thin film transistor.

12. a demultiplexer circuit formed in the peripheral region; The semiconductor device according to claim 10 , wherein the demultiplexer circuit includes the first thin film transistor and the second thin film transistor.

13. A semiconductor device comprising: a conductive film provided between the first semiconductor layer, the second semiconductor layer, and the substrate; The semiconductor device according to claim 1 , wherein the conductive film overlaps the first channel region and the second channel region.

14. The semiconductor device described in Claim 13, wherein the conductive film is formed from a light-shielding material.

15. A display device comprising the semiconductor device according to claim 11 as the active matrix substrate.

16. 16. The display device according to claim 15, which is a liquid crystal display device.

17. The display device according to claim 15, which is an organic electroluminescence display device.

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