Thin film transistor, display device, and method for manufacturing thin film transistor

Abstract

A thin film transistor according to one embodiment of the present invention is formed on a substrate and comprises: a channel which is formed of at least a part of a metal oxide semiconductor layer that contains at least indium (In); a gate electrode; a gate insulating layer which is arranged between the channel and the gate electrode; and a source electrode and a drain electrode, which are connected to the metal oxide semiconductor layer. For example, a threshold shift due to voltage stress is effectively suppressed by setting the average concentration of carbon atoms in a region from the surface to the depth of 5 nm of the channel to 1.5 × 1021cm-3 or less.

Description

[Technical field]

[0001] The present invention relates to a thin film transistor using a metal oxide semiconductor. [Background technology]

[0002] Thin-film transistors using metal oxide semiconductors such as InGaZnO (hereinafter referred to as IGZO) are used as elements for driving display pixels. Thin-film transistors using IGZO, which has a composition ratio of In and Ga of 1:1, have a thickness of 10 cm 2 This mobility is higher than that of a thin film transistor using amorphous silicon, but lower than that of a thin film transistor using low-temperature polysilicon.

[0003] In recent years, with displays such as 4K and 8K becoming larger and higher pixel count, IGZO is increasingly being adopted, as it allows the production of thin-film transistors with higher mobility than amorphous silicon and better uniformity over a large area than low-temperature polysilicon. For example, in order to improve the mobility of IGZO, thin-film transistors have been developed that use IGZO with an In-to-Ga composition ratio that is more In-rich than 1:1. In addition, thin-film transistors using metal oxide semiconductors that achieve higher mobility than IGZO are also being developed for next-generation displays. One such thin-film transistor, using InSnZnO (hereafter referred to as ITZO), has a 50cm 2A mobility of about / Vs can be achieved. Therefore, thin-film transistors used in circuits requiring high mobility can be replaced from low-temperature polysilicon to ITZO. On the other hand, n-type thin-film transistors using ITZO have a problem of a negative shift in threshold voltage (hereinafter, sometimes simply called threshold. The threshold before stress is shown as Vth, and the shift amount obtained by subtracting the threshold before stress from the threshold after stress is shown as ΔVth. Note that the threshold is used in the same way in the cases of NBIS and PBTS.) due to NBTS (Negative Bias Temperature Stress). In n-type thin-film transistors, the negative shift of the threshold due to continuous application of a negative bias voltage means that the transistor that should have been initially controlled to be in the off state by the application of a negative bias voltage will spontaneously turn on over time, so the amount of the negative shift must be sufficiently suppressed.

[0004] For example, Non-Patent Document 1 describes a method for solving this problem by introducing N into the back channel side of ITZO to prevent defects due to C=O and CO bonds that deteriorate the characteristics of thin film transistors. 2 It is disclosed that O plasma treatment is performed for an appropriate period of time. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] W.-H, Tseng et.al., Solid-State Electronics 103(2015), 173-177 Summary of the Invention [Problem to be solved by the invention]

[0006] According to Fig. 6 of Non-Patent Document 1, in an ITZO thin-film transistor, N 2It can be understood that as the time of O plasma treatment increases, the negative shift of the threshold due to NBTS decreases, but when the treatment time exceeds the optimal value, the negative shift increases. That is, in order to suppress the negative shift of the threshold according to the process described in Non-Patent Document 1, it is necessary to grasp the surface state of the back channel of ITZO and adjust the N 2 It is thought that the time of O plasma treatment needs to be precisely controlled. 2 When a passivation layer is formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) after O plasma treatment, N 2 The exposure time to the O plasma makes it more difficult to control. As a result, the need for such control can lead to manufacturing variability. 2 There is a need to suppress the negative shift in the threshold voltage by a method other than O plasma treatment.

[0007] An object of the present invention is to effectively suppress a threshold shift caused by voltage stress in a thin-film transistor using a metal oxide semiconductor layer containing In. Another object of the present invention is to effectively suppress a threshold shift caused by NBTS in a thin-film transistor using ITZO. [Means for solving the problem]

[0008] In one embodiment, the thin film transistor is a thin film transistor formed on a substrate, and includes a channel formed of at least a part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, and a source electrode and a drain electrode connected to the metal oxide semiconductor layer. The average concentration of carbon atoms in the range from the surface of the channel to a depth of 5 nm is 1.5×10 21 cm -3 The average concentration is 3.5×10 20 cm -3 It may be the following.

[0009] In one embodiment, the thin film transistor is a thin film transistor formed on a substrate, and includes a channel formed by at least a part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, and a source electrode and a drain electrode connected to the metal oxide semiconductor layer. The maximum concentration of carbon atoms in the range from the surface of the channel to a depth of 5 nm is 19 at% or less. The maximum concentration may be 8 at% or less.

[0010] The gate electrode may be disposed between the substrate and the channel.

[0011] The source electrode and the drain electrode may include an oxidation-resistant conductive material.

[0012] The channel may be disposed between the substrate and the gate electrode.

[0013] In the metal oxide semiconductor layer, a surface connected to the source electrode and a surface connected to the drain electrode may have a higher concentration of carbon atoms than a surface of the channel.

[0014] The voltage of the gate electrode relative to the source electrode and the drain electrode may be controlled to be Vth-20V, the temperature may be set to 60°C, and the device may be maintained in a dark state for 3600 seconds, and the threshold shift amount may be 0.5V or less.

[0015] The metal oxide semiconductor layer may further include tin (Sn) and zinc (Zn).

[0016] The semiconductor device may further include an insulating passivation layer covering the channel. The passivation layer may be a metal oxide layer containing zinc (Zn) and silicon (Si).

[0017] In one embodiment, the thin film transistor is a thin film transistor formed on a substrate, and includes a channel formed by at least a part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, a source electrode and a drain electrode connected to the metal oxide semiconductor layer, and an insulating passivation layer covering the channel, the electron affinity of the passivation layer being smaller than the electron affinity of the metal oxide semiconductor layer.

[0018] The passivation layer may have an electron affinity in the range of 2.0 eV to 4.0 eV, and an ionization potential in the range of 6.0 eV to 8.5 eV.

[0019] The passivation layer may include an amorphous material.

[0020] The metal oxide semiconductor layer may further include tin (Sn) and zinc (Zn).

[0021] A display device in one embodiment includes a plurality of pixel circuits, each of which includes the thin film transistor described above.

[0022] The pixel circuit may include a plurality of light emitting elements, and the plurality of pixel circuits may control light emission by the plurality of light emitting elements, respectively.

[0023] An electronic device in one embodiment includes the display device described above and a control device that controls the display device.

[0024] A method for manufacturing a thin film transistor in one embodiment includes forming a thin film transistor on a substrate, the thin film transistor including a channel formed by at least a portion of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, and a source electrode and a drain electrode connected to the metal oxide semiconductor layer, heating the channel in an exposed state in an oxygen-containing atmosphere to 350° C. or more, and forming an insulating layer covering the channel after the heating and before a layer containing carbon atoms contacts the exposed portion of the channel.

[0025] A method for manufacturing a thin film transistor in one embodiment includes forming a thin film transistor on a substrate, the thin film transistor including a channel formed by at least a portion of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, and a source electrode and a drain electrode connected to the metal oxide semiconductor layer, irradiating the channel with ultraviolet light in an atmosphere containing oxygen while the channel is exposed, and forming an insulating layer covering the channel after the irradiation and before a layer containing carbon atoms contacts the exposed portion of the channel.

[0026] A method for manufacturing a thin film transistor in one embodiment includes forming a thin film transistor on a substrate, the thin film transistor including a channel formed by at least a portion of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, and a source electrode and a drain electrode connected to the metal oxide semiconductor layer, and forming an insulating layer covering the channel by DC sputtering in an oxygen atmosphere while the channel is exposed.

[0027] The target used in the DC sputtering may be a conductive metal oxide.

[0028] The metal oxide semiconductor layer may be formed by a PVD method.

[0029] The average concentration of carbon atoms in the range from the surface of the exposed portion of the channel to a depth of 5 nm before the insulating layer is formed is 1.5×10 21 cm -3 The average concentration may be 3.5×10 or less after the insulating layer is formed. 20 cm -3 It may be the following.

[0030] The maximum concentration of carbon atoms in a range from the surface of the portion of the channel that was exposed before the insulating layer was formed to a depth of 5 nm may be 19 at% or less after the insulating layer is formed, and this maximum concentration may be 8 at% or less after the insulating layer is formed.

[0031] The gate electrode may be disposed between the substrate and the channel. After the source electrode and the drain electrode are formed, at least a portion of the carbon atoms present on a surface of the channel may be desorbed.

[0032] The channel may be disposed between the substrate and the gate electrode, the insulating layer that protects against the carbon atoms may be the gate insulating layer, and at least a portion of the carbon atoms present on a surface of the channel may be desorbed before the source electrode and the drain electrode are formed.

[0033] The metal oxide semiconductor layer may further include tin (Sn) and zinc (Zn).

[0034] The insulating layer may be a metal oxide layer containing zinc (Zn) and silicon (Si).

[0035] In one embodiment, a method for manufacturing a thin film transistor includes forming a thin film transistor on a substrate, the thin film transistor including a channel formed by at least a part of a metal oxide semiconductor layer containing at least indium (In), a gate electrode, a gate insulating layer disposed between the channel and the gate electrode, a source electrode and a drain electrode connected to the metal oxide semiconductor layer, and an insulating passivation layer covering the channel, the electron affinity of the passivation layer being smaller than the electron affinity of the metal oxide semiconductor layer.

[0036] The passivation layer may have an electron affinity in the range of 2.0 eV to 4.0 eV, and an ionization potential in the range of 6.0 eV to 8.5 eV.

[0037] The passivation layer may include an amorphous material.

[0038] The metal oxide semiconductor layer may further include tin (Sn) and zinc (Zn). Effect of the Invention

[0039] According to the present invention, it is possible to effectively suppress a threshold shift caused by voltage stress in a thin film transistor using a metal oxide semiconductor layer containing In. Also, according to the present invention, it is possible to effectively suppress a threshold shift caused by NBTS in a thin film transistor using ITZO. [Brief description of the drawings]

[0040] [Figure 1] FIG. 1 is a diagram showing a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a cross-sectional structure of a pixel according to an embodiment. [Diagram 3] 1A to 1C are diagrams illustrating a method for manufacturing a display device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating a method for manufacturing a display device according to an embodiment. [Diagram 5] 1A to 1C are diagrams illustrating a method for manufacturing a display device according to an embodiment. [Figure 6] FIG. 2 is a diagram showing a thin film transistor according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating a method for manufacturing a display device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating a method for manufacturing a display device according to an embodiment. [Figure 9] FIG. 1 shows a thin film transistor for measuring threshold shift. [Figure 10] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor for measurement. [Figure 11] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor for measurement. [Figure 12] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor for measurement. [Figure 13] FIG. 1 shows the results of TDS measurements before photoresist formation and after photoresist formation and removal. [Figure 14] FIG. 13 shows the HAX-PES measurement results (C1s) before photoresist formation and after photoresist formation and removal. [Figure 15] FIG. 13 shows the results of HAX-PES measurements (O1s) before photoresist formation and after photoresist formation and removal. [Figure 16] FIG. 1 is a diagram showing the results of TDS measurement at different heating temperatures. [Figure 17] FIG. 13 is a diagram showing the results of Auger electron spectroscopy measurement for an AfterPR sample and a sample after heat treatment. [Figure 18] FIG. 1 shows the measurement results of threshold shift by NBTS. [Figure 19] FIG. 1 shows the results of measuring threshold shifts using NBIS. [Figure 20] FIG. 1 shows the results of TDS measurements after photoresist formation and removal and after UV ozone treatment. [Figure 21]FIG. 1 shows the measurement results of threshold shifts caused by NBTS and PBTS after UV ozone treatment. [Figure 22] FIG. 1 is a diagram showing an ESL type thin film transistor according to an embodiment. [Figure 23] FIG. 2 is a diagram showing a top-gate thin film transistor according to an embodiment. [Figure 24] FIG. 1 illustrates an electronic device according to an embodiment. [Diagram 25] FIG. 1 illustrates a thin film transistor using a passivation layer in one embodiment. [Figure 26] FIG. 1 illustrates a thin film transistor using a passivation layer in one embodiment. [Figure 27] FIG. 1 illustrates a thin film transistor using a passivation layer in one embodiment. [Figure 28] FIG. 13 is a diagram showing the measurement results of a threshold shift due to a change in temperature. [Figure 29] FIG. 1 shows the results of measuring threshold shifts using NBIS. [Diagram 30] FIG. 13 is a diagram showing the measurement results of the electron concentration before and after light irradiation. [Diagram 31] FIG. 13 is a diagram showing the measurement results of the absorption coefficient. [Diagram 32] FIG. 13 is a diagram showing the measurement results of the change in threshold shift over time by NBS and a model formula. [Diagram 33] FIG. 1 shows the measurement results of threshold shifts caused by NBTS and PBTS. [Diagram 34] FIG. 1 shows the measurement results of threshold shifts caused by NBTS and PBTS. [Diagram 35] FIG. 1 shows the results of measuring threshold shifts using NBIS. [Diagram 36] FIG. 1 illustrates a top-gate thin film transistor using a passivation layer according to one embodiment. [Figure 37] FIG. 1 illustrates a top-gate thin film transistor using a passivation layer according to one embodiment. [Figure 38]FIG. 1 shows the results of measuring threshold shift (ITGO) by NBS with and without UV ozone treatment. [Figure 39] FIG. 1 shows the measurement results (IZO) of threshold shift by NBS with and without UV ozone treatment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The embodiments shown below are merely examples, and the present invention is not to be interpreted as being limited to these embodiments. In the drawings referred to in this embodiment, the same parts or parts having similar functions are given the same or similar symbols (symbols with A, B, etc. added after numbers) and repeated explanations may be omitted. In order to clarify the explanation, the drawings may be described schematically with dimensional ratios different from the actual ratios or parts of the configuration omitted from the drawings.

[0042] When indicating the positional relationship of a second component to a first component, the expressions "above" and "below" are not limited to cases where the second component is located directly above or below the first component, but also include cases where other components are present, unless otherwise specified.

[0043] [overview] The display device in one embodiment is an organic EL (Electro Luminescence) display using an OLED (Organic Light Emitting Diode) in this example. The organic EL display may realize color display by using a plurality of OLEDs that emit light of different colors, or may realize color display by using an OLED that emits white light and a color filter. The display device may further have a touch sensor function. The touch sensor detects contact of a finger, a stylus, or the like with the display surface by, for example, a self-capacitance method or a mutual capacitance method.

[0044] The display device includes a thin film transistor using ITZO. According to a driving method of the display device, the thin film transistor is controlled to be in an off state for a long time. Therefore, it is not desirable to use a thin film transistor that is prone to a negative shift in threshold voltage due to NBTS. As described in detail below, according to the thin film transistor using ITZO, a method based on the knowledge obtained by the inventors has been used to suppress the negative shift in threshold voltage due to NBTS.

[0045] First, the configuration of the display device will be described, and then the configuration of the thin film transistors included in the display device and the configuration for realizing suppression of the negative shift of the threshold voltage due to NBTS will be described.

[0046] [Display device configuration] FIG. 1 is a diagram showing a display device in an embodiment. The display device 1000 has a structure in which a first substrate 1 and a second substrate 2 are bonded together with a bonding material. The first substrate 1 includes a display region D1 and a driving circuit GD. A driver IC (Integrated Circuit) chip CD is mounted on the first substrate 1. The driver IC chip CD may be mounted on a FPC (Flexible Printed Circuits) connected to the first substrate 1. In FIG. 1, the FPC is omitted. The second substrate 2 protects elements formed on the first substrate 1. Instead of the second substrate 2, a cover layer that covers the elements formed on the first substrate 1 may be disposed.

[0047] In the display region D1, a plurality of scanning signal lines GL, a plurality of data signal lines SL, and a plurality of pixels PX are arranged. The plurality of pixels PX are arranged, for example, in a matrix. The scanning signal lines GL and the data signal lines SL are arranged to intersect with each other. A pixel PX is arranged at a portion where the scanning signal line GL and the data signal line SL intersect. Although FIG. 1 shows an example in which one scanning signal line GL and one data signal line SL are arranged for one pixel PX, other signal lines may be arranged.

[0048] The driving circuit GD is disposed adjacent to the display area D1 and is connected to the scanning signal lines GL. The driver IC chip CD is connected to the data signal lines SL and the driving circuit GD. The driver IC chip CD controls the signals supplied to the data signal lines SL based on an external control signal, and further controls the driving circuit GD to control the signals supplied to the scanning signal lines GL. In this example, the driving circuit GD includes a circuit such as a shift register using a thin-film transistor 100 (see FIG. 2). Since the thin-film transistor 100 is an n-type transistor, a bootstrap circuit may be used to realize the circuit configuration included in the driving circuit GD.

[0049] The pixel PX includes a light-emitting element that is an OLED, and a pixel circuit for controlling light emission by the light-emitting element. The pixel circuit includes elements such as a thin-film transistor 100 and a capacitor. In this example, a pixel circuit included in one pixel PX uses a plurality of thin-film transistors 100. In this example, light emitted from the light-emitting element travels in the opposite direction to the first substrate 1 on which the light-emitting element is formed, and is visually recognized by a user through the second substrate 2. That is, the display device 1000 employs a top emission system. The display device 1000 may employ a bottom emission system.

[0050] 2 is a diagram showing a schematic cross-sectional structure of a pixel in one embodiment. The first substrate 1 includes a first support substrate 10, a base insulating layer 110, a thin film transistor 100, an interlayer insulating layer 200, a pixel electrode 300, a bank layer 400, a light-emitting layer 500, a counter electrode 600, and a sealing layer 900. The second substrate 2 is disposed so as to cover the sealing layer 900. As described above, a plurality of thin film transistors 100 are used in one pixel circuit, but in FIG. 2, one thin film transistor 100 connected to the pixel electrode 300 is shown, and the other thin film transistors 100 are omitted.

[0051] The first support substrate 10 and the second substrate 2 are glass substrates. Either or both of the first support substrate 10 and the second substrate 2 may be a flexible substrate such as an organic resin substrate.

[0052] The base insulating layer 110 is disposed on the first support substrate 10 and prevents moisture and gas from penetrating into the inside. The base insulating layer 110 includes an insulating film such as silicon oxide or silicon nitride. The base insulating layer 110 may include a configuration in which multiple types of insulating films are stacked.

[0053] As described above, the thin film transistor 100 includes ITZO as a semiconductor layer, and is disposed on the base insulating layer 110. In this example, the thin film transistor 100 is a BCE (Back Channel Etch) type thin film transistor. The detailed configuration of the thin film transistor 100 will be described later.

[0054] The interlayer insulating layer 200 covers the thin-film transistor 100. The interlayer insulating layer 200 includes an inorganic insulating film such as silicon oxide or silicon nitride. The interlayer insulating layer 200 may include a configuration in which a plurality of types of insulating films are stacked. In this example, the silicon oxide film of the interlayer insulating layer 200 contacts the thin-film transistor 100. The interlayer insulating layer 200 may further include a planarizing insulating film on the inorganic insulating film. The planarizing insulating film may be an organic insulating film such as acrylic, polyimide, or epoxy. When the interlayer insulating layer 200 includes a configuration in which a plurality of insulating films are stacked, a conductive film such as wiring may be disposed between the plurality of insulating films.

[0055] The pixel electrode 300 is connected to the drain electrode 172 (see FIG. 6) of the thin film transistor 100 through a contact hole formed in the interlayer insulating layer 200. The pixel electrode 300 includes a conductive film that functions as a cathode of the light-emitting layer 500. The pixel electrode 300 includes one type of conductive film or a laminated structure of multiple types of conductive films. Depending on the configuration of the pixel circuit, the pixel electrode 300 may function as an anode of the light-emitting layer 500. In this case, the pixel electrode 300 is connected to the source electrode 171 of the thin film transistor 100. As described above, since the display device 1000 employs a top emission type, the pixel electrode 300 does not need to be optically transparent. If the display device 1000 employs a bottom emission type, the pixel electrode has optical transparency.

[0056] The bank layer 400 covers the ends of the pixel electrodes 300 and includes openings that expose parts of the pixel electrodes 300. The bank layer 400 includes an organic insulating film such as acrylic, polyimide, or epoxy.

[0057] The light-emitting layer 500 is disposed so as to cover a portion of the pixel electrode 300 and the bank layer 400. The light-emitting layer 500 has a structure in which a plurality of types of organic materials are laminated. The light-emitting layer 500 emits light when a current is supplied to the light-emitting layer 500. By changing at least one of the plurality of organic materials constituting the light-emitting layer 500, it is possible to make the emitted light colors different from each other.

[0058] The counter electrode 600 covers the light-emitting layer 500. The counter electrode 600 includes a conductive film that functions as an anode of the light-emitting layer 500. The counter electrode 600 includes one type of conductive film or a laminated structure of multiple types of conductive films. As described above, depending on the configuration of the pixel circuit, the counter electrode 600 may function as a cathode of the light-emitting layer 500. As described above, the display device 1000 employs a top emission system, and therefore the counter electrode 600 has optical transparency. The pixel electrode 300, the light-emitting layer 500, and the counter electrode 600 form a light-emitting element in each pixel PX.

[0059] The sealing layer 900 is an insulating layer that covers the entire display region D1 and suppresses the intrusion of moisture and gas into the light-emitting layer 500. The sealing layer 900 includes, for example, a configuration in which a silicon nitride film arranged on the counter electrode 600 and a planarization insulating film on the silicon nitride film are laminated, and has optical transparency. The planarization insulating film may be, for example, an organic insulating film such as acrylic, polyimide, or epoxy. The sealing layer 900 is disposed between the silicon nitride film and the second substrate 2, and may function as a member for bonding the first substrate 1 and the second substrate 2 together.

[0060] [Display device manufacturing method] Next, a method for manufacturing the display device 1000 will be described.

[0061] 3 to 5, 7 and 8 are diagrams for explaining a manufacturing method of the display device 1000 in one embodiment. In particular, in FIG. 3 to FIG. 5, a manufacturing method of the thin film transistor 100 in the display device 1000 will be explained. First, a first support substrate 10 is prepared, and a base insulating layer 110 is formed on the first support substrate 10. The base insulating layer 110 is formed by, for example, a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. The CVD method includes, for example, a PECVD method. The PVD method includes a sputtering method. The same applies to the following description.

[0062] The gate electrode 120 is obtained by forming a film of a conductive material formed by a PVD method on the base insulating layer 110 into a desired pattern. The desired pattern is formed, for example, by an etching process using a photoresist by photolithography or a lift-off process. The gate electrode 120 may be formed in a patterned state by a printing method, an inkjet method, or the like. When the gate electrode 120 is formed, at least one of the scanning signal line GL and the data signal line SL may be formed at the same time. The conductive material is, for example, a metal such as molybdenum, tantalum, tungsten, gold, copper, chromium, aluminum, or a metal compound containing at least one of these. The gate electrode 120 may include a structure in which a plurality of types of conductive materials are laminated. In this example, the gate electrode 120 includes a structure in which molybdenum and copper are laminated in order from the first support substrate 10 side.

[0063] The gate insulating layer 130 is formed by a CVD method or a PVD method so as to cover the gate electrode 120 and the base insulating layer 110. The thickness of the gate insulating layer 130 can be various, for example, 20 nm to 200 nm, and preferably 50 nm to 150 nm. The structure after the gate insulating layer 130 is formed corresponds to FIG. 3. The gate insulating layer 130 is formed of an inorganic insulating material. The inorganic insulating material is, for example, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or the like. The gate insulating layer 130 may include a structure in which a plurality of types of inorganic insulating materials are stacked. In this example, the gate insulating layer 130 includes a structure in which a silicon nitride film and a silicon oxide film are stacked in order from the gate electrode 120 side.

[0064] Next, an ITZO film is formed on the gate insulating layer 130 by a CVD method or a PVD method. In this example, the ITZO is formed by a sputtering method using a gas containing argon and oxygen. The ITZO film is amorphous in this example, but may contain microcrystals. It may contain elements other than In, Sn, Zn, and O. In a range of 5 nm from the surface of the channel CH (see FIG. 6), a portion where Sn is 10 at% or more may be included, or a portion where Sn is 13 at% or more may be included. In a range of 5 nm from the surface of the channel CH, a portion where the atomic percentage of Sn is greater than the atomic percentage of Zn may be included. The thickness of the ITZO film can be various, but is, for example, 10 nm or more and 200 nm or less, and preferably 20 nm or more and 100 nm or less. The semiconductor layer 150 is obtained by forming the ITZO film into a desired pattern. The desired pattern is formed, for example, by an etching process using a photoresist by photolithography or a lift-off process. The structure after forming a photoresist PR on the ITZO film and forming an island-shaped semiconductor layer 150 by an etching process corresponds to Fig. 4. The example shown in Fig. 4 shows the state before the photoresist PR is removed.

[0065] When photolithography is used, the upper surface 150a of the semiconductor layer 150 comes into contact with the photoresist PR. As will be described in detail later, when the semiconductor layer 150, which is an ITZO film, comes into contact with the photoresist PR, the carbon atom "C" of the organic compound contained in the photoresist PR is bonded to the contact surface (upper surface 150a). Even if the semiconductor layer 150 is exposed to an etching solution (hereinafter referred to as a stripping solution) for removing the photoresist PR, the carbon atom bonded to the upper surface 150a is not removed.

[0066] These carbon atoms remain as "CO" and "C=O" (hereinafter referred to as carbon residue components). ITZO is a type of SnO x (tin oxide), it is said that the surface is prone to adsorption of "CO" and "C=O". 2 O x (Indium oxide), ZnO x (zinc oxide) also has a small effect, but SnO x It is said that this tendency is similar to that of tin oxide (tin oxide). This carbon residue component introduces defects into ITZO. In ITZO, the carbon residue component supplies electrons, increasing the electron concentration, and NBTS traps holes in the defects, which are thought to be the factors that cause the threshold voltage to shift to the negative side.

[0067] When the semiconductor layer 150 is formed by a lift-off process, the photoresist PR does not come into contact with the upper surface 150a of the semiconductor layer 150. However, when the photoresist PR is removed for lift-off, the upper surface 150a may be exposed to a stripping solution, and carbon residues may similarly be generated on the upper surface 150a due to the effects of organic compounds contained in the stripping solution and the components of the dissolved photoresist PR.

[0068] The source electrode 171 and the drain electrode 172 are obtained by forming a film of a conductive material formed on the semiconductor layer 150 and the gate insulating layer 130 by a PVD method into a desired pattern. The desired pattern is formed, for example, by an etching process using a photoresist by photolithography or a lift-off process. When the source electrode 171 and the drain electrode 172 are formed, at least one of the scanning signal line GL and the data signal line SL may be formed at the same time. The conductive material is, for example, a metal such as molybdenum, tantalum, tungsten, gold, copper, chromium, aluminum, or a metal compound containing at least one of these metals.

[0069] The source electrode 171 and the drain electrode 172 are preferably made of a conductive material having oxidation resistance. The source electrode 171 and the drain electrode 172 may include a structure in which a plurality of types of conductive materials are laminated. In this case, it is preferable that at least the conductive material exposed on the upper surface has oxidation resistance. In this example, the source electrode 171 and the drain electrode 172 include a structure in which molybdenum and copper are laminated in this order from the semiconductor layer 150 side.

[0070] The configuration after forming the source electrode 171 and the drain electrode 172 by an etching process in which a photoresist PR is formed on a conductive material corresponds to Fig. 5. The example shown in Fig. 5 shows the state before the photoresist PR is removed. In this state, the back channel side surface 150b of the semiconductor layer 150 is not in contact with the photoresist PR, but when the photoresist PR is removed, it may be exposed to a stripping solution for removing the photoresist PR, which may similarly result in carbon residue components being generated on the back channel side surface 150b.

[0071] Depending on the etching solution used to form the source electrode 171 and the drain electrode 172, carbon residue may also be generated on the back channel side surface 150b. For example, in a PAN etching solution containing a mixture of phosphoric acid, nitric acid, and acetic acid, the acetic acid may be a factor in generating carbon residue. At least, the back channel side surface 150b is already in contact with the photoresist PR in the state shown in FIG. 4. Therefore, there is a possibility that carbon residue may continue to exist on the back channel side surface 150b.

[0072] When the source electrode 171 and the drain electrode 172 are formed by a lift-off process, a photoresist PR is formed on the back channel side surface 150b, resulting in carbon residue components on the back channel side surface 150b.

[0073] Fig. 6 is a diagram showing a thin film transistor in one embodiment. Fig. 6 corresponds to the thin film transistor 100 after removing the photoresist PR in Fig. 5. The region between the source electrode 171 and the drain electrode 172 in the semiconductor layer 150 is the channel CH. Although Fig. 6 does not show the range of the channel CH in the channel width direction (depth direction in Fig. 6), the channel CH includes, as generally defined, the region sandwiched between the source electrode 171 and the drain electrode 172 in the region where the semiconductor layer 150 and the gate electrode 120 overlap when the thin film transistor 100 is viewed in a direction perpendicular to the substrate.

[0074] The inventors have found that in order to suppress the negative shift of the threshold voltage due to NBTS, it is important to reduce the amount of carbon residue on the surface of the channel CH. That is, it is preferable to reduce the amount of carbon residue on the surface of the channel CH on the gate electrode 120 side (hereinafter referred to as the gate side surface 150g) and the opposite surface (the back channel side surface 150b).

[0075] On the other hand, as described above, when the surface of the channel CH is exposed, the carbon residue component may increase due to various manufacturing processes. There is no point in temporarily reducing the carbon residue component, and it is only meaningful that the carbon residue component on the surface of the channel CH is reduced when the surface of the channel CH is not exposed, that is, when the surface of the channel CH is covered with another layer. In addition, after the surface of the channel CH is not exposed, it is difficult to remove the carbon residue component from the surface of the channel CH.

[0076] The source surface 150s and the drain surface 150d do not function as the channel CH, and therefore do not need to have a reduced carbon residual component. The source surface 150s corresponds to a portion of the surface of the semiconductor layer 150 that is in contact with the source electrode 171. The drain surface 150d corresponds to a portion of the surface of the semiconductor layer 150 that is in contact with the drain electrode 172.

[0077] In this example, at least one of UV ozone treatment and heat treatment is performed in a state where a part of the back channel side surface 150b (a region between the source surface 150s and the drain surface 150d) is exposed as shown in FIG. 6. The UV ozone treatment is performed by irradiating ultraviolet light in an atmosphere containing oxygen. Carbon residue components in the exposed part of the back channel side surface 150b are decomposed by the ozone obtained by the ultraviolet light irradiation, more specifically, by active oxygen generated from the ozone, and carbon atoms are desorbed from the surface. The heat treatment is performed by heating to 350°C or higher, more preferably 370°C or higher, in an atmosphere containing oxygen. The heat treatment in an atmosphere containing oxygen decomposes carbon residue components in the exposed part of the back channel side surface 150b, and carbon atoms are desorbed from the surface.

[0078] The above-mentioned oxygen-containing atmosphere includes an air atmosphere and an atmosphere having an oxygen concentration higher than that of air. The oxygen-containing atmosphere does not exclude an atmosphere having an oxygen concentration lower than that of air, so long as oxygen is contained therein.

[0079] As a result of the desorption of the carbon atoms, the average concentration of carbon atoms in the range from the exposed portion of the back channel side surface 150b to a depth of 5 nm becomes 1.5×10 21 cm -3 The conditions of the UV ozone treatment or the heat treatment are set so that the average concentration of carbon atoms in the range from the exposed portion of the back channel side surface 150b to a depth of 5 nm is reduced to 3.5×10 20 cm -3 It is preferable to reduce it to:

[0080] The conditions of the UV ozone treatment or the heat treatment may be set so that, as a result of the desorption of carbon atoms, the maximum concentration of carbon atoms in the range from the exposed portion of the back channel side surface 150b to a depth of 5 nm is reduced to 19 at% or less when measured by Auger electron spectroscopy. It is preferable that the maximum concentration of carbon atoms in the range from the exposed portion of the back channel side surface 150b to a depth of 5 nm is reduced to 8 at% or less. The conditions of the UV ozone treatment are, for example, the intensity of ultraviolet light, the irradiation time, the oxygen concentration, the substrate temperature, etc. The conditions of the heat treatment are, for example, the heating temperature, the heating time, the oxygen concentration, etc.

[0081] Other than the exposed portion of the back channel side surface 150b, that is, the source surface 150s is covered with the source electrode 171, and the drain surface 150d is covered with the drain electrode 172. Therefore, the source surface 150s and the drain surface 150d hardly have any residual carbon components desorbed even when subjected to UV ozone treatment or heat treatment, and have a higher concentration of carbon atoms than the exposed portion of the back channel side surface 150b. However, since the source surface 150s and the drain surface 150d do not function as the channel of the thin film transistor 100, the presence of residual carbon components has little effect.

[0082] There is no factor that would cause carbon residue to occur on the gate-side surface 150g. Even if carbon residue exists on the gate insulating layer 130 before the ITZO film is formed on the gate insulating layer 130, the carbon residue is reduced by the process (oxygen-containing sputtering) when forming the ITZO film by the PVD method. As a result, carbon atoms are eliminated and the concentration falls within the above-mentioned range. Note that the gate insulating layer or the semiconductor layer is usually produced by a gas phase method, but if it is produced by a solution method instead of a gas phase method, there is a factor that would cause carbon residue to occur on the gate-side surface 150g.

[0083] After the process for reducing the carbon residue, an interlayer insulating layer 200 is formed to cover the thin film transistor 100. The thin film transistor 100, particularly the portion in contact with the exposed portion of the back channel side surface 150b, is protected from carbon atoms by an inorganic insulating material containing almost no carbon components so that carbon residue is not generated again. That is, after the carbon atoms are desorbed from the surface of the channel CH, an insulating layer that protects the channel CH is formed before a layer containing carbon atoms is formed again on the surface of the channel CH.

[0084] In this example, the interlayer insulating layer 200 includes a structure in which a silicon oxide film, a silicon nitride film, and an organic resin film are laminated in this order from the thin film transistor 100 side. The inorganic insulating material film is formed by a CVD method or a PVD method. When forming the inorganic insulating material film, a film formation method that requires the introduction of carbon atoms is not adopted. For example, forming aluminum oxide by an ALD (Atomic Layer Deposition) method is not preferable because it uses trimethylaluminum (TMA) containing carbon. However, even such aluminum oxide can be used as an inorganic insulating material that does not contact the surface of the channel CH. If the carbon residue component that is finally generated on the surface of the channel CH can be reduced by setting the deposition temperature, etc., the inorganic insulating material by the ALD method may be used as an inorganic insulating material that contacts the surface of the channel CH. The organic resin film is formed by a solution coating method or a printing method. A contact hole that leads to the drain electrode 172 is formed in the interlayer insulating layer 200.

[0085] The pixel electrode 300 is formed on the interlayer insulating layer 200 and is connected to the drain electrode 172 through a contact hole. The pixel electrode 300 is formed by, for example, a PVD method. The structure after the pixel electrode 300 is formed corresponds to FIG. 7. As shown in FIG. 8, a bank layer 400 is formed on the end of the pixel electrode 300 and on the interlayer insulating layer 200, and further a light-emitting layer 500 and a counter electrode 600 are formed. The sealing layer 900 is formed and the first substrate 1 is covered with the second substrate 2, thereby manufacturing the display device 1000 shown in FIG. 2.

[0086] In the above-described thin-film transistor 100, the carbon atoms are desorbed from the surface of the channel CH by the treatment for reducing the carbon residue components adsorbed on the surface of the channel CH, and an insulating layer is formed to cover the surface of the channel CH before the material containing carbon atoms comes into contact with the surface of the channel CH, thereby suppressing a negative shift in the threshold voltage due to NBTS.

[0087] [Experimental Example] Next, we will explain the experimental results showing that the negative threshold shift caused by NBTS can be suppressed by reducing the carbon residue. As described above, the inventors have found that the negative threshold shift caused by NBTS can be suppressed by reducing the carbon residue on the channel CH surface. To verify this, we fabricated a thin film transistor for measuring the threshold shift.

[0088] FIG. 9 is a diagram showing a thin film transistor for measuring a threshold shift. The thin film transistor for measuring a threshold shift includes a gate electrode 125, a gate insulating layer 135 on the gate electrode 125, a semiconductor layer 155 on the gate insulating layer 135, and a source electrode 176 and a drain electrode 177 connected to the semiconductor layer 155. The source electrode 176 and the drain electrode 177 are arranged on either side of the channel CH. The surface of the channel CH on the gate electrode 125 side is a gate side surface 155g, and the opposite surface is a back channel side surface 155b. The portion of the semiconductor layer 155 that contacts the source electrode 176 is a source surface 155s. The portion of the semiconductor layer 155 that contacts the drain electrode 177 is a drain surface 155d. In this example, the back channel side surface 155b is composed of an exposed portion of the channel CH surface, the source surface 155s, and the drain surface 155d.

[0089] The gate electrode 125 is a P-type silicon substrate having conductivity. The gate insulating layer 135 is a thermal oxide film formed on the surface of the silicon substrate, and has a thickness of 150 nm. The semiconductor layer 155 is ITZO, and has a thickness of 20 nm. The composition ratio In (indium):Sn (tin):Zn (zinc) excluding O (oxygen) is 20:40:40 (at%). This composition ratio is a feed value (nominal), and in the case of using a single target, it corresponds to the composition ratio of this target. The composition ratio of the semiconductor layer 155 actually formed is shown as the result of Auger electron spectroscopy measurement described later. The actual semiconductor layer 155 (similar to the above-mentioned semiconductor layer 150) may include a portion where Sn is 10 at% or more, or may include a portion where Sn is 13 at% or more, within a range of 5 nm from the surface of the channel CH. The atomic percentage of Sn may be greater than the atomic percentage of Zn, within a range of 5 nm from the surface of the channel CH. When the concentration of Sn is high, carbon residue components are likely to occur, but this is not a major problem because the carbon residue components can be reduced as described below. The length of the channel CH of this thin film transistor (channel length) is 30 μm, and the channel width is 60 μm. From the viewpoint of miniaturization, the channel length is preferably 100 μm or less, more preferably 30 μm or less, even more preferably 10 μm or less, and even more preferably 3 μm or less. Next, a method for manufacturing a thin film transistor for measuring threshold shift will be described.

[0090] 10 to 12 are diagrams for explaining a method for manufacturing a thin-film transistor for measurement. A gate electrode (P-type silicon substrate) 125 on which a gate insulating layer 135 (thermal oxide film) is formed is prepared, and a photoresist PR is formed as shown in FIG. 10, and an ITZO film 155f is further formed. As shown in FIG. 11, when the photoresist PR is removed by a lift-off process, unnecessary parts of the ITZO film 155f are removed together with the photoresist PR, and a semiconductor layer 155 is formed. The photoresist PR before the pattern is formed contacts the surface of the gate insulating layer 135, but no carbon residue is present in the gate insulating layer 135. Even if a small amount of carbon residue is present, the carbon residue is desorbed by sputtering in an oxygen-containing atmosphere when the ITZO film 155f is formed by the PVD method.

[0091] As shown in FIG. 12, a photoresist PR is formed, and a gold film 175f is further formed. When the photoresist PR is formed, the photoresist PR contacts the entire upper surface 155a of the semiconductor layer 155. As shown in FIG. 12, the photoresist PR remains in contact with the back channel side surface 155b even after the pattern is formed. When the photoresist PR is removed by a lift-off process, the source electrode 176 and the drain electrode 177 are formed as shown in FIG. 9. At this time, carbon residue components are present in the exposed portion of the back channel side surface 155b, the source surface 155s, and the drain surface 155d. As described above, the carbon residue components in the exposed portion of the back channel side surface 155b are reduced by the heat treatment or UV ozone treatment.

[0092] [Carbon residue components] An ITZO film was formed on a substrate, and a sample before photoresist was formed (hereinafter referred to as the BeforePR sample) and a sample from which photoresist was formed on the ITZO film and then the photoresist was removed (hereinafter referred to as the AfterPR sample) were prepared, and TDS (Thermal Desorption Spectrometry) and HAX-PES (Hard X-ray Photoelectron Spectroscopy) measurements were performed.

[0093] Figure 13 shows the results of TDS measurements before forming a photoresist and after forming and removing the photoresist. As shown in Figure 13, no CO was detected in the BeforePR sample. On the other hand, it was confirmed that CO was desorbed from the AfterPR sample at around 350°C. In other words, it was confirmed that when a photoresist is formed, CO remains on the surface of the ITZO film as a carbon residue, even if the photoresist is removed with a stripping solution or the like.

[0094] Figures 14 and 15 show the results of HAX-PES measurements before and after forming and removing photoresist. According to the results in Figure 14 (C1s) and Figure 15 (O1s), peaks related to "CO" and "C=O" were not detected in the BeforePR sample, but were detected in the AfterPR sample. These small peaks are due to carbon. In other words, the presence of carbon residue components has been confirmed in the AfterPR sample.

[0095] [Effect of heat treatment on carbon residue components] The effect of heat treatment on the desorption of carbon residue components from the AfterPR sample was confirmed.

[0096] Figure 16 shows the results of TDS measurements at different heating temperatures. For the AfterPR samples, samples that were not heat-treated (RT), samples that were heat-treated at 300°C for 1 hour, samples that were heat-treated at 350°C for 1 hour, and samples that were heat-treated at 400°C for 1 hour were prepared. According to the results of TDS measurements for each AfterPR sample, the amount of CO desorbed decreased as the heat treatment temperature increased. In other words, it was confirmed that the amount of carbon residue decreased as the heating temperature increased.

[0097] Specifically, the amount of CO desorbed was 1.0 × 10 for the AfterPR sample without heat treatment (RT). 15 cm -2and for the AfterPR sample heat-treated at 300 °C for 1 h, it was 0.5 × 10 15 cm -2 and for the AfterPR sample heat-treated at 350 °C for 1 h, it was 1.5 × 10 14 cm -2 and for the AfterPR sample heat-treated at 400 °C for 1 h, the detection limit (1.0 × 10 14 cm -2 ) or less.

[0098] FIG. 17 shows the results of Auger electron spectroscopy measurements of the AfterPR sample and the sample after heat treatment. The horizontal axis corresponds to the time (sputter time) for etching (sputtering) the surface of the ITZO with an Ar ion beam. In this example, the etching rate of ITZO is 2.5 nm / min. The composition ratio (atomic concentration) in the depth direction was obtained by repeating etching and Auger electron spectroscopy measurements. When the AfterPR sample was not heat treated, carbon atoms were detected at a depth of 2 nm or 3 nm from the surface of the ITZO film. In particular, 50 at % of carbon atoms were detected at the outermost surface. On the other hand, when the AfterPR sample was heat treated at 400° C., 8 at % of carbon atoms were detected at the outermost surface, but the carbon atoms were below the detection limit at a depth of less than 1 nm from the surface of the ITZO film.

[0099] Considering the results of the TDS measurement and the Auger electron spectroscopy measurement, the value of 1.0×10 15 cm -2 The amount of CO desorption was 1.0×10 at %, and 50 at % of carbon atoms was measured on the outermost surface. In this case, based on the relationship described below, the average concentration of carbon atoms in the range from the surface of the ITZO film to a depth of 5 nm was 1.0×10 22 cm -3 is at least 1.5 × 10 21 cm -3 It can be said that there are more.

[0100] For the AfterPR sample that was heat-treated at 400°C for 1 hour, the detection limit (1.0 × 10 14 cm -2 ), and 8 at% of carbon atoms were measured on the outermost surface. In this case, the average concentration of carbon atoms in the range from the surface of the ITZO film to a depth of 5 nm was 3.5 × 10 20 cm -3 It can be said that.

[0101] For the AfterPR sample heat-treated at 350 °C for 1 h, the 14 cm -2 Considering the TDS measurement results, it is estimated that when the treated sample is heated at 350°C, the maximum concentration of carbon atoms on the outermost surface is 19 at%. In this case, the average concentration of carbon atoms in the range from the surface of the ITZO film to a depth of 5 nm is 1.5×10 21 cm -3 It can be said that.

[0102] The relationship between the results of TDS measurement, Auger electron spectroscopy measurement, and carbon atom concentration is explained. Taking into account the molecular weight and film density, the number of atoms per unit volume (1 cubic centimeter) of ITZO is approximately 8.0 × 10 22 cm -3 According to the results of Auger electron spectroscopy, the total amount of C relative to the total amount of In, Sn, Zn, and O contained within the range of 5 nm deep from the surface of the ITZO film (sputtering time 2 minutes) is referred to as the relative carbon concentration below. The relative carbon concentration is obtained by integrating the atomic percentage of C within the range of 5 nm from the surface with respect to the value (100 x 5) integrated within the range of 5 nm from the surface, assuming that 100% is obtained.

[0103] According to the results of the AfterPR sample that was not heat-treated, the relative carbon concentration was approximately 12.5%. The number of carbon atoms per unit volume is obtained by multiplying the relative carbon concentration by the number of atoms per unit volume mentioned above. This number of carbon atoms per unit volume corresponds to the average concentration in the range from the surface to 5 nm, and is hereafter referred to as the carbon atom concentration.

[0104] The AfterPR sample without heat treatment had a carbon atom concentration of 1.0 × 10 22 cm -3 On the other hand, the AfterPR sample, which was heat-treated at 400°C for 1 hour, had a calculated carbon atom concentration of 3.5×10 20 cm -3 Here, according to the TDS measurement results, the amount of CO desorbed from the AfterPR sample that was heat-treated at 350°C for 1 hour was 0.15 times that of the AfterPR sample that was not heat-treated. Therefore, the carbon atom concentration of the AfterPR sample that was heat-treated at 350°C for 1 hour was 1.5×10 21 cm -3 It is assumed that.

[0105] Considering the carbon atom profiles from Auger electron spectroscopy of the AfterPR sample that was not heat-treated and the AfterPR sample that was heat-treated at 400°C for 1 hour, as well as the above-mentioned carbon atom concentrations, it is estimated that the maximum carbon atom concentration on the outermost surface of the AfterPR sample that was heat-treated at 350°C for 1 hour is 19 at%.

[0106] The position of the surface of the channel CH in the semiconductor layer 150 in the above-described thin-film transistor 100 may be defined as follows. In the case of the back channel side surface 150b, when measured from the inorganic insulating film of the adjacent interlayer insulating layer 200 toward the semiconductor layer 150 (channel CH) by Auger electron spectroscopy as described above, the surface is the position where In, Sn, and Zn are detected. On the other hand, in the case of the gate side surface 150g, when measured from the adjacent gate insulating layer 130 toward the semiconductor layer 150 (channel CH) by Auger electron spectroscopy as described above, the surface is the position where In, Sn, and Zn are detected.

[0107] [Impact on NBTS] As shown in FIG. 9, after forming the source electrode 176 and the drain electrode 177 for the thin film transistors for threshold measurement, the following were prepared: a thin film transistor without heat treatment (RT), a thin film transistor with heat treatment at 300°C for 1 hour, a thin film transistor with heat treatment at 350°C for 1 hour, and a thin film transistor with heat treatment at 400°C for 1 hour. NBTS was performed on these thin film transistors for measurement. NBTS was performed under the conditions that the voltage of the gate electrode relative to the source electrode and the drain electrode was controlled to be "Vth-20V", the temperature was set to 60°C, and the device was maintained in the dark. The time for which the NBTS was applied was maintained for a maximum of 3600 seconds.

[0108] FIG. 18 is a diagram showing the measurement results of the threshold shift by NBTS. The Id (Drain Current)-Vg (Gate Voltage) characteristic shown in FIG. 18 shows the drain current when the voltage of the gate electrode 172 is changed while controlling the voltage of the drain electrode 177 with respect to the source electrode 176 to be "0.1 V". FIG. 18 shows the NBTS time dependency of the threshold shift corresponding to each heat treatment condition. As shown in FIG. 18, the threshold shift before NBTS was "-12 V" without heat treatment, "-3.5 V" with 300°C heat treatment, "-0.5 V" with 350°C heat treatment, and "-0.1 V" with 400°C heat treatment. From this result, it was confirmed that the smaller the carbon residue component exists, the smaller the negative shift amount. If the threshold shift amount can be suppressed to the case of 350°C heat treatment, sufficient reliability can be obtained for practical use.

[0109] [Impact on NBIS] As shown in FIG. 9, after forming the source electrode 176 and the drain electrode 177, the thin film transistors for measuring the threshold voltage were prepared. The thin film transistors were prepared without heat treatment (RT) and with heat treatment at 400°C for 1 hour. NBIS (Negative Bias Illumination Stress) was performed on these thin film transistors for measurement. NBIS was performed under the condition that the voltage of the gate electrode relative to the source electrode and the drain electrode was controlled to be "Vth-20V" and maintained under light irradiation of 4000 lux. The time for which the NBIS was applied was maintained for a maximum of 3600 seconds.

[0110] FIG. 19 is a diagram showing the measurement results of the threshold shift by NBIS. The Id-Vg characteristics shown in FIG. 19 show the drain current when the voltage of the gate electrode 172 is changed while controlling the voltage of the drain electrode relative to the source electrode to be "0.1 V". FIG. 19 shows the NBIS time dependency of the threshold shift corresponding to each heat treatment condition. As shown in FIG. 19, the threshold shift amount was "-12.5 V" when no heat treatment was performed, and "-6.5 V" when heat treatment was performed at 400°C. From this result, it was confirmed that the negative shift amount was smaller when the presence of carbon residue components was smaller, even under light irradiation.

[0111] When a thin-film transistor having a threshold shift of "-6.5V" due to NBIS is used in a display device and this shift is problematic, a light-shielding layer may be provided in the vicinity of the thin-film transistor to block the path of light entering the channel CH. By preventing light from entering through the light-shielding layer, the negative shift in the threshold can be further suppressed, thereby improving the reliability of the thin-film transistor.

[0112] Although the display device in one embodiment does not include a light-shielding layer, a light-shielding layer may be disposed above or below the thin-film transistor 100 so as to prevent light from penetrating into the channel CH. By reducing the carbon residue, the threshold shift amount is reduced even under light irradiation. Therefore, the amount of light to be blocked can be reduced in order to realize the threshold shift amount necessary to ensure reliability. As a result, by reducing the carbon residue, the light-shielding layer disposed around the thin-film transistor 100 can be reduced in size or omitted.

[0113] [Effect of UV ozone treatment on carbon residue components] The effect of UV ozone treatment on the desorption of carbon residue components from the AfterPR sample was confirmed.

[0114] Figure 20 shows the TDS measurement results after photoresist formation / removal and after UV ozone treatment. The relationship between the BeforePR sample and the AfterPR sample is the same as that described above. The AfterPR sample that was subjected to UV ozone treatment at room temperature also showed TDS measurement results equivalent to those of the BeforePR sample. In other words, it was confirmed that the UV ozone treatment reduced the carbon residue on the surface of the ITZO film, making it equivalent to the state before the photoresist was formed.

[0115] Since the UV ozone treatment can be performed even at room temperature, it is possible to remove the carbon residue even if a material with low heat resistance is present before the thin film transistor 100 shown in Fig. 6 is formed. Although not shown, for example, when an organic insulating film such as a color filter is present between the thin film transistor 100 and the first support substrate 10, it is useful to reduce the carbon residue by the UV ozone treatment rather than the heat treatment.

[0116] [Impact on NBTS] As shown in FIG. 9, a source electrode 176 and a drain electrode 177 were formed in the thin film transistor for threshold measurement, and then a thin film transistor was prepared by performing UV ozone treatment. NBTS was performed on these thin film transistors for measurement. The conditions of NBTS were the same as those when the measurement results shown in FIG. 18 were obtained, and the voltage of the gate electrode relative to the source electrode and the drain electrode was controlled to be "Vth-20V", the temperature was set to 60°C, and the device was maintained in a dark state. PBTS (Positive Bias Temperature Stress) was also performed, in which the voltage of the gate electrode relative to the source electrode 176 and the drain electrode 177 was controlled to be "Vth+20V", the temperature was set to 60°C, and the device was maintained in a dark state.

[0117] Fig. 21 shows the measurement results of the threshold shift caused by NBTS and PBTS after UV ozone treatment. The Id-Vg characteristics shown in Fig. 21 show the drain current when the voltage of the drain electrode 177 relative to the source electrode 176 is controlled to "0.1 V" and the voltage of the gate electrode 172 is changed. As shown in Fig. 21, even in the UV ozone treatment, the amount of threshold shift caused by NBTS is kept sufficiently small.

[0118] The amount of threshold shift due to PBTS is also kept sufficiently small, just like NBTS. Although not mentioned in the above explanation, the amount of threshold shift due to PBTS is kept small even without treatment to reduce the carbon residue component in the AfterPR sample (UV ozone treatment or heat treatment), so it is presented for reference.

[0119] <Modification> The present disclosure is not limited to the above-described embodiments, and includes various other modified examples. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure, and are not necessarily limited to those having all of the configurations described. It is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. Some modified examples will be described below.

[0120] [Thin-film transistors with other structures] The thin film transistor used in the display device 1000 is not limited to the thin film transistor 100 in the above-described embodiment, and thin film transistors of various structures can be used. Two examples of typical structures of thin film transistors using ITZO will be described below.

[0121] The thin-film transistor 100 is a BCE type thin-film transistor, but an ESL (Etch Stop Layer) type thin-film transistor may also be applied to the display device 1000.

[0122] FIG. 22 is a diagram showing an ESL type thin film transistor in one embodiment. FIG. 22 shows an ESL type thin film transistor 100A. The thin film transistor 100A has a structure in which an etch stop layer 150e is added to the thin film transistor 100. The etch stop layer 150e is a layer that serves as an etching stopper when forming the source electrode 171 and the drain electrode 172, and is, for example, silicon oxide formed by a CVD method or a PVD method. When the source electrode 171 and the drain electrode 172 are formed, the exposed part of the back channel side surface 150b is already covered with the etch stop layer 150e. Therefore, in the case of the ESL type thin film transistor 100A, after the semiconductor layer 150 is formed, a process (heating process or UV ozone process) for removing carbon residual components is performed before the silicon oxide film that becomes the etch stop layer 150e is formed. That is, the etch stop layer 150e functions as an insulating layer that covers the channel.

[0123] In the ESL-type thin-film transistor 100A, the presence of the etch-stop layer 150e causes the source electrode 171 and the drain electrode 172 to contact the semiconductor layer 150 at positions different from those of the BCE-type thin-film transistor 100. Therefore, the region of the channel CH of the thin-film transistor 100A is different from the channel CH of the thin-film transistor 100, as shown in FIG.

[0124] Although the thin-film transistor 100 is a bottom-gate thin-film transistor, a top-gate thin-film transistor may also be applied to the display device 1000.

[0125] FIG. 23 is a diagram showing a top-gate type thin film transistor in one embodiment. In the bottom-gate type thin film transistor 100, the gate electrode 120 is disposed between the first support substrate 10 and the semiconductor layer 150. On the other hand, as shown in FIG. 23, in the top-gate type thin film transistor 100B, the semiconductor layer 150B is disposed between the first support substrate 10 and the gate electrode 120B. Therefore, the surface with which the photoresist PR comes into contact when processing the ITZO film is the back channel side surface 150b in the case of the bottom-gate type thin film transistor 100, but the surface is the gate side surface 150Bg in the case of the top-gate type thin film transistor 100B. Therefore, in the top-gate type thin film transistor 100B, after the semiconductor layer 150B is formed, a process (heating process or UV ozone process) for removing carbon residual components is performed before the gate insulating layer 130 is formed. Note that no carbon residual components exist on the back channel side surface 150Bb, and even if a small amount of carbon residual components exist, they are removed when the ITZO film is formed as described above.

[0126] In the top-gate type thin-film transistor 100B, a portion of the semiconductor layer 150B directly below the gate electrode 120B corresponds to the channel CH. A source region 151B is formed on the source electrode 171B side of the channel CH, and a drain region 152B is formed on the drain electrode 172B side of the channel CH. For example, the source region 151B and the drain region 152B are regions whose resistance is reduced by supplying hydrogen or the like to the semiconductor layer 150B in a self-aligned manner using the gate electrode 120B as a mask.

[0127] As described above, whatever structure a thin-film transistor has, it is sufficient to perform a process (heating process or UV ozone process) for removing carbon residual components while the channel CH is exposed. Then, after the process for removing carbon residual components and before a layer containing carbon atoms (e.g., a photoresist, an organic insulating layer, etc.) is formed on the channel CH, an insulating layer (e.g., an inorganic insulating material such as silicon oxide) for protecting the channel CH from carbon atoms is formed.

[0128] A thin film transistor using a semiconductor material other than ITZO may be used in combination with the thin film transistor 100. The semiconductor material other than ITZO may be, for example, another metal oxide semiconductor (e.g., IGZO) or a semiconductor using silicon such as amorphous silicon or polysilicon.

[0129] [Application to electronic devices] The display device 1000 described above may be applied as a display for various electronic devices such as a smartphone, a laptop computer, a television, etc. The display device 1000 is not limited to an organic EL display including a light-emitting layer whose light emission is controlled by a pixel circuit. For example, the display device 1000 may be a micro LED display in which the light-emitting layer is an LED (Light Emitting Diode), or a display including an optical element whose optical characteristics are controlled by a pixel circuit, for example, a liquid crystal display including a liquid crystal as an optical element.

[0130] Fig. 24 is a diagram showing an electronic device in one embodiment. The electronic device 2000 shown in Fig. 24 is a smartphone, and includes a display device 1000, a control device 1600, and a storage device 1700 housed in a housing 1500. The storage device 1700 is, for example, a non-volatile memory. The control device 1600 includes a CPU (Central Processing Unit) and the like, and controls the display device 1000 by executing a program stored in the storage device 1700, thereby controlling the image displayed on the display device 1000.

[0131] The above-mentioned thin film transistor may be applied not only to elements constituting the display device 1000, but also to elements constituting the control device 1600 and the storage device 1700. That is, the electronic device using the thin film transistor 100 includes a configuration not including the display device 1000. Examples of the electronic device include electronic devices other than the display device, such as a storage device, a logic circuit and its peripheral circuit device, a wireless signal processing device, an input device, an imaging device, and a neuromorphic computing device. In such electronic devices, a thin film transistor using a semiconductor material other than ITZO may be further used in combination with the thin film transistor using ITZO.

[0132] [ZSO passivation layer] In the thin film transistor 100, the back channel side surface 150b of the channel CH may be covered with a passivation layer formed of a predetermined film to form an insulating layer covering the channel. The passivation layer is preferably an oxide thin film that can be formed by DC sputtering under an oxygen atmosphere, and is formed of, for example, an amorphous ZSO (ZnSiO) film. From the viewpoint of adhesion, the passivation layer preferably contains at least a part of amorphous, but may also contain a crystalline structure such as microcrystals. The thickness of the passivation layer may be various, but is, for example, 2 nm or more and 200 nm or less, and preferably 3 nm or more and 50 nm or less. In this example, the thickness of the passivation layer is 5 nm. The passivation layer may also be applied to the top-gate type thin film transistor 100B shown in FIG. 23. In this case, as shown in Fig. 36, a passivation layer 160F may be formed between the base insulating layer 110 and the back channel side surface 150Bb, or as shown in Fig. 37, a passivation layer 160G may be formed between the gate insulating layer 130 and the gate side surface 150Bg. It is preferable that the passivation layer 160F and the passivation layer 160G are present at least in the channel CH region. In other words, the passivation layer 160F and the passivation layer 160G do not need to be present in regions other than the channel CH, and only need to cover at least the channel CH.

[0133] ZSO film is a composite of ZnO and SiO 2 It is formed by DC sputtering in an oxygen atmosphere using a target containing SiO. The ZSO film as a passivation layer has insulating properties. 2 As the ratio of ZnO to Zn increases, the state changes from an insulating state to a conductive state. The ZSO target is formed with a composition ratio that has conductivity, so it can be formed by DC sputtering. In order to suppress the surface of the semiconductor layer 150 from being reduced, it is preferable that the ZSO target contains Zn as a metal oxide rather than as a metal. On the other hand, by controlling the sputtering conditions, a passivation layer of the ZSO film having insulating properties is formed. The ZSO film may be formed by a PVD method other than DC sputtering, or may be formed by a CVD method or an ALD method as long as it can reduce the carbon residue component that is finally generated on the surface of the channel CH.

[0134] This passivation layer is not limited to a ZSO film, which is a metal oxide layer containing Zn and silicon (Si), but may be, for example, a ZSTO film, which is a metal oxide layer containing Zn, Si, and Sn. In this case, ZnO, SnO 2 Targets containing ZnO, SiO 2 , SnO 2 It may be formed by DC sputtering in an oxygen atmosphere using a target containing

[0135] In the case of a ZSO film, the Zn / (Zn+Si) ratio is preferably in the range of 0.30 to 0.95 in molar ratio, and more preferably in the range of 0.40 to 0.85 in molar ratio. In the case of a ZSTO film, the Sn / (Zn+Sn+Si) ratio is preferably in the range of 0.15 to 0.95 in molar ratio. Also, the Si / (Zn+Sn+Si) ratio is preferably in the range of 0.07 to 0.30 in molar ratio. These molar ratios are values ​​for the film.

[0136] The passivation layer may further contain at least one of titanium (Ti), gallium (Ga), niobium (Nb), aluminum (Al) and In in addition to the ZSO film or ZSTO film. In this case, it is preferable that these elements are contained in the target as metal oxides.

[0137] The electron affinity of the passivation layer is preferably smaller than that of the semiconductor layer 150 (ITZO film in this example). Furthermore, it is preferable that the electron affinity of the passivation layer is in the range of 2.0 eV to 4.0 eV, and the ionization potential of the passivation layer is in the range of 6.0 eV to 8.5 eV. More preferably, the electron affinity is 2.2 eV to 3.5 eV, and even more preferably, 2.5 eV to 3.0 eV. More preferably, the ionization potential is 6.0 eV to 7.5 eV, and even more preferably, 6.0 eV to 7.0 eV. By providing a passivation layer with an electron affinity smaller than that of the semiconductor layer, it has the effect of preventing the injection of electrons from the outside into the semiconductor layer. Furthermore, by providing a passivation layer with an ionization potential larger than that of the semiconductor layer, it has the effect of preventing the injection of holes from the outside into the semiconductor layer. These can suppress the threshold shift caused by NBS or PBS.

[0138] The electron affinity of the passivation layer can be adjusted by changing the composition ratio of the target. For example, in the case of a ZSO film, the ratio of ZnO and SiO in the target is 2 A desired electron affinity can be realized by adjusting the ratio of the above. The electron affinity and ionization potential can be determined by quantum chemical theoretical calculations (electron affinity=energy difference between neutral molecule and anion, ionization potential=energy difference between cation and neutral molecule) or by known measurement methods such as photoelectron spectroscopy. Specifically, the ionization potential is evaluated using ultraviolet photoelectron spectroscopy, the band gap is evaluated using a spectrophotometer, and the electron affinity is calculated from the difference between the ionization potential and the band gap.

[0139] 25 to 27 are diagrams showing a thin film transistor using a passivation layer in one embodiment. Each of FIGS. 25 to 27 shows an example in which a passivation layer of a ZSO film is applied to a thin film transistor 100. In the thin film transistor 100C shown in FIG. 25, a passivation layer 160 is formed at a position corresponding to the above-mentioned etch stop layer 150e. That is, after the semiconductor layer 150 is formed, a ZSO film is formed, and the ZSO film is formed into a desired pattern, thereby forming the passivation layer 160 on the back channel side surface 150b. A part of the passivation layer 160 is covered with a source electrode 171 and a drain electrode 172.

[0140] 26, a ZSO film is formed after the source electrode 171 and the drain electrode 172 are formed, and the ZSO film is formed into a desired pattern to form a passivation layer 160D on the exposed portion of the back channel side surface 150b. Similar to the passivation layer 160 in the thin film transistor 100C, the passivation layer 160D covers the exposed portion of the back channel side surface 150b. However, unlike the passivation layer 160 in the thin film transistor 100C, the passivation layer 160D also covers a portion of the source electrode 171 and the drain electrode 172.

[0141] The thin-film transistor 100E shown in Fig. 27 is an example in which the above-mentioned etch stop layer 150eE is formed on the passivation layer 160 in the thin-film transistor 100C shown in Fig. 25. The passivation layer 160 and the etch stop layer 150eE may be formed in the same pattern. By adjusting the thickness of the passivation layer 160, the passivation layer 160 may function as the etch stop layer 150e in the thin-film transistor 100C shown in Fig. 25.

[0142] Thus, the inventors have found that the passivation layer using the ZSO film suppresses the threshold shift caused by the application of a negative gate voltage under 60°C or light irradiation conditions. This passivation layer is believed to reduce the surface state of the ITZO and suppress the transfer of charges between the ITZO and the outside. The results of suppressing the threshold shift will be described below. The thin film transistor for measuring the threshold shift corresponds to the thin film transistor for measuring the threshold shift shown in FIG. 9. Therefore, the thin film transistor on which the passivation layer using the ZSO film is formed is formed on the back channel side surface 155b of the thin film transistor shown in FIG. 9. Here, the thin film transistor shown in FIG. 9 is formed, and after the heat treatment at 400°C is performed, a passivation layer using the ZSO film is further formed.

[0143] Fig. 28 is a diagram showing the measurement results of the threshold shift due to temperature change. The Id-Vg characteristics shown in Fig. 28 show the drain current when the voltage of the gate electrode 172 is changed while controlling the voltage of the drain electrode relative to the source electrode to be "0.1 V". Fig. 28 shows the Id-Vg characteristics at room temperature (RT) and 60°C in the case where a passivation layer of ZSO film is not used (w / o a-ZSO) and the case where a passivation layer of ZSO film is used (wa-ZSO).

[0144] When the ZSO film passivation layer is not used, the threshold at 60°C is shifted more negatively than the threshold at room temperature. On the other hand, when the ZSO film passivation layer is used, the threshold barely shifts at all, either at room temperature or at 60°C. In this way, the ZSO film passivation layer suppresses the temperature dependence of the threshold.

[0145] Fig. 29 is a diagram showing the measurement results of the threshold shift by NBIS. Fig. 29 shows the measurement results of NBIS corresponding to Fig. 19 described above, and the results when the ZSO film passivation layer is not used correspond to the 400°C heat treatment in Fig. 19. On the other hand, when the ZSO film passivation layer is used, the threshold hardly shifts. In this way, the negative shift of the threshold caused by NBIS is further suppressed by the ZSO film passivation layer.

[0146] FIG. 30 shows the results of measuring the electron concentration before and after light irradiation. FIG. 30 shows the results of measuring the electron concentration of the ITZO film by Hall measurement for a sample in which an ITZO film is formed on a glass substrate but no ZSO film is formed (w / o a-ZSO) and a sample in which a 5 nm ZSO film is further formed on the ITZO film (wa-ZSO). The electron concentration was measured before light irradiation (corresponding to "AS" on the time axis) and after light irradiation, and the time change after light irradiation ("0" on the time axis corresponds to immediately after irradiation) was also measured. Between before and after light irradiation, the ITZO film was irradiated with light obtained by a solar simulator from the opposite side to the glass substrate (the surface where the ITZO film was exposed or the surface where the ZSO film was exposed). The light irradiation time was 10 minutes.

[0147] As shown in FIG. 30, in the sample without the ZSO film, the electron concentration of the ITZO film was reduced by 2×10 17 cm -3 From 2 × 10 18 cm -3 On the other hand, in the sample with the ZSO film, the electron concentration of the ITZO film increased to 1×10 17 cm -3 The concentration of NBIS increases slightly from 0.2 to 1.0 μm, but returns to almost the original concentration after 6 hours. This phenomenon is presumably one of the reasons why the negative shift of the threshold voltage due to NBIS hardly occurs when the ZSO film passivation layer is used.

[0148] FIG. 31 shows the results of measuring the absorption coefficient. FIG. 31 shows the results of measuring the absorption coefficient of the same sample as in FIG. 30 by UV-Vis-NIR spectroscopy. As shown in FIG. 31, the absorption coefficient is almost the same regardless of whether the ZSO film is present or not. This measurement result is due to the fact that the ZSO film is very thin (5 nm) and has a wide band gap. Therefore, the results shown in FIG. 30 indicate that the main reason is not that the light irradiated to the ITZO film is blocked by the ZSO film.

[0149] Forming a ZSO film by DC sputtering has the effect of suppressing impurities on the surface of the ITZO film and on the interface between the ZSO film and the ITZO film, and the effect of suppressing damage caused by each process. As a result, it is presumed that the characteristic improvement effect obtained by the passivation layer of the ZSO film can be obtained. DC sputtering in an oxygen atmosphere also has the effect of reducing the carbon residue component mentioned above. Therefore, it is expected that the heat treatment and UV ozone treatment for reducing the carbon residue component can be omitted, or that the heat treatment and UV ozone treatment can be replaced with simpler treatments (lower temperature, lower illumination, or shorter treatment time).

[0150] Figure 32 shows the measurement results and model formula of the change over time of the threshold shift due to NBS (Negative Bias Stress). For NBS, the condition was used in which the voltage of the gate electrode relative to the source electrode and drain electrode was controlled and maintained at "Vth-20V". The time for which the NBS was applied was a maximum of 3600 seconds for the sample (unstable sample) that did not undergo the above-mentioned treatment to reduce carbon residues and did not use a passivation layer of ZSO film (lower figure), and a maximum of 86400 seconds for the sample (stable sample) that underwent treatment to reduce carbon residues and further had a passivation layer of ZSO film formed (upper figure).

[0151] Figure 32 shows each parameter when the threshold shift due to NBS is fitted using a stretched exponential function. Vth(0) is the initial threshold voltage. τ is the time constant, and β is the energy barrier parameter. τ and β vary greatly depending on whether or not the carbon residue components have been removed and whether or not a passivation layer has been formed on the ZSO film. Since β reflects the distribution of the energy barrier, it is thought that β varies when the charge transfer mechanism differs. It is also known that β varies greatly depending on the type of gas introduced in gas sensors using ZnO. In 2 O 3 It has also been shown that β may differ depending on the Fermi level in the TFT of . Furthermore, as shown in Figure 32, it was confirmed that ΔVth(t→∞) differs by two orders of magnitude between the two samples.

[0152] [ITZO with different compositions] In the embodiment described above, the composition ratio of the target In:Sn:Zn is 20:40:40 (at%), but it is not limited to this composition ratio. The measurement results of the threshold shift by NBTS, PBTS, and NBIS for a sample with this composition ratio of 40:40:20 (at%) will be described.

[0153] 33 and 34 are diagrams showing the measurement results of threshold shifts caused by NBTS and PBTS. FIG. 33 shows the measurement results when the composition ratio of the target In:Sn:Zn is 20:40:40 (at%). FIG. 34 shows the measurement results when the composition ratio of the target In:Sn:Zn is 40:40:20 (at%). The samples used for the measurements in FIGS. 33 and 34 were all treated to reduce carbon residues, and a passivation layer of the ZSO film was formed. There was almost no shift in threshold value for any of the composition ratios of the targets. In addition, the measurement results shown in FIG. 33 are roughly similar to the measurement results (FIG. 21) when the treatment to reduce carbon residues was performed and a passivation layer of the ZSO film was not formed. In other words, no adverse effects on NBTS and PBTS due to the presence of the ZSO film were confirmed.

[0154] Fig. 35 shows the measurement results of the threshold shift by NBIS. In Fig. 35, the measurement results by NBIS are compared for two ITZO samples with different target composition ratios. The sample (In 0.4 Sn 0.4 Zinc 0.2 O x ) has a field effect mobility of 70 cm 2 The target composition ratio In:Sn:Zn is 20:40:40 (at%). 0.2 Sn 0.4 Zinc 0.4 O x ) has a field effect mobility of 50 cm 2 / Vs.

[0155] The composition ratio of the target is In 0.4 Sn 0.4 Zinc 0.2 O x In the case of 0.2 Sn 0.4 Zinc 0.4 O xIn this case, the negative shift of the threshold is slightly larger than that in the case of 0.1V, because the mobility is higher, but the difference is not significant. In this way, even if the ITZO has a composition ratio other than the specific one, it is possible to obtain the effect of suppressing the threshold shift under various voltage stresses by using a similar method. 2 It has been confirmed that ITZO with a threshold voltage of 100 V or less has a sufficient effect of suppressing threshold shift due to voltage stress.

[0156] The threshold shift amount having a sufficient suppression effect is, for example, preferably equal to or less than 3 V, and more preferably equal to or less than 1 V. If such a suppression effect can be obtained, ITZO having a higher mobility can be used for a thin film transistor.

[0157] [Thin-film transistors using metal oxide semiconductors other than ITZO] The fact that the threshold shift due to voltage stress confirmed in the thin film transistor using the ITZO film for the semiconductor layer described above can be reduced by a process for reducing the carbon residue has also been confirmed for ITGO (In-Sn-Ga oxide) and IZO (In-Zn oxide) in addition to ITZO. Therefore, the above-mentioned knowledge regarding the effect of reducing the carbon residue can be generally applied to thin film transistors using a metal oxide semiconductor containing In as a channel. It can also be said that the knowledge regarding the passivation layer can be generally applied to thin film transistors using a metal oxide semiconductor containing In as a channel, if a passivation layer having a smaller electron affinity and a larger ionization potential than the semiconductor layer is used. In this way, it can be particularly preferably applied to thin film transistors using a metal oxide semiconductor having a high field effect mobility. A high field effect mobility is preferably 20 cm 2 / Vs or more, particularly preferably 40 cm 2 / Vs or more.

[0158] We will explain the effect of UV ozone treatment on the threshold shift caused by NBS when an ITGO film or an IZO film is used as the semiconductor layer.

[0159] Fig. 38 and Fig. 39 are diagrams showing the measurement results of threshold shift by NBS with and without UV ozone treatment. Fig. 38 shows the measurement results when an ITGO film is used for the semiconductor layer (when the target composition ratio In:Sn:Ga is 40:20:40 (at%)). Fig. 39 shows the measurement results when an IZO film is used for the semiconductor layer (when the target composition ratio In:Zn is 50:50 (at%)).

[0160] In the thin film transistor for threshold measurement, the sample structure and measurement conditions were the same as those for obtaining the measurement results shown in Fig. 21. As shown in Fig. 38 and Fig. 39, even when an ITGO film or an IZO film was used for the semiconductor layer, the amount of threshold shift due to NBS was kept sufficiently small.

[0161] The above-described thin film transistor may have the following characteristics.

[0162] A thin film transistor formed on a substrate, a channel formed by at least a portion of a metal oxide semiconductor layer containing at least indium (In), tin (Sn) and zinc (Zn); A gate electrode; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; an insulating layer covering the channel; Including, The length of the channel is 100 μm or less; A thin film transistor in which the threshold shift amount in each of NBTS, PBTS and NBIS is 3V or less. NBTS: Dark state, temperature "60°C", voltage of gate electrode relative to source electrode and drain electrode "Vth-20V", stress application time "3600 seconds" PBTS: Dark state, temperature "60°C", voltage of gate electrode relative to source electrode and drain electrode "Vth+20V", stress application time "3600 seconds" NBIS: Light irradiation conditions: "15000 Lux", voltage of gate electrode relative to source electrode and drain electrode: "Vth-20V", stress application time: "3600 seconds" Threshold voltage measurement: Voltage of drain electrode relative to source electrode "0.1V"

[0163] The channel may have a ratio of Sn to the total of In, Sn, and Zn of 30 (at%) or more.The channel may have a ratio of Sn to the total of In, Sn, and Zn of 40 (at%) or more.

[0164] The channel has a field effect mobility of 40 cm 2 / Vs or more. The channel may be 60 cm 2 / Vs or more.

[0165] The insulating layer may be a metal oxide layer containing zinc (Zn) and silicon (Si).

[0166] The length of the channel may be 50 μm or less.The length of the channel may be 20 μm or less.

[0167] The amount of shift in the threshold voltage in the NBTS may be 1V or less.

[0168] The threshold shift in the PBTS may be 1V or less.

[0169] The threshold shift amount in the NBIS may be 1V or less. [Explanation of symbols]

[0170] 1...first substrate, 2...second substrate, 10...first support substrate, 100, 100A, 100B, 100C, 100D, 100E...thin film transistor, 110...underlying insulating layer, 120, 120B, 125...gate electrode, 130, 135...gate insulating layer, 150, 150B, 155...semiconductor layer, 150a...upper surface, 150b, 150Bb, 155b...back channel side surface, 150d...drain surface, 150e, 150eE...etch stop layer, 151B...source region, 152B...drain region region, 155f...ITZO film, 150g, 150Bg, 155g...gate side surface, 150s...source surface, 160, 160D...passivation layer, 171, 171B, 176...source electrode, 172, 172B, 177...drain electrode, 175f...gold film, 200...interlayer insulating layer, 300...pixel electrode, 400...bank layer, 500...light-emitting layer, 600...counter electrode, 900...sealing layer, 1000...display device, 1500...casing, 1600...control device, 1700...storage device, 2000...electronic device

Claims

1. A thin film transistor formed on a substrate, The semiconductor layer is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In), and has a field effect mobility of 20 cm ２ / Vs or more; a gate electrode disposed between the substrate and the channel; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; Including, The average concentration of carbon atoms in the range from the surface of the channel to a depth of 5 nm is 1.5×10 ２１ cm －３ The following is a thin film transistor.

2. A thin film transistor formed on a substrate, A gate electrode; The semiconductor layer is disposed between the substrate and the gate electrode, and is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In). The field effect mobility is 20 cm ２ / Vs or more; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; Including, The average concentration of carbon atoms in the range from the surface of the channel to a depth of 5 nm is 1.5×10 ２１ cm －３ The following is a thin film transistor.

3. A thin film transistor formed on a substrate, The semiconductor layer is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In), and has a field effect mobility of 20 cm ２ / Vs or more; a gate electrode disposed between the substrate and the channel; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; Including, A thin film transistor, wherein the maximum concentration of carbon atoms in a range from the surface of the channel to a depth of 5 nm is 19 at % or less.

4. A thin film transistor formed on a substrate, A gate electrode; The semiconductor layer is disposed between the substrate and the gate electrode, and is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In). The field effect mobility is 20 cm ２ / Vs or more; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; Including, A thin film transistor, wherein the maximum concentration of carbon atoms in a range from the surface of the channel to a depth of 5 nm is 19 at % or less.

5. 5. The thin film transistor according to claim 1, wherein the surface of the metal oxide semiconductor layer connected to the source electrode and the surface of the metal oxide semiconductor layer connected to the drain electrode have a higher concentration of carbon atoms than a surface of the channel.

6. Further comprising a passivation layer having insulating properties and covering the channel; The thin film transistor according to claim 1 , wherein the electron affinity of the passivation layer is smaller than the electron affinity of the metal oxide semiconductor layer.

7. Further comprising a passivation layer having insulating properties and covering the channel; The thin film transistor of claim 1 , wherein the passivation layer is a metal oxide layer containing zinc (Zn) and silicon (Si).

8. The thin film transistor of claim 6 , wherein the metal oxide semiconductor layer further comprises tin (Sn) and zinc (Zn).

9. A thin film transistor formed on a substrate, The semiconductor layer is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In), and has a field effect mobility of 20 cm ２ / Vs or more; A gate electrode; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; a passivation layer having insulating properties and covering the channel; Including, the passivation layer is a metal oxide layer containing zinc (Zn) and silicon (Si); A thin film transistor, wherein the electron affinity of the passivation layer is less than the electron affinity of the metal oxide semiconductor layer.

10. The gate electrode is disposed between the substrate and the channel; The thin film transistor of claim 9 , wherein the passivation layer covers a back channel side surface of the channel.

11. The thin film transistor of claim 9, wherein the metal oxide semiconductor layer is a metal oxide except when it contains both zinc (Zn) and silicon (Si).

12. The thin film transistor of claim 9, wherein the metal oxide semiconductor layer further contains tin (Sn) and zinc (Zn).

13. A thin film transistor formed on a substrate, comprising: a channel formed at least in part of a metal oxide semiconductor layer containing at least indium (In) and having a field effect mobility of 20 cm 2 / Vs or more; A gate electrode; a gate insulating layer disposed between the channel and the gate electrode; a source electrode and a drain electrode connected to the metal oxide semiconductor layer; a passivation layer having insulating properties and covering the channel; Including, The voltage of the gate electrode relative to the source electrode and the drain electrode is controlled to be Vth-20V, the temperature is set to 60°C, and the device is maintained in a dark state for 3600 seconds. When this device is maintained in a dark state for 3600 seconds, the shift amount of the threshold voltage is 0.5V or less. A thin film transistor, wherein the electron affinity of the passivation layer is less than the electron affinity of the metal oxide semiconductor layer.

14. 14. The thin film transistor according to claim 9 or 13, wherein the passivation layer has an electron affinity in the range of 2.0 eV to 4.0 eV, and an ionization potential in the range of 6.0 eV to 8.5 eV.

15. The thin film transistor according to claim 1 , wherein the metal oxide semiconductor layer further contains tin (Sn) and zinc (Zn).

16. The thin film transistor of claim 1 , wherein the source electrode and the drain electrode comprise a conductive material having oxidation resistance.

17. 10. The thin film transistor according to claim 1, wherein the voltage of the gate electrode relative to the source electrode and the drain electrode is controlled to be Vth-20V, the temperature is set to 60°C, and the thin film transistor is maintained in a dark state for 3600 seconds, and the amount of shift of the threshold voltage is 0.5V or less.

18. A plurality of pixel circuits are included. A display device, wherein each of the plurality of pixel circuits includes a thin film transistor according to claim 1 .

19. The semiconductor layer is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In), and has a field effect mobility of 20 cm ２ 1. A method for manufacturing a thin film transistor on a substrate, the thin film transistor including: a channel having a gate insulating layer between the channel and the gate electrode, the gate insulating layer having a gate potential greater than or equal to Vs; and a source electrode and a drain electrode connected to the metal oxide semiconductor layer, the method comprising the steps of: With the channel exposed, the channel is heated to 350° C. or higher in an oxygen-containing atmosphere to reduce the average concentration of carbon atoms in the area from the surface of the exposed portion of the channel to a depth of 5 nm to 1.5×10 ２１ cm －３ The following steps: forming an insulating layer overlying the channel after the heating and before the layer comprising carbon atoms contacts the exposed portion of the channel; Including, A method for manufacturing a thin film transistor.

20. The semiconductor layer is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In), and has a field effect mobility of 20 cm ２ 1. A method for manufacturing a thin film transistor on a substrate, the thin film transistor including: a channel having a gate insulating layer between the channel and the gate electrode, the gate insulating layer having a gate potential greater than or equal to Vs; and a source electrode and a drain electrode connected to the metal oxide semiconductor layer, the method comprising the steps of: With the channel exposed, ultraviolet light was irradiated in an oxygen-containing atmosphere to reduce the average concentration of carbon atoms in the area from the surface of the exposed part of the channel to a depth of 5 nm to 1.5×10 ２１ cm －３ The following steps: forming an insulating layer overlying the channel after the irradiation and before the layer containing carbon atoms contacts the exposed portion of the channel; Including, A method for manufacturing a thin film transistor.

21. The semiconductor layer is formed of at least a portion of a metal oxide semiconductor layer containing at least indium (In), and has a field effect mobility of 20 cm ２ 1. A method for manufacturing a thin film transistor on a substrate, the thin film transistor including: a channel having a gate insulating layer between the channel and the gate electrode, the gate insulating layer having a gate potential greater than or equal to Vs; and a source electrode and a drain electrode connected to the metal oxide semiconductor layer, the method comprising the steps of: With the channel exposed, DC sputtering was performed in an oxygen atmosphere to reduce the average concentration of carbon atoms in the area from the surface of the exposed part of the channel to a depth of 5 nm to 1.5×10 ２１ cm －３ forming an insulating layer overlying the channel, A method for manufacturing a thin film transistor.

22. 22. The method for manufacturing a thin film transistor according to claim 19, wherein the metal oxide semiconductor layer further contains tin (Sn) and zinc (Zn).

23. 22. The method for manufacturing a thin film transistor according to claim 19, wherein the insulating layer is a metal oxide layer containing zinc (Zn) and silicon (Si).

24. 22. The method for producing a thin film transistor according to claim 21, wherein a target used in the DC sputtering is a metal oxide having electrical conductivity.

25. the gate electrode is disposed between the substrate and the channel; 22. The method for producing a thin film transistor according to claim 19, further comprising the step of: eliminating at least a part of carbon atoms present on a surface of the channel after the source electrode and the drain electrode are formed.

26. the channel is disposed between the substrate and the gate electrode; the insulating layer that protects against carbon atoms is the gate insulating layer; 22. The method for producing a thin film transistor according to claim 19, further comprising the step of: eliminating at least a part of carbon atoms present on a surface of the channel before the source electrode and the drain electrode are formed.

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