Display panel and display terminal

Abstract

According to an embodiment of the present application, a display panel and a display terminal are disclosed, the display panel including a base, a first metal layer provided on the base, and a second metal layer provided on the first metal layer, the first metal layer including a plurality of data lines extending along a first direction and sources of thin film transistors electrically connected to the data lines, and the second metal layer including drains of thin film transistors located between two adjacent data lines.

Description

[Technical field]

[0001] The present application relates to the display field, in particular to a display panel and a display terminal. [Background technology]

[0002] Various types of display panels are widely used in display screens for mobile phones, computers, AR (Augmented Reality), VR (Virtual Reality), etc. Conventional 3D displays mainly achieve the purpose of making the contents seen by the left and right eyes different based on a method sacrificing resolution, which requires higher resolution.

[0003] However, the current pixel layout space and process capability limit the improvement of the resolution. In particular, the resolution of a liquid crystal display panel is significantly limited, making it difficult to improve the resolution of the current display panel. Summary of the Invention [Problem to be solved by the invention]

[0004] According to an embodiment of the present application, a display panel and a display terminal are provided to solve the problem that the resolution of current display panels is difficult to improve. [Means for solving the problem]

[0005] According to an embodiment of the present application, a base and The base Above a first metal layer provided on the The first metal layer Above and a second metal layer provided on the display panel, A display panel is provided in which the first metal layer includes a plurality of data lines extending along a first direction and sources of thin film transistors electrically connected to the data lines, and the second metal layer includes drains of the thin film transistors located between two adjacent data lines.

[0006] Optionally, in some embodiments of the present application, a third metal layer disposed between the base and the first metal layer; The above 3 a semiconductor layer disposed between the metal layer and the base, The third metal layer includes a scan line extending along a second direction, the semiconductor layer includes a plurality of active members of a plurality of the thin film transistors, the active members including a source end and a drain end, and an active connection member connected between the source end and the drain end, the first direction being different from the second direction, the source end and the drain end are located on both sides of the corresponding scan line, and the active connecting members extend along at least a third direction different from the first direction and the second direction; The source is electrically connected to the source terminal, and the drain is electrically connected to the drain terminal.

[0007] Optionally, in some embodiments herein, the thin film transistor is a single gate structure.

[0008] Optionally, in some embodiments herein, the angle between the third direction and the first direction is greater than or equal to 5 degrees and less than or equal to 15 degrees.

[0009] Optionally, in some embodiments herein, the angle between the third direction and the first direction is 7 degrees.

[0010] Optionally, in some embodiments of the present application, the display panel includes a plurality of sub-pixels, each of which includes a pixel electrode, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel respectively located on both sides of the scan line, and a gap is provided between the pixel electrode of the first sub-pixel and the pixel electrode of the second sub-pixel, the gap corresponding to the scan line.

[0011] Optionally, in some embodiments of the present application, a gate insulating layer disposed between the semiconductor layer and the third metal layer; a first insulating layer provided between the third metal layer and the first metal layer; A second insulating layer provided between the first metal layer and the second metal layer, The display panel further includes a first through hole penetrating the gate insulating layer and the first insulating layer, and a second through hole penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, wherein the source is electrically connected to the source terminal through the first through hole, and the drain is electrically connected to the drain terminal through the second through hole.

[0012] Optionally, in some embodiments of the present application, the first metal layer Above a first electrode layer provided on the The first electrode layer Above a fourth insulating layer provided on the The fourth insulating layer Above and a second electrode layer provided on the One of the first electrode layer and the second electrode layer includes a pixel electrode of the sub-pixel.

[0013] Optionally, in some embodiments herein, the first electrode layer comprises a pixel electrode of the sub-pixel directly connected to the drain.

[0014] Optionally, in some embodiments of the present application, the method further includes a third insulating layer disposed between the second insulating layer and the second metal layer, the second insulating layer being an organic material and the third insulating layer being an inorganic material, and the second through hole further penetrating the third insulating layer.

[0015] Optionally, in some embodiments of the present application, the pixel electrode further includes a third electrode layer disposed between the second insulating layer and the third insulating layer, the third electrode layer including a plurality of storage electrodes at least partially overlapping the pixel electrodes.

[0016] Optionally, in some embodiments of the present application, the second metal layer has a thickness of 3500 Angstroms. (350 nm) That's all.

[0017] Optionally, in some embodiments of the present application, a first blind hole formed by a recess in the first electrode layer, the fourth insulating layer, and the second electrode layer at a portion corresponding to the second through hole; and a fifth insulating layer that is an organic material filled in at least the first blind hole.

[0018] Optionally, in some embodiments of the present application, the color film substrate further includes a substrate and a support pillar provided on the substrate, the support pillar being located between the substrate and the base, and an orthogonal projection of the support pillar on the base and an orthogonal projection of the fifth insulating layer on the base do not overlap.

[0019] Therefore, according to the embodiment of the present application, Including display panels with the above configurations A display terminal is further provided. Effect of the Invention

[0025] In an embodiment of the present application, a display panel and a display terminal are provided, the display panel including a base, a first metal layer disposed on the base, and a second metal layer disposed on the first metal layer, the first metal layer including a plurality of data lines extending along a first direction and a source of a thin film transistor electrically connected to the data line, and the second metal layer including a drain of the thin film transistor located between two adjacent data lines. In the embodiment of the present application, the data lines, the source and the drain are disposed on the first metal layer and the second metal layer, respectively, the drain is disposed between two adjacent data lines, the drain and the data line are disposed on different layers, and there is no problem of limitation in the etching process compared with the conventional technology in which the drain and the data line are disposed on the same layer, so that the distance between the drain and the data line is reduced and the parasitic capacitance between the drain and the data line is reduced, the two adjacent data lines can be disposed closer to each other, and the size of the subpixel can be reduced, thereby improving the resolution of the display panel. [Brief description of the drawings]

[0026] In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly describes the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without creative efforts.

[0027] [Figure 1] 1 is a first schematic cross-sectional view of a display panel according to an embodiment of the present application; [Diagram 2] 1 is a first schematic plan view of a partial structure of a display panel according to an embodiment of the present application. [Diagram 3] FIG. 2 is a second schematic plan view of a partial structure of a display panel according to an embodiment of the present application. [Figure 4] 2 is a second partial cross-sectional schematic diagram of a display panel according to an embodiment of the present application. FIG. [Diagram 5] FIG. 11 is a third schematic partial cross-sectional view of a display panel according to an embodiment of the present application. [Figure 6] 11 is a fourth schematic partial cross-sectional view of a display panel according to an embodiment of the present application. FIG. [Figure 7] FIG. 1 is a schematic diagram of a display terminal according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, the technical means in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, and are not all embodiments. Based on the embodiments of the present application, all other embodiments that can be obtained by a person skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific embodiments described in this specification are only intended to explain and interpret the present application, and do not limit the present application. In this application, unless otherwise stated, the directional terms used, such as "up" and "down", usually refer to the up and down of the device in actual use or operation, specifically the drawing direction in the drawings. In addition, "inside" and "outside" refer to the contour of the device.

[0029] According to an embodiment of the present application, there is provided a display panel including a base, a first metal layer provided on the base, and a second metal layer provided on the first metal layer, wherein the first metal layer includes a plurality of data lines extending along a first direction and sources of thin film transistors electrically connected to the data lines, and the second metal layer includes drains of thin film transistors located between two adjacent data lines.

[0030] According to an embodiment of the present application, a display terminal including the above-mentioned display panel is further provided. Each of the embodiments will be described in detail below. Note that the order of the following description of the embodiments does not limit the preferred order of the embodiments. Example 1

[0031] 1, 2 and 3, Fig. 1 is a first partial cross-sectional schematic diagram of a display panel according to an embodiment of the present application, Fig. 2 is a first plan view schematic diagram of a partial structure of a display panel according to an embodiment of the present application, and Fig. 3 is a second plan view schematic diagram of a partial structure of a display panel according to an embodiment of the present application. Figs. 2 and 3 show plan views of the same portion of the display panel, and Figs. 2 and 3 selectively show different layer structures in order to more clearly explain the structure of the display panel 100.

[0032] According to an embodiment of the present application, there is provided a display panel 100 including a base 11, a first metal layer 18 provided on the base 11, and a second metal layer 20 provided on the first metal layer 18, where the first metal layer 18 includes a plurality of data lines 182 extending along a first direction X and sources 181 of thin film transistors 101 electrically connected to the data lines 182, and the second metal layer 20 includes drains 201 of the thin film transistors 101 located between two adjacent data lines 182.

[0033] Specifically, the display panel 100 includes a base 11, a first metal layer 18 provided on the base 11, and a second metal layer 20 provided on the first metal layer 18, and a corresponding insulating layer is further provided between the first metal layer 18 and the second metal layer 20, which will be described in detail in the examples described below.

[0034] Specifically, the base 11 may be a material such as glass, but is not limited thereto.

[0035] Specifically, the first metal layer 18 includes a plurality of data lines 182 extending along the first direction X, and a source 181 of the thin film transistor 101 electrically connected to the data line 182. In FIG. 2, the source 181 is a part of the data line 182, but is not limited thereto. For example, the source 181 is a protruding part of the data line 182.

[0036] Specifically, the source 181 is electrically connected to the data line 182, and the second metal layer 20 includes a drain 201 of the thin film transistor 101 located between two adjacent data lines 182. The drain 201 and the source 181 are metal layers of different layers.

[0037] Specifically, in this embodiment, the data line 182, the source 181 and the drain 201 are located in the first metal layer 18 and the second metal layer 20, respectively, the drain 201 is located between two adjacent data lines 182, and the drain 201 and the data line 182 are located in different layers. Compared with the prior art in which the drain 201 and the data line 182 are located in the same layer, there is no problem of restrictions on the etching process (in the prior art, the drain 201 and the data line 182 are located in the same metal layer, and a large distance needs to be maintained between the drain 201 and the data line 182 to avoid short circuits caused by etching residues and to avoid excessively large parasitic capacitance), so that the distance between the drain 201 and the data line 182 is reduced and the parasitic capacitance between the drain 201 and the data line 182 is reduced, so that the two adjacent data lines 182 can be arranged closer to each other, and the size of the sub-pixel can be reduced, thereby improving the resolution of the display panel 100. Example 2

[0038] This embodiment is the same as or similar to the first embodiment, but differs from the first embodiment in that it further limits the characteristics of the display panel 100. Please refer to FIGS.

[0039] In some embodiments, the display panel 100 further includes a third metal layer 16 disposed between the base 11 and the first metal layer 18, and a semiconductor layer 14 disposed between the first metal layer 18 and the base 11, where the third metal layer 16 includes a scan line 162 extending along the second direction Y, and the semiconductor layer 14 includes a plurality of active members 141 of a plurality of thin film transistors 101, where the active member 141 includes a source end 1411 and a drain end 1412, and a source end 1411 and an active connecting member 1414 connected between the source end 1411 and the drain end 1412, where a first direction X is different from a second direction Y, the source end 1411 and the drain end 1412 are located on both sides of the corresponding scan line 162, the active connecting member 1414 extends at least along a third direction Z which is different from the first direction X and the second direction Y, the source 181 is electrically connected to the source end 1411, and the drain 201 is electrically connected to the drain end 1412.

[0040] Specifically, the first direction X, the second direction Y, and the third direction Z all refer to directions on the same plane, and all refer to directions parallel to the plane of the base 11.

[0041] Specifically, the material of the semiconductor layer 14 may be, but is not limited to, polycrystalline silicon. The active member 141 is a portion of the semiconductor layer 14 corresponding to one thin film transistor 101. The source end 1411 and the drain end 1412 are redoped regions in the active member 141, the source end 1411 being the source region of the active member 141, and the drain end 1412 being the drain region of the active member 141.

[0042] Specifically, the plurality of data lines 182 extend along a first direction X, and the plurality of scan lines 162 extend along a second direction Y, where the first direction X is different from the second direction Y, i.e., the first direction X intersects with the second direction Y. Preferably or optionally, the first direction X and the second direction Y are mutually perpendicular.

[0043] Specifically, the active member 141 includes a source end 1411 and a drain end 1412, and an active connecting member 1414 connected between the source end 1411 and the drain end 1412, where the source end 1411 and the drain end 1412 are located on both sides of the corresponding scan line 162, and the active connecting member 1414 extends at least along the third direction Z. In FIG. 2 and FIG. 3, the orthogonal projection of the active connecting member 1414 on the base 11 and the orthogonal projection of the scan line 162 on the base intersect so that the source end 1411 and the drain end 1412 are located on both sides of the corresponding scan line 162, and compared with the case where the source end 1411 and the drain end 1412 are located on one side of the corresponding scan line 162, the width of the sub-pixel in the first direction X and / or the second direction Y can be reduced, thereby improving the resolution of the display panel.

[0044] Specifically, the active connection member 1414 extends along a third direction Z that is different from at least the first direction X and the second direction Y. That is, the third direction Z is inclined with respect to the first direction X and is inclined with respect to the second direction Y.

[0045] Specifically, the portion where the scanning line 162 and the active connecting member 1414 are stacked in a direction perpendicular to the base 11 is the gate 161, that is, the gate 161 may be a part of the scanning line 162, but is not limited thereto. For example, the gate 161 may be a protruding or extending part of the scanning line 162.

[0046] Specifically, the active connecting member 1414 extends at least along the third direction Z, and at least a portion of the drain end 1412 can be positioned between two adjacent data lines 182, so that the drain 201 can be positioned between two adjacent data lines 182 and electrically connected to the drain end 1412, thereby improving the resolution of the display panel 100.

[0047] In some embodiments, the thin film transistor 101 is a single gate structure.

[0048] Specifically, the thin film transistor 101 is of a single-gate structure, which has only one gate, and compared with the two-gate structure, the size of the sub-pixel can be made smaller, thereby improving the resolution of the display panel 100 .

[0049] Specifically, in any of the above display panels 100, the thin film transistor 101 has a single-gate structure, that is, the orthogonal projection of the active connecting member 1414 on the base 11 and the orthogonal projection of the scan line 162 on the base intersect once, so that the width of the sub-pixel in the first direction X and / or the second direction Y is small, thereby improving the resolution of the display panel.

[0050] In some embodiments, the angle α between the third direction Z and the first direction X is greater than or equal to 5 degrees and less than or equal to 15 degrees.

[0051] Specifically, by making the angle α between the third direction Z and the first direction X greater than or equal to 5 degrees, the orthogonal projection of the drain end 1412 on the base 11 and the orthogonal projection of the drain 201 on the base at least partially overlap, which is convenient for electrically connecting the drain 201 to the drain end 1412 via the second through hole 106 described in the embodiment described later.

[0052] In some embodiments, the angle α between the third direction Z and the first direction X is 7 degrees.

[0053] Specifically, the angle α between the third direction Z and the first direction X is preferably 7 degrees, which can ensure that the active component 141 of the thin film transistor 101 has a channel 1413 with an appropriate aspect ratio, and can also ensure good electrical connection performance between the drain 201 and the drain end 1412, which is suitable for high-resolution display panels.

[0054] In some embodiments, in any of the above display panels 100, the display panel 100 includes a plurality of sub-pixels 110, each of which includes a first sub-pixel 111 and a second sub-pixel 112 located on either side of a scanning line 162, and a gap 113 is provided between the pixel electrode 211 of the first sub-pixel 111 and the pixel electrode 211 of the second sub-pixel 112, corresponding to the scanning line 162.

[0055] Specifically, there is a gap 113 between the pixel electrode 211 of the first sub-pixel 111 and the pixel electrode 211 of the second sub-pixel 112. In other words, the pixel electrode 211 of the first sub-pixel 111 and the pixel electrode 211 of the second sub-pixel 112 correspond to each other or are spaced apart by the gap 113, and the pixel electrode 211 of the first sub-pixel 111 and the pixel electrode 211 of the second sub-pixel 112 do not need to extend to the other side of the corresponding scan line 162. This allows the shielding width of the black matrix (BM) on the color film substrate to be reduced, thereby improving the aperture ratio and helping to improve the resolution of the display panel. Example 3

[0056] This embodiment may be the same as or similar to any of the display panels 100 of the above embodiments, but differs in that the characteristics of the display panel 100 are further defined.

[0057] Referring to Figures 1, 4, 5, and 6, Figure 4 is a second partial cross-sectional schematic diagram of a display panel according to an embodiment of the present application, Figure 5 is a third partial cross-sectional schematic diagram of a display panel according to an embodiment of the present application, and Figure 6 is a fourth partial cross-sectional schematic diagram of a display panel according to an embodiment of the present application.

[0058] In some embodiments, as shown in FIG. 1, the display panel 100 further includes a gate insulating layer 15, a first insulating layer 17, and a second insulating layer 19. The gate insulating layer 15 is provided between the semiconductor layer 14 and the third metal layer 16, the first insulating layer 17 is provided between the third metal layer 16 and the first metal layer 18, and the second insulating layer 19 is provided between the first metal layer 18 and the second metal layer 20. Here, the display panel 100 further includes a first through hole 105 penetrating the gate insulating layer 15 and the first insulating layer 17, and a second through hole 106 penetrating the gate insulating layer 15, the first insulating layer 17, and the second insulating layer 19, and the source 181 is electrically connected to the source end 1411 through the first through hole 105, and the drain 201 is electrically connected to the drain end 1412 through the second through hole 106.

[0059] Specifically, the material of the first insulating layer 17 and the second insulating layer 19 may include an inorganic material or an organic material. For example, the material of the first insulating layer 17 and the second insulating layer 19 may include, but is not limited to, silicon nitride and / or silicon oxide.

[0060] Specifically, the drain 201 is electrically connected to the drain end 1412 via the second through hole 106, thereby realizing an electrical connection between the drain 201 and the thin film transistor 101.

[0061] In some embodiments, as shown in FIG. 1, the display panel 100 further includes a first electrode layer 21 provided on the first metal layer 18, a fourth insulating layer 22 provided on the first electrode layer 21, and a second electrode layer 23 provided on the fourth insulating layer 22, and one of the first electrode layer 21 and the second electrode layer 23 includes a pixel electrode 211 of the subpixel 110.

[0062] Specifically, when the display panel 100 is a liquid crystal display panel, the first electrode layer 21 may include a pixel electrode 211, and the second electrode layer 23 may include a common electrode 231. Or, when the display panel 100 is a liquid crystal display panel, the first electrode layer 21 may include a common electrode, and the second electrode layer 23 may include a pixel electrode. Both of these two cases have the beneficial effects of the above embodiment.

[0063] In some embodiments, as shown in FIGS. 1, 4 and 5, the first electrode layer 21 includes a pixel electrode 211 of the sub-pixel that is directly connected to the drain 201.

[0064] Specifically, the first electrode layer 21 includes a pixel electrode 211 of a sub-pixel directly connected to the drain 201. In this case, the first electrode layer 21 can be directly manufactured after manufacturing the second metal layer 20, and there is no need to provide an insulating layer between the first electrode layer 21 and the second metal layer 20, which has the effect of simplifying the process.

[0065] In some embodiments, as shown in FIG. 5 , the display panel 100 further includes a third insulating layer 25 disposed between the second insulating layer 19 and the second metal layer 20, where the second insulating layer 19 is an organic material and the third insulating layer 25 is an inorganic material, and the second through hole 106 further penetrates the third insulating layer 25.

[0066] Specifically, the third insulating layer 25 is provided between the second insulating layer 19 and the second metal layer 20, the second insulating layer 19 is an organic material, and the third insulating layer 25 is an inorganic material. In the process of forming the second through hole 106, the third insulating layer 25 and the second insulating layer 19 are etched in the same process. The third insulating layer 25 plays a role in protecting the second insulating layer 19, preventing the second insulating layer 19, which is an organic material, from being over-etched, thereby avoiding the formation of an undercut structure, and improving the connection reliability between the drain 201 and the drain end 1412.

[0067] In some embodiments, as shown in FIG. 5 , the display panel 100 further includes a third electrode layer 26 disposed between the second insulating layer 19 and the third insulating layer 25, and the third electrode layer 26 includes a plurality of storage electrodes 261 at least partially overlapping the pixel electrodes 211.

[0068] Specifically, the storage electrode 261 and the pixel electrode 211 at least partially overlap, ie, the orthogonal projection of the storage electrode 261 on the base 11 and the projection of the pixel electrode 211 on the base 11 at least partially overlap.

[0069] Specifically, since the overlapping area between the pixel electrode 211 and the common electrode in a high-resolution display panel is small and the storage capacity is insufficient, a third electrode layer 26 including a plurality of storage electrodes 261 at least partially overlapping with the pixel electrode 211 is provided, so that the storage capacity in the high-resolution display panel can be increased, the voltage stability after charging of the pixel electrode 211 is improved, and the display effect is improved.

[0070] In some embodiments, the thickness of second metal layer 20 is greater than or equal to 3500 Angstroms.

[0071] Specifically, the second through-hole 106 penetrates many film layers and has a large depth, and the thickness of the second metal layer 20 is 3,500 angstroms or more. The second metal layer 20 plays a role of filling or flattening the second through-hole 106 to a certain extent, and can provide a flat support interface for film layers such as the pixel electrode 211 described later.

[0072] In some embodiments, the display panel 100 further includes a first blind hole 107 formed by recesses in the first electrode layer 21, the fourth insulating layer 22 and the second electrode layer 23 at a position corresponding to the second through hole 106, and a fifth insulating layer 24 which is an organic material filled at least in the first blind hole 107.

[0073] Specifically, the film layers of the first electrode layer 21, the fourth insulating layer 22 and the second electrode layer 23 are thin, and a first blind hole 107 is formed by a recess in the first electrode layer 21, the fourth insulating layer 22 and the second electrode layer 23 at a portion corresponding to the second through hole 106, and a fifth insulating layer 24 made of an organic material is provided. The fifth insulating layer 24 can fill the first blind hole 107 flatly. When the display panel 100 is a liquid crystal display panel, this provides a flat interface for the liquid crystal layer 301 provided on the fifth insulating layer 24, and helps to maintain the uniformity of the liquid crystal case thickness of the display panel 100.

[0074] In some embodiments, as shown in FIG. 6 , the display panel 100 further includes a color film substrate 30 including a substrate 31 and a support pillar 32 provided on the substrate 31, where the support pillar 32 is located between the substrate 31 and the base 11, and the orthogonal projection of the support pillar 32 on the base 11 does not overlap with the orthogonal projection of the fifth insulating layer 24 on the base 11.

[0075] Specifically, since the fifth insulating layer 24 is an organic material, the thickness of the fifth insulating layer 24 varies to a certain extent, and by ensuring that the orthogonal projection of the support pillar 32 on the base 11 and the orthogonal projection of the fifth insulating layer 24 on the base 11 do not overlap, unevenness in the thickness of the liquid crystal case of the display panel 100 can be avoided.

[0076] In addition, in any of the display panels 100 of the above embodiments, the display panel 100 may include a display area AA and a non-display area BB that at least partially surrounds the display area AA, and the thin film transistor 101 in the above embodiments may be provided in the display area AA or in the non-display area BB. The third metal layer 16, the first metal layer 18, the second metal layer 20, the first electrode layer 21, and the second electrode layer 23 may simultaneously function as wiring, a connection electrode, a bridge electrode, etc. in the non-display area BB, for example, the third metal layer 16 includes a common wiring 163, the second metal layer 20 includes a connection electrode 202, and the second electrode layer 23 includes a peripheral common electrode 232 electrically connected to the common wiring 163 via the connection electrode 202, and are not limited here.

[0077] In addition, in the display panel 100 of any of the above-mentioned embodiments, when forming the first through hole 105, the portion of the first insulating layer 17 corresponding to the first through hole 105 is entirely etched, the portion of the first insulating layer 17 corresponding to the second through hole 106 is only partially etched, and the portion of the first insulating layer 17 corresponding to the second through hole 106 is partially reserved to protect the drain end 1412. In addition, when forming the second through hole 106, the reserved portion of the first insulating layer 17 and the portion of the second insulating layer 19 corresponding to the second through hole 106 are simultaneously etched, or the reserved portion of the first insulating layer 17 and the portions of the second insulating layer 19 and the third insulating layer 25 corresponding to the second through hole 106 are simultaneously etched. Example 4

[0078] Please refer to FIG. 7, which is a schematic diagram of a display terminal according to an embodiment of the present application.

[0079] According to an embodiment of the present application, there is further provided a display terminal 1000 including the display panel 100 according to any of the above-mentioned embodiments.

[0080] Specifically, the display terminal 1000 may be a mobile phone, a notebook computer, a television, or the like, and may include a terminal body 1001 integrally combined with the display panel 100. The terminal body 1001 may be a structure and member such as an outer casing of the display terminal 1000.

[0081] The display panel and display terminal according to the embodiment of the present application have been described in detail above, and the principles and embodiments of the present application have been described in this specification by applying specific examples. The above description of the embodiment is intended to help the reader understand the method and core idea of ​​the present application, and those skilled in the art may recognize that there are changes in both the specific embodiment and the scope of application based on the idea of ​​the present application. Therefore, the contents of this specification should not be construed as limitations of the present application.

Claims

1. With the base, a first metal layer disposed above the base; a second metal layer provided above the first metal layer, the first metal layer includes a plurality of data lines extending along a first direction and sources of thin film transistors electrically connected to the data lines, and the second metal layer includes drains of the thin film transistors located between two adjacent data lines; Display panel.

2. a third metal layer disposed between the base and the first metal layer; a semiconductor layer provided between the third metal layer and the base, The third metal layer includes a scan line extending along a second direction, the semiconductor layer includes a plurality of active members of a plurality of the thin film transistors, the active members including a source end and a drain end, and an active connection member connected between the source end and the drain end, the first direction being different from the second direction, the source end and the drain end are located on both sides of the corresponding scan line, and the active connecting members extend along at least a third direction different from the first direction and the second direction; The source is electrically connected to the source terminal, and the drain is electrically connected to the drain terminal. The display panel according to claim 1 .

3. The thin film transistor has a single gate structure. The display panel according to claim 2 .

4. The angle between the third direction and the first direction is greater than or equal to 5 degrees and less than or equal to 15 degrees. The display panel according to claim 3 .

5. The angle between the third direction and the first direction is 7 degrees. The display panel according to claim 4.

6. A plurality of sub-pixels are included. The sub-pixel includes a pixel electrode. the plurality of sub-pixels include a first sub-pixel and a second sub-pixel located on both sides of the scanning line, and a gap is provided between the pixel electrode of the first sub-pixel and the pixel electrode of the second sub-pixel, the gap corresponding to the scanning line; The display panel according to claim 2 .

7. a gate insulating layer provided between the semiconductor layer and the third metal layer; a first insulating layer provided between the third metal layer and the first metal layer; a second insulating layer provided between the first metal layer and the second metal layer, the display panel further includes a first through hole penetrating the gate insulating layer and the first insulating layer, and a second through hole penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, the source being electrically connected to the source terminal through the first through hole, and the drain being electrically connected to the drain terminal through the second through hole. The display panel according to claim 6.

8. a first electrode layer provided above the first metal layer; a fourth insulating layer provided above the first electrode layer; a second electrode layer provided above the fourth insulating layer, one of the first electrode layer and the second electrode layer includes a pixel electrode of the sub-pixel; The display panel according to claim 7.

9. the first electrode layer includes a pixel electrode of the sub-pixel directly connected to the drain; The display panel according to claim 8.

10. a third insulating layer provided between the second insulating layer and the second metal layer, the second insulating layer being made of an organic material, the third insulating layer being made of an inorganic material, and the second through hole further penetrating the third insulating layer; The display panel according to claim 8.

11. a third electrode layer disposed between the second insulating layer and the third insulating layer, the third electrode layer including a plurality of storage electrodes at least partially overlapping the pixel electrodes; The display panel according to claim 10.

12. The thickness of the second metal layer is 350 nm or more. The display panel according to claim 7.

13. a first blind hole formed by a recess in the first electrode layer, the fourth insulating layer, and the second electrode layer at a portion corresponding to the second through hole; a fifth insulating layer being an organic material filled in at least the first blind hole; The display panel according to claim 8.

14. The color film substrate further includes a substrate and a support pillar provided on the substrate, the support pillar being located between the substrate and the base, and an orthogonal projection of the support pillar on the base does not overlap with an orthogonal projection of the fifth insulating layer on the base. The display panel according to claim 13.

15. A display device comprising the display panel according to any one of claims 1 to 14. Display terminal.

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