Programmable logic circuit device and image processing device

Abstract

To ensure that, when abnormality occurs, the abnormality is eliminated without initializing the whole of a reconfiguration region including a circuit that is reconfigured by a change of an inter-element connection.SOLUTION: The sequence processing which is executed upon occurrence of abnormality is a sequence processing ID "S08." In the sequence processing of the sequence processing ID "S08," reconfiguration data of reconfiguration data IDs "R03," "G05," and "W03" are designated as reconfiguration data for use at abnormality time. The reconfiguration data designed in this sequence processing for use at abnormality time, is reconfiguration data that designates connection between elements so as to not perform the sequence processing that was being executed when abnormality occurred.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a programmable logic circuit device and an image processing device. [Background technology]

[0002] In recent years, programmable logic devices such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) have been used as prototype devices or alternative devices when manufacturing application specific integrated circuits (ASICs) in the field of digital circuit devices, for example. Programmable logic devices can realize the logic functions desired by users by changing the connections between elements and rewriting the circuit (hereinafter referred to as reconfiguration). In addition, programmable logic devices can easily respond to specification changes and correct circuit defects by reconfiguring the circuit.

[0003] For example, Patent Document 1 describes a number of reconfigurable areas having circuits that are reconfigured by changing connections between elements, and a method of selectively reconfiguring these reconfigurable areas to a power-saving state based on the state of the processing executed by each of the multiple reconfigurable areas. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-199639 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to resolve an abnormality when it occurs without initializing the entire reconfiguration domain that includes a circuit that is reconfigured by changing connections between elements. [Means for solving the problem]

[0006] A programmable logic circuit device according to claim 1 of the present invention comprises a processor and a plurality of reconfigurable areas each including a circuit configured by changing connections between elements, and when an abnormality is detected while a process is being executed by connecting elements in the reconfigurable areas in accordance with reconfiguration data that specifies the connections between the elements, the processor changes the reconfiguration data that specifies the connections between the elements so as not to execute the process that is being executed. Reconstruction data for discarding the read data and changes connections between elements in the reconstruction domain according to the designation of the acquired reconstruction data.

[0007] A programmable logic circuit device according to claim 2 of the present invention comprises: The system includes a processor and a plurality of reconfiguration areas each having a circuit formed by changing connections between elements, and when an abnormality is detected while a process is being executed by connecting elements in the reconfiguration area in accordance with reconfiguration data specifying the connections between the elements, the processor obtains reconfiguration data specifying the connections between the elements so as not to execute the process being executed, the reconfiguration data being used to discard data after processing has been performed on loaded data, and changes the connections between the elements in the reconfiguration area in accordance with the specifications of the obtained reconfiguration data.

[0008] A programmable logic circuit device according to claim 3 of the present invention comprises: The present invention includes a processor and a plurality of reconfigurable regions each including a circuit configured by changing connections between elements, and when an abnormality is detected while a process is being executed by connecting elements in the reconfigurable region in accordance with reconfiguration data that specifies the connections between the elements, the processor acquires reconfiguration data for writing predetermined data to a memory that writes data after processing is performed on read data, and changes the connections between the elements in the reconfigurable region in accordance with the specifications in the acquired reconfiguration data. The reconfiguration data specifies the connections between the elements so as not to execute the process that is being executed. .

[0009] A programmable logic circuit device according to claim 4 of the present invention comprises: The present invention comprises a processor and a plurality of reconfigurable regions each including a circuit configured by changing connections between elements, and when an abnormality is detected while a process is being executed by connecting elements in the reconfigurable region in accordance with reconfiguration data specifying the connections between the elements, the processor acquires reconfiguration data for performing an operation check in the reconfigurable region, the reconfiguration data specifying the connections between the elements so as not to execute the process being executed, and changes the connections between the elements in the reconfigurable region in accordance with the specifications in the acquired reconfiguration data. .

[0010] A programmable logic circuit device according to claim 5 of the present invention comprises: The present invention comprises a processor and a plurality of reconfigurable regions each including a circuit configured by changing connections between elements, and when an abnormality is detected while a process is being executed by connecting elements in the reconfigurable region in accordance with reconfiguration data that specifies the connections between the elements, the processor acquires reconfiguration data that specifies the connections between the elements so as not to execute the process being executed, which differs depending on a cause of the abnormality, and changes the connections between the elements in the reconfigurable region in accordance with the specifications in the acquired reconfiguration data. .

[0012] Claims of the invention 6 The image processing device according to the present invention comprises: 5 The present invention relates to a programmable logic circuit device. Effect of the Invention

[0013] Claim 1, 6 According to the programmable logic circuit device of the present invention, when an abnormality occurs, the abnormality is eliminated without initializing the entire reconfigurable area including the circuit that is reconfigured by changing the connection between elements. Furthermore, when an abnormality occurs in the circuit that is reconfigured by changing the connections between elements, the read data is discarded. .

[0015] Claim 2 According to the programmable logic circuit device of the present invention, When an abnormality occurs, the abnormality is eliminated without initializing the entire reconfiguration domain including the circuit that is reconfigured by changing the connections between the elements, andWhen an abnormality occurs in a circuit that is reconfigured by changing the connections between elements, the data that has been read and processed is discarded.

[0016] Claim 3 According to the programmable logic circuit device of the present invention, When an abnormality occurs, the abnormality is eliminated without initializing the entire reconfiguration domain including the circuit that is reconfigured by changing the connections between the elements, and When an abnormality occurs in a circuit that is reconfigured by changing the connections between elements, predetermined data is written to a memory that writes data after processing read data.

[0017] Claim 4 According to the programmable logic circuit device of the present invention, When an abnormality occurs, the abnormality is eliminated without initializing the entire reconfiguration domain including the circuit that is reconfigured by changing the connections between the elements, and When an abnormality occurs in a circuit that is reconfigured by changing the connections between elements, the operation is checked in the reconfiguration area.

[0018] Claim 5 According to the programmable logic circuit device of the present invention, When an abnormality occurs, the abnormality is eliminated without initializing the entire reconfiguration domain including the circuit that is reconfigured by changing the connections between the elements, and When an anomaly occurs in a circuit that is reconfigured by changing connections between elements, a different reconfiguration is performed depending on the anomaly. [Brief description of the drawings]

[0019] [Figure 1] 1 is a block diagram illustrating the configuration of a programmable logic circuit device according to an embodiment of the present invention; [Diagram 2] FIG. 4 is a diagram illustrating management data according to the embodiment; [Diagram 3] FIG. 2 is a diagram illustrating an example of reconstruction data according to the present embodiment. [Figure 4] 10 is a flowchart showing an operation relating to reconstruction according to the present embodiment. [Diagram 5] 11 is a timing chart illustrating the time required for operations related to the reconstruction according to the present embodiment. [Figure 6] FIG. 13 is a diagram illustrating an example of reconstruction data as a comparative example. [Figure 7] 10 is a timing chart illustrating the time required for operations related to reconstruction as a comparative example; [Figure 8] 5 is a flowchart showing an operation when an abnormality occurs in the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] With reference to FIG. 1, the configuration of a programmable logic circuit device 100 according to an embodiment of the present invention will be described. The programmable logic circuit device 100 is, for example, a field programmable gate array (FPGA) or a programmable logic device (PLD), and includes a processor 10, an internal memory 11, and a plurality of reconfigurable areas 12a, 12b, 12... (hereinafter collectively referred to as reconfigurable areas 12). The processor 10 may be composed of a plurality of processors. The internal memory 11 is composed of rewritable memory elements such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) and an SRAM (Static Random Access Memory). The reconfigurable areas 12 include logic cells 13a, 13b, 13c... (hereinafter collectively referred to as logic cells 13), which are circuits configured by changing the connections between elements, and a look-up table (not shown) in which reconfiguration data specifying the connections between elements in the logic cells is written. Here, rewriting the logic cells 13 by changing the connections between elements is referred to as reconfiguration. The external memory 200 is composed of a rewritable memory element such as an EEPROM or SRAM.

[0021] The processor 10 receives an instruction for sequence processing from, for example, an external CPU (Central Processing Unit). The sequence processing refers to a series of processing including a plurality of processings whose execution order is specified, and is an example of the "processing" in the present invention. For example, when the programmable logic circuit device 100 is implemented in an image processing device such as a printer, the sequence processing is composed of three types of processing: a processing for reading data from the outside of the programmable logic circuit device 100, image processing for the read data, and a processing for writing data after image processing to the outside of the programmable logic circuit device 100. Among these, the processing for reading data from the outside of the programmable logic circuit device 100 includes a plurality of reading processes in which the data is read in a different order, for example, whether data is read in the sub-scanning direction or the main scanning direction. In other words, the connection between elements in the reconstruction area 12 for performing the reading processing is different for each reading processing, and different reconstruction data is required for each reading processing. In addition, the image processing for the read data includes a plurality of image processing in which the processing itself for the data is different, such as color conversion processing and filter processing. Therefore, the connections between elements in the reconstruction area 12 for performing image processing are different for each image processing, and different reconstruction data is required for each image processing. In addition, with regard to the writing process of data after image processing, there are a number of writing processes in which the data writing order is different, such as rotating or enlarging / reducing an image, or writing data in the sub-scanning direction or the main scanning direction. Therefore, the connections between elements in the reconstruction area 12 for performing writing processes are different for each write process, and different reconstruction data is required for each write process.

[0022] Fig. 2 is a diagram illustrating an example of reconfiguration data. In the example of Fig. 2, there are reconfiguration data R01 and reconfiguration data R02 as reconfiguration data for reading data from outside the programmable logic circuit device 100. Furthermore, there is reconfiguration data R03 for abnormality as reconfiguration data related to the reading of data from outside when an abnormality occurs. An abnormality here refers to, for example, a failure of the fan of the image processing device, an abnormality related to heat, no response from the CPU, a processing timeout, etc. The connections between elements in the logic cell specified by each of these reconfiguration data are different.

[0023] In addition, there are reconfiguration data G01, G02, G03, and G04 as reconfiguration data for performing image processing on the read data. Furthermore, there is reconfiguration data G05 for abnormality as reconfiguration data related to image processing when an abnormality occurs. The connections between elements in the logic cell specified by each of these reconfiguration data are different.

[0024] In addition, there are reconfiguration data W01 and reconfiguration data W02 as reconfiguration data for writing data after image processing to the outside of the programmable logic circuit device 100. Furthermore, there is reconfiguration data W03 for abnormality as reconfiguration data related to the writing of data from the outside when an abnormality occurs. The connections between elements in the logic cell specified by each of these reconfiguration data are different.

[0025] 2 is stored in the external memory 200. Therefore, the storage capacity of the internal memory 11, that is, the circuit scale of the programmable logic circuit device 100, is smaller than when the reconfiguration data is stored in the internal memory 11.

[0026] The internal memory 11 stores management data that specifies a plurality of pieces of reconfiguration data for executing a plurality of processes that constitute each sequence process. FIG. 3 is a diagram illustrating an example of the management data. In the example of FIG. 3, each of the sequence process IDs "S01" to "S08" is associated with a reconfiguration data ID of a plurality of pieces of reconfiguration data that specifies connections between elements in the logic cell 13 for executing the sequence process. For example, reconfiguration data with IDs "R01", "G01", and "W01" are specified as reconfiguration data for executing the sequence process of the sequence process ID "S01". The reconfiguration data with ID "R01" is reconfiguration data for reading data from the outside in the sequence process of the sequence process ID "S01". The reconfiguration data with ID "G01" is reconfiguration data for performing image processing on the read data in the sequence process of the sequence process ID "S01". The reconfiguration data with ID "W01" is reconfiguration data for performing write processing on data after image processing in the sequence process of the sequence process ID "S01". Furthermore, since such management data does not contain the actual reconfiguration data (i.e., connection information between elements), but only contains a reconfiguration data ID, which is identification information for the reconfiguration data, the total data size is smaller than if the actual reconfiguration data were included.

[0027] When the abnormality occurs, the sequence process with the sequence process ID "S08" is executed. In the sequence process with the sequence process ID "S08", the reconfiguration data with the reconfiguration data IDs "R03", "G05", and "W03" are specified as the reconfiguration data for the abnormality. These reconfiguration data for the abnormality are reconfiguration data that specify the connection between elements so that the sequence process that was being executed when the abnormality occurred (hereinafter, referred to as the running sequence process when the abnormality occurred) is not executed. Specifically, the reconfiguration data with the reconfiguration data ID "R03" is reconfiguration data for discarding data read from the outside in the running sequence process when the abnormality occurred. The reconfiguration data with the reconfiguration data ID "G05" is reconfiguration data for discarding data after image processing is performed on the data read in the running sequence process when the abnormality occurred. The reconfiguration data with the reconfiguration data ID "W03" is reconfiguration data for writing predetermined data to a memory in which data after image processing is performed on the data read in the running sequence process when the abnormality occurred is written. The predetermined data here is, for example, meaningless data such as "0".

[0028] Next, an example of normal operation of the programmable logic circuit device 100, that is, operation when no abnormality occurs, will be described with reference to Fig. 4. In Fig. 4, an external CPU or the like instructs the processor 10 to perform a certain sequence process by specifying a sequence process ID. The processor 10 accepts the specification of the sequence process ID (step S1) and obtains management data corresponding to the sequence process ID from the internal memory 11 (step S2).

[0029] Next, the processor 10 confirms that the data read process corresponding to the previous sequence process has been completed (step S3), and then judges whether the reconfiguration data ID of the read process specified by the acquired management data is the same as the reconfiguration data ID of the data read process corresponding to the previous sequence process (step S4). If the reconfiguration data ID of the read process specified by the management data is not the same as the reconfiguration data ID of the read process corresponding to the previous sequence process (step S4; No), the processor 10 needs to reconfigure the reconfiguration area, and acquires reconfiguration data corresponding to the reconfiguration data ID from the external memory 200 using the reconfiguration data ID of the read process specified by the management data as a key. Then, the processor 10 reconfigures the logic cell 13 of the reconfiguration area 12 based on the acquired reconfiguration data (step S5). Specifically, when the processor 10 writes the reconfiguration data to the lookup table of any of the reconfiguration areas, the lookup table is referenced in the reconfiguration area to change the connections between the elements in the logic cell. The reconfigured logic cell 13 starts reading data from the outside. In addition, if the reconstruction data ID of the read process specified by the management data is the same as the reconstruction data ID of the read process corresponding to the previous sequence process (step S4; Yes), the processor 10 skips the processing of step S5 since reconstruction of the reconstruction area is not necessary.

[0030] Next, the processor 10 confirms that the image processing corresponding to the previous sequence processing has been completed (step S6), and then judges whether or not the reconfiguration data ID of the image processing specified by the acquired management data is the same as the reconfiguration data ID of the image processing corresponding to the previous sequence processing (step S7). If the reconfiguration data ID of the image processing specified by the management data is not the same as the reconfiguration data ID of the image processing corresponding to the previous sequence processing (step S7; No), the processor 10 uses the reconfiguration data ID of the image processing specified by the management data as a key to acquire reconfiguration data corresponding to the reconfiguration data ID from the external memory 200. Then, the processor 10 performs reconfiguration in the logic cell 13 of the reconstruction area 12 based on the acquired reconfiguration data (step S8). The reconfigured logic cell 13 starts image processing for the read data. Note that if the reconfiguration data ID of the image processing specified by the management data is the same as the reconfiguration data ID of the image processing corresponding to the previous sequence processing (step S7; Yes), the processor 10 skips the process of step S8.

[0031] Next, the processor 10 confirms that the data write process corresponding to the previous sequence process has been completed (step S9), and then judges whether the reconfiguration data ID of the write process specified by the acquired management data is the same as the reconfiguration data ID of the data write process corresponding to the previous sequence process (step S10). If the reconfiguration data ID of the write process specified by the management data is not the same as the reconfiguration data ID of the write process corresponding to the previous sequence process (step S10; No), the processor 10 uses the reconfiguration data ID of the write process specified by the management data as a key and acquires reconfiguration data corresponding to the reconfiguration data ID from the external memory 200. Then, the processor 10 performs reconfiguration in the logic cells 13 of the reconstruction area 12 based on the acquired reconfiguration data (step S11). After the above image processing, the reconfigured logic cells 13 start writing the processed data. If the reconfiguration data ID of the write process specified by the management data is the same as the reconfiguration data ID of the write process corresponding to the previous sequence process (step S10; Yes), the processor 10 skips the process of step S11.

[0032] When the final write process constituting the sequence process is completed (step S12; Yes), the processor 10 ends the process shown in FIG.

[0033] Here, FIG. 5 is a diagram illustrating an example of reconstructed data as a comparative example. In the example of FIG. 5, for each sequence process, a set of reconstructed data for executing each of the read process, image process, and write process constituting the sequence process is prepared, and each set is stored in a memory corresponding to the internal memory 11 illustrated in the above embodiment. Therefore, for example, the same reconstructed data (e.g., reconstructed data R01, etc.) is duplicated and stored in the memory. In contrast, in the data structure according to the above embodiment as illustrated in FIG. 2, the reconstructed data is not duplicated and stored in the memory. However, in the case of the above embodiment, it is necessary to store management data as illustrated in FIG. 3 in addition to the reconstructed data, but as described above, the management data does not include the entity of the reconstructed data, but only includes the ID of the reconstructed data, so the total data size is smaller than when the entity of the reconstructed data is included.

[0034] Next, FIG. 6 is a timing chart illustrating the time required for the operation related to the reconstruction as a comparative example based on FIG. 5, and FIG. 7 is a timing chart illustrating the time required for the operation related to the reconstruction according to this embodiment. FIG. 6 shows the operation when three sequence processes S01, S05, and S06 are performed consecutively by three reconstruction regions, and time progresses from left to right. When the sequence process S01 is started, the reconstruction region at the top of the figure performs reconstruction to execute the read process constituting the sequence process S01, and after the reconstruction, starts the read process. In parallel with this, the reconstruction region at the middle performs reconstruction to execute the image process constituting the sequence process S01, and after the reconstruction, starts the image process. In parallel with this, the reconstruction region at the bottom performs reconstruction to execute the write process constituting the sequence process S01, and after the reconstruction, starts the write process.

[0035] The reconstruction area at the top of the figure executes a read process constituting the sequence process S01, then performs a reconfiguration to execute a read process constituting the sequence process S05, and starts the read process after the reconfiguration. The reconstruction area at the middle executes an image process constituting the sequence process S01, then performs a reconfiguration to execute an image process constituting the sequence process S05, and starts the image process after the reconfiguration. The reconstruction area at the bottom executes a write process constituting the sequence process S01, then performs a reconfiguration to execute a write process constituting the sequence process S05, and starts the write process after the reconfiguration. Similarly, the read process, image process, and write process constituting the sequence process S06 are executed after the reconfiguration of each reconstruction area. In these reconstructions, it is not taken into consideration whether the reconfiguration data for executing the process constituting the sequence process to be started is the same as the reconfiguration data for executing the process constituting the previous sequence process.

[0036] 7, which illustrates the operation of this embodiment, when the sequence process S01 is started, the topmost reconstruction area in the figure reconfigures to execute the read process constituting the sequence process S01, and starts the read process after the reconfiguration. In parallel with this, the middle reconstruction area reconfigures to execute the image process constituting the sequence process S01, and starts the image process after the reconfiguration. In parallel with this, the bottommost reconstruction area reconfigures to execute the write process constituting the sequence process S01, and starts the write process after the reconfiguration.

[0037] Here, the reconstruction area at the top of the figure performs reconfiguration for executing the read process constituting the sequential process S05 after performing the read process constituting the sequential process S01. At this time, the reconfiguration data of the read process constituting the sequential process S01 is the same as the reconfiguration data of the read process constituting the sequential process S05 (see FIG. 3), so no reconfiguration is performed. That is, at this timing, the connections between the elements are not changed in the reconstruction area at the top of the figure. Similarly, the reconfiguration data of the read process constituting the sequential process S05 is the same as the reconfiguration data of the read process constituting the sequential process S06 (see FIG. 3), so the reconstruction area at the top does not perform reconfiguration. In addition, the reconstruction area at the bottom performs reconfiguration for executing the write process constituting the sequential process S05 after performing the write process constituting the sequential process S01. At this time, the reconfiguration data of the write process constituting the sequential process S01 is the same as the reconfiguration data of the write process constituting the sequential process S05 (see FIG. 3), so no reconfiguration is performed. That is, in the reconstruction area at the bottom of the figure, the connections between elements are not changed. Similarly, since the reconstruction data of the write process constituting the sequence process S05 and the reconstruction data of the write process constituting the sequence process S06 are the same (see FIG. 3), the reconstruction area at the bottom is not reconfigured. In this way, when changing the connections between elements according to the designation by the reconstruction data, if the designation by at least one of the reconstruction data of the multiple processes constituting one sequence process does not require a change in the connections between elements in the reconstruction area, the connections between elements are not changed in the reconstruction area, that is, the same reconstruction data as when the elements in the reconstruction area were connected is used. Therefore, compared to the case of FIG. 6, the total time required to execute the sequence processes S01, S05, and S06 in FIG. 7 is shorter.

[0038] Next, an example of the operation of the programmable logic circuit device 100 when an abnormality occurs will be described with reference to Fig. 8. In Fig. 8, when some abnormality is detected by a predetermined abnormality detection device or abnormality detection algorithm (step S101), the processor 10 resets the management data that was being used for the sequence processing being executed at the time when the abnormality occurred (step S102).

[0039] Next, the processor 10 writes an abnormal state occurrence flag to the internal memory 11 to check whether a memory write to the internal memory 11 is possible (step S103). Next, the processor 10 checks whether the abnormal state occurrence flag has been read from the internal memory 11 to check whether a memory read from the internal memory 11 is possible (step S104). Here, if the abnormal state occurrence flag has not been read from the internal memory 11 (step S104; No), the processor 10 notifies the outside of the stop of processing (step S105).

[0040] On the other hand, if the abnormal condition occurrence flag can be read from the memory 11 (step S104; Yes), the processor 10 reads and obtains the management data for the sequence processing for abnormal situations corresponding to the sequence processing ID "08" from the internal memory 11 (step S106).

[0041] Next, the processor 10 acquires, from the external memory 200, the reconfiguration data for an abnormality corresponding to the reconfiguration data ID (here, the reconfiguration data IDs "R03", "G05", and "W03") using the reconfiguration data ID specified by the acquired management data as a key. Then, the processor 10 performs reconfiguration in the logic cells 13 in the reconfiguration area 12 according to the specification of the acquired reconfiguration data (step S107). Specifically, when the processor 10 writes the reconfiguration data to a lookup table in any of the reconfiguration areas, the lookup table is referenced in the reconfiguration area to change the connections between the elements in the logic cells. Each reconfigured logic cell 13 starts an operation for an abnormality (step S108). As a result, the sequence processing being executed is not performed, and data is discarded and predetermined data is written as described above.

[0042] Next, the processor 10 judges whether the sequence processing at the time of the abnormality is completed within a predetermined time (step S109). If the sequence processing at the time of the abnormality is not completed within the predetermined time (step S109; No), the processor 10 notifies the outside of the stop of the processing (step S110). If the sequence processing at the time of the abnormality is completed within the predetermined time (step S109; Yes), the processor 10 notifies the outside of the fact that the abnormality has been recovered from (step S111).

[0043] According to the above-described embodiment, when an abnormality occurs, the abnormality is resolved without initializing the entire reconstruction area.

[0044] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims.

[0045] The reconfiguration data may be any data that specifies connections between elements in the reconfiguration area 12 so as not to perform ongoing sequence processing when an abnormality occurs, and may be, for example, reconfiguration data for performing operation check in the reconfiguration area 12. Specifically, this reconfiguration data is reconfiguration data for reading predetermined data from outside in ongoing sequence processing when an abnormality occurs, reconfiguration data for performing predetermined processing on the read data, and reconfiguration data for writing data after the predetermined processing has been performed to the internal memory 11. If processing is completed within a predetermined time in the reconfiguration area 12 reconfigured in accordance with the specification of this reconfiguration data, it means that operation check in the reconfiguration area 12 has been performed.

[0046] The reconfiguration data may be different depending on the cause of the abnormality. These reconfiguration data may be only reconfiguration data that performs at least one of reading data, processing the read data, and writing the processed data depending on the cause of the abnormality, such as a fan failure of the image processing device, a heat-related abnormality, no response from the CPU, a processing timeout, etc., or may be reconfiguration data for performing different operation checks for each of these abnormality causes.

[0047] In the above embodiment, the sequence process is, for example, image processing on image data, but it may be processing other than image processing.

[0048] The management data is stored in the internal memory 11, but may be stored in the external memory 200. In addition, the reconstruction data is stored in the external memory 200, but may be stored in the internal memory 11. [Explanation of symbols]

[0049] 10: processor; 11: internal memory; 12, 12a, 12b, 12c: reconfigurable area; 13, 13a, 13b, 13c: logic cells; 100: programmable logic circuit device; 200: external memory

Claims

1. A processor; a plurality of reconfigurable regions each including a circuit configured by changing a connection between elements; The processor, When an abnormality is detected when a process is being executed by connecting elements in the reconstruction area in accordance with reconstruction data specifying the connections between the elements, the reconstruction data is obtained, the reconstruction data specifying the connections between the elements so as not to execute the process being executed, and the reconstruction data is used to discard the read data; Changing connections between elements in the reconstruction region according to the acquired reconstruction data. Programmable logic circuit device.

2. A processor; a plurality of reconfigurable regions each including a circuit configured by changing a connection between elements; The processor, When an abnormality is detected when elements in the reconstruction area are connected in accordance with reconstruction data specifying connections between the elements to execute processing, reconstruction data is obtained that specifies connections between the elements so as not to execute the processing being executed, and that is for discarding data after processing is performed on the read data; Change the connections between elements in the reconstruction area according to the acquired reconstruction data. Programmable logic circuit device.

3. A processor; a plurality of reconfigurable regions each including a circuit configured by changing a connection between elements; The processor, When an abnormality is detected when elements in the reconfiguration area are connected in accordance with reconfiguration data specifying connections between the elements to prevent the processing being performed, reconfiguration data is acquired for writing predetermined data to a memory for writing data after processing the read data, Changing connections between elements in the reconstruction region according to the acquired reconstruction data.

2. The programmable logic device of claim 1.

4. A processor; a plurality of reconfigurable regions each including a circuit configured by changing a connection between elements; The processor, When an abnormality is detected when elements in the reconfiguration region are connected in accordance with reconfiguration data specifying connections between the elements to cause a process to be executed, reconfiguration data is obtained for performing an operation check in the reconfiguration region, the reconfiguration data specifying connections between the elements so as to stop the process being executed; Changing connections between elements in the reconstruction region according to the acquired reconstruction data. Programmable logic circuit device.

5. A processor; a plurality of reconfigurable regions each including a circuit configured by changing a connection between elements; The processor, When an abnormality is detected when elements in the reconstruction area are connected in accordance with reconstruction data specifying connections between the elements to execute a process, the reconstruction data specifies connections between the elements so as to not execute the process being executed, and different reconstruction data is acquired in accordance with a cause of the abnormality; Changing connections between elements in the reconstruction region according to the acquired reconstruction data. Programmable logic circuit device.

6. 6. An image processing device comprising the programmable logic circuit device according to claim 1.

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