Wiring board and manufacturing method thereof

Abstract

To provide a wiring board with reduced warpage.SOLUTION: The present wiring board includes a first wiring structure including a first wiring layer and a first insulating layer containing a non-photosensitive thermosetting resin as a main component, a second wiring structure including a plurality of second wiring layers and a plurality of second insulating layers containing a photosensitive resin as a main component and laminated on the first wiring structure, and a sealing resin layer containing a non-photosensitive thermosetting resin as a main component and laminated on the uppermost second insulating layer, and the uppermost second wiring layer includes a pad protruding from the uppermost second insulating layer, the sealing resin layer exposes the upper surface of the pad and covers at least part of the side surface of the pad, and the coefficient of thermal expansion of the first insulating layer and the coefficient of thermal expansion of the sealing resin layer are lower than the coefficient of thermal expansion of the second insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] Conventionally, as a wiring board on which electronic components such as semiconductor chips are mounted, a wiring board in which a plurality of wiring layers and insulating layers are alternately laminated by a build-up method in order to increase the density of the wiring pattern has been known. As this type of wiring board, a wiring board has been proposed in which a high-density wiring layer including an insulating layer made of a photosensitive resin is formed on a low-density wiring layer including an insulating layer made of a thermosetting resin (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-157666 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned wiring board, warping may occur due to the difference in thermal expansion coefficient between the insulating layer made of a thermosetting resin and the insulating layer made of a photosensitive resin.

[0005] The present invention has been made in consideration of the above-mentioned points, and an object of the present invention is to provide a wiring board with reduced warping. [Means for solving the problem]

[0006] The wiring board includes a first wiring structure including a first wiring layer and a first insulating layer mainly composed of a non-photosensitive thermosetting resin, a plurality of second wiring layers and a plurality of second insulating layers mainly composed of a photosensitive resin, and is laminated on the first wiring structure, and a sealing resin layer mainly composed of a non-photosensitive thermosetting resin is laminated on the second insulating layer of a top layer, the second wiring layer of the top layer includes pads protruding from the second insulating layer of the top layer, the sealing resin layer exposes upper surfaces of the pads and covers at least a part of the side surfaces, and the thermal expansion coefficient of the first insulating layer and the thermal expansion coefficient of the sealing resin layer are lower than the thermal expansion coefficient of the second insulating layer. Ku , The thermal expansion coefficient of the first insulating layer and the thermal expansion coefficient of the sealing resin layer are substantially equal to each other. . Effect of the Invention

[0007] According to the disclosed technique, it is possible to provide a wiring board with reduced warping. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment (part 1). [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 5A to 5C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; [Diagram 5] FIG. 13 is a diagram showing a simulation result. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0010] First embodiment [Wiring board structure] First, a description will be given of the structure of the wiring board according to the first embodiment. Fig. 1 is a cross-sectional view illustrating the wiring board according to the first embodiment.

[0011] 1, the wiring board 1 according to the first embodiment has a first wiring structure 1L, a second wiring structure 1H laminated on the first wiring structure 1L, and a sealing resin layer 24 laminated on the second wiring structure 1H. The planar shape of the wiring board 1 can be, for example, a square or rectangular shape. However, the planar shape is not limited to this, and the wiring board 1 can be any planar shape.

[0012] The first wiring structure 1L is a low-density wiring layer having a wiring layer with a lower wiring density than the second wiring structure 1H, and includes a wiring layer 11, an insulating layer 12, and a wiring layer 13. In contrast, the second wiring structure 1H is a high-density wiring layer having a wiring layer with a higher wiring density than the first wiring structure 1L, and includes a wiring layer 14, an insulating layer 15, a wiring layer 16, an insulating layer 17, a wiring layer 18, an insulating layer 19, and a wiring layer 21.

[0013] In this embodiment, for convenience, the sealing resin layer 24 side of the wiring board 1 is referred to as the upper side or one side, and the insulating layer 12 side is referred to as the lower side or the other side. Also, the surface of each part on the sealing resin layer 24 side is referred to as one side or upper side, and the surface on the insulating layer 12 side is referred to as the other side or lower side. However, the wiring board 1 can be used upside down or placed at any angle. Also, a planar view refers to viewing an object from the normal direction of the upper surface 24a of the sealing resin layer 24, and a planar shape refers to the shape of the object viewed from the normal direction of the upper surface 24a of the sealing resin layer 24.

[0014] The wiring layer 11 is the lowest wiring layer exposed on the lower surface side of the insulating layer 12, and its upper surface and side surfaces are covered by the insulating layer 12. The lower surface of the wiring layer 11 is exposed, for example, at a position recessed from the lower surface 12b of the insulating layer 12 toward the wiring layer 13 side. However, if necessary, the lower surface of the wiring layer 11 may be flush with the lower surface 12b of the insulating layer 12. Alternatively, a part of the side surface and the lower surface of the wiring layer 11 may protrude downward from the lower surface 12b of the insulating layer 12.

[0015] The wiring layer 11 is, for example, a circular pad with a planar shape of about 150 μm in diameter, but may include a wiring pattern. The interval between adjacent wiring layers 11 may be, for example, about 200 μm. The material of the wiring layer 11 may be, for example, copper (Cu), etc. The thickness of the wiring layer 11 may be, for example, about 10 to 20 μm. The wiring layer 11 may be used as an external connection terminal (pad) for electrically connecting to another wiring board.

[0016] A surface treatment layer 110 may be formed on the lower surface of the wiring layer 11. Examples of the surface treatment layer 110 include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and a Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and a Au layer in this order), etc. In addition, an oxidation prevention treatment such as an OSP (Organic Solderability Preservative) treatment may be performed on the lower surface of the wiring layer 11.

[0017] The insulating layer 12 covers the top and side surfaces of the wiring layer 11. The insulating layer 12 is mainly composed of a non-photosensitive thermosetting resin, and has a reinforcing member 128. The insulating layer 12 can be configured by impregnating the reinforcing member 128 with a non-photosensitive thermosetting resin. Here, "mainly composed of a non-photosensitive thermosetting resin" means that the insulating layer 12 may contain other components such as a filler in addition to the thermosetting resin.

[0018] Examples of the non-photosensitive thermosetting resin used in the insulating layer 12 include epoxy resin, imide resin, phenol resin, and cyanate resin. Examples of the reinforcing member 128 include woven or nonwoven fabrics of glass fiber, carbon fiber, aramid fiber, and the like. Examples of the filler contained in the insulating layer 12 include silica (SiO2), kaolin (Al2Si2O5(OH4)), talc (Mg3SiO4O 10 Examples of the reinforcing material include aluminum oxide (Al2O3), alumina (Al2O3), etc. Also, these may be mixed together. The reinforcing material 128 may be, for example, a glass cloth using glass fiber bundles, carbon fiber bundles, polyester fiber bundles, nylon fiber bundles, aramid fiber bundles, etc.

[0019] The thickness T1 of the insulating layer 12 can be, for example, about 60 to 70 μm. The thermal expansion coefficient of the insulating layer 12 can be, for example, 5 ppm / ° C. or more and 10 ppm / ° C. or less. The thermal expansion coefficient of the insulating layer 12 can be adjusted to a predetermined value by, for example, the filler content, the composition of the insulating resin, etc. The thermal expansion coefficient of the insulating layer 12 is lower than the thermal expansion coefficient of each of the insulating layers 15, 17, and 19.

[0020] The reinforcing member 128 is unevenly distributed in the insulating layer 12 toward the second wiring structure 1H side (here, the upper side) from the center of the insulating layer 12 in the thickness direction. Specifically, the reinforcing member 128 is disposed at a position biased toward the second wiring structure 1H side from the center of the insulating layer 12 in the thickness direction. More specifically, in the insulating layer 12, the thickness of the resin layer (specifically, the thickness from the upper surface 12a of the insulating layer 12 to the reinforcing member 128) is set to be thinner than the thickness of the resin layer (specifically, the thickness from the reinforcing member 128 to the lower surface 12b of the insulating layer 12).

[0021] The upper surface 12a of the insulating layer 12 is a smooth surface (low roughness surface) with few irregularities. For example, the upper surface 12a of the insulating layer 12 is a polished surface. The upper surface 12a of the insulating layer 12 has a surface roughness smaller than that of the inner surface of the via hole 12x. The roughness of the upper surface 12a of the insulating layer 12 is set to have a surface roughness Ra value of, for example, about 15 to 40 nm. The roughness of the inner surface of the via hole 12x is set to have a surface roughness Ra value of, for example, about 300 to 400 nm. Here, the surface roughness Ra value is a kind of numerical value representing the surface roughness, and is called the arithmetic mean roughness, and specifically, it is the arithmetic mean of the absolute values ​​of the heights that change within the measurement area measured from the surface, which is the average line.

[0022] The wiring layer 13 is a via wiring buried in the insulating layer 12. More specifically, the wiring layer 13 is a via wiring filled in a via hole 12x that penetrates the insulating layer 12 and exposes the upper surface of the wiring layer 11, and is electrically connected to the wiring layer 11. The via hole 12x may be an inverted truncated cone-shaped recess in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 11. The diameter of the opening of the via hole 12x may be, for example, about 60 to 70 μm.

[0023] The upper surface of the wiring layer 13, which is a via wiring, is exposed from the upper surface 12a of the insulating layer 12. The upper surface of the wiring layer 13 may be flush with the upper surface 12a of the insulating layer 12, for example. The upper surface of the wiring layer 13 is directly bonded to the lower surface of the wiring layer 14. In addition, the lower surface of the wiring layer 13 is directly bonded to the wiring layer 11 within the insulating layer 12. The material of the wiring layer 13 may be the same as that of the wiring layer 11, for example.

[0024] The upper end surface of the wiring layer 13 is a smooth surface (low roughness surface) with few irregularities, similar to the upper surface 12a of the insulating layer 12. For example, the upper end surface of the wiring layer 13 is a polished surface. The roughness of the upper end surface of the wiring layer 13 is set to, for example, about 15 to 40 nm in terms of surface roughness Ra value.

[0025] In this embodiment, the wiring layer 13 is composed only of via wiring formed in the via hole 12x of the insulating layer 12. In other words, the wiring layer 13 does not have a wiring pattern integrally formed on the upper surface 12a of the insulating layer 12. The wiring layer 13 and the wiring layer 14 are electrically connected but are not integral. Specifically, in a manufacturing method described later, when the wiring layer 14 is formed by a semi-additive method, a seed layer is interposed at the boundary between the upper surface of the wiring layer 13 and the lower surface of the wiring layer 14. The reason for adopting such a structure is to form a high-density wiring pattern (for example, a line / space of about 3 μm / 3 μm) as the wiring layer 14 described later. Details will be described in the section on the manufacturing method of the wiring board 1.

[0026] The wiring layer 14 is formed on the upper surface 12a of the insulating layer 12. The wiring layer 14 is formed directly on the upper surface 12a of the insulating layer 12, and includes wiring (wiring patterns and pads) electrically connected to the wiring layer 11 via the wiring layer 13. That is, a part of the lower surface of the wiring layer 14 contacts the upper surface of the wiring layer 13, and the two are electrically connected. For example, copper (Cu) or the like can be used as the material of the wiring layer 14. The wiring layer 14 may be a laminated film in which a plurality of conductor layers are laminated.

[0027] The wiring layer 14 has a higher wiring density (narrower line / space) than the wiring layer 11, and is thinner than the wiring layer 11. In this specification, a wiring layer with a line / space of 8 μm / 8 μm or less is defined as a wiring layer with a high wiring density. The line / space of the wiring layer 14 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm. The thickness of the wiring layer 14 can be, for example, about 1 to 3 μm.

[0028] In line / space, the line represents the wiring width, and the space represents the distance between adjacent wirings (wiring distance). For example, if the line / space is described as 2 μm / 2 μm, it means that the wiring width is 2 μm and the distance between adjacent wirings is 2 μm.

[0029] The insulating layer 15 is an insulating layer whose main component is a photosensitive resin. "Whose main component is a photosensitive resin" means that the insulating layer 15 may contain other components such as a filler in addition to the photosensitive resin. For example, the insulating layer 15 may contain a filler such as silica (SiO2).

[0030] The insulating layer 15 is formed on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14. Examples of photosensitive resins used for the insulating layer 15 include insulating resins such as phenolic resins and polyimide resins. The thickness T2 of the insulating layer 15 can be, for example, 5 μm or more and 10 μm or less. The thermal expansion coefficient of the insulating layer 15 can be, for example, 40 ppm / ° C. or more and 60 ppm / ° C. or less. The thermal expansion coefficient of the insulating layer 15 can be adjusted to a predetermined value by, for example, the content of the filler, the composition of the insulating resin, etc.

[0031] The wiring layer 16 is formed on one side of the insulating layer 15 and is electrically connected to the wiring layer 14. The wiring layer 16 includes via wiring filled in a via hole 15x that penetrates the insulating layer 15 and exposes the upper surface of the wiring layer 14, and a wiring pattern formed on the upper surface of the insulating layer 15. The via hole 15x may be an inverted truncated cone-shaped recess in which the diameter of the opening on the insulating layer 17 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14. The diameter of the opening of the via hole 15x may be, for example, about 10 to 20 μm. The material of the wiring layer 16 and the thickness of the wiring pattern constituting the wiring layer 16 may be, for example, the same as that of the wiring layer 14.

[0032] The line / space of the wiring layer 16 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm, but it is possible to make the line / space narrower than that of the wiring layer 14. That is, the upper surface 12a of the insulating layer 12 is a polished surface and is smoother than the lower surface 12b of the insulating layer 12. The upper surface of the insulating layer 15, which is mainly composed of a photosensitive resin, is smoother than the upper surface 12a of the insulating layer 12, which is mainly composed of a non-photosensitive thermosetting resin. Therefore, the line / space of the wiring layer 16 can be narrower than that of the wiring layer 14. For example, the line / space of the wiring layer 14 can be 3 μm / 3 μm, and the line / space of the wiring layer 16 can be 1 μm / 1 μm. The same applies to the wiring layer 18 described later.

[0033] The insulating layer 17 is formed on one surface of the insulating layer 15 so as to cover the wiring layer 16. The material, thickness, and thermal expansion coefficient of the insulating layer 17 may be, for example, similar to those of the insulating layer 15. The insulating layer 17 may contain a filler such as silica (SiO2).

[0034] The wiring layer 18 is formed on one side of the insulating layer 17 and is electrically connected to the wiring layer 16. The wiring layer 18 includes via wiring filled in a via hole 17x that penetrates the insulating layer 17 and exposes the upper surface of the wiring layer 16, and a wiring pattern formed on the upper surface of the insulating layer 17. The via hole 17x may be an inverted truncated cone-shaped recess in which the diameter of the opening opened on the insulating layer 19 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 16. The diameter of the opening of the via hole 17x may be, for example, about 10 to 20 μm. The material of the wiring layer 18 and the thickness of the wiring pattern constituting the wiring layer 18 may be, for example, the same as that of the wiring layer 14. The line / space of the wiring pattern constituting the wiring layer 18 may be, for example, the same as that of the wiring layer 16.

[0035] The insulating layer 19 is formed on one surface of the insulating layer 17 so as to cover the wiring layer 18. In the second wiring structure 1H, the insulating layer 19 is the uppermost insulating layer. The material, thickness, and thermal expansion coefficient of the insulating layer 19 may be the same as those of the insulating layer 15, for example. The insulating layer 19 may contain a filler such as silica (SiO2).

[0036] The wiring layer 21 is formed on one side of the insulating layer 19. In the second wiring structure 1H, the wiring layer 21 is the uppermost wiring layer. The wiring layer 21 includes via wirings 22 filled in via holes 19x that penetrate the insulating layer 19 and expose the upper surface of the wiring layer 18, and pads 23 protruding from the upper surface of the insulating layer 19. The via holes 19x may be recesses in the shape of inverted truncated cones, with the diameter of the opening opening on the pad 23 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 18. The diameter of the opening of the via holes 19x may be, for example, about 10 to 20 μm.

[0037] The material of the wiring layer 21 may be, for example, the same as that of the wiring layer 14. The thickness of the wiring layer 21 (the sum of the thickness of the via wiring 22 and the thickness of the pad 23) may be, for example, about 100 μm. The thickness of the pad 23 (the thickness from the upper surface of the insulating layer 19 to the upper surface of the pad 23) may be, for example, 80 to 150 μm. The planar shape of the pad 23 may be, for example, a circle with a diameter of about 20 to 30 μm. The pitch of the pads 23 may be, for example, about 40 to 50 μm. The portions of the pads 23 exposed from the sealing resin layer 24 may be used as external connection terminals for electrical connection to a semiconductor chip.

[0038] A surface treatment layer 210 similar to the surface treatment layer 110 may be formed on the upper surface of the pad 23. When a part of the side surface and the upper surface of the pad 23 protrudes from the upper surface 24a of the sealing resin layer 24, the surface treatment layer 210 is formed only on the upper surface of the pad 23, or on a part of the side surface and the upper surface.

[0039] The sealing resin layer 24 is laminated on the insulating layer 19, which is the uppermost insulating layer in the second wiring structure 1H. The sealing resin layer 24 exposes the upper surface of the pad 23 and covers at least a part of the side surface of the pad 23. The sealing resin layer 24 may expose the upper surface of the pad 23 and cover the entire side surface of the pad 23. In this case, the upper surface of the pad 23 is flush with the upper surface 24a of the sealing resin layer 24, for example. However, a part of the side surface and the upper surface of the pad 23 may be protruded from the upper surface 24a of the sealing resin layer 24, or the upper surface of the pad 23 may be exposed at a position recessed from the upper surface 24a of the sealing resin layer 24. In addition, when a part of the side surface and the upper surface of the pad 23 are protruded from the upper surface 24a of the sealing resin layer 24, a gap between the sealing resin layer 24 and the semiconductor chip can be secured, so that it is easy to fill the underfill resin between the sealing resin layer 24 and the semiconductor chip.

[0040] For example, a mold resin can be used as the material of the sealing resin layer 24. The mold resin is an insulating resin mainly composed of a non-photosensitive thermosetting resin that can be used in a transfer molding method, a compression molding method, an injection molding method, etc. The mold resin is, for example, an insulating resin such as a non-photosensitive thermosetting epoxy resin, and may contain a filler similar to that of the insulating layer 12, but does not contain a reinforcing member such as glass fiber.

[0041] From the viewpoint of reducing warpage of the wiring board 1, it is preferable that the thickness T3 of the sealing resin layer 24 is thicker than the thickness T1 of the insulating layer 12. If the thickness T1 of the insulating layer 12 is 60 μm or more and 70 μm or less, the thickness T3 of the sealing resin layer 24 can be, for example, 80 μm or more and 150 μm or less. The thermal expansion coefficient of the sealing resin layer 24 is lower than the thermal expansion coefficients of each of the insulating layers 15, 17, and 19.

[0042] In order to reduce warping of the wiring board 1, it is preferable that the thermal expansion coefficient of the sealing resin layer 24 is approximately equal to the thermal expansion coefficient of the insulating layer 12. Here, approximately equal means that the thermal expansion coefficient of the sealing resin layer 24 is within ±20% of the thermal expansion coefficient of the insulating layer 12.

[0043] For example, if the thermal expansion coefficient of the insulating layer 12 is 5 ppm / ° C. or more and 10 ppm / ° C. or less, the thermal expansion coefficient of the sealing resin layer 24 is also preferably 5 ppm / ° C. or more and 10 ppm / ° C. or less. The thermal expansion coefficient of the sealing resin layer 24 can be adjusted to a predetermined value by, for example, the filler content, the composition of the insulating resin, etc.

[0044] [Method for manufacturing wiring board according to the first embodiment] Next, a method for manufacturing a wiring board according to the first embodiment will be described. Figs. 2 to 4 are diagrams illustrating the manufacturing process of a wiring board according to the first embodiment. Here, an example of a process for manufacturing one wiring board is shown, but a process in which a plurality of parts that become wiring boards are manufactured and then diced into individual wiring boards may be used. Here, an example of a process for forming a layer structure only on one side of a support is shown, but a process in which a layer structure is formed on both one side and the other side of a support may be used.

[0045] First, in the process shown in FIG. 2(a), a support 100 is prepared, a wiring layer 11 and an insulating layer 12 are formed on the support 100, a via hole 12x is formed in the insulating layer 12, and then a laminated structure of a seed layer 131 and an electrolytic plating layer 132 is formed on the insulating layer 12 and in the via hole 12x.

[0046] The support 100 has a structure in which, for example, a copper foil 104 with a carrier is laminated on one side of a core substrate 101. The core substrate 101 is, for example, a resin substrate having a thickness of about 0.7 mm, and may have a reinforcing member such as glass fiber. The copper foil 104 with a carrier has a structure in which a thin foil 104a made of, for example, copper and having a thickness of about 1.5 to 5 μm is peelably attached to a thick foil (carrier foil) 104b made of, for example, copper and having a thickness of about 10 to 50 μm, via a peeling layer (not shown). The thick foil 104b is provided as a support material to facilitate handling of the thin foil 104a.

[0047] The above-mentioned structure of the support 100 is an example, and the support 100 is not limited thereto. For example, in the support 100, a laminate in which a plurality of prepregs are laminated may be used instead of the core substrate 101. The support 100 may have a structure in which a carrier-attached copper foil 104 is disposed on one side of a glass substrate, a metal substrate, or the like, via a release layer.

[0048] After the support 100 is prepared, first, the wiring layer 11 is formed on one side of the support 100. Specifically, a resist layer having an opening in a portion where the wiring layer 11 is to be formed is formed on the upper surface of the carrier-attached copper foil 104 (upper surface of the thin foil 104a) using a dry film resist or the like. Then, by an electrolytic plating method using the carrier-attached copper foil 104 as a power supply layer, the wiring layer 11, which is an electrolytic plating layer, is formed on the upper surface of the carrier-attached copper foil 104 exposed in the opening. The material and thickness of the wiring layer 11 are as described above. Thereafter, the resist layer is peeled off.

[0049] Next, the insulating layer 12 that covers the wiring layer 11 is formed on the upper surface of the copper foil 104 with the carrier. Specifically, a semi-cured film-like insulating resin that is mainly composed of a non-photosensitive thermosetting resin and has a reinforcing member 128 is prepared. Then, this insulating resin is laminated on the upper surface of the copper foil 104 with the carrier, and cured under heat and pressure to form the insulating layer 12. The material, thickness, thermal expansion coefficient, etc. of the insulating layer 12 are as described above.

[0050] Next, via holes 12x are formed in the insulating layer 12 so as to penetrate the insulating layer 12 and expose the upper surface of the wiring layer 11. The via holes 12x can be formed by a laser processing method using, for example, a CO2 laser, a YAG laser, an excimer laser, or the like. After the via holes 12x are formed, it is preferable to perform a desmear process to remove resin residues adhering to the surfaces of the wiring layer 11 exposed at the bottoms of the via holes 12x.

[0051] Next, a laminated structure of a seed layer 131 and an electrolytic plating layer 132 is formed on the upper surface 12a of the insulating layer 12 and in the via holes 12x, for example, by using a semi-additive method. Specifically, first, the seed layer 131 is formed on the upper surface 12a of the insulating layer 12, the inner wall surface of the via holes 12x, and the upper surface of the wiring layer 11 exposed in the via holes 12x, by electroless plating or sputtering. As the seed layer 131, for example, a copper layer having a thickness of about 100 to 350 nm can be used. Alternatively, as the seed layer 131, a laminated film in which a titanium layer having a thickness of about 20 to 50 nm and a copper layer having a thickness of about 100 to 300 nm are laminated in this order may be used. By forming a titanium layer under the seed layer 131, the adhesion between the insulating layer 12 and the wiring layer 13 can be improved. Titanium nitride or the like may be used instead of titanium. Note that titanium and titanium nitride are metals having higher corrosion resistance than copper. Then, an electrolytic plating layer 132 (eg, a copper layer) is formed on the seed layer 131 by electrolytic plating using the seed layer 131 as a power supply layer.

[0052] 2(b), the upper surface side of the laminated structure of the seed layer 131 and the electrolytic plating layer 132 shown in FIG. 2(a) is polished to expose the upper surface 12a of the insulating layer 12, and the wiring layer 13, which is the via wiring filled in the via hole 12x, is formed. For example, a chemical mechanical polishing (CMP) method or the like can be used to polish the wiring layer 13. For example, the upper surface of the wiring layer 13 can be flush with the upper surface 12a of the insulating layer 12.

[0053] When the wiring layer 13 is polished, a part of the upper surface 12a of the insulating layer 12 may be polished and removed at the same time. By polishing the upper surface 12a of the insulating layer 12 together with the wiring layer 13 and removing a part of the upper surface 12a of the insulating layer 12, the roughness of the upper surface 12a of the insulating layer 12 can be made smaller than that before polishing. That is, the smoothness of the upper surface 12a of the insulating layer 12 can be improved. The roughness of the upper surface 12a of the insulating layer 12 is, for example, about Ra 300 to 400 nm before performing the CMP method (before polishing), and can be made about Ra 15 to 40 nm by performing the CMP method. In this way, by reducing the roughness of the upper surface 12a of the insulating layer 12 and improving the smoothness, it becomes possible to form fine wiring (a wiring layer with a high wiring density) in a later process. The roughness of the lower surface 12b of the insulating layer 12 is, for example, about Ra 180 to 280 nm.

[0054] 2(c), a wiring layer 14 having a predetermined pattern is formed on the upper surface of the wiring layer 13 and the upper surface 12a of the insulating layer 12. The wiring layer 14 can be formed, for example, by a semi-additive method, like the wiring layer 13. Specifically, first, a seed layer is formed by electroless plating or sputtering so as to continuously cover the upper surface of the wiring layer 13 and the upper surface 12a of the insulating layer 12.

[0055] Then, a photosensitive resist layer is formed on the entire upper surface of the seed layer, and the resist layer is exposed and developed to form an opening that exposes the portion where the wiring layer 14 is to be formed. Then, an electrolytic plating layer is formed on the upper surface of the seed layer exposed in the opening by electrolytic plating using the seed layer as a power supply layer. Then, after peeling off the resist layer, the electrolytic plating layer is used as a mask to remove the seed layer in the portion not covered by the electrolytic plating layer by etching. This forms the wiring layer 14 in which the electrolytic plating layer is laminated on the seed layer. The material, thickness, line / space, etc. of the wiring layer 14 are as described above. Note that the wiring layer 14 has a structure in which the electrolytic plating layer is laminated on the seed layer, but the distinction between the seed layer and the electrolytic plating layer is omitted in FIG. 2(c) and the like (the same may be omitted for other wiring layers).

[0056] 3(a), a liquid or paste-like photosensitive resin is applied to the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14, and then heated at a temperature at which the resin does not harden to form the insulating layer 15 in a semi-hardened state. The material and thickness of the insulating layer 15 are as described above. Next, for example, via holes 15x are formed by photolithography, and the insulating layer 15 is heated to a hardening temperature or higher to harden it. The upper surface of the insulating layer 15, which is mainly composed of a photosensitive resin, is smoother than the upper surface 12a of the insulating layer 12. The roughness of the upper surface of the insulating layer 15 can be, for example, about Ra 2 to 6 nm.

[0057] 3(b), the same steps as those shown in Fig. 2(c) and Fig. 3(a) are repeated to form the wiring layer 16, the insulating layer 17, the wiring layer 18, and the insulating layer 19, and then the wiring layer 21 including the via wiring 22 and the pad 23 is formed in the same manner as in the step shown in Fig. 2(c). The materials and thicknesses of the wiring layer 16, the insulating layer 17, the wiring layer 18, the insulating layer 19, and the wiring layer 21 are as described above.

[0058] Next, in the step shown in FIG. 3(c), a sealing resin layer 24 is formed on the insulating layer 19 so as to cover the upper and side surfaces of the pads 23 of the wiring layer 21. The sealing resin layer 24 can be formed, for example, by a molding method using a mold resin. For example, the structure shown in FIG. 3(b) is placed in a metal mold, and a pressure (for example, 5 to 10 MPa) is applied to the metal mold to introduce a fluidized mold resin. Thereafter, the mold resin is heated at a temperature of about 180° C. to harden the mold resin, thereby forming the sealing resin layer 24. Then, after the required sealing process is completed, the structure covered with the sealing resin layer 24 is removed from the metal mold. For example, a transfer molding method, a compression molding method, an injection molding method, or the like can be used as the molding method.

[0059] Next, in the step shown in Fig. 4(a), the upper surface side of the sealing resin layer 24 shown in Fig. 3(c) is polished to expose at least the upper surface of the pad 23. For example, a CMP method or the like can be used to polish the sealing resin layer 24. For example, the upper surface of the pad 23 can be flush with the upper surface 24a of the sealing resin layer 24. However, by adjusting the amount of polishing of the sealing resin layer 24, a part of the side surface and the upper surface of the pad 23 may be made to protrude from the upper surface 24a of the sealing resin layer 24, or the upper surface of the pad 23 may be exposed at a position recessed from the upper surface 24a of the sealing resin layer 24.

[0060] 4(b), the support 100 is removed. To remove the support 100, the core substrate 101 and the thick foil 104b are first mechanically peeled off from the thin foil 104a. The thin foil 104a is then removed by wet etching using, for example, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like. At this time, if the wiring layer 11 is made of copper, the lower surface side of the wiring layer 11 is also etched, and the lower surface of the wiring layer 11 is recessed from the lower surface 12b of the insulating layer 12 toward the wiring layer 13.

[0061] 4(c), if necessary, a surface treatment layer 210 is formed on the upper surface of the pad 23 of the structure of FIG. 4(b), and a surface treatment layer 110 is formed on the lower surface of the wiring layer 11, and then the structure is singulated to complete the wiring board 1. As the surface treatment layers 110 and 210, for example, the above-mentioned metal layer or a laminate of metal layers may be formed by electroless plating, or an oxidation prevention treatment such as OSP treatment may be performed.

[0062] In this manner, in the wiring board 1, the first wiring structure 1L including the insulating layer 12 mainly made of a non-photosensitive thermosetting resin and the sealing resin layer 24 mainly made of a non-photosensitive thermosetting resin are arranged on either side of the second wiring structure 1H including the insulating layers 15, 17, and 19 mainly made of a photosensitive resin. The thermal expansion coefficients of the insulating layer 12 and the sealing resin layer 24 are lower than the thermal expansion coefficients of the insulating layers 15, 17, and 19. This structure improves the imbalance of the thermal expansion coefficients in the thickness direction of the wiring board 1, thereby reducing warping of the wiring board 1.

[0063] Furthermore, by reducing the warping of wiring board 1, it becomes easier to mount a semiconductor chip on the sealing resin layer 24 side of wiring board 1, or to mount wiring board 1 on another wiring board.

[0064] 4(a) may be the shipping form, that is, the wiring board 1 with the support 100 attached may be the shipping form.

[0065] <Warp Simulation> A simulation was performed on the warpage of a wiring board (referred to as wiring board A) having the structure of FIG. 1 when it was heated to 150° C. and then returned to room temperature. Specifically, the planar shape of wiring board A was a rectangle of 44 mm×31 mm. The thickness T1 of insulating layer 12 was set to 60 μm. The thickness T2 of each of insulating layers 15, 17, and 19 constituting second wiring structure 1H was set to 5 μm.

[0066] A simulation was performed on the warpage of the wiring board A when the thickness T3 of the sealing resin layer was changed from 10 μm to 150 μm in 10 μm increments. As a comparative example, a simulation of warpage was also performed on a wiring board (referred to as wiring board X) that did not have a sealing resin layer.

[0067] [Table 1] The simulation results are shown in Table 1 and Figure 5. As shown in Table 1 and Figure 5, in the comparative example that does not have a sealing resin layer, warping occurred in the wiring board X in a direction in which the wiring layer 11 side was convex, and the amount of warping was -2.69 mm. Note that the amount of warping here is the distance in the thickness direction between the highest and lowest points when the wiring board is placed on a flat surface. Also, a negative value indicates that the warping is in a direction in which the wiring layer 11 side is convex.

[0068] In contrast, when a 10 μm thick sealing resin layer 24 was provided, the wiring board A still had warpage in the direction in which the wiring layer 11 side was convex, as in the wiring board X, but the amount of warpage was reduced to -2.35 mm. As the sealing resin layer 24 was made thicker, the amount of warpage of the wiring board A was further reduced, and when the sealing resin layer 24 was 110 μm thick, the direction of the warpage of the wiring board A changed to a direction in which the wiring layer 11 side was concave, and the amount of warpage was 0.03 mm. As the sealing resin layer 24 was made thicker, the amount of warpage in the direction in which the wiring layer 11 side was concave increased, and when the sealing resin layer 24 was 150 μm thick, the amount of warpage was 0.25 mm.

[0069] In this way, it was confirmed that warping of the wiring board A can be reduced by sandwiching the second wiring structure 1H including an insulating layer 15 mainly composed of a photosensitive resin and an encapsulating resin layer 24 between them.

[0070] In addition, warping is reduced by making the thickness of the sealing resin layer 24 thicker than the thickness of the insulating layer 12. Specifically, when the thickness of the insulating layer 12 is 60 μm, the thickness of the sealing resin layer 24 can be set to 80 μm or more and 150 μm or less to suppress the warping to ±0.5 mm or less. When the thickness of the insulating layer 12 is 60 μm, the thickness of the sealing resin layer 24 can be set to 90 μm or more and 130 μm or less to suppress the warping to ±0.2 mm or less. Furthermore, when the thickness of the insulating layer 12 is 60 μm, the thickness of the sealing resin layer 24 can be set to 100 μm or more and 120 μm or less to suppress the warping to ±0.1 mm or less. A large warping occurred due to an imbalance in the thermal expansion coefficient between the insulating layer 12 mainly composed of a thermosetting resin and the insulating layers 15, 17, and 19 mainly composed of a photosensitive resin. However, by providing the sealing resin layer 24 mainly composed of a thermosetting resin, the imbalance in the thermal expansion coefficient is improved and the warping is reduced.

[0071] If the thickness of the insulating layer 12 is changed, the thickness of the sealing resin layer 24 may be adjusted to be thicker than the thickness of the insulating layer 12 to reduce the warpage. This can reduce the warpage of the wiring board to almost zero, as in the results of this simulation. However, if the thickness of the sealing resin layer 24 is increased to 150 μm or more, the warpage gradually increases. In such a case, there is a risk of this having an effect when mounting the wiring board A on another wiring board. Therefore, the thickness of the sealing resin is set to a value that suppresses the warpage to within ±0.1 mm to ±0.5 mm. Preferably, the thickness of the sealing resin is set to a value that suppresses the warpage to within ±0.1 mm to ±0.2 mm.

[0072] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0073] For example, the first wiring structure 1L is not limited to the structure of FIG. 1 as long as it includes an insulating layer 12 whose main component is a non-photosensitive thermosetting resin, and may be a multilayer wiring structure having a wiring layer within the insulating layer 12. [Explanation of symbols]

[0074] 1. Wiring board 1H 2nd wiring structure 1L 1st wiring structure 11, 13, 14, 16, 18, 21 wiring layer 12, 15, 17, 19 Insulating layer 12a, 24a top surface 12b Bottom side 12x, 15x, 17x, 19x via holes 22 Via wiring 23 Pad 24 Sealing resin layer 100 support 101 Core Board 104 Copper foil with carrier 104a thin foil 104b thick foil 110, 210 Surface treatment layer 128 Reinforcement member 131 Seed Layer 132 Electrolytic plating layer

Claims

1. a first wiring structure including a first wiring layer and a first insulating layer mainly composed of a non-photosensitive thermosetting resin; a second wiring structure including a plurality of second wiring layers and a plurality of second insulating layers mainly made of a photosensitive resin, the second wiring structure being laminated on the first wiring structure; a sealing resin layer including a non-photosensitive thermosetting resin as a main component, the sealing resin layer being laminated on the second insulating layer as a top layer; the second wiring layer, which is a top layer, includes a pad protruding from the second insulating layer, which is a top layer; the sealing resin layer exposes an upper surface of the pad and covers at least a portion of a side surface of the pad; a thermal expansion coefficient of the first insulating layer and a thermal expansion coefficient of the sealing resin layer are lower than a thermal expansion coefficient of the second insulating layer; A wiring board, wherein the thermal expansion coefficient of the first insulating layer and the thermal expansion coefficient of the sealing resin layer are substantially equal to each other.

2. The wiring board according to claim 1 , wherein the sealing resin layer is thicker than the first insulating layer.

3. the thermal expansion coefficient of the first insulating layer and the thermal expansion coefficient of the sealing resin layer are 5 ppm / ° C. or more and 10 ppm / ° C. or less; 3. The wiring board according to claim 1, wherein the second insulating layer has a thermal expansion coefficient of 40 ppm / .degree. C. or more and 60 ppm / .degree. C. or less.

4. The wiring board according to claim 1 , wherein the first insulating layer has a reinforcing member.

5. In the first wiring structure, the first wiring layer is exposed on a lower surface side of the first insulating layer, the first wiring structure includes a via wiring that penetrates the first insulating layer and is connected to the first wiring layer; The wiring board according to claim 1 , wherein the second wiring layer, which is a lowermost layer of the second wiring structure, is directly bonded to the via wiring.

6. 6. The wiring board according to claim 1, wherein the pads are external connection terminals for electrically connecting to a semiconductor chip.

7. forming a first wiring structure including a first wiring layer and a first insulating layer mainly composed of a non-photosensitive thermosetting resin; forming a second wiring structure including a plurality of second wiring layers and a plurality of second insulating layers mainly made of a photosensitive resin, the second wiring structure being laminated on the first wiring structure; laminating an encapsulation resin layer mainly composed of a non-photosensitive thermosetting resin on the second insulating layer, which is the uppermost layer; the second wiring layer, which is a top layer, includes a pad protruding from the second insulating layer, which is a top layer; a thermal expansion coefficient of the first insulating layer and a thermal expansion coefficient of the sealing resin layer are lower than a thermal expansion coefficient of the second insulating layer; A method for manufacturing a wiring board, wherein in the step of forming the sealing resin layer, the sealing resin layer is formed so as to cover the upper and side surfaces of the pads, and the upper surface side of the sealing resin layer is polished to expose the upper surfaces of the pads.

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