Semiconductor Device

Abstract

To provide a storage device including a storage element capable of being operated by a thin film transistor having a small off-state current without problems.SOLUTION: Provided is a storage device in which storage elements each having at least one thin film transistor having an oxide semiconductor layer are arranged in a matrix. The thin film transistor having the oxide semiconductor layer has high electron field-effect mobility and can reduce an off-state current, and hence can be successfully operated without problems. In addition, power consumption can be reduced. Regarding the above-described storage device, it is especially effective in the case where the thin film transistor having the oxide semiconductor layer is provided in a pixel of a display device, for example, because the memory device can be formed on the same substrate.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a memory circuit (for example, This document relates to memory devices. [Background technology]

[0002] The technology of constructing transistors using thin semiconductor films on substrates with insulating surfaces has been attracting attention. Transistors are used in display devices such as liquid crystal televisions. Silicon is widely used as a material for semiconductor thin films that can be used in transistors, but In recent years, oxide semiconductors have also been attracting attention.

[0003] Zinc oxide or materials containing zinc oxide are known as oxide semiconductor materials. (For example, Patent Documents 1 and 2) 18 cm - 3 A transistor formed of an amorphous oxide (oxide semiconductor) of less than For example, Patent Document 3). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2006-165529 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the case of oxide semiconductors, deviation from the stoichiometric composition occurs during the thin film formation process. The electrical conductivity of the oxide semiconductor changes depending on whether there is an excess or deficiency of oxygen. In addition, hydrogen that is mixed in during the formation of the oxide semiconductor thin film forms bonds with oxygen (OH bonds). The OH bond acts as an electron donor, which changes the electrical conductivity. This can change the characteristics of active devices such as transistors made of oxide semiconductors. This is a motivating factor.

[0006] The electron carrier concentration is 10 18 cm -3 Even if the valence rate is less than 100%, the oxide semiconductor is essentially n-type. The on / off ratio of the transistors disclosed in Patent Documents 1 to 3 is 10 3 degree The reason why the on / off ratio of such transistors is low is due to their high off current. The on / off ratio refers to the ratio of the on current value to the off current value.

[0007] In view of the above problems, one aspect of the present invention is to provide a semiconductor device having stable electrical characteristics (for example, an extremely low off-state current). The objective of the present invention is to provide a transistor having a reduced capacitance (Cu-Si). [Means for solving the problem]

[0008] One embodiment of the present invention is an oxide semiconductor having a hydrogen content of 5×10 19 cm -3 The following is preferred: 5×10 18 cm -3 Less than or equal to 5×10 17 cm -3 So that it becomes as follows: The hydrogen or OH group contained in the oxide semiconductor is removed, and the carrier concentration is reduced to 5×10 1 4 cm-3 Less than or equal to 5×10 12 cm -3 The following oxide semiconductor film is used as a channel: The semiconductor device has a memory circuit formed by transistors in which a formation region is formed.

[0009] Here, the energy gap of the oxide semiconductor film is 2 eV or more, preferably 2.5 eV or more. More preferably, 3 eV or more should be set to minimize impurities such as hydrogen that form donors. The carrier concentration was increased to 1×10 14 cm -3 Less than or equal to 1×10 12 cm -3 below So that it becomes.

[0010] The thus-purified oxide semiconductor film is used for a channel formation region of a transistor. Even if the channel width is as long as 10 mm, the drain voltage is 1 V and 10 V, and the gate voltage is When the voltage is between -5V and -20V, the drain current is 1×10 -13 Below A It can be said that: Effect of the Invention

[0011] According to one embodiment of the present invention, a circuit is formed using a transistor including a highly purified oxide semiconductor film. By configuring the MOSFET, the operation of the circuit can be stabilized. In addition, the off-current is 1×10 - 13 A or less, when applied to a display device, the signal It is no longer necessary to provide an additional capacitor to hold the voltage. In this case, since each pixel does not require a storage capacitor, the aperture ratio can be improved.

[0012] According to one aspect of the present invention, when applied to a display device, a pixel is kept in a certain state (e.g., When displaying a still image, it is possible to hold the image in the state where the video signal is written. It is possible to achieve stable operation even in such a case.

[0013] According to one embodiment of the present invention, the field-effect mobility is high and the off-current is small; therefore, It is possible to realize a semiconductor device having a memory circuit which operates satisfactorily without any problems and consumes low power. A semiconductor device having such a memory circuit can be, for example, a transistor having an oxide semiconductor layer. When a transistor is provided in a pixel of a display device, a semiconductor device having a memory circuit is provided on the same substrate. This is particularly advantageous since it can be formed on a plate. [Brief description of the drawings]

[0014] [Figure 1] 1A to 1C illustrate a transistor according to one embodiment of the present invention, a manufacturing method thereof, and a capacitor according to one embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Diagram 3] 1A to 1C are diagrams illustrating initial characteristics of a transistor according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate examples of manufacturing a transistor according to one embodiment of the present invention. [Diagram 5] FIG. 13 shows Vg-Id characteristics of a transistor according to one embodiment of the present invention. [Figure 6] 1 illustrates a memory circuit (DRAM) according to one embodiment of the present invention. [Figure 7] 1A and 1B are diagrams illustrating a refresh circuit of a memory circuit according to one embodiment of the present invention. [Figure 8] 1A and 1B illustrate a memory circuit (SRAM) according to one embodiment of the present invention. [Figure 9] 1A and 1B illustrate a memory circuit (SRAM) according to one embodiment of the present invention. [Figure 10]1A to 1C illustrate a transistor according to one embodiment of the present invention and a manufacturing method thereof; [Figure 11] 1A to 1C illustrate a transistor according to one embodiment of the present invention and a manufacturing method thereof; [Figure 12] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a transistor according to one embodiment of the present invention and a manufacturing method thereof; [Figure 14] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate a transistor according to one embodiment of the present invention and a manufacturing method thereof; [Figure 17] 1A to 1C are diagrams illustrating a transistor according to one embodiment of the present invention. [Figure 18] 18 is an energy band diagram (schematic diagram) taken along the line A-A' in FIG. 17. [Figure 19] FIG. 18 is an energy band diagram (schematic diagram) taken along the line B-B' in FIG. 17. [Figure 20] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 21] FIG. 2 illustrates a CPU according to one embodiment of the present invention. [Figure 22] 1A to 1C are diagrams illustrating a wireless communication semiconductor device according to one embodiment of the present invention. [Figure 23] 1A to 1C are diagrams illustrating a wireless communication semiconductor device according to one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating a wireless communication semiconductor device according to one embodiment of the present invention. [Diagram 25] 1A to 1C are diagrams illustrating a wireless communication semiconductor device according to one embodiment of the present invention. [Figure 26] 1A to 1C are diagrams illustrating application examples of a wireless communication semiconductor device according to one embodiment of the present invention. [Figure 27] 1A and 1B illustrate an example of a display device which is one embodiment of the present invention. [Figure 28] 1A to 1C illustrate examples of electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present invention will be described below with reference to the drawings. The present invention is not limited to the above description without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and detail may be made. Therefore, the present invention should not be construed as being limited to the following embodiments and examples. In addition, when explaining the configuration of the present invention using the drawings, The reference numerals are commonly used even among different drawings.

[0016] The size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may vary. may be exaggerated for clarity and are not necessarily to scale Not limited to.

[0017] In addition, terms using ordinal numbers such as first, second, and third used in this specification refer to components. The numbers are added for the convenience of identification and are not intended to limit the number.

[0018] (Embodiment 1) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described.

[0019] First, a transistor that can be used in the semiconductor device of this embodiment will be described with reference to FIG. This will be explained in light of the above.

[0020] The transistor 110 shown in FIG. 1 is an inverted staggered transistor with a bottom gate structure. .

[0021] The transistor 110 is a transistor having a single gate structure, but may be In some cases, a transistor having a multi-gate structure having a plurality of channel formation regions may be used.

[0022] First, a conductive film is formed on a substrate 100 having an insulating surface, and then a first photolithography process is performed. The gate electrode layer 111 is formed by a deposition process. The gate electrode layer 111 may be formed by processing a conductive film using a resist mask. When the photomask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. can be reduced.

[0023] There is no significant limitation on the substrate that can be used for the substrate 100 having an insulating surface. At the very least, it is necessary for the insulation material to have sufficient heat resistance to withstand subsequent heat treatment. The substrate 100 having a surface is a barium borosilicate glass substrate or an aluminoborosilicate A glass substrate such as an acid glass substrate can be used.

[0024] The glass substrate may be made of aluminosilicate glass, aluminoborosilicate glass, A substrate made of a glass material such as barium borosilicate glass may be used, but the substrate may be damaged due to the heat treatment to be performed later. When the processing temperature is high, it is preferable to use a material having a strain point of 730° C. or higher. By including more BaO compared to B2O3, a more practical heat-resistant glass can be obtained. For this reason, it is preferable to use a glass substrate containing more BaO than B2O3.

[0025] Instead of the above glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used. Alternatively, a substrate made of crystallized glass may be used. It is also possible.

[0026] Note that an insulating film serving as a base film is provided between the substrate 100 and the gate electrode layer 111. The underlayer has a function of preventing diffusion of impurity elements from the substrate 100. A silicon film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film is selected. The insulating film may be formed by laminating one or more films.

[0027] The material of the gate electrode layer 111 is Mo, Ti, Cr, Ta, W, Al, Cu, Nd, Sc. These are made of metal materials or alloy materials that mainly contain these materials, and are formed in a single layer or laminated form. When the gate electrode layer 111 is a two-layer structure, for example, an M layer is formed on an Al layer. A structure in which an Mo layer is laminated on a Cu layer, a structure in which a TiN layer or a TiN layer is laminated on a Cu layer, or a structure in which a tantalum nitride layer is laminated, a structure in which a titanium nitride layer and a Mo layer are laminated, or It is preferable that the gate electrode has a structure in which a tungsten nitride layer and a W layer are laminated. When the pole layer 111 has three layers, it is made up of a W layer or a tungsten nitride layer and an alloy of Al and Si. The structure is a laminate of a titanium nitride layer or an alloy layer of Al and Ti and a titanium nitride layer or a Ti layer. is preferred.

[0028] Next, the gate insulating layer 102 is formed on the gate electrode layer 111 .

[0029] The gate insulating layer 102 is formed by oxidizing the gate insulating layer 102 using a plasma CVD method or a sputtering method. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an alumina oxide layer. The aluminum layer can be formed as a single layer or a laminate. For example, the source gas is Silicon oxynitride was produced by plasma CVD using SiH4 gas, oxygen gas, and nitrogen gas. The thickness of the gate insulating layer 102 is set to 100 nm or more and 500 nm or less. Alternatively, when the gate insulating layer 102 has a stacked structure of a plurality of insulating layers, for example, For example, a first gate insulating layer having a thickness of 50 nm to 200 nm and a second gate insulating layer on the first gate insulating layer. It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the gate insulating layer. Even when the layer 102 has a laminated structure of a plurality of insulating layers, the total thickness of the laminated insulating layers is The total may be between 100 nm and 500 nm.

[0030] Here, the gate insulating layer 102 is formed by a plasma CVD method to a thickness of 100 nm or less. A silicon oxynitride layer is formed.

[0031] Next, an oxide semiconductor film 1 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 102. Form 30.

[0032] Before the oxide semiconductor film 130 is formed by a sputtering method, A plasma is generated under atmospheric conditions to perform reverse sputtering, and the gate insulating layer 102 is adhered to the surface of the gate insulating layer 102. It is preferable to remove the dust that is present in the argon atmosphere. Oxygen may also be used.

[0033] The oxide semiconductor film 130 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O, The In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O system, binary metal oxides In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, Using In-Sn-O type, or In-O type, Sn-O type, or Zn-O type oxide semiconductor film Here, the oxide semiconductor film 130 is an In-Ga-Zn-O-based oxide semiconductor ter. The cross section at this stage is shown in Figure 1(A). The oxide semiconductor film 130 is heated under a rare gas (for example, argon) atmosphere with oxygen gas. Sputtering in a mixed gas atmosphere of rare gas (e.g. argon) and oxygen When the sputtering method is used, the SiO2 A target containing 2% by weight or more and 10% by weight or less may be used.

[0034] Examples of targets for forming the oxide semiconductor film 130 by a sputtering method include For example, a metal oxide target mainly composed of zinc oxide can be used. Other examples of oxide targets include oxide semiconductor targets containing In, Ga, and Zn. (The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio], In:Ga:Zn=1:1:0.5 [atom ratio]) can be used. As an oxide semiconductor target containing In, Ga, and Zn, In:Ga:Zn=1:1: 1 [atom ratio] or In:Ga:Zn=1:1:2 [atom ratio] target The filling rate of the oxide semiconductor target is preferably 90% or more and 100% or less. The filling rate is preferably 95% or more and 99.9% or less. As a result, the oxide semiconductor film formed becomes a dense film.

[0035] The sputtering gas used to form the oxide semiconductor film 130 is hydrogen, water, a hydroxyl group, or a hydride. High-quality products in which impurities such as these have been removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a pure gas. This refers to the gas that is introduced into the room.

[0036] First, the substrate is placed in a processing chamber maintained in a reduced pressure state, and the substrate temperature is increased to 100° C. or higher, up to 600° C. ℃ or less (preferably 200 ℃ or more and 400 ℃ or less). By this, the concentration of impurities in the formed oxide semiconductor film can be reduced. Damage caused by the ring is reduced. Also, hydrogen and moisture are removed while removing residual moisture in the processing chamber. The sputtering gas from which the metal oxide has been removed is introduced, and an oxide semiconductor is deposited on the substrate using the metal oxide as a target. It is preferable to use an adsorption type vacuum pump to evacuate the inside of the processing chamber. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means is preferably a turbo pump with a cold trap. From the processing chamber evacuated using a cryopump, for example, hydrogen atoms, water, etc. Since compounds containing hydrogen atoms and compounds containing carbon atoms are removed, The concentration of impurities contained in the formed oxide semiconductor film can be reduced.

[0037] For example, the oxide semiconductor film is processed with the substrate and target at a distance of 100 mm. The pressure in the room was set to 0.6 Pa, and a direct current (DC) voltage was applied in an oxygen atmosphere (oxygen flow rate 100%). The power of the power source is set to 0.5 kW. If a pulsed direct current (DC) power source is used, It is possible to suppress the generation of powdery substances (also called particles or dust) that occur during film formation, The thickness of the oxide semiconductor film to be formed is preferably 5 to 100 nm. However, the thickness is not limited to this and may be more appropriate for the oxide semiconductor material. The thickness can be selected appropriately.

[0038] Next, the oxide semiconductor film 130 is divided into island-shaped oxide semiconductor layers by a second photolithography process. Alternatively, the resist mask formed by the ink-jet method is used to process the conductive layer. Alternatively, the oxide semiconductor film 130 may be processed to form an island-shaped oxide semiconductor layer. When the inkjet method is used, no photomask is used, reducing manufacturing costs. It is possible.

[0039] Next, the oxide semiconductor layer is subjected to a first heat treatment. The semiconductor layer can be dehydrated or dehydrogenated. The temperature should be from 400° C. to below the distortion point of the substrate. In this example, the substrate 100 is carried into an electric furnace, which is one type of heat treatment device, and the oxide semiconductor layer is After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the material was oxidized without being exposed to air. The re-incorporation of water or hydrogen into the oxide semiconductor layer is prevented, and an oxide semiconductor layer 131 is obtained (FIG. 1(B)).

[0040] The heat treatment device is not limited to the electric furnace described above, and may be a device that transfers heat from a heating element such as a resistance heating element. Alternatively, a heat treatment device having a mechanism for heating the object to be treated by thermal induction or thermal radiation may be used. For example, GRTA (Gas Rapid Thermal Anneal) equipment, LRT RTA (Rap A (Lamp Rapid Thermal Anneal) equipment, etc. A GRTA (Gradual Thermal Anneal) device can be used. The apparatus is a heat treatment apparatus that uses high-temperature gas for heating. Unlike rare gases such as argon or nitrogen gas, it does not react easily with the workpiece when heated. Inert gas is used. LRTA devices use halogen lamps, metal halide lamps, Xenon arc lamp, carbon arc lamp, high pressure sodium lamp or high pressure mercury lamp Heat treatment equipment that heats the workpiece by radiating light (electromagnetic waves) from lamps such as It is located.

[0041] For example, in the first heat treatment, a treatment chamber filled with high-temperature gas at 650°C to 700°C is The substrate is carried into the processing chamber, exposed to the high-temperature gas for several minutes, and then carried out from the processing chamber (GRTA). The use of such a GRTA allows for heat treatment in a short period of time.

[0042] In the first heat treatment, the gas introduced into the treatment chamber is nitrogen or helium. The rare gases, such as uranium, neon, or argon, do not contain water or hydrogen. Alternatively, the nitrogen, helium, neon or arsenic introduced into the heat treatment device may be The purity of rare gases such as nitrile is 6N (99.9999%) or more, preferably 7N (99.9 9999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to set the above.

[0043] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, the crystallization rate is 90% or more. In some cases, the first heat treatment condition is 80% or more, or the film is a microcrystalline film. Depending on the material of the oxide semiconductor layer, the oxide semiconductor film may be an amorphous oxide semiconductor film that does not contain crystalline components. In some cases, microcrystals (grain size 1 nm to 20 nm (e.g. 2 nm)) are present in the amorphous film. There may be cases where a mixture of 4nm or more) is used.

[0044] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, the second heat treatment may be performed on the semiconductor film 130. The substrate is then removed from the substrate and processed into island-shaped oxide semiconductor layers through a photolithography process. good.

[0045] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After forming the oxide semiconductor layer, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, or after forming the source electrode and the drain electrode on the oxide semiconductor layer, After forming a protective insulating film on the source electrode and the drain electrode, good.

[0046] In addition, when a contact hole is formed in the gate insulating layer 102, the oxide semiconductor film 1 This may be carried out before the dehydration or dehydrogenation treatment in step 30, or after the dehydration or dehydrogenation treatment. After this, a contact hole may be formed in the gate insulating layer 102 .

[0047] Next, a conductive film is formed over the gate insulating layer 102 and the oxide semiconductor layer 131. The conductive film may be formed by sputtering or vacuum deposition. The elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the components thereof In addition, Mn, The conductive film may be made of one or more of the following materials: Mg, Zr, Be, and Th. The structure may be a single layer or a laminate of multiple layers. For example, an Al film containing Si A single-layer structure with a Ti film on an Al film, a two-layer laminate structure with a Ti film on an Al film, and an Al film with two Ti films. Alternatively, when the conductive film is an Al film, Nd Alternatively, Sc may be contained. These films may be nitride films.

[0048] Next, the conductive film is processed by a third photolithography process to form a source electrode layer 115. a and drain electrode layer 115b are formed. Then, the resist mask is removed (FIG. 1( C).

[0049] The third photolithography process uses ultraviolet light and KrF for exposure when forming the resist mask. Laser light or ArF laser light may be used. The distance between the source and drain electrode layers defines the channel of the transistor that will be formed later. When the exposure is performed for a channel length L of less than 25 nm, the third photolithography is performed. The exposure time for forming the resist mask in the lithography process is extremely short, ranging from a few nm to a few tens of nm. This is done using short Extreme Ultra Violet rays. The exposure by this method has high resolution and a large depth of focus. It is also possible to set the channel length L to 10 nm or more and 1000 nm or less, and the operating speed of the circuit can be increased. This enables high speed operation and, since the off-current value is extremely small, low power consumption can also be achieved.

[0050] Note that the conductive film is etched so as not to remove the oxide semiconductor layer 131. Therefore, it is necessary to appropriately adjust the materials and etching conditions.

[0051] Here, a Ti film is used as the conductive film, and an In-Ga-Zn Using -O-based oxide semiconductor, ammonia hydrogen peroxide (ammonia, water, hydrogen peroxide) was used as an etchant. A mixture of hydrogen peroxide and water is used.

[0052] Note that in the third photolithography step, the oxide semiconductor layer 131 is only partially etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). 115a, a resist mask for forming the drain electrode layer 115b is formed by the inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, the manufacturing cost can be reduced.

[0053] Alternatively, the oxide semiconductor layer 131 and the source electrode layer 115a and the drain electrode layer 115b An oxide conductive layer may be formed between the source electrode layer and the oxide conductive layer. The conductive layer for forming the drain electrode layer can be formed in succession. The oxide conductive layer can function as the source and drain regions.

[0054] The source and drain regions are formed by using an oxide semiconductor layer and a source electrode layer and a drain electrode layer. By providing an oxide conductive layer between the source region and the drain region, the resistance of the source region and the drain region can be reduced. This makes it possible to increase the operating speed of the transistor.

[0055] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The etching process may be performed using a resist mask formed from a gradation mask.

[0056] Next, plasma treatment is performed using nitrous oxide gas, nitrogen gas, Ar gas, or the like. The plasma treatment removes adsorbed water and the like from the exposed surface of the oxide semiconductor layer. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen gas and Ar. After the plasma treatment, the exposed oxide semiconductor layer was heated without being exposed to air. An insulating oxide layer 116 is formed to be a protective insulating film in contact with the surface.

[0057] The insulating oxide layer 116 has a thickness of at least 1 nm. It is formed using a method (such as sputtering) that does not mix with impurities such as water and hydrogen. When the insulating oxide layer 116 contains hydrogen, the hydrogen penetrates into the oxide semiconductor layer. Hydrogen enters the oxide semiconductor layer or extracts oxygen from the oxide semiconductor layer, and the insulating oxide of the oxide semiconductor layer is formed. The portion in contact with the layer 116 becomes low-resistance (N-type), and a parasitic channel is formed. Therefore, the insulating oxide layer 116 should contain as little hydrogen as possible. It is important to form it so that

[0058] Here, a silicon oxide film having a thickness of 200 nm is formed as the insulating oxide layer 116 by sputtering. The substrate temperature during the formation is set to room temperature or higher and 300° C. or lower. Here, the temperature is set to 100°C. The formation of the silicon oxide film by the sputtering method is performed using a rare gas (e.g. In an atmosphere of oxygen gas, or in a mixture of rare gas (e.g. argon) and oxygen gas, The target is a silicon oxide gas. A silicon target or a silicon target can be used. Using a sintered body, an oxide film was deposited by sputtering in a mixed gas atmosphere of oxygen and nitrogen gas. The insulating oxide formed in contact with the oxide semiconductor layer having a low resistance can be formed. The oxide layer 116 does not contain impurities such as moisture, hydrogen ions, and hydroxyl groups, and these impurities are not absorbed from the outside. For example, a silicon oxide film or an oxynitride film is used as an inorganic insulating film to block the penetration of oxygen from the A silicon film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0059] At this time, it is preferable to form the insulating oxide layer 116 while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 131 and the insulating oxide layer 116 contain hydrogen, a hydroxyl group, or moisture. This is to prevent this from happening.

[0060] As described above, it is preferable to use an adsorption type vacuum pump to evacuate the processing chamber. By using an adsorption type vacuum pump, the concentration of impurities contained in the insulating oxide layer 116 can be reduced. It can be reduced.

[0061] The sputtering gas used to form the insulating oxide layer 116 is hydrogen, water, hydroxyl, or hydride. High-quality products in which impurities such as these have been removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a pure gas.

[0062] Next, a second heat treatment is performed. The temperature of the second heat treatment is preferably 200° C. or higher. The temperature is preferably 250° C. or higher and 350° C. or lower. The heat treatment may be performed in an inert gas atmosphere or an oxygen gas atmosphere. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen gas atmosphere. This is performed with a part of the conductor layer (channel formation region) in contact with the insulating oxide layer 116 .

[0063] Through the above steps, the oxide semiconductor film after formation is dehydrated or dehydrogenated. The oxide semiconductor film is selectively heated to a state in which there is an excess of oxygen. As a result, the conductivity of the channel formation region 113 overlapping with the gate electrode layer 111 is reduced. The high-resistance source region 114a overlaps the source electrode layer 115a, forming an I-shaped structure. A high-resistance drain region 114b overlapping the drain electrode layer 115b is formed in a self-aligned manner. In the above steps, a transistor 110 is formed (FIG. 1(D)).

[0064] Furthermore, in the atmosphere, the temperature is set to 100° C. or higher and 200° C. or lower for 1 hour or longer and 30 hours or shorter. Heat treatment may be performed. Here, heat treatment is performed at 150° C. for 10 hours. The heating may be performed by keeping the temperature constant, or by heating from room temperature to 100°C to 200°C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be carried out under reduced pressure before the formation of the insulating oxide layer. By carrying out the heating process under reduced pressure, the heating time can be shortened. In addition, the insulating oxide layer can be used to form a defect-free transistor. When a silicon oxide layer containing a large amount of silicon is used, the heat treatment can reduce defects. can be done.

[0065] Note that the oxide semiconductor layer overlapping with the drain electrode layer 115b (and the source electrode layer 115a) A high-resistance drain region 114b (or a high-resistance source region 114a) is provided in the layer. This improves the reliability of the transistor. By forming the anti-drain region 114b, a high resistance drain is formed from the drain electrode layer 115b. The conductivity of the region 114b and the channel forming region 113 is changed stepwise. Therefore, a wiring for supplying a high power supply potential Vdd to the drain electrode layer 115b can be provided. When the electrodes are connected to each other, the potential between the gate electrode layer 111 and the drain electrode layer 115b is Even if the difference is large, the high-resistance drain region 114b acts as a buffer to The withstand voltage of the semiconductor device can be increased.

[0066] In addition, the high-resistance source region 114a or the high-resistance drain region 1 When the oxide semiconductor layer has a thickness of 15 nm or less, the oxide semiconductor layer 14b is formed over the entire thickness direction. However, when the thickness of the oxide semiconductor layer is as large as 30 nm or more and 50 nm or less, In a part of the compound semiconductor layer (the area in contact with the source electrode layer or the drain electrode layer and its vicinity), Then, a high-resistance source region 114a or a high-resistance drain region 114b is formed, and an oxide semiconductor The region of the body layer close to the gate insulating film may be made I-shaped.

[0067] A protective insulating layer may be further formed on the insulating oxide layer 116. As the layer, for example, a silicon nitride film is formed by using an RF sputtering method. The tarpaulin method is suitable for mass production and is therefore preferred as a method for forming the protective insulating layer. It does not contain impurities such as moisture, hydrogen ions, or hydroxyl groups, and prevents these from entering from the outside. The insulating film is formed using an inorganic insulating film capable of blocking the electric field. For example, a silicon nitride film, a nitride An aluminum film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like is used. A protective insulating layer 103 is formed using a silicon nitride film (FIG. 1(E)).

[0068] Here, the substrate 100 on which the insulating oxide layer 116 is formed as the protective insulating layer 103 is The material is brought into the processing chamber and heated to a temperature between 100℃ and 400℃, where hydrogen and moisture are removed. A sputtering gas containing high-purity nitrogen gas was introduced into the processing chamber, and the silicon target was Here, the protective insulating layer 103 is formed by using an insulating oxide layer. As in the case of forming 116, it is preferable to perform this while removing residual moisture in the processing chamber.

[0069] Note that a planarization insulating layer for planarization may be provided over the protective insulating layer 103.

[0070] As described above with reference to FIG. 1, the semiconductor device of this embodiment can be manufactured. In addition, a capacitor element can be simultaneously manufactured by the above process. The gate electrode layer 111 and the source electrode layer 115a (and the drain electrode layer 115b) are formed on the same The gate electrode layer 111 is formed of a gate insulating layer 102. A gate insulating layer 102 is provided on the gate insulating layer 102 (see FIG. 1(F)). When a transistor is manufactured, the capacitor element is also formed by forming a gate electrode layer and a source electrode layer. and a gate insulating layer between the gate electrode layer and the source electrode layer. However, the semiconductor device of this embodiment is not limited to this, and may have the configuration shown in FIG. FIG.

[0071] In fabricating the transistor 140 shown in FIG. 2, first, a gate electrode layer is formed on the substrate 120. 121, and then a first gate insulating layer 122a and a second gate insulating layer 122b are laminated. Here, the gate insulating layer is formed as a two-layer stack structure, and the first gate insulating layer 122 An insulating nitride layer is disposed on a, and an insulating oxide layer is disposed on the second gate insulating layer 122b.

[0072] The insulating oxide layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. Alternatively, an aluminum oxynitride layer or the like can be used. is a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer. A layer of tungsten or the like can be used.

[0073] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 121 side. The first gate insulating layer 122a is formed by sputtering to a thickness of 50 A silicon nitride layer (SiNy(y>0 )) is formed on the first gate insulating layer 122a as a second gate insulating layer 122b. A silicon oxide layer (SiOx(x) with a thickness of 5 nm to 300 nm (here, 100 nm thick) >0)) to form a gate insulating layer (here, 150 nm thick). do.

[0074] Next, an oxide semiconductor film is formed over the gate insulating layer, and the oxide semiconductor film is photolithographically The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer by a lithography process. Formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. do.

[0075] The oxide semiconductor film is preferably formed while removing moisture remaining in a treatment chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the semiconductor film. It is preferable to use an adsorption type vacuum pump for exhausting the inside of the chamber.

[0076] The sputtering gas used for forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High-purity gas with impurities removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a .

[0077] Next, a first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the heat treatment in step 1 may be 400° C. or higher and 750° C. or lower, and preferably 400° C. or higher. The temperature must be below the distortion point of the upper substrate. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. However, if the temperature is less than 425° C., the heat treatment time is preferably longer than 1 hour. Here, the substrate is carried into an electric furnace, which is a type of heat treatment device, and a nitride film is formed on the oxide semiconductor layer. After the heat treatment in a nitrogen atmosphere, the oxide semiconductor layer was not exposed to the air. The oxide semiconductor layer is obtained by preventing the re-incorporation of water or hydrogen into the oxide semiconductor layer. , high purity N2O gas, or ultra-dry air (dew point below -40℃, preferably below -60℃) The oxygen gas or N2O gas must not contain water or hydrogen. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment device is preferably 6 N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., acid The concentration of impurities in the nitrogen gas or N2O gas is 1 ppm or less, preferably 0.1 ppm or less. ) is preferable.

[0078] The heat treatment device used here is not limited to an electric furnace, and may be any device that uses a heating element such as a resistance heating element. A heat treatment device equipped with a mechanism for heating the object to be treated by thermal conduction or thermal radiation may be used. For example, an RTA device such as a GRTA device or an LRTA device may be used. Then, the RTA method is used to perform heat treatment at 600°C to 750°C for several minutes.

[0079] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Preferably, heating is performed at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. Processing may be carried out.

[0080] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the The substrate is removed and a photolithography process is performed.

[0081] Through the above steps, the entire oxide semiconductor film can be made into an oxygen-excess state. Therefore, the entire surface of the oxide semiconductor layer 132 can be made i-type. It is possible.

[0082] Next, a conductive film is formed over the second gate insulating layer 122b and the oxide semiconductor layer 132. A resist mask is formed on the conductive film by a photolithography process, and the conductive film is selectively etched. After forming the source electrode layer 135a and the drain electrode layer 135b by etching, The mask is removed, and an insulating oxide layer 136 is formed by sputtering.

[0083] At this time, it is preferable to form the insulating oxide layer 136 while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 132 and the insulating oxide layer 136 contain hydrogen, a hydroxyl group, or moisture. This is to prevent the inside of the processing chamber from being evacuated. is preferred.

[0084] The sputtering gas used in forming the insulating oxide layer 136 is hydrogen, water, a hydroxyl group, or Impurities such as hydrides are removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a high purity gas that has been

[0085] Next, in order to reduce the variation in the electrical characteristics of the transistors in the substrate plane, Heat treatment in an atmosphere of acid gas or nitrogen gas (preferably 150°C or higher but less than 350°C). Here, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0086] In addition, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. Here, the heat treatment is performed at 150° C. for 10 hours. The heating may be performed by keeping the temperature at 100° C. or higher and heating the temperature to 100° C. or higher and 200° C. or lower. The heating temperature may be repeatedly lowered to room temperature several times. The heat treatment may be carried out under reduced pressure before the formation of the insulating oxide layer. This heat treatment reduces the heating time. You can get transistors.

[0087] Next, a protective insulating layer 123 is formed on the insulating oxide layer 136. As the film 123, a silicon nitride film is formed to a thickness of 100 nm by sputtering.

[0088] By forming the protective insulating layer 123 and the first gate insulating layer 122a as insulating nitride layers, water It does not contain impurities such as hydrogen, hydrides, and hydroxides, and blocks the intrusion of these substances from the outside. It is also possible to

[0089] Therefore, it is possible to prevent the intrusion of moisture from the outside during the manufacturing process. Even after a semiconductor device, such as a liquid crystal display device, is completed, the device may be damaged due to long-term exposure to external This prevents the intrusion of impurities such as moisture, improving the long-term reliability of devices. It is possible.

[0090] In addition, the protective insulating layer 123 made of an insulating nitride layer and the first gate insulating layer 122a The insulating layer provided between the first and second gate insulating layers 122a and 123a is removed. A structure in contact with the surface may also be used.

[0091] Note that a planarization insulating layer for planarization may be provided over the protective insulating layer 123.

[0092] As described above with reference to FIG. 2, the semiconductor device of this embodiment can be manufactured. Cut.

[0093] In this embodiment, the temperature of the heat treatment is not limited to the above. Thus, the temperature of the heat treatment may be less than 400°C.

[0094] Note that hydrogen, a hydroxyl group, and moisture are preferably not contained in the gate insulating layer and the oxide semiconductor film. As a pretreatment, the substrate on which the gate electrode layer is formed is heated in the preheating chamber of the sputtering device. The substrate on which the plate or gate insulating layer has been formed is preheated, and hydrogen or water adsorbed on the substrate is removed. It is advisable to remove impurities such as oxygen and exhaust them. The preheating temperature should be 100℃ or higher. The preheating chamber is preferably at least 150°C and at most 300°C. It is preferable that a cryopump is connected to the preheating chamber and the preheating chamber is evacuated by the cryopump. It is preferable that the pre-heating is performed before the insulating oxide layer is formed on the source electrode layer. The same procedure may be carried out on a substrate on which up to the drain electrode layer has been formed.

[0095] The above pretreatment is suitable for LCD panels, electroluminescent display panels, electronic inks, Used in the manufacture of backplanes (substrates on which transistors are formed) for display devices and other devices The above pretreatment is carried out at a temperature of less than 400°C, so the thickness is less than 1 mm. It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 400°C, making it ideal for manufacturing display panels. This means that you don't have to consume a lot of energy to do so.

[0096] In the fabrication of the above-described transistor, the gate insulating layer is also formed by sputtering. However, this is not limited to the above. For example, A chemical vapor deposition (CVD) method may also be used.

[0097] Next, the off-state current of the evaluation element (TEG) in which the above transistor was formed was measured. This is explained below.

[0098] Figure 4(A) shows 200 transistors with L / W = 3 μm / 50 μm connected in parallel (L / The top view of the transistor with a width of 3 μm / 10,000 μm is shown. FIG. 4(B) shows an enlarged top view of a part of the structure. The area surrounded by the dotted line in FIG. 4(B) is the L / The transistor has W=3μm / 50μm and Lov=1.5μm. The temperature was room temperature. Figure 3 shows the results when the source-drain voltage (drain voltage Vd) was 1 V or The source-gate voltage (gate voltage Vg) is set to 10V and changed from -20V to +20V. The change in the source-drain current (drain current Id) when the In addition, in FIG. 3, Vg is shown in the range of −20V to +5V.

[0099] As shown in FIG. 3, when Vd is 1 V and when Vd is 10 V, the off-state current is 1×10 -13 This value is less than [A]. The resolution of the Agilent 4156C (Agilent) is less than 100 fA. A method for manufacturing a transistor with extremely low off-state current will be described below. do.

[0100] First, a silicon nitride layer is formed on a glass substrate as a base layer by the CVD method. A silicon oxynitride layer was formed on the silicon layer. A tungsten film was formed as the electrode layer by sputtering. The silicon film was selectively etched to form a gate electrode layer.

[0101] Next, a 100 nm thick oxide film was formed on the gate electrode layer by CVD as a gate insulating layer. A silicon nitride layer was formed.

[0102] Next, an In-Ga-Zn-O oxide semiconductor was deposited on the gate insulating layer by sputtering. Using a solid target (In2O3:Ga2O3:ZnO=1:1:2 (molar ratio)) Then, an oxide semiconductor film having a thickness of 50 nm was formed. Here, the oxide semiconductor film was selectively etched. Then, island-shaped oxide semiconductor layers were formed.

[0103] Next, the oxide semiconductor layer is heated to 450° C. in a nitrogen atmosphere using a clean oven. Then, a heat treatment (first heat treatment) was carried out for 1 hour.

[0104] Next, a titanium layer (thickness 1 The source electrode layer and the drain electrode layer were formed by sputtering. The layers are selectively etched to reduce the channel length L of one transistor to 3 μm and the channel width W By connecting 200 pieces in parallel, the L / W ratio is 3μm / 10000μm. I made it happen.

[0105] Next, a protective insulating layer was formed by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer was then selectively etched. The gate electrode layer, the source electrode layer, and the drain electrode layer were then subjected to etching to form openings. Then, a heat treatment (second heat treatment) was carried out at 250° C. for 1 hour in a nitrogen atmosphere. Before measuring the Vg-Id characteristics, the device was heat-treated at 150°C for 10 hours in an inert atmosphere. In this manner, an inverted staggered transistor with a bottom gate structure was fabricated.

[0106] As shown in Figure 3, the off-state current of the transistor is 1×10 -13 Very small, below [A] The reason is that the hydrogen concentration in the oxide semiconductor layer could be sufficiently reduced in the above manufacturing process. Here, the hydrogen concentration in the oxide semiconductor layer is 5×10 19 cm -3 The following are the preferred Or 5×10 18 cm -3 Less than 5×10, more preferably 17 cm -3 The following applies. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This can be done using standard ion mass spectroscopy (NMS).

[0107] Although an example using an In-Ga-Zn-O-based oxide semiconductor is shown here, there is no particular limitation. However, other oxide semiconductor materials, such as In-Sn-Zn-O, Sn-Ga-Zn -O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, In- Sn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn-O Alternatively, as the oxide semiconductor material, AlOx at 2.5 to 1 In-Al-Zn-O system containing 0 wt% SiOx, and In-Al-Zn-O system containing 2.5 to 10 wt% SiOx An n-Zn-O based material may also be used.

[0108] The carrier density of the oxide semiconductor layer is 5×10 14 cm -3 Less than or equal to 5×10 1 2 cm -3 Less than 1.45×10, more preferably 10 cm -3 Equal to or greater than That is, the carrier concentration of the oxide semiconductor layer can be made as close to zero as possible. do.

[0109] In addition, the channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. It is Noh.

[0110] In addition, when the transistor is off, the oxide semiconductor layer acts as an insulator in the circuit design. It is possible to do so.

[0111] Next, we evaluated the temperature dependence of the off-current of the above transistor. Temperature dependency is important for the environmental resistance of the final product in which the transistor is used, and for maintaining its performance. It is important to consider the above. Naturally, it is preferable that the temperature dependence of the off-current is small. This increases the freedom of product design.

[0112] Temperature dependence was measured by keeping the substrate on which the transistor was formed at a constant temperature in a thermostatic chamber and measuring the drain The Vg-Id curve was obtained by changing the gate voltage from -20V to +20V and the on-voltage from 6V. The temperature was maintained at -30, 0, 25, 40, The temperatures were either 60, 80, 100, or 120°C.

[0113] FIG. 5(A) shows the Vg-Id curves measured at each of the above temperatures, and FIG. 5(B) shows The curve on the right side indicated by the arrow in the figure is -30°C. The leftmost curve is obtained at 120°C, and the other curves are obtained at other temperatures. The curve is located between them. The on-current has almost no temperature dependence. The gate current is close to the resolution of the measuring instrument at all temperatures until the gate voltage drops to about -20V. 1×10 -12 [A] or less, and almost no temperature dependence is observed. Even at a high temperature of 120°C, the off-state current is 1×10 -12 [A] or lower has been maintained, Considering that the channel width W is 10000 μm, the off-current of this transistor is It turns out to be very small.

[0114] A transistor using a highly purified oxide semiconductor (purified OS) The temperature dependence of the gate current is almost nonexistent. This is because the oxide semiconductor is highly purified. Therefore, the conductivity type approaches the intrinsic type and the Fermi level is located in the center of the forbidden band. This is because the temperature dependence is eliminated. This is also due to the fact that the gap is 3 eV or more and there are very few thermally excited carriers. The source and drain regions are in a degenerate state, which is also the reason why no temperature dependence appears. The transistor operates by using electrons injected from the degenerate source region into the oxide semiconductor. The above-mentioned characteristic is due to the fact that most of the phenomenon is caused by carriers and the carrier density does not depend on temperature. This can explain the lack of temperature dependence of the off-state current.

[0115] Such a transistor with an extremely low off-state current can be used for a memory circuit (memory element) or the like. When such a device is fabricated, the off-current is small and there is almost no leakage, so the stored data is retained. The time for which the

[0116] Next, a semiconductor device to which the above-described transistor is applied will be described.

[0117] FIG. 6 is a block diagram of an example of a memory circuit. The memory circuit shown in FIG. 152, a write and refresh circuit 154, a column decoder 156, and a write and The memory device includes a refresh circuit 158 ​​and a plurality of memory elements 150 arranged in a matrix. The signal lines connected to the memory elements 150 arranged in a matrix form are used for writing and reflecting. The memory cells are connected to the row decoder 152 via a memory cell 154 and arranged in a matrix. The scan lines connected to the elements 150 are coupled to column decoders 156 via write and refresh circuits 158. The row decoder 152 is connected to a row decoder 156. A bit signal is input to the row decoder 152. The read / write enable signal (R E / WE), data signal (DATA), output signal (OUT), and write The signal is output from the write and refresh circuit 154.

[0118] Each of the memory elements 150 includes a capacitor and a transistor. One of the source and drain of the transistor is connected to a signal line, and the other of the source and drain of the transistor is connected to a signal line. is connected to one electrode of the capacitance element, and the other electrode of the capacitance element is connected to a low potential (preferably a substrate). It is connected to the wiring on the sub-potential (Vss) side.

[0119] FIG. 7 illustrates a refresh circuit that can be provided in the write and refresh circuit 154 shown in FIG. The write and refresh circuit 158 ​​may be a similar circuit. It can be provided as a structure.

[0120] The write and refresh circuit shown in FIG. 7 is composed of a logical product circuit (AND circuit) and a sense amplifier. The first AND circuit 160, the second AND circuit 162, and the third AND circuit 172 are A signal from the row decoder 152 is input to one input of the circuit 164. The other input of the circuit 160 receives the PRC signal, and the other input of the second AND circuit 162 A write enable signal (WE) is input to the other input of the third AND circuit 164. A read enable signal (RE) is input to the first AND circuit 160. The output of the second AND circuit 162 controls the on / off of the first switch 166. The output of the third AND circuit 164 controls the on / off of the third switch 168. The precharge signal line Vprc controls the first switch 166 to be turned on or off. The data signal line DATA is connected to the signal line DATA via a second switch 168. is connected to

[0121] The signal line connected via the first switch 166 and the second switch 168 is a third The sense amplifier 172 is connected to the switch 170. A signal is output from these to the output signal line (OUT).

[0122] The above-mentioned AND circuit may be of a general configuration and may be of a simple configuration. It is preferable.

[0123] Note that a sense amplifier refers to a circuit having a function of amplifying an input signal.

[0124] In this case, the signal may be, for example, an analog signal using a voltage, a current, a resistance, or a frequency. For example, the potential can be changed to at least a first potential. and the second potential, and the first potential is set to high level (high potential, V H It is also written as A low potential is used as the second potential (low potential, V L (also written as ) By doing so, it is possible to set a binary digital signal. H and V Lis a constant value However, taking into consideration the effect of noise, H and V L It is also acceptable to provide some width.

[0125] As described above, a memory (DRAM) circuit is fabricated using the above-mentioned transistor. It is possible.

[0126] The refresh timing of the memory circuit is determined based on the read timing of the memory element 150 that has been evaluated in advance. The refresh time can be determined at the design stage based on the refresh current. Timing is based on the temperature dependence of leakage current after the memory circuit chip is completed and the fluctuation of the manufacturing process. It is set taking into consideration the following.

[0127] The off-current of the above-mentioned transistor shows almost no temperature dependence and has an extremely small value. This allows the refresh interval to be set longer than with silicon-based transistors. This makes it possible to reduce power consumption during standby.

[0128] The memory circuit used here is not limited to the above-mentioned DRAM. For example, You can replace the child with SRAM.

[0129] FIG. 8 shows an example of a circuit configuration of an SRAM in which six transistors are provided in one memory element. Although only one memory element is shown in FIG. 8, the present invention is not limited to this. The SRAM storage element 180 shown is comprised of a transistor 186 and a transistor 188. An inverter circuit formed by a transistor 190 and a transistor 192 an inverter circuit, a transistor 182 acting as a switch transistor, and a transistor It is composed of 184 resistors.

[0130] The write operation of the SRAM shown in FIG. 8 will be described. The line is V H When this occurs, the transistors 182 and 184 are turned on, forming an inverter circuit An inverter circuit formed by a pair (transistor 186 and transistor 188; The inverter circuit formed by transistors 190 and 192 When the data writing is completed, the transistor 182 and the transistor The inverter 184 is turned off, and the data written to the inverter circuit pair is held.

[0131] Next, a read operation of the SRAM shown in FIG. 8 will be described. First, the first signal line and The second signal line is precharged to a specific potential (precharge potential) from outside the memory element array. This precharge potential should be set to the midpoint between Vdd and Vss. The first signal line and the second signal line, which are at the charge potential, are in a floating state. The rear scan line is V H This causes transistors 182 and 184 to turn on, The first signal line and the second signal line are driven in opposite directions by the inverter circuit pair, and the difference voltage is detected by a sense amplifier, and the data is read out.

[0132] The off-current of the above-mentioned transistor shows almost no temperature dependence and has an extremely small value. This allows the refresh interval to be set longer than with silicon-based transistors. This makes it possible to reduce power consumption during standby.

[0133] When using SRAM as memory, the number of transistors is limited to six. It is not something that is done.

[0134] FIG. 9 shows the circuit configuration of an SRAM in which four transistors are provided for one memory element. FIG. 9 shows an example of the transistor 186 and the transistor 190 of the SRAM shown in FIG. is replaced with a resistive element 194 and a resistive element 196.

[0135] Even with the SRAM circuit configuration shown in Fig. 9, the link is smaller than that of silicon-based transistors. The refresh interval can be set longer, reducing power consumption during standby. Cut.

[0136] As described above, a semiconductor device which is one embodiment of the present invention can be achieved.

[0137] (Embodiment 2) In this embodiment mode, a transistor that can be used in the semiconductor device described in the first embodiment mode is The following describes the differences between the first and second embodiments.

[0138] FIG. 10 shows a cross-sectional structure of a transistor according to this embodiment. The transistor 220 is a bottom gate transistor called a channel protection type (or a channel stop type). The transistor 220 is formed on the substrate 200. The process is described below.

[0139] First, a conductive film is formed on a substrate 200 having an insulating surface, and a first photolithography process is performed. The conductive film is processed to form a gate electrode layer 202 .

[0140] The material for forming the gate electrode layer 202 is the same as that for the gate electrode layer 111. Alternatively, a plurality of layers may be laminated.

[0141] The resist mask may be formed by an ink-jet method. The jet method does not require a photomask, which reduces manufacturing costs. Cut.

[0142] Next, a gate insulating layer 204 is formed to cover the gate electrode layer 202. As the gate insulating layer 204, a silicon oxynitride layer is formed by a plasma CVD method. good.

[0143] Next, an oxide semiconductor film is formed over the gate insulating layer 204 and then subjected to a second photolithography process. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer by a process. In this embodiment, the oxide semiconductor film is formed to a thickness of 200 nm or more. The film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. At this time, it is preferable to perform sputtering while removing residual moisture in the processing chamber. This is to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film. As described in the first embodiment, an adsorption type vacuum pump is used to evacuate the processing chamber. It is preferable that

[0144] Here, the sputtering gas used for forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or a hydrogen Impurities such as chlorides are removed to a concentration of 1 ppm or less (preferably 10 ppb or less). In addition, it is preferable to use a high purity gas.

[0145] Next, the oxide semiconductor layer is subjected to first heat treatment in a manner similar to that of Embodiment 1. The substrate 200 is carried into an electric furnace, which is one type of heat treatment device, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in the atmosphere, the oxide semiconductor Re-incorporation of water or hydrogen into the layer is prevented, and an oxide semiconductor layer 206 is obtained (FIG. 10A).

[0146] Next, a plasma treatment may be performed using gas such as N2O, N2, or Ar. Water and the like adhering to the surface of the exposed oxide semiconductor layer 206 is removed by the plasma treatment. The plasma treatment may be performed using a mixed gas of O2 and Ar.

[0147] Next, an insulating oxide film is formed on the gate insulating layer 204 and the oxide semiconductor layer 206, and then An insulating oxide layer 208 is formed by a third photolithography process, and a resist mask is formed. Remove.

[0148] Here, for example, the insulating oxide film that becomes the insulating oxide layer 208 is a 200 nm thick insulating oxide film. A silicon oxide film is formed by sputtering. The substrate temperature during the formation is set to 30°C above room temperature. The temperature should be 0°C or lower, and here it is 100°C. (e.g., argon), oxygen, or a mixture of rare gases and oxygen. The target may be, for example, a silicon oxide target or a silicon target. For example, a silicon target can be used to produce a mixture of oxygen and nitrogen. Silicon oxide can be formed by performing a sputtering method in a mixed atmosphere. The insulating oxide layer 208 formed in contact with the oxide semiconductor layer with reduced resistance is resistant to moisture, hydrogen, and the like. It does not contain impurities such as ions and hydroxyl groups, and blocks these from entering from the outside. The insulating film may be formed of an inorganic insulating material that can be used for the insulating film. For example, the insulating film may be a silicon oxide film or an oxynitride film. A silicon film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. It is preferable to perform sputtering while removing moisture remaining in the treatment chamber. In order to prevent hydrogen, hydroxyl groups, or moisture from being contained in the insulating oxide layer 206 and the insulating oxide layer 208, Therefore, when forming the insulating oxide film, as described above, the suction type vacuum pump is used. The sputtering gas used in the formation is preferably hydrogen, water, hydroxyl or hydrogen. Impurities such as chlorine and chlorides are removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a high purity gas that has been

[0149] At this point, a second heat treatment may be performed.

[0150] The temperature of the second heat treatment is preferably 200° C. or more and 400° C. or less, and more preferably The second heat treatment is preferably performed at a temperature of 250° C. or higher and 350° C. or lower. The second heat treatment is preferably performed in an inert gas atmosphere. In this example, the heating is performed at 250°C for 1 hour under a nitrogen gas atmosphere. The second heat treatment is performed to remove part of the oxide semiconductor layer 206 (channel type oxide semiconductor layer 206). The insulating oxide layer 208 is heated while in contact with the insulating oxide layer 208.

[0151] Alternatively, a further heat treatment may be performed after the second heat treatment. The oxide semiconductor layer 206, which is partially exposed, is heated in a nitrogen gas atmosphere. Further heat treatment is performed under atmospheric air, inert gas atmosphere, or reduced pressure. The exposed regions of the oxide semiconductor layer 206 that are not covered by 08 are immersed in a nitrogen gas atmosphere. The resistance can be reduced by performing heat treatment under low pressure, in an inert gas atmosphere, or under reduced pressure. Here, for example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing heat treatment in this manner on the oxide semiconductor layer 206 provided with the oxide layer 208, As a result, the exposed region of the oxide semiconductor layer 206 has a low resistance, and the oxide semiconductor layer 206 has an oxide semiconductor layer having regions with different resistance. In FIG. 10B, the white area not indicated by the hatching is a low-temperature semiconductor layer 210. This is an area of ​​resistance.

[0152] Through the steps up to the second heat treatment, the oxide semiconductor film after formation can be Then, heat treatment for dehydration or dehydrogenation is performed to reduce the resistance of the oxide semiconductor film. As a result, the channel formation region overlapping the gate electrode layer 202 is The conductivity of the drain region decreases and becomes I-type. The high-resistance source region overlapping the source electrode layer and the drain region overlapping the source electrode layer become I-type. A high resistance drain region overlying the electrode layer is formed in a self-aligned manner.

[0153] Next, on the gate insulating layer 204, the oxide semiconductor layer 210, and the insulating oxide layer 208, After forming the conductive film, a source electrode and a drain electrode are formed by a fourth photolithography process. After the layer 212 is formed, the resist mask is removed (FIG. 10(C)).

[0154] The material for forming the source and drain electrode layer 212 is the same as that of the source electrode layer 115a and the drain electrode layer 215b. Similar to the rain electrode layer 115b, it may be a single layer or a laminate of multiple layers.

[0155] Furthermore, in the atmosphere, the temperature is set to 100° C. or higher and 200° C. or lower for 1 hour or longer and 30 hours or shorter. Heat treatment may be performed. Here, heat treatment is performed at 150° C. for 10 hours. The heating may be performed by keeping the temperature constant, or by heating from room temperature to 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be carried out under reduced pressure before the formation of the insulating oxide layer. By carrying out the treatment under reduced pressure, the heating time can be shortened. It is possible to obtain a transistor that is turned off.

[0156] Note that a high resistance is formed in the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer). By providing a drain region (or a high-resistance source region), The reliability can be improved. Specifically, by forming a high-resistance drain region, The conductivity is gradually increased from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, the drain electrode layer can be provided with a high power supply potential Vd When the wiring supplying d is connected and the device is operated, the voltage between the gate electrode layer and the drain electrode layer is Even if the potential difference is large, the high-resistance drain region acts as a buffer to reduce the withstand voltage of the transistor. can be made high.

[0157] Through the above steps, the transistor 220 is formed.

[0158] Next, a protective insulating layer is formed on the insulating oxide layer 208 and the source and drain electrode layers 212. An edge layer 214 is formed. Here, the protective insulating layer 214 is formed using, for example, a silicon nitride film. (FIG. 10(D)).

[0159] In addition, an insulating oxide layer 208 and the source and drain electrode layers 212 may be formed on the insulating oxide layer 208. A dielectric oxide layer may be formed and a protective insulating layer 214 formed over the dielectric oxide layer.

[0160] Although not shown, the transistor 220 may be provided with a plurality of gate electrodes. A transistor having a multi-gate structure having a plurality of channel forming regions may also be used.

[0161] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0162] (Embodiment 3) The present embodiment relates to a transistor that can be used in the semiconductor device described in the first embodiment. The following describes the data transfer function that is different from that of the first and second embodiments.

[0163] FIG. 11 shows a cross-sectional structure of a transistor according to this embodiment. The transistor 320 is a type of bottom gate transistor. The process for fabricating the transistor 320 is described below.

[0164] First, a conductive film is formed on a substrate 300 having an insulating surface, and a first photolithography process is performed. The conductive film is processed to form a gate electrode layer 302 .

[0165] The material for forming the gate electrode layer 302 is the same as that for the gate electrode layer 111. Alternatively, a plurality of layers may be laminated.

[0166] The resist mask may be formed by an ink-jet method. The jet method does not require a photomask, which reduces manufacturing costs. Cut.

[0167] Next, a gate insulating layer 304 is formed to cover the gate electrode layer 302. As the gate insulating layer 304, a silicon oxynitride layer is formed by a plasma CVD method. good.

[0168] Next, a conductive film is formed on the gate insulating layer 304, and a second photolithography process is performed to A source electrode and a drain electrode layer 306a and a source electrode and a drain electrode layer 306b. (Figure 11(A)).

[0169] A source electrode and a drain electrode layer 306a and a source electrode and a drain electrode layer 306b The materials for forming the source electrode layer 115a and the drain electrode layer 115b are similar to those for the source electrode layer 115a and the drain electrode layer 115b. It may be a single layer, or a plurality of layers may be laminated.

[0170] Next, a source electrode and drain electrode layer 306a and a source electrode layer 306b are formed on the gate insulating layer 304. An oxide semiconductor film 308 is formed over the electrode layer 306b (FIG. 11B). After that, the oxide semiconductor film 308 is subjected to a third photolithography process to form an island-shaped oxide At this time, similar to the first embodiment, the remaining moisture in the processing chamber is removed. In the case where hydrogen, a hydroxyl group, or a water atom is added to the oxide semiconductor film 308, sputtering is preferably performed. This is to prevent the inclusion of any residuals in the processing chamber, as described in the first embodiment. It is preferable to use an adsorption type vacuum pump for exhausting the inside of the chamber.

[0171] Next, the oxide semiconductor layer is subjected to first heat treatment in a manner similar to that of Embodiment 1. The substrate 300 is carried into an electric furnace, which is one type of heat treatment device, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in the atmosphere, the oxide semiconductor The re-incorporation of water or hydrogen into the layer is prevented, and an oxide semiconductor layer 310 is obtained (FIG. 11C).

[0172] An insulating oxide layer 314 is formed to be a protective insulating film in contact with the oxide semiconductor layer 310. The insulating oxide layer 314 has a thickness of at least 1 nm. As with the case of the insulating film, it is advisable to form the film using a method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide layer 314, the hydrogen enters the oxide semiconductor layer or The oxygen in the oxide semiconductor layer is extracted, and the oxide semiconductor layer 310 is in contact with the insulating oxide layer 314. The part that is connected to the MOSFET becomes low-resistance (N-type), and there is a risk of a parasitic channel being formed. Therefore, the insulating oxide layer 314 is formed so as to contain as little hydrogen as possible. It is important to do so.

[0173] Insulating oxide layer 314 may be formed similarly to insulating oxide layer 116 .

[0174] Next, a second heat treatment is performed. The second heat treatment can be performed in the same manner as in the first embodiment. The second heat treatment can be performed so that a part of the oxide semiconductor layer (a channel formation region) is converted into an insulating oxide layer. It is heated in contact with 314.

[0175] Through the above steps, the oxide semiconductor film after formation is dehydrated or dehydrogenated. The resistance of the oxide semiconductor film is reduced by performing heat treatment for oxidation, and the entire surface of the oxide semiconductor film is made into an oxygen-excess state. As a result, an i-type oxide semiconductor layer 312 is formed.

[0176] As described above, a transistor 320 is formed.

[0177] Furthermore, in the atmosphere, the temperature is set to 100° C. or higher and 200° C. or lower for 1 hour or longer and 30 hours or shorter. Heat treatment may be performed. Here, heat treatment is performed at 150° C. for 10 hours. The heating may be performed by keeping the temperature constant, or by heating from room temperature to 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be carried out under reduced pressure before the formation of the insulating oxide layer. By carrying out the treatment under reduced pressure, the heating time can be shortened. It is possible to obtain a transistor that is turned off.

[0178] On the insulating oxide layer 314, a protective insulating layer 31 similar to the protective insulating layer 103 is further formed. Such a protective insulating layer 316 may be formed by, for example, RF sputtering. A silicon nitride film is formed by the deposition method (FIG. 11(D)).

[0179] A planarization insulating layer for planarization may be provided on the protective insulating layer 316 .

[0180] Although not shown, the transistor 320 may be provided with a plurality of gate electrodes. A transistor having a multi-gate structure having a plurality of channel forming regions may also be used.

[0181] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0182] (Embodiment 4) The present embodiment relates to a transistor that can be used in the semiconductor device described in the first embodiment. The following describes the data transfer function that is different from the first to third embodiments.

[0183] FIG. 12A shows an example of a plan view of the semiconductor device of this embodiment, and FIG. 12(A) is a cross-sectional view taken along line C1-C2 of FIG. 12(A) and FIG. The transistor 410 is one of the top-gate structure transistors.

[0184] The transistor 410 is formed on a substrate 400 having an insulating surface, an insulating layer 407, an oxide semiconductor a gate insulating layer 402; a source electrode layer 415a; a drain electrode layer 415b; , a gate electrode layer 411, a source electrode layer 415a, and a drain electrode layer 415b. The wiring layer 414a and the wiring layer 414b are provided in contact with each other, and the source electrode layer 415a is The drain electrode layer 415b is electrically connected to the wiring layer 414b. is connected.

[0185] A process for fabricating a transistor 410 over a substrate 400 will be described below.

[0186] First, an insulating layer 407 is formed as a base film over a substrate 400 having an insulating surface. The layer 407 may be a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an oxide layer. It is preferable to use an insulating oxide layer such as an aluminum nitride layer. As a method, a plasma CVD method or a sputtering method can be used. In order to prevent impurities such as hydrogen from being contained in the edge layer 407, a sputtering method is used. It is preferable to form an insulating layer 407 .

[0187] Here, as the insulating layer 407, a silicon oxide layer is formed by a sputtering method. The substrate 400 is carried into a processing chamber, and a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is used. The gas is introduced into the processing chamber and a silicon oxide layer is formed using a silicon or quartz target. The substrate 400 may be at room temperature or may be heated.

[0188] At this time, it is preferable to perform sputtering while removing residual moisture from within the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the insulating layer 407. As described in the first embodiment, an adsorption type vacuum pump can be used to evacuate the processing chamber. preferable.

[0189] Here, the sputtering gas used to form the insulating layer 407 is hydrogen, water, a hydroxyl group, or a hydride. Impurities such as these have been removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use high purity gases.

[0190] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer from the substrate 400 side, An insulating nitride layer such as a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer The insulating layer may have a laminated structure of a nitride layer and the insulating oxide layer.

[0191] For example, a silicon oxide layer and a substrate are provided with a space between them that contains high-purity nitrogen from which hydrogen and moisture have been removed. A putter gas is introduced into the processing chamber, and a silicon nitride layer is formed using a silicon target. In this case, as in the case of the silicon oxide layer, the nitriding process is performed while removing the residual moisture in the processing chamber. It is preferable to form a silicon layer.

[0192] When the insulating layer 407 is formed by laminating a silicon oxide layer on a silicon nitride layer, The silicon layer and silicon oxide layer are processed in the same processing chamber using a common silicon target. First, a sputtering gas containing nitrogen is introduced into the processing chamber. A silicon nitride layer is formed by sputtering using a silicon target of Then, the gas introduced into the processing chamber was changed to a sputtering gas containing oxygen, and the same silicon ter A silicon oxide layer is formed using a target. The silicon layer and silicon oxide layer can be formed successively without exposure to air, so nitridation is It is possible to prevent impurities such as hydrogen and moisture from being adsorbed on the surface of the silicon layer.

[0193] Next, an oxide semiconductor film is formed over the insulating layer 407. It is preferable to form the film by a coating method to a thickness of 2 nm or more and 200 nm or less.

[0194] In addition, in order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, a pretreatment The substrate 400 on which the insulating layer 407 is formed is preheated in a preheating chamber of a sputtering device. Impurities such as hydrogen or moisture adsorbed on the substrate 400 may be desorbed and exhausted by heating. The preheating chamber is connected to a cryopump, and the preheating chamber is heated by the cryopump. In addition, this pre-heating pretreatment is preferably performed in order to prevent the gate This may be performed on the substrate 400 before the formation of the insulating layer 402, or on the source electrode layer 415 to be formed later. The same process may be performed on the substrate 400 on which the layers up to the drain electrode layer 415a and the drain electrode layer 415b have been formed.

[0195] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or a hydrogenated High-temperature filter in which impurities such as fluoride have been removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a pure gas.

[0196] The oxide semiconductor film is heated by a spa from which hydrogen and moisture are removed while removing moisture remaining in the treatment chamber. A target gas is introduced into the processing chamber, and a metal oxide is formed as a target. For evacuation, it is preferable to use an adsorption type vacuum pump.

[0197] Next, the oxide semiconductor film is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is formed by ink jet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing cost can be reduced.

[0198] The etching of the oxide semiconductor film may be performed by dry etching or wet etching. Alternatively, these may be used in combination.

[0199] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. Reactive ion etching (ICP) and Inductively Coupled Plasma (ICP) Inductively Coupled Plasma (ICP) etching techniques can be used.

[0200] The etchant used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia hydrogen peroxide (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) Specifically, a transparent conductive film etcher manufactured by Kanto Chemical Co., Ltd. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.), which is commercially available as a conductive material, may be used.

[0201] In addition, the etchant after wet etching is washed away together with the etched material. The waste liquid of the etchant containing the removed material is refined, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By collecting and reusing materials such as these, it is possible to make effective use of resources and reduce costs. Cut.

[0202] Here, a wet etchant solution containing phosphoric acid, acetic acid, and nitric acid is used. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer by a etching method.

[0203] Next, the oxide semiconductor layer is subjected to first heat treatment in a manner similar to that in Embodiment 1. The substrate 400 is carried into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After heat treatment at 450℃ for 1 hour in an atmosphere, the oxide semiconductor was removed by not exposing it to the air. The re-incorporation of water and hydrogen into the oxide layer is prevented, and an oxide semiconductor layer 412 is obtained (FIG. 13(A)).

[0204] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the The substrate is taken out and a photolithography process is performed.

[0205] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After forming the oxide semiconductor layer, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, or after forming the source electrode and the drain electrode on the oxide semiconductor layer, After forming the gate insulating layer on the source electrode and the drain electrode, good.

[0206] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film may be formed in a similar manner to the conductive film which is to be the source electrode layer 115a and the drain electrode layer 115b. .

[0207] Next, a resist mask is formed over the conductive film by a second photolithography process. The conductive film is processed to form the source electrode layer 415a and the drain electrode layer 415b. The resist mask is removed (FIG. 13(B)). If the ends of the electrode layer are tapered, the gate insulating layer formed by laminating them on the electrode layer has good coverage. This is preferable because it improves the

[0208] Here, a Ti film is used as the conductive film, and an In-Ga- Using Zn-O-based oxide semiconductor, ammonia hydrogen peroxide (ammonia, water) was used as an etchant. A mixture of hydrogen peroxide and water is used.

[0209] Note that in the second photolithography step, the oxide semiconductor layer 412 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). A resist mask for forming the drain electrode layer 415a and the drain electrode layer 415b is formed by inkjet printing. If the resist mask is formed by the inkjet method, a photomask can be used. Since no additional heat treatment is required, the manufacturing cost can be reduced.

[0210] The exposure to light during the formation of the resist mask in the second photolithography process uses ultraviolet light and KrF Laser light or ArF laser light is preferably used. Note that exposure with a channel length L of less than 25 nm is recommended. When carrying out this treatment, extreme ultraviolet rays with extremely short wavelengths of several nm to several tens of nm are used. It is recommended to use tetra Violet.

[0211] Next, the insulating layer 407, the oxide semiconductor layer 412, the source electrode layer 415a, and the drain electrode layer 415b are A gate insulating layer 402 is formed on the electrode layer 415b (FIG. 13(C)).

[0212] The gate insulating layer 402 can be formed in a similar manner to the gate insulating layer 102 .

[0213] Next, a resist mask is formed by a third photolithography process, and selectively etched. A part of the gate insulating layer 402 is removed by etching to form the source electrode layer 415a and the drain electrode layer 415b. An opening 421a and an opening 421b are formed so as to reach the gate electrode layer 415b (FIG. 13(D)).

[0214] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b, and then A gate electrode layer 411, a wiring layer 414a, and a wiring layer 414 are formed by a fourth photolithography process. The resist mask 14b may be formed by an ink-jet method. When the photomask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. can be reduced.

[0215] The gate electrode layer 411, the wiring layer 414a, and the wiring layer 414b are It can be formed in the same manner as 1.

[0216] Note that the gate electrode layer 411 can also be formed using a light-transmitting conductive film. An example of a conductive film having optical properties is a light-transmitting conductive oxide.

[0217] A second heat treatment may then be performed.

[0218] The temperature of the second heat treatment is preferably 200° C. or more and 400° C. or less, and more preferably The second heat treatment is preferably performed at a temperature of 250° C. or higher and 350° C. or lower. The second heat treatment is preferably performed in an inert gas atmosphere. In this example, the heating is performed at 250°C for 1 hour in a nitrogen atmosphere. The second heat treatment is performed. Note that the second heat treatment is performed after forming a protective insulating layer or This may be performed after forming a planarizing insulating layer.

[0219] Furthermore, in the atmosphere, the temperature is set to 100° C. or higher and 200° C. or lower for 1 hour or longer and 30 hours or shorter. Heat treatment may be performed. Here, heat treatment is performed at 150° C. for 10 hours. The heating may be performed by keeping the temperature constant, or by heating from room temperature to 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be carried out under reduced pressure before the formation of the insulating oxide layer. By carrying out the treatment under reduced pressure, the heating time can be shortened. It is possible to obtain a transistor that is turned off.

[0220] Through the above steps, the transistor 410 can be formed (FIG. 13E).

[0221] A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. may be used as a protective insulating layer. , a silicon nitride oxide layer, or an aluminum oxide layer is formed as a single layer or a stacked layer. can be done.

[0222] When the oxide semiconductor film is formed as described above, residual moisture in the treatment chamber is removed. By this, the concentrations of hydrogen and hydride contained in the oxide semiconductor film can be reduced. do.

[0223] Although not shown, the transistor 410 may be provided with a plurality of gate electrodes. A transistor having a multi-gate structure having a plurality of channel forming regions may also be used.

[0224] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0225] (Embodiment 5) The present embodiment relates to a transistor that can be used in the semiconductor device described in the first embodiment. The following describes the data transfer function that is different from the first to fourth embodiments.

[0226] FIG. 14A shows a cross-sectional structure of a transistor according to this embodiment. The transistor 520 is insulated from the substrate 400 in the transistor 410 shown in FIG. An insulating layer 522 and a conductive layer 527 are sandwiched between the edge layers 407. The transistor 27 overlaps with the entire surface of the oxide semiconductor layer 512. 521 is a region between the substrate 400 and the insulating layer 407 in the transistor 410 shown in FIG. Sandwiched between them are an insulating layer 522 and a conductive layer 524. The conductive layer 524 is made of oxide. The insulating layer 514 overlaps with a part of the compound semiconductor layer 512 (specifically, the channel formation region).

[0227] The conductive layers 524 and 527 are connected to the transistors 520 and 521. The gate electrode layer 10 may be formed using the same material and method as the gate electrode layer 10, or may be formed using different materials and methods. The conductive layer 524 and the conductive layer 527 can also function as a second gate electrode layer. The potential of the conductive layer 524 and the conductive layer 527 may be a fixed potential of GND or 0V.

[0228] The conductive layers 524 and 527 form the transistors 520 and 521. It is possible to control the electrical characteristics (such as threshold voltage) of the semiconductor device.

[0229] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0230] (Embodiment 6) The present embodiment relates to a transistor that can be used in the semiconductor device described in the first embodiment. The following describes the data transfer function that is different from the first to fifth embodiments.

[0231] FIG. 15A is a plan view of a transistor 610 having a top-gate structure according to this embodiment. FIG. 15B is a cross-sectional view taken along line D1-D2 in FIG. 15A.

[0232] The transistor 610 includes an insulating layer 607, a source electrode 608, a gate insulating layer 609, a gate insulating layer 610, a gate insulating layer 611, a gate insulating layer 612, a gate insulating layer 613, a gate insulating layer 614, a gate insulating layer 615, a gate insulating layer 616, a gate insulating layer 617, a gate insulating layer 618, a gate insulating layer 619, a gate insulating layer 620, a gate insulating layer 621, a gate insulating layer 622, a gate insulating layer 623, a gate insulating layer 624, a gate insulating layer 625, a gate insulating layer 626, a gate insulating layer 627, a gate insulating layer 628, a gate insulating layer 629, a gate insulating layer 630, a gate insulating layer 631, a gate insulating layer 632, a gate insulating layer 633, a gate insulating layer 63 and the drain electrode layer 615a (615a1, 615a2), the oxide semiconductor layer 612, a source electrode and drain electrode layer 615b, a wiring layer 618, a gate insulating layer 602, and a gate electrode layer 611 (611a, 611b), and the source and drain electrode layers 615a (615 a1, 615a2) are electrically connected to the wiring layer 614 via the wiring layer 618. Although not shown, the source and drain electrode layers 615b are also formed on the gate insulating layer 602. The insulating layer 614 is electrically connected to the wiring layer 614 through an opening provided in the insulating layer 614 .

[0233] The process of manufacturing a transistor 610 on a substrate 600 is shown in FIGS. The following description will be given with reference to the above.

[0234] First, an insulating layer 607 serving as a base film is formed over a substrate 600 having an insulating surface.

[0235] Here, as the insulating layer 607, a silicon oxide layer is formed by a sputtering method. The substrate 600 is carried into a processing chamber, and a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. and then irradiating the substrate 600 with a silicon target or quartz (preferably synthetic quartz). A silicon oxide layer is formed as an insulating layer 607. Alternatively, a mixture of oxygen and argon gas is used.

[0236] At this time, it is preferable to perform sputtering while removing residual moisture from within the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the insulating layer 607. As described in the first embodiment, an adsorption type vacuum pump can be used to evacuate the processing chamber. preferable.

[0237] Here, the sputtering gas used to form the insulating layer 607 is hydrogen, water, a hydroxyl group, or a hydride. Impurities such as these have been removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use high purity gases.

[0238] The insulating layer 607 may have a laminated structure, for example, a silicon nitride layer from the substrate 600 side, Insulating layers such as silicon oxynitride layers, aluminum nitride layers, or aluminum oxynitride layers A laminated structure of a nitride layer and the insulating oxide layer may be used.

[0239] For example, a silicon oxide layer and a substrate are provided with a space between them that contains high-purity nitrogen from which hydrogen and moisture have been removed. A putter gas is introduced into the processing chamber, and a silicon nitride layer is formed using a silicon target. In this case, as in the case of the silicon oxide layer, the nitriding process is performed while removing the residual moisture in the processing chamber. It is preferable to form a silicon layer.

[0240] Next, a conductive film is formed on the insulating layer 607, and the conductive film is then exposed by a first photolithography process. A resist mask is formed on the conductive film, and the conductive film is processed to form source and drain electrode layers 6. After forming the source and drain electrode layers 615a1 and 615a2, a resist mask is The source and drain electrode layers 615a1 and the source and drain electrode layers 615a1 and 615b are removed (FIG. 16(A)). The electrode layer 615a2 is shown as being separated in the cross-sectional view. In reality, they are not separated. When the electrode and drain electrode layer 615a2 has a tapered shape, the oxide semiconductor layer This is preferable since it improves the coverage of 612.

[0241] The source and drain electrode layers 615a1 and 615a The material 2 is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or Examples of the alloy include an alloy containing these elements, and an alloy film made by combining these elements. Alternatively, one or more of Mn, Mg, Zr, Be, and Th may be used. The conductive film may be a single layer or may have a structure in which multiple layers are laminated. For example, A single-layer structure of an Al film containing Si, a two-layer structure with a Ti film laminated on an Al film, and two Ti Alternatively, the conductive film may be an Al film. In some cases, Nd or Sc may be included. These films may be nitride films. good.

[0242] Here, the source and drain electrode layer 615a1 and the source and drain electrode As the layer 615a2, a titanium film is formed to a thickness of 150 nm by sputtering.

[0243] Next, the insulating layer 607, the source electrode and drain electrode layer 615a1, An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on the drain electrode layer 615a2. do.

[0244] The oxide semiconductor film is preferably formed while removing moisture remaining in a treatment chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the semiconductor film. It is preferable to use an adsorption type vacuum pump for exhausting the inside of the chamber.

[0245] The sputtering gas used for forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High purity, with impurities removed to a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a high-temperature gas.

[0246] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer. In this example, an In-Ga-Zn-O oxide semiconductor film is used as the oxide semiconductor film. The insulating film is formed by a sputtering method using an oxide semiconductor target.

[0247] Here, the island-shaped oxide semiconductor layer is subjected to first heat treatment to be dehydrated or The temperature of the first heat treatment may be 400° C. or higher and 750° C. or lower. The temperature is preferably 400° C. or higher and lower than the distortion point of the substrate. The substrate 600 is carried into an electric furnace, and the oxide semiconductor layer is heated in a nitrogen atmosphere at 450° C. for one hour. After the heat treatment, the oxide semiconductor layer is not exposed to the air, so that water and hydrogen are not recontaminated in the oxide semiconductor layer. Thus, an oxide semiconductor layer 612 is obtained (FIG. 16B).

[0248] The heat treatment device is not limited to the electric furnace described above, and may be a device that transfers heat from a heating element such as a resistance heating element. Alternatively, a heat treatment device having a mechanism for heating the object to be treated by thermal induction or thermal radiation may be used. For example, GRTA (Gas Rapid Thermal Anneal) equipment, LRT RTA (Rap A (Lamp Rapid Thermal Anneal) equipment, etc. A GRTA (Gradual Thermal Anneal) device can be used. The apparatus is a heat treatment apparatus that uses high-temperature gas for heating. Unlike rare gases such as argon or nitrogen gas, it does not react easily with the workpiece when heated. An inert gas is used. Using GRTA allows high temperature heat treatment in a short time.

[0249] In the first heat treatment, the gas introduced into the treatment chamber is nitrogen or helium. The rare gases, such as uranium, neon, or argon, do not contain water or hydrogen. Alternatively, the nitrogen, helium, neon or arsenic introduced into the heat treatment device may be The purity of rare gases such as nitrile is 6N (99.9999%) or more, preferably 7N (99.9 9999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to set the above.

[0250] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the The substrate is taken out and a photolithography process is performed.

[0251] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the formation of the oxide semiconductor layer, a source electrode and a drain electrode are further laminated on the oxide semiconductor layer. At any time after forming a gate insulating layer on the source electrode and the drain electrode, You may go.

[0252] Next, a conductive film is formed over the insulating layer 607 and the oxide semiconductor layer 612. A resist mask is formed on the conductive film by a lithography process, and the conductive film is processed. A source electrode and drain electrode layer 615b and a wiring layer 618 are formed. The mask is removed (FIG. 16C). Layer 618 is a source and drain electrode layer 615a1 and a source and drain electrode layer 615b2. It may be formed using the same materials and processes as 615a2.

[0253] Here, the source and drain electrode layers 615b and the wiring layer 618 are formed by sputtering. A titanium film with a thickness of 150 nm is formed by the etching method. Electrode layer 615a1, source and drain electrode layer 615a2, source and drain electrode Since the same titanium film is used for the electrode layer 615b, the source electrode and drain electrode layers 615a 1, and the source electrode and drain electrode layer 615a2, and the source electrode and drain electrode layer 6 Therefore, the source and drain electrode layer 615 a1, the source and drain electrode layer 615a2 is the source and drain electrode layer 61 In order to prevent etching of the semiconductor layer 5b, the semiconductor layer 512 is not covered with the oxide semiconductor layer 612. A wiring layer 618 is provided over the source and drain electrode layers 615a2. A drain electrode layer 615a1, a source electrode and drain electrode layer 615a2, and a source electrode and When it is possible to increase the etching selectivity of the wiring layer 615b and the drain electrode layer 615c, 618 does not necessarily have to be provided.

[0254] Note that the conductive film was etched so as not to etch the oxide semiconductor layer 612. The materials and etching conditions are adjusted as appropriate.

[0255] Here, a Ti film is used as the conductive film, and an In-Ga-Zn Using -O-based oxide semiconductor, ammonia hydrogen peroxide (ammonia, water, hydrogen peroxide) was used as an etchant. A mixture of hydrogen peroxide and water is used.

[0256] Note that in the third photolithography step, only a part of the oxide semiconductor layer 612 is In some cases, the oxide semiconductor layer is etched to have a groove (a recess). A resist mask for forming an electrode and drain electrode layer 615b and a wiring layer 618 is formed by in-situ deposition. If the resist mask is formed by the inkjet method, the photoresist mask may be formed by the inkjet method. Since no mask is used, the manufacturing cost can be reduced.

[0257] Next, the insulating layer 607, the oxide semiconductor layer 612, and the source and drain electrode layers 615 a1, source and drain electrode layer 615a2, source and drain electrode layer 615 A gate insulating layer 602 is formed on b.

[0258] The gate insulating layer 602 is formed by oxidizing the gate insulating layer 602 using a plasma CVD method or a sputtering method. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an alumina oxide layer. The aluminum layer can be formed as a single layer or a stacked layer. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 60, a sputtering method is used. It is preferable to form a silicon oxide film by sputtering. The target is a silicon target or a quartz target, and the sputtering gas is The process is carried out using oxygen or a mixture of oxygen and argon gas.

[0259] The gate insulating layer 602 is a source electrode and drain electrode layer 615a1, A silicon oxide layer is formed on the source and drain electrode layer 615a2 and the source and drain electrode layer 615b. A layer of silicon nitride and a layer of oxygen can be stacked. A silicon oxide layer having a thickness of 100 nm is formed by sputtering in a gas atmosphere.

[0260] Next, a resist mask is formed by a fourth photolithography process, and selectively etched. 6. A part of the gate insulating layer 602 is removed by etching to form an opening 623 reaching the wiring layer 618. (FIG. 16(D)). Although not shown, when the opening 623 is formed, the source electrode and the drain electrode are An opening may be formed that reaches the inner electrode layer 615b.

[0261] Next, a conductive film is formed on the gate insulating layer 602 and the opening 623, and then a fifth photolithography is performed. The gate electrode layer 611 (the gate electrode layer 611a and the gate electrode layer 611 b) and a wiring layer 614 are formed. Note that a resist mask is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. , the manufacturing costs can be reduced.

[0262] In addition, the gate electrode layer 611 (the gate electrode layer 611a and the gate electrode layer 611b), wiring The material of the layer 614 is a metal material such as Mo, Ti, Cr, Ta, W, Al, Cu, Nd, or Sc. It can be formed in a single layer or multilayer using materials or alloy materials that have these as the main components. can.

[0263] Here, the gate electrode layer 611 (the gate electrode layer 611a and the gate electrode layer 611b) and As the wiring layer 614, a titanium film having a thickness of 150 nm is formed by sputtering.

[0264] Next, a second heat treatment is performed. The temperature of the second heat treatment is preferably 200° C. or higher. The temperature is preferably 250° C. or higher and 350° C. or lower. The heat treatment may be performed in an inert gas atmosphere or an oxygen gas atmosphere. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen gas atmosphere. This is performed in a state where a part of the conductor layer (channel formation region) is in contact with the gate insulating layer 602. The second heat treatment is performed after forming a protective insulating layer and a planarizing insulating layer over the transistor 610. You may go.

[0265] Furthermore, in the atmosphere, the temperature is set to 100° C. or higher and 200° C. or lower for 1 hour or longer and 30 hours or shorter. Heat treatment may be performed. This heat treatment may be performed by maintaining the heating temperature at a constant level. Then, the temperature is raised from room temperature to a heating temperature of 100°C or more and 200°C or less, and then the temperature is lowered from the heating temperature to room temperature. The above-mentioned heating and lowering steps may be repeated several times. Before formation, the reaction may be carried out under reduced pressure.

[0266] Through the above steps, the oxide semiconductor layer 6 is obtained in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced. A transistor 610 having 12 can be formed (FIG. 16(E)).

[0267] In addition, a protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 610. Although not shown, a source voltage is applied to the gate insulating layer 602, the protective insulating layer, and the planarizing insulating layer. An opening is formed that reaches the source electrode and drain electrode layer 615b. A wiring layer is formed to be electrically connected to the inner electrode layer 615b.

[0268] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0269] (Embodiment 7) In this embodiment, a transistor having a structure similar to that shown in FIG. A transistor according to one embodiment of the present invention will be described with reference to an energy band diagram.

[0270] FIG. 17 shows an inverted staggered thin film transistor including an oxide semiconductor, which is described in this embodiment. The vertical cross-sectional view of the gate electrode (GE1) is shown. A semiconductor film (OS) is provided, on which a source electrode (S) and a drain electrode (D) are provided. is.

[0271] FIG. 18 shows an energy band diagram (schematic diagram) along the line A-A' in FIG. A shows the case where the voltage between the source and drain is equipotential (Vd = 0V), as shown in Figure 18( B) shows the case where a positive potential (Vd>0) is applied to the drain with respect to the source.

[0272] FIG. 19 shows an energy band diagram (schematic diagram) taken along line B-B' in FIG. 19(A) shows the state where a positive potential (+Vg) is applied to the gate (G1), and the source and This shows the on-state where carriers (electrons) flow between the drain and the gate. A negative potential (-Vg) is applied to the gate (G1), and the transistor is in the off state (minority carry). A indicates the case where no flow occurs.

[0273] Figure 20 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Indicates the relationship.

[0274] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are generally n-type, and the Fermi level (Ef) in this case is It is located away from the intrinsic Fermi level (Ei) in the center of the gap and closer to the conduction band. In addition, part of hydrogen in an oxide semiconductor becomes a donor, which is one of the reasons for its n-type nature. It is known that...

[0275] In contrast, the oxide semiconductor of the present embodiment removes hydrogen, which is an n-type impurity, from the oxide semiconductor. The oxide semiconductor is then highly purified to remove impurities other than the main component of the oxide semiconductor. In other words, impurities are added to the Instead of adding hydrogen and water to make it i-type, impurities such as hydrogen and water are removed as much as possible to achieve high purity. The feature of this method is that it is an i-type (intrinsic semiconductor) or close to it. Therefore, the Fermi level (Ef) can be made equal to the intrinsic Fermi level (Ei). Cut.

[0276] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) The source and drain electrodes are made of titanium (Ti). The charge function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, At the interface between the two layers, no Schottky barrier is formed for electrons.

[0277] In other words, when the work function of the metal (φM) and the electron affinity of the oxide semiconductor (χ) are almost equal, In this case, when the two come into contact, the energy band diagram (schematic diagram) shown in Figure 18(A) is shown. do.

[0278] In FIG. 18(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The dashed line shows the case where a positive voltage (Vg>0) is applied to the gate. If there is no potential barrier, carriers (electrons) cannot flow from the electrode to the oxide semiconductor. On the other hand, when a positive voltage is applied to the gate, the potential The barrier between the MOSFET and the MOSFET is lowered, indicating an on-state in which current flows.

[0279] At this time, the electrons pass through the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable portion on the oxide semiconductor side at the interface with the body.

[0280] In FIG. 19B, when a negative potential is applied to the gate (G1), the minority carry Since the number of holes, which are ions, is essentially zero, the current is very close to zero.

[0281] For example, if the channel width W of a thin-film transistor is 1×10 4 μm and the channel length is 3 μm Even if the off-state current is 10 -13 A or less, and the subthreshold swing value (S value) is 0.1 V / dec. (gate insulating film thickness 100 nm).

[0282] In this way, the oxide semiconductor is highly purified so that impurities other than the main component are not included as much as possible. As a result, the operation of the thin film transistor can be improved. can be reduced.

[0283] (Embodiment 8) This embodiment is an embodiment of the present invention, in which the semiconductor device described in Embodiment 1 is applied. This section describes the central processing unit (CPU).

[0284] FIG. 21 shows an example of a block diagram of a CPU. The CPU 801 shown in FIG. A command control circuit 802, a command analysis decoder 803, a register array 804, an address A logic buffer circuit 805, a data bus interface 806, and an ALU 807 ( The arithmetic logic unit (ALM) 806 and instruction register 808 are included.

[0285] The circuitry of the CPU 801 includes the transistors described in the first to seventh embodiments. The transistors described in any of Embodiments 1 to 7 can be used. Since a hydrogen ion semiconductor layer is used, the field effect mobility can be increased. By sufficiently reducing the concentration, the off-state current of the transistor can be made extremely small. At least a part of the CPU 801 is a transistor having an oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced. By configuring it with transistors, the power consumption of the central processing unit can be reduced. .

[0286] Each circuit included in the CPU 801 will be briefly described below.

[0287] The timing control circuit 802 receives commands from the outside and converts them into internal information. It also has the function of converting the data into information and sending it to other blocks. It gives instructions to the outside world such as reading and writing data.

[0288] The command analysis decoder 803 has a function of converting an external command into an internal command.

[0289] The register array 804 has a function of temporarily storing data. has.

[0290] The address logic buffer circuit 805 has a function of specifying an address of an external memory. do.

[0291] The data bus interface 806 is used to connect external memory or devices such as a printer to the data bus. It has the function of exchanging data.

[0292] The ALU 807 has a function of performing calculations.

[0293] The instruction register 808 has a function of temporarily storing instructions. has.

[0294] At least a part of the CPU 801 is made of the transistor described in the first to seventh embodiments. By using a capacitor, leakage current is reduced, so power consumption during standby (standby power) is reduced. This reduces the power consumption of the central processing unit. Among the circuits included in the .01, particularly the register array 804 or the instruction register 808 As the memory element, for example, the memory element described in Embodiment 1 can be used.

[0295] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0296] (Embodiment 9) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. As an example of a semiconductor device to which the transistor described in any of Embodiments 1 to 7 is applied, A wireless communication semiconductor device capable of inputting and outputting data will be described. The wireless communication semiconductor device capable of outputting is an RFID tag, an ID tag, an IC tag, an RF tag, They are also called radio tags, electronic tags or radio chips.

[0297] An example of the structure of the wireless communication semiconductor device of this embodiment will be described with reference to FIGS. The wireless communication semiconductor device shown in FIG. A semiconductor integrated circuit chip 900 having a (booster) antenna 902 is provided. The semiconductor integrated circuit chip 900 includes the support substrate 904 and the The insulating layer 908 is formed on the antenna 902. The insulating layer 908 is made of: A semiconductor integrated circuit chip 900 can be fixed onto a support substrate 904 and an antenna 902. Any material that can be used may be used, and it may be formed of, for example, a sealing material.

[0298] The surface of the semiconductor integrated circuit chip 900 is protected against electrostatic damage (damage to the circuit) caused by electrostatic discharge. It is preferable that a conductive shield is provided to prevent malfunctions and damage to the semiconductor elements. If the resistance of the conductive shield is high and the patterns of the antenna 902 are not electrically connected, The antenna 902 and the conductive shield provided on the surface of the semiconductor integrated circuit chip 900 are not connected to each other. It may be provided as such.

[0299] The semiconductor integrated circuit provided in the semiconductor integrated circuit chip 900 includes a memory section and a logic section. These memory and logic parts are provided with a plurality of transistors and other elements. As the transistor constituting the above, the transistors described in the first to seventh embodiments are used. can be used.

[0300] FIG. 23(A) shows a semiconductor integrated circuit chip 900 shown in FIG. 22(A) (on 23A shows an enlarged view of an antenna 9 and a semiconductor integrated circuit. Reference numeral 12 denotes a rectangular loop antenna with one turn, but is not limited to this. 912 may have a curved shape (e.g., circular), and the number of turns of antenna 912 may be If the number of turns of the antenna 912 is 1, the semiconductor integrated circuit 910 and This is preferable because the parasitic capacitance occurring between the antennas 912 can be reduced.

[0301] In FIG. 23A, an antenna 912 surrounds the semiconductor integrated circuit 910. The antenna 9 is surrounded by a power supply point 918. 12 is disposed in a different area from the semiconductor integrated circuit 910. As shown in FIG. In addition, the antenna 912 is disposed in a region different from the semiconductor integrated circuit 910, It is possible to reduce the parasitic capacitance occurring between the conductor integrated circuit 910 and the antenna 912. However, the present invention is not limited to this. As shown in FIG. 23(B), a point corresponding to a power supply point 918 shown by a broken line may be used. The antenna 912 is arranged so as to overlap at least a part of the semiconductor integrated circuit 910 except for the part where the antenna 912 is arranged. The electrodes may be arranged as follows.

[0302] In FIG. 22A, the antenna 902 is mainly a loop-shaped portion surrounded by a dashed line 906. The antenna 912 of the semiconductor integrated circuit chip 900 and the signal The antenna 902 can receive and transmit power or supply electric power. In the area other than the area enclosed by 6, signals are sent and received with an external interrogator by radio waves. In addition to transmitting and receiving signals, power may be supplied from an external interrogator. Between the interrogator and the semiconductor integrated circuit chip 900, a carrier is used. The frequency of the radio waves to be used is not particularly limited, but is preferably between 30 MHz and 5 GHz. For example, a frequency band such as 950 MHz or 2.45 GHz may be used.

[0303] The antenna 902 has a rectangular shape with one turn in the area surrounded by the dashed line 906. The antenna 902 may be a curved shape (e.g., a loop antenna, but is not limited to this). For example, the antenna 902 may be circular, and the number of turns of the antenna 902 may be multiple. If the number of turns in the portion of antenna 902 surrounded by dashed line 906 is 1, This is preferable because the parasitic capacitance occurring between the antennas 912 can be reduced.

[0304] The communication method of the wireless communication semiconductor device of the present embodiment is not particularly limited. For example, the communication method may be an electromagnetic induction method. The method may be an electromagnetic coupling method or a microwave method. (For example, UHF band (860MHz to 960MHz band), 2.45GHz band, etc.) In this case, the length and shape of the antenna 902 and the antenna 912 are determined according to the wavelength of the electromagnetic wave used. In addition to the above, the antenna shape can be a linear shape (e.g., a dipole antenna). antenna), flat shape (e.g., patch antenna or ribbon type shape), etc. The antenna shape may be a meandering shape other than the above, or a combination of these. It may be combined.

[0305] As described above, the communication method of the wireless communication semiconductor device of the present embodiment is an electromagnetic induction method or FIG. 24 shows a configuration in which the electromagnetic induction method or the electromagnetic coupling method is applied. Here is an example.

[0306] In FIG. 24, a coil-shaped antenna 902 is provided as a booster antenna. A semiconductor integrated circuit chip 90 having a coil-shaped antenna 912 provided on a support substrate 904. 0 is provided.

[0307] Next, regarding the structure and arrangement of the semiconductor integrated circuit chip 900 and the booster antenna, FIG. 22B shows the semiconductor integrated circuit chip 900 and the support substrate shown in FIG. 9 shows a perspective view of a semiconductor device in which an antenna 902 formed on a plate 904 is stacked. FIG. 22C shows a cross-sectional view taken along dashed line XY in FIG. 22B.

[0308] The semiconductor integrated circuit 910 shown in FIG. 22C includes a first insulator 914 and a second insulator 91 6, and the sides are also sealed. After the first insulator and the second insulator are bonded together, they are separated into laminates for each semiconductor integrated circuit. When a conductive shield is formed on the cut laminate, the semiconductor integrated circuit chip 90 0 is completed. Here, the means of division is a means that can divide physically. It is not limited to a specific one as long as it can be cut by irradiating it with a laser beam. can be done.

[0309] In FIG. 22C, a semiconductor integrated circuit 910 is closer to an antenna 902 than an antenna 912. However, the present invention is not limited to this. 10 may be located closer to antenna 902 than antenna 902 .

[0310] Next, the operation of the wireless communication semiconductor device of this embodiment will be briefly described. FIG. 22 is a block diagram showing an example of the configuration of a wireless communication semiconductor device according to the present embodiment. The same reference numerals are used to denote the same parts as those in Figs. 25 to 24. The body device includes an antenna 902 , a semiconductor integrated circuit 910 , and an antenna 912 . Antenna 902 is a booster antenna, and antenna 912 is an on-chip antenna. do.

[0311] First, a case where the wireless communication semiconductor device receives a signal and power from the interrogator 920 will be described. First, an electromagnetic wave is transmitted from the interrogator 920, and the antenna 902 receives the electromagnetic wave. This generates an alternating current in the antenna 902 and a magnetic field around the antenna 902 . The loop-shaped portion of the antenna 902 and the loop-shaped antenna 912 are electromagnetically coupled. When the two are coupled together, an induced electromotive force is generated in the antenna 912. The semiconductor integrated circuit 910 By using induced electromotive force, a signal or power is received from the interrogator 920 .

[0312] Conversely, a case where the wireless communication semiconductor device transmits a signal to the interrogator 920 will be described. At this time, the antenna 912 is energized in accordance with a signal generated in the semiconductor integrated circuit 910. By passing a current through the antenna 902 to generate an induced electromotive force, the A signal can be transmitted to the interrogator 920 via the reflected wave of an incoming radio wave.

[0313] The antenna 902 is mainly a loop-shaped antenna that is electromagnetically coupled to the antenna 912. The part that mainly receives radio waves from the interrogator 920 can be divided into two parts. In the portion for receiving radio waves from the device 920, the antenna 902 is shaped so as to be able to receive radio waves. For example, dipole antennas, folded dipole antennas, slot antennas, etc. For example, a meander line antenna, a microstrip antenna, or the like may be used.

[0314] In the above description, only one on-chip antenna and one booster antenna are provided. The present invention is not limited to the above. An antenna for power and an antenna for transmitting and receiving signals may be provided separately. This allows the frequency of the radio waves that supply power to be different from the frequency of the radio waves that transmit signals. This allows for highly efficient power supply and signal transmission / reception.

[0315] In the semiconductor device of the present embodiment, an on-chip antenna and a semiconductor device not connected to the on-chip antenna are provided. Since it uses a booster antenna that communicates by contact, an external antenna is not required. Compared to when the semiconductor integrated circuit and the antenna are directly connected to each other, the connection between the semiconductor integrated circuit and the antenna is affected by external forces. is less likely to be disconnected, and the occurrence of initial defects in the connection can be suppressed.

[0316] In addition, since the semiconductor device of this embodiment mode uses a booster antenna, The size or shape of the on-chip antenna is different from that of the semiconductor device compared to using only the on-chip antenna. Therefore, the frequency band of radio waves that can be received is limited. In addition, the communication distance can be made longer than when only the on-chip antenna is used.

[0317] The semiconductor integrated circuit of this embodiment may be formed on a flexible substrate. When the integrated circuit is formed on a flexible substrate, the elements may be formed directly on the flexible substrate. A semiconductor integrated circuit is formed on a substrate for production such as a glass substrate, and a flexible substrate such as a plastic substrate is formed on the substrate. In addition, a semiconductor integrated circuit formed on a manufacturing substrate may be transferred to a flexible substrate. The method of placing the semiconductor integrated circuit is not particularly limited. For example, a peeling layer may be formed between the substrate and the semiconductor integrated circuit. The following method can be used.

[0318] When the semiconductor integrated circuit is transferred to a flexible substrate, for example, a peeling layer is formed by a metal oxide. In this case, the weakening can be prevented by crystallizing the formed metal oxide. Then, the element layer including the semiconductor integrated circuit, which is the layer to be peeled, may be peeled off from the formation substrate. After the metal oxide is crystallized, a part of the peeling layer is further degassed with a solution or halogen fluoride gas (NF 3, BrF3, ClF3, etc.) may be used to remove and peel the film.

[0319] Alternatively, a film containing nitrogen, oxygen, hydrogen, etc. (e.g., an amorphous silicon film containing hydrogen) may be used as the peeling layer. A transparent substrate is used as the substrate. In the case of using a substrate having a fluorine atom, the peeling layer is irradiated with laser light from the preparation substrate to form a fluorine atom-containing film in the peeling layer. The nitrogen, oxygen, or hydrogen contained therein may be vaporized to remove the film.

[0320] Alternatively, the prepared substrate may be mechanically (e.g., polished) or chemically (e.g., by using a fluoride treatment as described above). Alternatively, a method of removing the insulating layer (etching with halogen gas) may be used. In this case, A release layer may not be used.

[0321] Alternatively, a groove is formed by irradiating a laser beam or by using a sharp blade to expose the peeling layer. The groove may be used as a starting point for peeling.

[0322] The above-mentioned peeling can be performed, for example, by applying a mechanical force. Examples of methods include peeling the material off with a hand or a gripping tool, or rolling the material over a roller. Examples of such processes include separation of the

[0323] An example of a material for forming the release layer is tungsten. When the electrode is made of tungsten, it is heated with a mixture of ammonia water and hydrogen peroxide. The peeling can be performed while the peeling layer is etched.

[0324] The transistors described in any of Embodiments 1 to 7 have small off-state current; By applying the present invention to the semiconductor device of the embodiment, power consumption can be reduced.

[0325] In addition, by covering the semiconductor integrated circuit with a conductive shield, electrostatic damage to the semiconductor integrated circuit can be prevented. It is possible.

[0326] In addition, the semiconductor integrated circuit is sandwiched between a pair of insulators, making the device thin, compact, and reliable. A highly reliable semiconductor device can be provided.

[0327] This realizes a semiconductor device that consumes low power, is suppressed from electrostatic damage, and is highly reliable. It is possible.

[0328] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0329] (Embodiment 10) This embodiment is an aspect of the present invention, which is the wireless communication semiconductor device described in the ninth embodiment. An example in which the above is applied will be described.

[0330] FIG. 26 shows a semiconductor device 1000 similar to the wireless communication semiconductor device described in the ninth embodiment. An application example will be shown. The semiconductor device 1000 utilizes the function of being able to transmit and receive electromagnetic waves. It can be used for various objects and systems. For example, the object is a key (see Fig. 26( A), banknotes, coins, securities, bearer bonds, certificates (such as driver's licenses and resident cards), See Fig. 26(B), books, containers (such as petri dishes, see Fig. 26(C), Personal items (bags, glasses, etc., see Figure 26(D)), packaging containers (wrapping paper, bottles, etc., see Figure 2 6(E) and (F)), recording media (such as disks and video tapes), vehicles (such as bicycles) cars, food, clothing, daily necessities, electronic devices (liquid crystal display devices, EL display devices, televisions) The semiconductor device 1000 is a It is attached to the surface of various objects or embedded in them. Examples of systems include goods management systems, authentication function systems, and distribution systems. .

[0331] As explained in the ninth embodiment, the present invention has low power consumption, suppresses electrostatic damage, and is highly reliable. By using a semiconductor device with high reliability, a highly reliable system can be realized.

[0332] This embodiment mode can be freely combined with the configurations of the other embodiments.

[0333] (Embodiment 11) In this embodiment, the transistors described in any of the first to seventh embodiments are applied. The display device will now be described.

[0334] The display device of the present embodiment may be a liquid crystal display device or an EL display device. Here, as an example, electronic paper using electrophoretic elements will be described.

[0335] FIG. 27 shows a cross-section of an active matrix type electronic paper display panel. The electronic paper has high visibility similar to that of paper and consumes less energy than other display panels. It requires low power and can be made thin and lightweight.

[0336] FIG. 27(A) shows a cross-sectional view of electronic paper using the twist ball method. The ball method is a method in which spherical particles painted black and white are placed between the electrode layers used in the display element. The method of displaying images is to control the orientation of spherical particles by adjusting the voltage between the electrode layers. cormorant.

[0337] The electronic paper using the twist ball method shown in FIG. 27(A) is a display unit 1114 and a drive unit. The display unit 1114 includes a transistor 1102 on a substrate 1100. A first electrode layer 1104 connected to the substrate 1106 and a second electrode layer 110 8, and spherical particles 1110 disposed between the first electrode layer 1104 and the second electrode layer 1108. The spherical particle 1110 has a black region 1110a and a white region 1110b. The spherical particle 1110 includes a cavity 1110c that is filled with liquid. The second electrode layer 1108 is filled with a filler 1112 such as an organic resin. The driving circuit unit 1116 corresponds to a common electrode and is electrically connected to a common potential line. The transistor 1102 in the display portion 1114 is formed in the same process as the transistor 1102. include.

[0338] FIG. 27(B) shows a cross-sectional view of electronic paper using an electrophoretic element system. In FIG. 27(A), a microcapsule 1118 is used instead of the spherical particle 1110. The microcapsule 1118 is composed of a transparent liquid 1118c and negatively charged black particles 1118c. The microcapsules 1118 have white particles 1118a and positively charged white particles 1118b. The size is about 10 μm to 200 μm in diameter.

[0339] The microcapsules 1 are provided between the first electrode layer 1104 and the second electrode layer 1108. 118 is driven by a first electrode layer 1104 and a second electrode layer 1108 when an electric field is applied thereto. The first particle, the white particle 1118b, and the second particle, the black particle 1118a, are in the opposite direction. The display element that applies this principle is called electrophoretic display. Electrophoretic display elements have high reflectivity, so they do not require auxiliary lights and consume little power. It consumes little power and is highly visible even in dimly lit places. Even in this state, it is possible to hold an image that has been displayed once.

[0340] The first and second particles contain a dye and do not move in the absence of a potential gradient. In addition, the colors of the first and second particles are not limited to black and white, but may be different (eg, white, black, white ... (including color) is acceptable.

[0341] The above-mentioned microcapsules dispersed in a solvent are called electronic ink. Electronic ink can be printed on surfaces such as glass, plastic, fabric and paper. In addition, color displays are possible by using color filters or particles containing pigments. .

[0342] The first and second particles in the microcapsule 1118 are made of a conductive material and an insulating material. materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from electrochromic materials, magnetophoretic materials, or a combination of these materials The material should be used.

[0343] FIG. 27(C) shows a cross-sectional view of electronic paper using the electronic powder method. 104, the second electrode layer 1108, and the space 1122 surrounded by the ribs 1120 are positively charged. The negatively charged black powder 1124A and the negatively charged white powder 1124B are filled. The space 1122 may be filled with air, for example.

[0344] When a potential gradient is generated by the first electrode layer 1104 and the second electrode layer 1108, the black powder particles The white powder 1124A and the white powder 1124B move in opposite directions to display white or black. As the powder, color powder such as red, yellow, and blue may be used.

[0345] In FIG. 27, the substrate 1100 is a light-transmitting plastic substrate or the like. Here, as the plastic substrate, FRP (Fibreglass) can be used. ss-Reinforced Plastics) board, PVF (Poly Vinyl Fluoride film, polyester film or acrylic resin film Aluminum foil can also be wrapped with PVF film or polyester film. A sandwiched sheet structure may also be used.

[0346] When a plastic substrate or the like is used as the substrate 1100, for example, A release layer is formed, an element is formed on the release layer, and the upper surface of the element is attached to another substrate to form a release layer. The substrate may be transferred by removing the substrate and then transferring the substrate from the other substrate onto a plastic substrate. Here, the peeling layer can be made of, for example, tungsten oxide. It is preferable to form the film from tungsten, since it can be peeled off by water. The other substrates mentioned may also be plastic substrates.

[0347] According to this embodiment, a transistor with high field effect mobility is formed on a large-area substrate, Since the driving circuit and the pixel circuit can be formed on the same substrate, double-speed driving is possible. This allows us to provide high added value electronic paper.

[0348] In addition, in this embodiment, electronic paper using an electrophoretic element or the like according to one embodiment of the present invention is However, the present invention is not limited to this example, and other types of electronic paper may be used. For example, electronic paper using liquid crystal elements or EL elements as display elements may be used.

[0349] This embodiment mode can be freely combined with the configurations of other embodiments. do.

[0350] (Embodiment 12) This embodiment is one example of the present invention in which the display device described in the eleventh embodiment is applied to a display unit. An electronic device according to an embodiment will now be described.

[0351] An example of an electronic device in which the display device according to the eleventh embodiment is applied to a display unit is a video camera. , digital cameras, goggle-type displays, navigation systems, audio playback devices ( Car audio, audio components, etc.), computers, game devices, mobile information terminals ( Mobile computers, mobile phones, portable game consoles, e-books, etc.), Image playback devices that incorporate the Digital Versatile Disc (DVD) (Devices equipped with a display that can play back recording media such as a 3D camera and display the images) Can be obtained.

[0352] The display shown in FIG. 28A includes a housing 1200, a support base 1201, and a display unit 120. 2, and displays various input information (still images, videos, text images, etc.) on the display unit 1202 Note that the functions of the display shown in FIG. However, the device may be equipped with a speaker, and may be capable of inputting information as well as displaying information. The display device may be a touch panel.

[0353] The television device shown in FIG. 28B has a display unit 1212 built in a housing 1211. The display unit 1212 can display an image. 1210 to support the rear side of the housing.

[0354] The television device shown in FIG. 28B is operated using an operation switch or the like provided on the housing 1211. This can be done by a remote control device 1215. The operation keys 1214 allow the user to operate the channel and volume. The image displayed on the remote control unit 1215 can be operated. A display unit 1213 for displaying information output from an operating device 1215 may be provided.

[0355] The television device shown in FIG. 28(B) is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts and can also receive TV signals via a modem. By connecting the device to a wired or wireless communication network, It communicates information in a two-way (between sender and receiver, or between receivers) or two-way (between sender and receiver, etc.) manner. It is also possible.

[0356] The computer shown in FIG. 28C includes a main body 1220, a housing 1221, a display unit 1222, A keyboard 1223, an external connection port 1224, and a pointing device 1225 are included. and a function to display various information (still images, videos, text images, etc.) on the display unit 1222. Note that the functions of the computer shown in FIG. 28(C) are not limited to those described above. For example, it may be a touch panel that is capable of not only displaying information but also inputting information.

[0357] The semiconductor device described in the first embodiment is stored in a storage unit of the electronic device described in the first embodiment. By using the body device, it is possible to realize electronic devices that are highly reliable and consume low power. .

[0358] The display device described in the eleventh embodiment is used as the display unit of the electronic device described in the present embodiment. By using the above, it is possible to realize an electronic device that is highly reliable and consumes low power. , the aperture ratio can be improved.

[0359] This embodiment mode can be freely combined with the configurations of other embodiments. do. [Explanation of symbols]

[0360] 100 Substrates 102 Gate insulating layer 103 Protective insulation layer 110 Transistor 111 Gate electrode layer 113 Channel formation region 114a High resistance source region 114b High-resistance drain region 115a Source electrode layer 115b Drain electrode layer 116 Insulating oxide layer 120 Substrate 121 Gate electrode layer 122a Gate insulating layer 122b Gate insulating layer 123 Protective Insulation Layer 130 Oxide Semiconductor Film 131 Oxide semiconductor layer 132 Oxide semiconductor layer 135a Source electrode layer 135b Drain electrode layer 136 Insulating Oxide Layer 140 Transistor 150 Memory elements 152 Line Decoder 154 Write and refresh circuit 156 Column Decoder 158 Write and refresh circuit 160 AND Circuit 162 AND Circuit 164 AND Circuit 166 Switch 168 Switch 170 Switch 172 Sense Amplifier 180 Memory elements 182 Transistor 184 Transistors 186 Transistors 188 Transistors 190 Transistors 192 Transistors 194 Resistance element 196 Resistance Element 200 boards 202 Gate electrode layer 204 Gate insulating layer 206 Oxide semiconductor layer 208 Insulating oxide layer 210 Oxide semiconductor layer 212 Source and drain electrode layers 214 Protective insulation layer 220 Transistor 300 Substrates 302 Gate electrode layer 304 Gate insulation layer 306a Source and drain electrode layers 306b source and drain electrode layers 308 Oxide Semiconductor Film 310 Oxide semiconductor layer 312 Oxide semiconductor layer 314 Insulating oxide layer 316 Protective Insulation Layer 320 Transistor 400 Substrates 402 Gate insulating layer 407 Insulating Layer 410 Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Source electrode layer 415b Drain electrode layer 421a aperture 421b Aperture 512 Oxide semiconductor layer 520 Transistor 521 Transistor 522 Insulating layer 524 Conductive Layer 527 Conductive Layer 600 Substrates 602 Gate insulating layer 607 Insulating Layer 610 Transistor 611 Gate electrode layer 611a Gate electrode layer 611b Gate electrode layer 612 Oxide semiconductor layer 614 Wiring layer 615a Source and drain electrode layers 615b source and drain electrode layers 615a1 Source and drain electrode layers 615a2 Source and drain electrode layers 618 Wiring layer 623 Aperture 801 CPU 802 Timing control circuit 803 Instruction Parsing Decoder 804 Register Array 805 Address Logic Buffer Circuit 806 Data Bus Interface 807 ALU 808 Instruction Register 900 Semiconductor Integrated Circuit Chip 902 Antenna 904 Support Substrate 906 Dashed Line 908 Insulation layer 910 Semiconductor Integrated Circuits 912 Antenna 914 Insulators 916 Insulators 918 Power supply point 920 Interrogator 1000 Semiconductor device 1100 Substrate 1102 Transistor 1104 Electrode layer 1106 Board 1108 Electrode layer 1110 Spherical particles 1112 Filling material 1114 Display section 1116 Drive circuit section 1118 Microcapsules 1120 Rib 1122 Space 1200 Cabinet 1201 Support stand 1202 Display section 1210 Wall 1211 Case 1212 Display section 1213 Display section 1214 Operation key 1215 Remote control device 1220 Main unit 1221 Case 1222 Display section 1223 Keyboard 1224 External connection port 1225 Pointing Device

Claims

[Claim 1] A plurality of circuits arranged in a matrix form are included, one of the circuits includes at least a first transistor, a second transistor, a third transistor, and a fourth transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one of the source and the drain of the fourth transistor, the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor and one of the source and the drain of the third transistor, the other of the source and the drain of the third transistor is electrically connected to a first wiring; a gate of the third transistor and a gate of the fourth transistor are electrically connected to a common scanning line; the other of the source and the drain of the fourth transistor is electrically connected to a second wiring, an oxide semiconductor layer having a region in contact with a top surface of a first insulating layer and including a channel formation region of the first transistor; a first conductive layer overlapping the channel formation region; a second conductive layer having a region in contact with the oxide semiconductor layer and a region in contact with the first insulating layer; a third conductive layer having a region in contact with the oxide semiconductor layer and a region in contact with the first insulating layer; a second insulating layer having a region in contact with a top surface of the second conductive layer, a region in contact with the third conductive layer, and a region in contact with a top surface of the oxide semiconductor layer; a fourth conductive layer having a region in contact with an upper surface of the second insulating layer and a region in contact with an upper surface of the second conductive layer through an opening in the second insulating layer; a fifth conductive layer having a region in contact with the upper surface of the second insulating layer; the fourth conductive layer and the fifth conductive layer have the same material; the first conductive layer has a region that functions as a gate electrode of the first transistor; the second conductive layer has a region functioning as one of a source electrode and a drain electrode of the first transistor, the third conductive layer has a region functioning as the other of the source electrode and the drain electrode of the first transistor, the fifth conductive layer overlaps with the channel formation region, the first conductive layer has a region overlapping with the opening without the oxide semiconductor layer therebetween.

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