Signal Processing Circuit

Abstract

To provide a signal processing circuit capable of switching a time constant of a filter circuit while reducing the circuit scale.SOLUTION: A signal processing circuit 1 includes a filter circuit 21 that removes noise from a target signal, and a control unit 50 that controls the filter circuit 21. The filter circuit 21 includes a CMOS switch 25 including transistors 27 and 28 which have different channel types and are connected in parallel, and a capacitor 26 electrically connected between output of the CMOS switch 25 and a ground potential. The control unit 50 switches the state of the CMOS switch 25 between a first state in which the transistor 27 is in an on-state and a second state in which the transistor 27 is in an off-state and the transistor 28 is in an on-state. An ON resistance value of transistor 28 is greater than the ON resistance value of transistor 27.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a signal processing circuit. [Background technology]

[0002] In imaging devices, a low-pass filter may be provided to reduce noise in pixel circuits. For example, Patent Document 1 describes an imaging device that includes a low-pass filter including a resistive element, a switch provided in parallel with the resistive element, and a sample-and-hold circuit, and a control circuit that switches the switch. In this imaging device, in order to shorten the time required for sampling, the switch is switched from an on state to an off state during sampling by the sample-and-hold circuit, thereby increasing the time constant of the low-pass filter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-198263 A Summary of the Invention [Problem to be solved by the invention]

[0004] To achieve a cutoff frequency that can sufficiently remove noise, the size of the resistor element becomes large. For example, in the imaging device described in Patent Document 1, the size of the resistor element becomes large relative to the pitch between pixels. For this reason, a circuit configuration that can switch the time constant of the filter circuit while reducing the circuit scale is desired.

[0005] The present disclosure describes a signal processing circuit capable of switching the time constant of a filter circuit while reducing the circuit size. [Means for solving the problem]

[0006] A signal processing circuit according to an aspect of the present disclosure includes a filter circuit that removes noise from a target signal, and a control unit that controls the filter circuit. The filter circuit includes a CMOS switch including a first MOSFET and a second MOSFET connected in parallel, the first MOSFET and the second MOSFET having different channel types from each other, and a capacitor electrically connected between an output of the CMOS switch and a ground potential. The control unit switches the state of the CMOS switch between a first state in which the first MOSFET is in an on state and a second state in which the first MOSFET is in an off state and the second MOSFET is in an on state. The on-resistance value of the second MOSFET is greater than the on-resistance value of the first MOSFET.

[0007] In this signal processing circuit, a low-pass filter is formed by the CMOS switch and a capacitor. Since the on-resistance value of the second MOSFET is larger than the on-resistance value of the first MOSFET, the resistance value of the CMOS switch in the second state is larger than the resistance value of the CMOS switch in the first state. Therefore, by switching the state of the CMOS switch between the first state and the second state, it is possible to switch the time constant of the filter circuit. As a result, it is possible to omit the resistive element, thereby making it possible to switch the time constant of the filter circuit while reducing the circuit size.

[0008] The control unit may switch the state of the CMOS switch from the first state to the second state while the capacitor is being charged by the target signal. In this case, the time constant of the filter circuit is switched from a small value to a large value while the capacitor is being charged by the target signal. Therefore, it is possible to reduce the settling time while removing noise from the target signal.

[0009] The signal processing circuit may further include a light receiving element that generates and accumulates electric charges when irradiated with light, and an amplifier circuit that amplifies an output signal of the filter circuit. The filter circuit may receive a signal corresponding to the electric charges accumulated by the light receiving element as the target signal. In this case, the filter circuit is provided between the light receiving element and the amplifier circuit. Therefore, noise contained in the signal is removed by the filter circuit before being amplified by the amplifier circuit, so that the noise can be effectively removed.

[0010] The signal processing circuit may further include a light receiving element that generates and accumulates electric charges when irradiated with light, and an amplifier circuit that generates a target signal by amplifying a signal corresponding to the electric charges accumulated by the light receiving element and supplies the target signal to the filter circuit. In this case, the filter circuit is provided after the amplifier circuit. Therefore, the filter circuit can be driven by the amplifier circuit.

[0011] The amplifier circuit may include a setting circuit that sets a reset level of the target signal. The resistance value of the first MOSFET and the resistance value of the second MOSFET may vary depending on the input voltage (voltage value of the target signal) of the CMOS switch. Therefore, by appropriately setting the reset level, the resistance value of the CMOS switch in the first state and the resistance value of the CMOS switch in the second state can be set to desired values.

[0012] The signal processing circuit may further include a setting circuit for setting a reset level of the target signal. The resistance value of the first MOSFET and the resistance value of the second MOSFET may vary depending on the input voltage (voltage value of the target signal) of the CMOS switch. Therefore, by appropriately setting the reset level, the resistance value of the CMOS switch in the first state and the resistance value of the CMOS switch in the second state can be set to desired values.

[0013] The setting circuit may set the reset level so that the voltage of the target signal fluctuates in a range in which the on-resistance of the second MOSFET is greater than the on-resistance of the first MOSFET. In this case, the magnitude relationship between the resistance of the CMOS switch in the first state and the resistance of the CMOS switch in the second state is determined, making it possible to reliably switch the time constant of the filter circuit.

[0014] The first state may be a state in which the first MOSFET and the second MOSFET are both on. In this case, the resistance value of the CMOS switch in the first state is smaller than the resistance value of the CMOS switch when only the second MOSFET is on. Therefore, the time constant of the filter circuit when the CMOS switch is in the first state can be further reduced.

[0015] The first MOSFET may be a p-channel MOSFET. The second MOSFET may be an n-channel MOSFET. As the input voltage of the CMOS switch increases, the resistance value of the p-channel MOSFET tends to decrease and the resistance value of the n-channel MOSFET tends to increase. Therefore, when the input voltage of the CMOS switch is high, it is possible to more reliably switch the time constant of the filter circuit.

[0016] The first MOSFET may be an n-channel MOSFET, and the second MOSFET may be a p-channel MOSFET. In this configuration, when the input voltage of the CMOS switch is low, the time constant of the filter circuit can be switched more reliably. Effect of the Invention

[0017] According to the present disclosure, it is possible to switch the time constant of a filter circuit while reducing the circuit size. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a signal processing circuit according to the first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the reset level set by the setting circuit shown in FIG. [Diagram 3] FIG. 3 is a diagram for explaining the voltage of the floating diffusion node shown in FIG. [Figure 4] FIG. 4 is a diagram showing input / output characteristics of the source follower circuit shown in FIG. [Diagram 5] FIG. 5 is a diagram for explaining the resistance value of the CMOS switch shown in FIG. [Figure 6] FIG. 6 is a timing chart showing a part of the operation of the signal processing circuit shown in FIG. [Figure 7] FIG. 7 is a diagram for explaining the settling time in the column circuit shown in FIG. [Figure 8] FIG. 8 is a diagram showing a circuit configuration of a signal processing circuit according to the second embodiment. [Figure 9] FIG. 9 is a diagram showing a modified example of the pixel circuit. [Figure 10] FIG. 10 is a diagram for explaining the reset level set by the setting circuit shown in FIG. [Figure 11] FIG. 11 is a diagram for explaining the voltage of the floating diffusion node shown in FIG. [Figure 12] FIG. 12 is a diagram showing input / output characteristics of the source follower circuit shown in FIG. [Figure 13] FIG. 13 is a diagram illustrating an example of a circuit configuration of a monitor circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated description will be omitted.

[0020] (First embodiment) The configuration of a signal processing circuit according to a first embodiment will be described with reference to Figs. 1 to 5. Fig. 1 is a diagram showing a circuit configuration of the signal processing circuit according to the first embodiment. Fig. 2 is a diagram for explaining a reset level set by a setting circuit shown in Fig. 1. Fig. 3 is a diagram for explaining a voltage of a floating diffusion node shown in Fig. 1. Fig. 4 is a diagram showing input / output characteristics of a source follower circuit shown in Fig. 1. Fig. 5 is a diagram for explaining a resistance value of a CMOS switch shown in Fig. 1.

[0021] The signal processing circuit 1 shown in FIG. 1 is applied to an imaging device. The imaging device can be used under low illuminance. An example of the imaging device is an imaging device for Raman spectroscopy. The signal processing circuit 1 includes a pixel circuit 10, a column circuit 20, and a controller 50. Although the imaging device includes a pixel array arranged two-dimensionally in M ​​rows and N columns, the following description will be given using the circuit configuration of the signal processing circuit 1 focusing on one pixel. M and N are integers of 2 or more.

[0022] The pixel circuit 10 is a circuit that generates an output voltage Vpix according to the amount of light irradiation. The pixel circuit 10 corresponds to one pixel included in the pixel array. The pixel circuit 10 includes a light receiving element 11, a transistor 12, a setting circuit 13, and a source follower circuit 14.

[0023] The light receiving element 11 is an element that generates electric charge when irradiated with light. An example of the light receiving element 11 is a photodiode. The anode of the light receiving element 11 is electrically connected to a ground potential. The electric charge generated in the light receiving element 11 is accumulated in a parasitic capacitance (not shown). Note that when two circuit elements are "electrically connected," it can include not only that the two circuit elements are directly connected by wiring or the like, but also that the two circuit elements are indirectly connected via another circuit element.

[0024] The transistor 12 is a circuit element for transferring the charge accumulated by the light receiving element 11. The transistor 12 is, for example, an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The drain of the transistor 12 is electrically connected to the cathode of the light receiving element 11. The source of the transistor 12 is electrically connected to a node N1. The node N1 is a floating diffusion node. A transfer signal TX is supplied to the gate of the transistor 12. When a high-level transfer signal TX is supplied to the gate of the transistor 12, the transistor 12 is turned on, and the charge accumulated in the light receiving element 11 is output from the source of the transistor 12.

[0025] The setting circuit 13 is a circuit for setting a reset level of the output voltage Vpix. The setting circuit 13 sets the reset level of the output voltage Vpix by setting the reset level of the node voltage Vfd. The node voltage Vfd is the voltage of the node N1. The setting circuit 13 includes a transistor 15. The transistor 15 is, for example, an n-channel MOSFET. The drain of the transistor 15 is set to a reset potential Vr. The source of the transistor 15 is electrically connected to the node N1. A reset signal Pix_reset is supplied to the gate of the transistor 15. By supplying a high-level pulse-shaped reset signal Pix_reset to the gate of the transistor 15, a reset operation of the node voltage Vfd is performed while the reset signal Pix_reset is at a high level (reset period). In the reset operation, the transistor 15 is turned on, and the node voltage Vfd is set to the reset level.

[0026] As shown in FIG. 2, the reset level of the node voltage Vfd is smaller than the reset potential Vr. More specifically, when the transistor 15 is turned on, the source voltage of the transistor 15 (i.e., the node voltage Vfd) rises, and the gate-source voltage Vgs of the transistor 15 drops. Then, before the drain-source voltage Vds of the transistor 15 becomes zero, the gate-source voltage Vgs of the transistor 15 becomes smaller than the threshold voltage Vthn of the transistor 15. Therefore, the reset current (=β×(Vgs−Vthn)×Vds) becomes zero. The gain coefficient β is a value that depends on the process of the transistor 15.

[0027] That is, the node voltage Vfd stops fluctuating before the source voltage of the transistor 15 becomes equal to the drain voltage of the transistor 15 (i.e., the reset potential Vr). As a result, the node voltage Vfd fluctuates to a potential obtained by subtracting the threshold voltage Vthn from the reset potential Vr during the reset period. Furthermore, when the reset period ends and the transistor 15 is switched from the on state to the off state, the node voltage Vfd is further reduced due to the influence of the clock feedthrough component and charge injection. As a result, the node voltage Vfd is set to the reset level.

[0028] As shown in FIG. 3, when transistor 12 is in the on state, the node voltage Vfd decreases from the reset level as the amount of stored charge increases.

[0029] The source follower circuit 14 is a circuit that generates an output voltage Vpix by amplifying a node voltage Vfd. The source follower circuit 14 includes a transistor 16 and a transistor 17. The transistors 16 and 17 are, for example, n-channel MOSFETs. The drain of the transistor 16 is electrically connected to a power supply line that supplies a power supply voltage Vdd. The gate of the transistor 16 is electrically connected to a node N1. The source of the transistor 16 and the drain of the transistor 17 are electrically connected to each other and electrically connected to a column signal line Lc. The source of the transistor 17 is electrically connected to a ground potential. A bias voltage is supplied to the gate of the transistor 17. The transistor 17 functions as a load transistor. The node voltage Vfd supplied to the gate of the transistor 16 is amplified, and the output voltage Vpix is ​​output from the source of the transistor 16 to the column signal line Lc.

[0030] The source follower circuit 14 has input / output characteristics shown in FIG. 4. The horizontal axis of FIG. 4 indicates the input voltage (node ​​voltage Vfd), and the vertical axis of FIG. 4 indicates the output voltage Vpix. The node voltage Vfd is input to the source follower circuit 14 as an input voltage. As described above, the node voltage Vfd decreases from the reset level according to the amount of accumulated charge. In the range in which the node voltage Vfd varies, the input voltage and the output voltage of the source follower circuit 14 are directly proportional to each other. That is, the output voltage Vpix is ​​obtained by multiplying the node voltage Vfd by a predetermined amplification factor. As the node voltage Vfd decreases, the output voltage Vpix also decreases. In other words, the output voltage Vpix is ​​a signal according to the charge accumulated by the light receiving element 11.

[0031] The pixel circuit 10 may further include a row selection transistor between the source of the transistor 16 and the column signal line Lc.

[0032] The column circuit 20 is a circuit that receives a target signal (output voltage Vpix) from the pixel circuit 10, and amplifies and removes noise from the target signal. A column circuit 20 is provided for each column of the pixel array. That is, M pixel circuits 10 belonging to the same column are commonly connected to one column circuit 20 via the same column signal line Lc. The column circuit 20 includes a filter circuit 21, an amplifier circuit 22, a sample-and-hold circuit 23, and a sample-and-hold circuit 24.

[0033] The filter circuit 21 is a circuit that removes noise from a target signal. In this embodiment, the filter circuit 21 receives an output voltage Vpix as a target signal from the pixel circuit 10. The filter circuit 21 configures a low-pass filter. The filter circuit 21 includes a CMOS switch 25 and a capacitor 26. The CMOS switch 25 has a terminal 25a and a terminal 25b. The terminal 25a is electrically connected to the column signal line Lc. The terminal 25b is electrically connected to one end of the capacitor 26 and is also electrically connected to the subsequent amplifier circuit 22. The CMOS switch 25 includes a transistor 27 (first MOSFET) and a transistor 28 (second MOSFET).

[0034] The transistor 27 and the transistor 28 are MOSFETs having different channel types. In this embodiment, the transistor 27 is a p-channel MOSFET, and the transistor 28 is an n-channel MOSFET. The transistor 27 and the transistor 28 are connected in parallel. Specifically, the source of the transistor 27 and the drain of the transistor 28 are electrically connected to each other and to the terminal 25a. The drain of the transistor 27 and the source of the transistor 28 are electrically connected to each other and to the terminal 25b.

[0035] A selection signal P_sel is supplied to the gate of the transistor 27. A selection signal N_sel is supplied to the gate of the transistor 28. When the low-level selection signal P_sel is supplied to the gate of the transistor 27, the transistor 27 is turned on. When the high-level selection signal P_sel is supplied to the gate of the transistor 27, the transistor 27 is turned off. When the high-level selection signal N_sel is supplied to the gate of the transistor 28, the transistor 28 is turned on. When the low-level selection signal N_sel is supplied to the gate of the transistor 28, the transistor 28 is turned off.

[0036] The on-resistance value Rp of transistor 27 and the on-resistance value Rn of transistor 28 have the characteristics shown in Fig. 5. The horizontal axis of Fig. 5 represents the input voltage (unit: V), and the vertical axis of Fig. 5 represents the resistance value (unit: Ω). As shown in Fig. 5, the on-resistance value Rp and the on-resistance value Rn vary according to the input voltage Vin of CMOS switch 25. As the input voltage Vin increases, the on-resistance value Rp decreases. On the other hand, as the input voltage Vin increases, the on-resistance value Rn increases.

[0037] Specifically, up to an input voltage Vin of about 1.7 V, as the input voltage Vin increases, the on-resistance value Rp decreases rapidly, and once the input voltage Vin exceeds 1.7 V, the on-resistance value Rp decreases gradually as the input voltage Vin increases. Up to an input voltage Vin of about 1.7 V, as the input voltage Vin increases, the on-resistance value Rn increases gradually, and once the input voltage Vin exceeds 1.7 V, the on-resistance value Rn increases rapidly as the input voltage Vin increases. The combined resistance value of the on-resistance values ​​Rp and Rn is a substantially constant value (about 2000 Ω) regardless of the input voltage Vin.

[0038] When both the transistor 27 and the transistor 28 are in the off state, the CMOS switch 25 is in the cut-off state. In the cut-off state, the terminal 25a and the terminal 25b are electrically isolated. When at least one of the transistors 27 and 28 is in the on state, the CMOS switch 25 is in the conductive state. In the conductive state, the terminal 25a and the terminal 25b are electrically connected. In the conductive state, the resistance value Rc of the CMOS switch 25 changes depending on the states of the transistors 27 and 28. When the transistor 27 is in the on state and the transistor 28 is in the off state, the resistance value Rc is the on resistance value Rp. When the transistor 27 is in the off state and the transistor 28 is in the on state, the resistance value Rc is the on resistance value Rn. When both the transistors 27 and 28 are in the on state, the resistance value Rc is the combined resistance value of the on resistance value Rp and the on resistance value Rn.

[0039] In this embodiment, the CMOS switch 25 is used in a conductive state and is switched between a state in which the resistance value Rc is low (low resistance state; first state) and a state in which the resistance value Rc is high (high resistance state; second state). In this embodiment, the input voltage Vin is the output voltage Vpix, and the fluctuation range of the input voltage Vin is a range larger than the voltage at which the on-resistance value Rn and the on-resistance value Rp have the same resistance value (about 1.7 V in the example shown in FIG. 5). In this fluctuation range, the on-resistance value Rn is larger than the on-resistance value Rp, and the combined resistance value of the on-resistance value Rp and the on-resistance value Rn is smaller than each of the on-resistance value Rn and the on-resistance value Rn. Therefore, the low resistance state is realized by setting both the transistor 27 and the transistor 28 to the on state. The high resistance state is realized by setting the transistor 27 to the off state and the transistor 28 to the on state. The reset potential Vr is set so that the fluctuation range of the input voltage Vin is within the above range. In other words, the setting circuit 13 sets the reset level of the output voltage Vpix so that the output voltage Vpix fluctuates within a range in which the on-resistance value Rn is greater than the on-resistance value Rp.

[0040] The capacitor 26 is electrically connected between the terminal 25b of the CMOS switch 25 and the ground potential. The time constant of the filter circuit 21 is the product of the resistance value Rc and the capacitance value of the capacitor 26.

[0041] The amplifier circuit 22 is a circuit that amplifies the output signal of the filter circuit 21. The amplifier circuit 22 includes an amplifier 31, a capacitor 32, a capacitor 33, and a switch 34. The amplifier 31 has an inverting input terminal, a non-input inverting terminal, and an output terminal. The non-inverting input terminal of the amplifier 31 is set to a reference potential Vref. The inverting input terminal of the amplifier 31 is electrically connected to the output of the filter circuit 21 via the capacitor 32.

[0042] The capacitor 33 is electrically connected between the inverting input terminal and the output terminal of the amplifier 31. The switch 34 is electrically connected between the inverting input terminal and the output terminal of the amplifier 31. The switch 34 is switched between an on state and an off state by a reset signal Amp_reset. When a high-level reset signal Amp_reset is supplied to the switch 34, the switch 34 is turned on. When a low-level reset signal Amp_reset is supplied to the switch 34, the switch 34 is turned off. The amplification factor (gain) of the amplifier circuit 22 is calculated by dividing the capacitance value of the capacitor 32 by the capacitance value of the capacitor 33.

[0043] The sample-and-hold circuit 23 is a circuit for holding a reset level of the output signal of the amplifier circuit 22. The sample-and-hold circuit 23 includes a switch 35 and a capacitor 36. One end of the capacitor 36 is electrically connected to the output terminal of the amplifier 31 via the switch 35. The other end of the capacitor 36 is electrically connected to the ground potential. The switch 35 is switched between an on state and an off state by a switching signal phi1. When a high-level switching signal phi1 is supplied to the switch 35, the switch 35 is turned on. When a low-level switching signal phi1 is supplied to the switch 35, the switch 35 is turned off. When the switch 35 is in the on state, the capacitor 36 is charged by the output signal of the amplifier circuit 22.

[0044] The sample-and-hold circuit 24 is a circuit for holding the output signal of the amplifier circuit 22. The sample-and-hold circuit 24 includes a switch 37 and a capacitor 38. One end of the capacitor 38 is electrically connected to the output terminal of the amplifier 31 via the switch 37. The other end of the capacitor 38 is electrically connected to the ground potential. The switch 37 is switched between an on state and an off state by a switching signal phi2. When a high-level switching signal phi2 is supplied to the switch 37, the switch 37 is turned on. When a low-level switching signal phi2 is supplied to the switch 37, the switch 37 is turned off. When the switch 37 is in the on state, the capacitor 38 is charged by the output signal of the amplifier circuit 22. The capacitance value of the capacitor 36 and the capacitance value of the capacitor 38 are equal to each other.

[0045] The control unit 50 is a circuit that controls the signal processing circuit 1. The control unit 50 is a computer device including hardware such as a processor and a memory. An example of the processor is a CPU (Central Processing Unit). The memory is composed of a RAM (Random Access Memory) and a ROM (Read Only Memory). The control unit 50 outputs a transfer signal TX and a reset signal Pix_reset to the pixel circuit 10 to control the pixel circuit 10. The control unit 50 outputs a selection signal P_sel and a selection signal N_sel to the filter circuit 21 to control the filter circuit 21. The control unit 50 switches the state of the CMOS switch 25 between a low resistance state and a high resistance state, for example. Specifically, the control unit 50 switches the state of the CMOS switch 25 from a low resistance state to a high resistance state while the capacitor 26 is being charged by the output voltage Vpix.

[0046] The control unit 50 outputs a reset signal Amp_reset to the amplifier circuit 22 to control the amplifier circuit 22. The control unit 50 outputs a switching signal phi1 to the sample and hold circuit 23 to control the sample and hold circuit 23. The control unit 50 outputs a switching signal phi2 to the sample and hold circuit 24 to control the sample and hold circuit 24. The control unit 50 may be a timing generator provided inside the signal processing circuit 1.

[0047] Next, a part of the read operation performed by the signal processing circuit 1 will be described with reference to Figs. 6 and 7. Fig. 6 is a timing chart showing a part of the operation of the signal processing circuit shown in Fig. 1. Fig. 7 is a diagram for explaining the settling time in the column circuit shown in Fig. 1. As shown in Fig. 6, before the start of the read operation (time t0), the reset signal Pix_reset, the reset signal Amp_reset, the transfer signal TX, the selection signal P_sel, the switching signal phi1, and the switching signal phi2 are all set to a low level. The selection signal N_sel is set to a high level.

[0048] At time t1, when the control unit 50 receives a trigger signal from the outside to start a read operation, it switches the reset signal Pix_reset, the reset signal Amp_reset, the switching signal phi1, and the switching signal phi2 from low level to high level. The states of the remaining signals are maintained. As the reset signal Pix_reset is switched to high level, the transistor 15 is turned on, and the reset operation of the node voltage Vfd of the node N1 is started. As the reset signal Amp_reset is switched to high level, the switch 34 is turned on. As a result, both ends of the capacitor 33 are short-circuited, and the charge accumulated in the capacitor 33 is discharged (reset). That is, the amplifier circuit 22 is in a reset state. At this time, the potentials of the inverting input terminal, the non-inverting input terminal, and the output terminal of the amplifier 31 are all set to the reference potential Vref.

[0049] Furthermore, as a result of the switching signal phi1 being switched to a high level, the switch 35 is turned on, and the sample-and-hold circuit 23 is placed in a state in which it can perform sampling. Similarly, as a result of the switching signal phi2 being switched to a high level, the switch 37 is turned on, and the sample-and-hold circuit 24 is placed in a state in which it can perform sampling.

[0050] Next, at time t2, the control unit 50 switches the reset signal Pix_reset from high to low. The states of the remaining signals are maintained. As a result of the reset signal Pix_reset being switched to low, the transistor 15 is turned off. This sets the node voltage Vfd to the reset level.

[0051] The time between time t1 and time t2 is set to, for example, a time required for the node voltage Vfd to be set to a potential obtained by subtracting the threshold voltage Vthn from the reset potential Vr after the reset signal Pix_reset is switched to a high level. In this case, the control unit 50 performs processing at time t2 in response to the passage of the above-mentioned time from time t1. When a monitor circuit that monitors the level of the node voltage Vfd detects that the node voltage Vfd has reached a potential obtained by subtracting the threshold voltage Vthn from the reset potential Vr, the circuit may output a trigger signal to the control unit 50. In this case, the control unit 50 performs processing at time t2 in response to receiving the trigger signal.

[0052] Subsequently, at time t3, the control unit 50 switches the reset signal Amp_reset from high to low. The states of the remaining signals are maintained. As the reset signal Amp_reset is switched to low, the switch 34 is turned off and the amplifier circuit 22 is in an operating state. At this time, the selection signal P_sel is at low level and the selection signal N_sel is at high level, so that the transistors 27 and 28 are both in an on state. Therefore, the CMOS switch 25 is in a low resistance state. That is, the time constant of the filter circuit 21 is small and the cutoff frequency of the filter circuit 21 is large. Therefore, as shown in the period T1 in FIG. 7, although the filter circuit 21 does not sufficiently remove noise such as thermal noise from the output voltage Vpix, the capacitors 36 and 38 are charged at high speed.

[0053] The time between time t2 and time t3 is set to, for example, a time required for the node voltage Vfd to be set to the reset level after the reset signal Pix_reset is switched to a low level. If necessary, the time may be set in consideration of the time required for the fluctuation in the input / output potential of the amplifier 31 accompanying the fluctuation in the node voltage Vfd to settle. In this case, the control unit 50 performs the process at time t3 in response to the passage of the time from time t2. When a monitor circuit that monitors the level of the node voltage Vfd detects that the node voltage Vfd has reached the reset level, a trigger signal may be output from the circuit to the control unit 50. In this case, the control unit 50 performs the process at time t3 in response to receiving the trigger signal.

[0054] Subsequently, at time t4, the control unit 50 switches the selection signal P_sel from low level to high level. The states of the remaining signals are maintained. As a result of the selection signal P_sel being switched to high level, the transistor 27 is turned off. Therefore, the CMOS switch 25 is in a high resistance state. That is, the time constant of the filter circuit 21 becomes large, and the cutoff frequency of the filter circuit 21 decreases. Therefore, as shown in period T2 in FIG. 7, noise such as thermal noise is sufficiently removed from the output voltage Vpix by the filter circuit 21, but the capacitors 36 and 38 are charged slowly.

[0055] The time between time t3 and time t4 may be preset based on the time constant of the filter circuit 21 when the CMOS switch 25 is in a low resistance state. In this case, the control unit 50 performs the process at time t4 in response to the passage of the above-mentioned time from time t3. When a monitor circuit that monitors the level of the charging voltage of the capacitor 26 detects that the charging voltage has reached a switching voltage determined in response to the output voltage Vpix, the circuit may output a trigger signal to the control unit 50. In this case, the switching voltage is smaller than the output voltage Vpix. When another monitor circuit that monitors the output voltage Vpix detects that the amplitude due to ringing of the output voltage Vpix becomes smaller than an arbitrary set value, a trigger signal may be output by another monitor circuit that monitors the output voltage Vpix. In this way, when a monitor circuit is used, the control unit 50 performs the process at time t4 in response to receiving the trigger signal.

[0056] Next, at time t5, the control unit 50 switches the switching signal phi1 from high to low. The states of the other signals are maintained. As a result of the switching signal phi1 being switched to low, the switch 35 is turned off and the charging voltage of the capacitor 36 is maintained.

[0057] The time between time t4 and time t5 may be preset based on the time constant of the filter circuit 21 when the CMOS switch 25 is in a high resistance state. In this case, the control unit 50 performs the process at time t5 in response to the passage of the above-mentioned time from time t4. When a monitor circuit that monitors the level of the charging voltage of the capacitor 26 detects that the charging voltage has reached a convergence voltage determined in response to the output voltage Vpix, a trigger signal may be output from the above circuit to the control unit 50. In this case, the control unit 50 performs the process at time t5 in response to receiving the trigger signal.

[0058] Subsequently, at time t6, the control unit 50 switches the selection signal P_sel from high level to low level, and switches the transfer signal TX from low level to high level. The states of the remaining signals are maintained. As the selection signal P_sel is switched to low level, the transistor 27 is turned on. Therefore, the CMOS switch 25 is in a low resistance state. Furthermore, as the transfer signal TX is switched to high level, the transistor 12 is turned on, and the charge accumulated in the light receiving element 11 is transferred to the node N1 via the transistor 12. The time between time t5 and time t6 is set to an arbitrary time. The control unit 50 performs the process at time t6 in response to the passage of the above-mentioned time from time t5.

[0059] Subsequently, at time t7, the control unit 50 switches the transfer signal TX from high level to low level. The states of the remaining signals are maintained. The transfer signal TX is switched to low level, and the transistor 12 is turned off. While the transfer signal TX is at high level, all the charges accumulated in the light receiving element 11 are transferred to the node N1. As described above, the node voltage Vfd drops from the reset level according to the amount of charge. Then, the node voltage Vfd is amplified by the source follower circuit 14 and converted into the output voltage Vpix, and the output voltage Vpix is ​​output to the column circuit 20 via the column signal line Lc. At this time, since the CMOS switch 25 is in a low resistance state, as shown in the period T1 of FIG. 7, the capacitor 38 is charged at high speed, although noise such as thermal noise is not sufficiently removed from the output voltage Vpix by the filter circuit 21.

[0060] The time between time t6 and time t7 is set to, for example, a time required for all the charges accumulated in the light receiving element 11 to be transferred to the node N1 after the transfer signal TX is switched to a high level. The control unit 50 performs the process at time t7 in response to the passage of the above-mentioned time from time t6.

[0061] Subsequently, at time t8, the control unit 50 switches the selection signal P_sel from low level to high level. The states of the remaining signals are maintained. As the selection signal P_sel is switched to high level, the transistor 27 is turned off. Therefore, the CMOS switch 25 is in a high resistance state, and as shown in period T2 in FIG. 7, noise such as thermal noise is sufficiently removed from the output voltage Vpix by the filter circuit 21, but the capacitor 38 is charged slowly. The trigger for the control unit 50 to perform the process at time t8 is the same as the trigger for the control unit 50 to perform the process at time t4.

[0062] Subsequently, at time t9, the control unit 50 switches the switching signal phi2 from high to low. The states of the remaining signals are maintained. As a result of the switching signal phi2 being switched to low, the switch 37 is turned off and the charging voltage of the capacitor 38 is maintained. The trigger for the control unit 50 to perform the process at time t9 is the same as the trigger for the control unit 50 to perform the process at time t5.

[0063] Subsequently, at time t10, the control unit 50 switches the selection signal P_sel from high level to low level. The states of the remaining signals are maintained. As a result of the selection signal P_sel being switched to low level, the transistor 27 is turned on. Therefore, the CMOS switch 25 is in a low resistance state. The time between time t9 and time t10 is set to an arbitrary time. The control unit 50 performs the process at time t10 in response to the passage of the above-mentioned time from time t9.

[0064] Then, the charging voltage of the capacitor 36 and the charging voltage of the capacitor 38 are supplied to the subsequent circuit. This completes the series of operations in the read process.

[0065] In the signal processing circuit 1 described above, a low-pass filter is configured by the CMOS switch 25 and the capacitor 26. The CMOS switch 25 includes a transistor 27 and a transistor 28 connected in parallel. The transistor 27 is a p-channel MOSFET, and the transistor 28 is an n-channel MOSFET. As the input voltage of the CMOS switch 25 increases, the on-resistance value Rp of the transistor 27 tends to decrease, and the on-resistance value Rn of the transistor 28 tends to increase. In the signal processing circuit 1, the CMOS switch 25 is used in a range in which the on-resistance value Rn is greater than the on-resistance value Rp. Therefore, the resistance value Rc of the CMOS switch 25 when the transistor 27 is in an off state and the transistor 28 is in an on state (high resistance state) is greater than the resistance value Rc of the CMOS switch 25 when both the transistors 27 and 28 are in an on state (low resistance state). Therefore, by switching the state of the CMOS switch 25 between a low resistance state and a high resistance state, the time constant of the filter circuit 21 can be switched. As a result, it is possible to omit the resistive element, thereby making it possible to reduce the circuit scale and to switch the time constant of the filter circuit.

[0066] For example, if the cutoff frequency is set to 10 kHz, the time constant is approximately 16 μsec. This time constant can be realized, for example, with a resistance value of 1 MΩ and a capacitance value of 16 pF. With a unit capacitance of 10 fF / μm 2 When a capacitor with a capacitance of 16 pF is created, the area of ​​the capacitor is 1591.5 μm 2 When a resistor element having a resistance value of 1 MΩ is fabricated using a sheet resistor having a width of 1.5 μm and a resistance value of 2 kΩ, the area of ​​the resistor element is 1125 μm 2 Therefore, the area of ​​the filter circuit is 2716.5 μm 2 On the other hand, if the CMOS switch 25 is fabricated using a 90 nm process, the area of ​​the CMOS switch 25 is 1.92 μm 2 Therefore, the area of ​​the filter circuit 21 is 1593.5 μm 2From the above, the area of ​​CMOS switch 25 is approximately 1 / 600 of the area of ​​a resistive element. Although there are some differences depending on the process and various conditions, the area of ​​CMOS switch 25 is reduced to approximately 1 / 200 to 1 / 600 of the area of ​​a resistive element. Even when comparing the area of ​​the entire filter circuit, the area of ​​filter circuit 21 is approximately 1 / 1.7 of the area of ​​a filter circuit using resistive elements.

[0067] The control unit 50 switches the state of the CMOS switch 25 from a low resistance state to a high resistance state while the capacitor 26 is being charged by the output voltage Vpix. According to this configuration, the time constant of the filter circuit 21 is switched from a small value to a large value while the capacitor 26 is being charged by the output voltage Vpix. Since the CMOS switch 25 is in a low resistance state from when the charging of the capacitor 26 starts by the output voltage Vpix until the charging voltage of the capacitor 26 approaches the output voltage Vpix, the capacitor 26 is charged at high speed. Then, when the charging voltage of the capacitor 26 approaches the output voltage Vpix, the state of the CMOS switch 25 is switched from a low resistance state to a high resistance state, and the capacitor 26 is charged slowly while noise is removed from the output voltage Vpix. In this way, it is possible to shorten the settling time required for the charging voltage of the capacitor 26 to reach the output voltage Vpix while removing noise from the output voltage Vpix.

[0068] In the signal processing circuit 1, the filter circuit 21 is provided between the light receiving element 11 (pixel circuit 10) and the amplifier circuit 22. The output voltage Vpix contains noise such as thermal noise caused by the source follower circuit 14. This noise is removed by the filter circuit 21 before being amplified by the amplifier circuit 22, so that the noise can be effectively removed.

[0069] As described above, the on-resistance value Rp and the on-resistance value Rn can vary depending on the input voltage (output voltage Vpix) of the CMOS switch 25. Therefore, by appropriately setting the reset level of the output voltage Vpix, the resistance value Rc in the low resistance state and the resistance value Rc in the high resistance state can be set to desired values.

[0070] Specifically, the setting circuit 13 sets the reset level of the output voltage Vpix so that the output voltage Vpix fluctuates within a range in which the on-resistance value Rn is greater than the on-resistance value Rp. With this configuration, the magnitude relationship between the resistance value Rc in the low resistance state and the resistance value Rc in the high resistance state is determined, so that the time constant of the filter circuit 21 can be reliably switched.

[0071] The low resistance state is a state in which both the transistor 27 and the transistor 28 are in the on state. In this case, the resistance value Rc in the low resistance state is the combined resistance value of the on resistance value Rp and the on resistance value Rn. Therefore, the resistance value Rc is smaller than the on resistance value Rp and the on resistance value Rn. This makes it possible to further reduce the time constant of the filter circuit 21 when the CMOS switch 25 is in the low resistance state.

[0072] Second embodiment Next, the configuration of a signal processing circuit according to a second embodiment will be described with reference to Fig. 8. Fig. 8 is a diagram showing the circuit configuration of a signal processing circuit according to a second embodiment. As shown in Fig. 8, the signal processing circuit 1A differs from the signal processing circuit 1 mainly in that it includes a column circuit 20A instead of the column circuit 20. The column circuit 20A differs from the column circuit 20 mainly in that it includes an amplifier circuit 22A instead of the amplifier circuit 22 and in the arrangement of the filter circuit 21.

[0073] The amplifier circuit 22A differs from the amplifier circuit 22 mainly in that it further includes a switch 41 and a switch 42, and in that it includes an amplifier 31A instead of the amplifier 31. The amplifier 31A is a single amplifier. The switch 41 is connected in series with the capacitor 33, and the series circuit of the capacitor 33 and the switch 41 is electrically connected between the input terminal and the output terminal of the amplifier 31A. One end of the switch 42 is electrically connected to the connection point between the capacitor 33 and the switch 41. The other end of the switch 42 is supplied with a reference potential Vref.

[0074] The filter circuit 21 is provided in the subsequent stage of the amplifier circuit 22A. That is, the amplifier circuit 22A generates an output signal (target signal) by amplifying the output voltage Vpix, and supplies the output signal to the filter circuit 21. The filter circuit 21 removes noise from the output signal of the amplifier circuit 22A.

[0075] The signal processing circuit 1A also has the same effect as the signal processing circuit 1. In the signal processing circuit 1, the filter circuit 21 is provided at the rear stage of the source follower circuit 14, whereas in the signal processing circuit 1A, the filter circuit 21 is provided at the rear stage of the amplifier circuit 22A. Since the source follower circuit 14 is disposed in the pixel array, the circuit size cannot be increased. Therefore, when the filter circuit 21 is driven by the source follower circuit 14 (current is fed into the filter circuit 21), the filter circuit 21 needs to be driven by several transistors. On the other hand, since the amplifier circuit 22A is restricted only by the column width, the circuit size can be made larger than that of the source follower circuit 14. Therefore, the amplifier circuit 22A can feed more current into the filter circuit 21. This allows the capacitor 26 to be charged quickly and reach a target potential in a short time.

[0076] The amplifier circuit 22A has a function as a setting circuit that sets the reset level of the output signal. Specifically, first, the switches 34 and 42 are set to the ON state, and the switch 41 is set to the OFF state. As a result, a potential difference obtained by subtracting the offset voltage of the amplifier 31A from the reference potential Vref is generated in the capacitor 33. Next, the switch 42 is set to the ON state, and the switches 34 and 41 are set to the OFF state. As a result, the input terminal of the amplifier 31A is in a floating state. Next, the switches 34, 41, and 42 are set to the OFF state. As a result, a charge corresponding to the potential difference obtained by subtracting the offset voltage of the amplifier 31A from the reference potential Vref is held in the capacitor 33. Next, the switch 41 is set to the ON state, and the switches 34 and 42 are set to the OFF state. As a result, the output signal of the amplifier circuit 22A (amplifier 31A) is level-shifted to the reference potential Vref. In this manner, the reset level of the output signal is set to the reference potential Vref.

[0077] As described above, the on-resistance value Rp and the on-resistance value Rn can vary depending on the input voltage Vin (output voltage Vpix) of the CMOS switch 25. Therefore, by appropriately setting the reset level of the output voltage Vpix, the resistance value Rc in the low resistance state and the resistance value Rc in the high resistance state can be set to desired values.

[0078] The signal processing circuit according to the present disclosure is not limited to the above embodiment.

[0079] For example, the column circuit 20 may include an amplifier circuit 22A instead of the amplifier circuit 22. The column circuit 20A may include an amplifier circuit 22 instead of the amplifier circuit 22A.

[0080] Since the input voltage Vin can take a value of, for example, 0 V to 3.3 V, the fluctuation range of the input voltage Vin does not need to be greater than the voltage range at which the on-resistance value Rn and the on-resistance value Rp have the same resistance value. Since the combined resistance value of the on-resistance value Rn and the on-resistance value Rp is smaller than both the on-resistance value Rn and the on-resistance value Rp, the low resistance state can be realized by setting both the transistor 27 and the transistor 28 to the on state, and the high resistance state can be realized by setting either the transistor 27 or the transistor 28 to the on state and the other to the off state.

[0081] In the signal processing circuits 1, 1A, the CMOS switch 25 is used in a range in which the on-resistance value Rn is greater than the on-resistance value Rp, so that the low resistance state of the CMOS switch 25 may be achieved by setting the transistor 27 to the on state and the transistor 28 to the off state.

[0082] In the above embodiment, the combined resistance value of the on-resistance value Rp and the on-resistance value Rn is substantially constant regardless of the input voltage Vin, but it does not have to be constant. In the example shown in FIG. 5, the on-resistance value Rn when the input voltage Vin is a low voltage and the on-resistance value Rp when the input voltage Vin is a high voltage are substantially equal, so the combined resistance value of the on-resistance value Rp and the on-resistance value Rn is substantially constant regardless of the input voltage Vin. In contrast, for example, the on-resistance value Rp may be set to a value lower than that in the example shown in FIG. 5. In other words, the on-resistance value Rp when the input voltage Vin is a high voltage may be set to a value smaller than the on-resistance value Rn when the input voltage Vin is a low voltage. In this case, the resistance value Rc in the low resistance state can be further lowered, so that the settling time can be further shortened.

[0083] The signal processing circuit 1 may further include an output buffer in the subsequent stage of the column circuit 20.

[0084] The transistor 15 may be a p-channel MOSFET. In this case, when the reset signal Pix_reset is at a low level, the transistor 15 is turned on. Therefore, a low-level pulsed reset signal Pix_reset is used.

[0085] For example, when the input voltage Vin is known in advance, the reset level of the output voltage Vpix is ​​set in advance according to the input voltage Vin. That is, the signal processing circuit 1 may be configured in advance so that the CMOS switch 25 is used in a range in which the on-resistance value Rn is greater than the on-resistance value Rp. In this case, the pixel circuit 10 does not need to include the setting circuit 13.

[0086] The circuit configuration of the pixel circuit 10 is not limited to the circuit configuration shown in Fig. 1 and Fig. 8. Modified examples of the pixel circuit will be described with reference to Figs. 9 to 12. Fig. 9 is a diagram showing a modified example of the pixel circuit. Fig. 10 is a diagram for explaining a reset level set by the setting circuit shown in Fig. 9. Fig. 11 is a diagram for explaining the voltage of the floating diffusion node shown in Fig. 9. Fig. 12 is a diagram showing the input / output characteristics of the source follower circuit shown in Fig. 9.

[0087] 9 differs from the pixel circuit 10 mainly in that a setting circuit 13A is provided instead of the setting circuit 13, a source follower circuit 14A is provided instead of the source follower circuit 14, and in the wiring of the light receiving element 11. In the pixel circuit 10A, the cathode of the light receiving element 11 is electrically connected to a power supply line that supplies a power supply voltage Vdd, and the anode of the light receiving element 11 is electrically connected to the drain of the transistor 12.

[0088] The setting circuit 13A differs from the setting circuit 13 mainly in that it includes a transistor 15A instead of the transistor 15. The transistor 15A is a p-channel MOSFET. The drain of the transistor 15A is set to a reset potential Vr. The source of the transistor 15A is electrically connected to a node N1. A reset signal Pix_reset is supplied to the gate of the transistor 15A. A low-level pulsed reset signal Pix_reset is supplied to the gate of the transistor 15A, whereby a reset operation of the node voltage Vfd is performed while the reset signal Pix_reset is at a low level (reset period). In the reset operation, the transistor 15A is turned on, and the node voltage Vfd is set to the reset level.

[0089] 10, the reset level of the node voltage Vfd is greater than the reset potential Vr. More specifically, when transistor 15A is turned on, the source voltage of transistor 15A (i.e., node voltage Vfd) drops, and the source-gate voltage Vsg of transistor 15A drops. Then, before the source-drain voltage Vsd of transistor 15A becomes zero, the source-gate voltage Vsg of transistor 15A becomes smaller than the threshold voltage Vthp of transistor 15A. Therefore, the reset current (=β×(Vsg-Vthp)×Vsd) becomes zero.

[0090] That is, the fluctuation of the node voltage Vfd stops before the source voltage of the transistor 15A becomes equal to the drain voltage of the transistor 15A (i.e., the reset potential Vr). As a result, the node voltage Vfd fluctuates to a potential obtained by adding the threshold voltage Vthp to the reset potential Vr during the reset period. Furthermore, when the reset period ends and the transistor 15A is switched from the on state to the off state, the node voltage Vfd further increases due to the influence of the clock feedthrough component and charge injection. As a result, the node voltage Vfd is set to the reset level.

[0091] As shown in FIG. 11, when transistor 12 is in the on state, the node voltage Vfd rises from the reset level as the amount of stored charge increases.

[0092] The source follower circuit 14A differs from the source follower circuit 14 mainly in that the source follower circuit 14A includes transistors 16A and 17A instead of the transistors 16 and 17. The transistors 16A and 17A are, for example, p-channel MOSFETs. The drain of the transistor 16A is electrically connected to a ground potential. The gate of the transistor 16A is electrically connected to a node N1. The source of the transistor 16A and the drain of the transistor 17A are electrically connected to each other and to a column signal line Lc. The source of the transistor 17A is electrically connected to a power supply line that supplies a power supply voltage Vdd. A bias voltage is supplied to the gate of the transistor 17A. The transistor 17A functions as a load transistor. The node voltage Vfd supplied to the gate of the transistor 16A is amplified, and an output voltage Vpix is ​​output from the source of the transistor 16A to the column signal line Lc.

[0093] The source follower circuit 14A has input / output characteristics shown in FIG. 12. The horizontal axis of FIG. 12 indicates the input voltage (node ​​voltage Vfd), and the vertical axis of FIG. 12 indicates the output voltage Vpix. The node voltage Vfd is input to the source follower circuit 14A as an input voltage. As described above, the node voltage Vfd increases from the reset level according to the amount of accumulated charge. In the range in which the node voltage Vfd varies, the input voltage and the output voltage of the source follower circuit 14A have a directly proportional relationship. That is, the output voltage Vpix is ​​obtained by multiplying the node voltage Vfd by a predetermined amplification factor. As the node voltage Vfd increases, the output voltage Vpix also increases. In other words, the output voltage Vpix is ​​a signal according to the charge accumulated by the light receiving element 11.

[0094] The fluctuation range of the input voltage Vin of the CMOS switch 25 provided in the subsequent stage is less than the voltage (about 1.7V in the example shown in FIG. 5) at which the on-resistance value Rn and the on-resistance value Rp have the same resistance value. In this fluctuation range, the on-resistance value Rp is larger than the on-resistance value Rn, and the combined resistance value of the on-resistance value Rp and the on-resistance value Rn is smaller than the on-resistance value Rn and the on-resistance value Rn, respectively. Therefore, the low resistance state is realized by setting both the transistor 27 (second MOSFET) and the transistor 28 (first MOSFET) to the on state. The high resistance state is realized by setting the transistor 27 to the on state and the transistor 28 to the off state. The reset potential Vr is set so that the fluctuation range of the input voltage Vin is within the above range. In other words, the setting circuit 13A sets the reset level of the output voltage Vpix so that the output voltage Vpix fluctuates within a range in which the on-resistance value Rp is larger than the on-resistance value Rn.

[0095] Even in this configuration, the fluctuation range of the input voltage Vin does not have to be less than the voltage at which the on-resistance value Rn and the on-resistance value Rp have the same resistance value. Since the combined resistance value of the on-resistance value Rn and the on-resistance value Rp is smaller than both the on-resistance value Rn and the on-resistance value Rp, the low resistance state can be realized by setting both the transistor 27 and the transistor 28 to the on state, and the high resistance state can be realized by setting either the transistor 27 or the transistor 28 to the on state and the other to the off state.

[0096] The pixel circuit 10A may further include a row selection transistor between the source of the transistor 16A and the column signal line Lc.

[0097] In the signal processing circuits 1, 1A including the pixel circuit 10A, the CMOS switch 25 is used in a range in which the on-resistance value Rp is greater than the on-resistance value Rn, so that the resistance value Rc when the transistor 27 is on and the transistor 28 is off (high resistance state) is greater than the resistance value Rc when the transistors 27 and 28 are both on (low resistance state). Therefore, when the input voltage Vin of the CMOS switch 25 is low, the time constant of the filter circuit 21 can be switched more reliably.

[0098] Any circuit may be used as the monitor circuit that monitors the level of the node voltage Vfd and the level of the charging voltage of the capacitor 26. Fig. 13 is a diagram showing an example of the circuit configuration of the monitor circuit. The monitor circuit 60 shown in Fig. 13 is a circuit that monitors the level of the charging voltage of the capacitor 26. The monitor circuit 60 includes an amplifier 61, a resistive element 62, a resistive element 63, and a comparator 64.

[0099] The amplifier 61 has an inverting input terminal, a non-input inverting terminal, and an output terminal. The non-inverting input terminal of the amplifier 61 is electrically connected to the column signal line Lc. The inverting input terminal of the amplifier 61 is electrically connected to the output terminal of the amplifier 61. That is, the amplifier 61 constitutes a voltage follower circuit, and receives the output voltage Vpix and outputs the output voltage Vpix. One end of the resistance element 62 is electrically connected to the output terminal of the amplifier 61, and the other end of the resistance element 62 is electrically connected to one end of the resistance element 63 and the inverting input terminal of the comparator 64. The other end of the resistance element 63 is electrically connected to the ground potential. A resistive voltage divider circuit is constituted according to the resistance elements 62 and 63. The output voltage Vpix is ​​divided by the resistance value of the resistance element 62 and the resistance value of the resistance element 63, and a switching voltage that is several percent lower than the output voltage Vpix is ​​supplied to the inverting input terminal of the comparator 64.

[0100] The non-inverting input terminal of the comparator 64 is electrically connected to one end of the capacitor 26. The charging voltage of the capacitor 26 is supplied to the non-inverting input terminal of the comparator 64. The output terminal of the comparator 64 is electrically connected to the control unit 50. While the charging voltage is smaller than the switching voltage, the comparator 64 outputs a low-level trigger signal. When the charging voltage exceeds the switching voltage, the comparator 64 outputs a high-level trigger signal. When the control unit 50 receives a high-level trigger signal from the comparator 64, it switches the selection signal P_sel from low to high (see time t4 and time t8 in FIG. 6). [Explanation of symbols]

[0101] 1,1A...signal processing circuit, 10,10A...pixel circuit, 11...light receiving element, 12...transistor, 13,13A...setting circuit, 14,14A...source follower circuit, 15,15A...transistor, 16,16A...transistor, 17,17A...transistor, 20,20A...column circuit, 21...filter circuit, 22,22A...amplifier circuit, 23...sample and hold circuit, 24...sample and hold circuit, 25...CMOS switch, 25a...terminal, 25b...terminal, 26...capacitor, 27...transistor, 28...transistor, 31...amplifier, 32...capacitor, 33...capacitor, 34...switch, 35...switch, 36...capacitor, 37...switch, 38...capacitor, 41...switch, 42...switch, 50...control unit, Lc...column signal line, N1...node.

Claims

1. a filter circuit for removing noise from the target signal; A control unit that controls the filter circuit; Equipped with The filter circuit includes: a CMOS switch including a first MOSFET and a second MOSFET having different channel types connected in parallel; a capacitor electrically connected between the output of the CMOS switch and a ground potential; Equipped with the control unit switches a state of the CMOS switch between a first state in which the first MOSFET is in an on state and a second state in which the first MOSFET is in an off state and the second MOSFET is in an on state; an on-resistance value of the second MOSFET is greater than an on-resistance value of the first MOSFET;

2. 2 . The signal processing circuit according to claim 1 , wherein the control unit switches the state of the CMOS switch from the first state to the second state while the capacitor is being charged by the target signal.

3. a light receiving element that generates and accumulates electric charges when irradiated with light; an amplifier circuit that amplifies an output signal of the filter circuit, 3. The signal processing circuit according to claim 1, wherein the filter circuit receives, as the target signal, a signal corresponding to the charge accumulated by the light receiving element.

4. a light receiving element that generates and accumulates electric charges when irradiated with light; 3. The signal processing circuit according to claim 1, further comprising: an amplifier circuit that generates the target signal by amplifying a signal corresponding to the charge accumulated by the light receiving element, and supplies the target signal to the filter circuit.

5. 5. The signal processing circuit according to claim 4, wherein the amplifier circuit includes a setting circuit that sets a reset level of the target signal.

6. 5. The signal processing circuit according to claim 1, further comprising a setting circuit that sets a reset level of the target signal.

7. 7. The signal processing circuit according to claim 5, wherein the setting circuit sets the reset level so that a voltage of the target signal fluctuates within a range in which an on-resistance value of the second MOSFET is greater than an on-resistance value of the first MOSFET.

8. 8. The signal processing circuit according to claim 1, wherein the first state is a state in which the first MOSFET and the second MOSFET are both in an on state.

9. the first MOSFET is a p-channel MOSFET, 9. The signal processing circuit according to claim 1, wherein the second MOSFET is an n-channel MOSFET.

10. the first MOSFET is an n-channel MOSFET, 9. The signal processing circuit according to claim 1, wherein the second MOSFET is a p-channel MOSFET.

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