Phase detection method and device

Abstract

The present invention provides a phase detection method and apparatus. The phase detection apparatus includes a signal processing assembly, a phase detection component, and a phase comparison assembly. The signal processing assembly is configured to acquire a reference clock signal and its initial phase value. The phase detection component is configured to acquire a clock signal under test and to derive a first phase difference signal based on the reference clock signal and the clock signal under test. The phase comparison assembly is configured to derive a phase adjustment signal based on the first phase difference signal. The signal processing assembly is further configured to adjust the phase of the reference clock signal in response to the phase adjustment signal so as to reduce the first phase difference signal, accumulate the adjusted phase values ​​to obtain a phase accumulation value, and obtain a phase value of the clock signal under test based on the phase accumulation value and the initial phase value.

Description

[Technical field]

[0001] This application is filed based on a Chinese patent application bearing application number 202010428524.6 and filed on May 20, 2020, and claims priority to that Chinese patent application, the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE Embodiments of the invention relate to the field of communications technology, particularly but not exclusively to phase detection methods and devices. [Background technology]

[0003] At present, in 5G communication, the requirements for the accuracy of clock time in IEEE 1588 are becoming higher and higher, and the time synchronization accuracy of a single node is already required to be within a few nanoseconds. To further improve the accuracy of the clock signal, it is necessary to either increase the frequency of the clock signal or measure and compensate the phase of the clock signal. The former places high requirements on chips and processes, while the latter places relatively low requirements on chips and processes, so the latter has better cost performance.

[0004] There are three main clock phase measurement methods currently in common use. The first method is to sample the clock signal under test with a clock signal of a very high frequency to obtain phase information. The second method is to first generate several clock signals with the same frequency but different phases from one clock signal by phase shifting, compare them with the clock signal under test, and find the one clock signal with the closest phase to obtain phase information. The third method is to sample the clock signal under test while shifting the phase of one clock signal by a small step size, and obtain phase information from the sampled value obtained after one period. The first method has high requirements for chips and processes. The cost of realizing the second method is relatively small, but the accuracy is not high. The third method is highly accurate but has a slow measurement speed, and the higher the accuracy, the slower the speed becomes.

[0005] Therefore, how to accomplish clock phase measurement with high accuracy and high speed has become an issue that needs to be solved as soon as possible. Summary of the Invention [Problem to be solved by the invention]

[0006] The following is a summary of the subject matter described in detail herein, which is not intended to limit the scope of protection of the claims.

[0007] An embodiment of the present invention provides a phase detection method and an apparatus and device thereof. [Means for solving the problem]

[0008] In a first aspect, an embodiment of the present invention provides a phase detection apparatus comprising: a signal processing assembly configured to acquire a reference clock signal and an initial phase value of the reference clock signal, and output the reference clock signal; a phase detection component connected to the signal processing assembly and configured to acquire a measured clock signal, and to acquire and output a first phase difference signal based on the reference clock signal and the measured clock signal; and a phase comparison assembly connected to the phase detection component and the signal processing assembly, respectively, and configured to acquire and output a phase adjustment signal based on the first phase difference signal, wherein the signal processing assembly is further configured to: perform a phase adjustment on the reference clock signal in response to the phase adjustment signal so that the first phase difference signal is smaller, accumulate the adjusted phase values ​​to obtain a phase accumulation value, and obtain a phase value of the measured clock signal based on the phase accumulation value and the initial phase value.

[0009] In a second aspect, an embodiment of the present invention further provides a phase detection method applied to a phase detection device, the phase detection device comprising a signal processing assembly, a phase detection component, and a phase comparison assembly, which are serially connected in sequence as a loop, the method including the steps of: acquiring a reference clock signal and an initial phase value of the reference clock signal by the signal processing assembly, and outputting the reference clock signal to the phase detection component; acquiring a measured clock signal by the phase detection component, acquiring a first phase difference signal based on the reference clock signal and the measured clock signal, and outputting the first phase difference signal to the phase comparison assembly; acquiring a phase adjustment signal based on the first phase difference signal by the phase comparison assembly, and outputting the phase adjustment signal to the signal processing assembly; adjusting the phase of the reference clock signal by the signal processing assembly according to the phase adjustment signal so that the first phase difference signal is smaller, accumulating the adjusted phase values ​​to obtain a phase accumulation value, and obtaining a phase value of the measured clock signal based on the phase accumulation value and the initial phase value.

[0010] In a third aspect, embodiments of the present invention further provide an apparatus comprising the phase detection apparatus of the first aspect described above.

[0011] Additional features and advantages of the invention will be set forth in the following specification, and in part will be obvious from the specification, or may be learned by the practice of the invention. The objectives and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims and drawings.

[0012] The accompanying drawings are intended to provide a further understanding of the technical solution of the present invention, constitute a part of the specification, and are used to interpret the technical solution of the present invention together with the embodiments of the present invention, and are not intended to constitute limitations on the technical solution of the present invention. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic diagram of a phase detection apparatus provided according to an embodiment of the present invention; [Diagram 2] FIG. 4 is a schematic diagram of a phase detection device provided according to another embodiment of the present invention. [Diagram 3] FIG. 4 is a schematic diagram of a phase detection device provided according to another embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram of a phase detection device provided according to another embodiment of the present invention. [Diagram 5] FIG. 4 is a schematic diagram of a phase detection device provided according to another embodiment of the present invention. [Figure 6] 4 is a flow chart of a phase detection method provided by one embodiment of the present invention. [Figure 7] 4 is a flowchart of a phase detection method provided by another embodiment of the present invention. [Figure 8] 4 is a flowchart of a phase detection method provided by another embodiment of the present invention. [Figure 9] 4 is a flowchart of a phase detection method provided by another embodiment of the present invention. [Figure 10] 4 is a flowchart of a phase detection method provided by another embodiment of the present invention. [Figure 11] 1 is a schematic diagram of an apparatus provided according to one embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in more detail below in combination with the accompanying drawings and examples. The specific examples described herein are only used to interpret the present invention, and are not used to limit the present invention.

[0015] In addition, although the schematic diagram of the device shows a functional module division and the flowchart shows a logical order, in some cases, the steps shown or described may be performed in a manner different from the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims, and above drawings are intended to distinguish similar objects and are not necessarily intended to describe a specific order or sequence.

[0016] An embodiment of the present invention provides a phase detection method and an apparatus and device thereof, and the phase detection apparatus includes a signal processing assembly, a phase detection component, and a phase comparison assembly, which are connected in series as a loop. The phase comparison assembly obtains a phase adjustment signal based on a first phase difference signal output from the phase detection component, and the first phase difference signal is obtained by the phase detection component based on a reference clock signal and a clock signal to be measured. Meanwhile, the signal processing assembly performs a phase adjustment on the reference clock signal according to the phase adjustment signal so that the first phase difference signal becomes smaller. That is, by adjusting the phase of the reference clock signal, the first phase difference signal output from the phase detection component based on the reference clock signal and the clock signal to be measured is gradually decreased, and the phase of the reference clock signal is brought closer to the phase of the clock signal to be measured, so that the accuracy of the first phase difference signal output from the phase detection component can be gradually increased, and the phase detection accuracy for the clock signal can be further increased. In addition, since phase adjustment is performed on the reference clock signal within the numerical range of the first phase difference signal and for the purpose of reducing the first phase difference signal, phase detection on the clock signal can be achieved by performing processing only a limited number of times within the numerical range of the first phase difference signal. In some cases, therefore, a superior phase detection speed can be obtained compared to a method of acquiring phase information over one clock period, thereby improving the phase detection accuracy and phase detection speed on the clock signal.

[0017] Embodiments of the invention will now be further described with reference to the accompanying drawings, in which: As shown in FIG. 1, FIG. 1 is a schematic diagram of a phase detection device provided by an embodiment of the present invention. In the example of FIG. 1, the phase detection device 100 includes a signal processing assembly 110, a phase detection component 120, and a phase comparison assembly 130, which are connected in series as a loop in order. The signal processing assembly 110 can be configured to obtain a reference clock signal and an initial phase value of the reference clock signal, and output the reference clock signal. The phase detection component 120 can be configured to obtain a measured clock signal, and obtain and output a first phase difference signal based on the reference clock signal and the measured clock signal. The phase comparison assembly 130 can be configured to obtain and output a phase adjustment signal based on the first phase difference signal. Note that the signal processing assembly 110 can be further configured to perform a phase adjustment on the reference clock signal according to the phase adjustment signal so that the first phase difference signal is small, accumulate the adjusted phase values ​​to obtain a phase accumulation value, and obtain a phase value of the measured clock signal based on the phase accumulation value and the initial phase value. Thus, the signal processing assembly 110, the phase detection component 120, and the phase comparison assembly 130 cooperate to provide phase detection for the clock signal.

[0018] In one embodiment, the test clock signal is a clock signal for which phase detection is desired and the reference clock signal is a known clock signal that is configured to detect the phase of the test clock signal. When the signal processing assembly 110 first acquires the reference clock signal, the signal processing assembly 110 can acquire an initial phase value of the reference clock signal, thereby providing the necessary baseline for obtaining the phase value of the test clock signal in subsequent operations.

[0019] In one embodiment, the first phase difference signal is a signal obtained by the phase detection component 120 based on the reference clock signal and the measured clock signal, and due to constraints such as manufacturing technology or calculation accuracy of the phase detection component 120, the first phase difference signal output from the phase detection component 120 is not accurate. Therefore, a signal processing assembly 110 and a phase comparison assembly 130 are provided, and the signal processing assembly 110, the phase detection component 120, and the phase comparison assembly 130 are connected in series in sequence as a loop, and the phase comparison assembly 130 obtains a phase adjustment signal based on the first phase difference signal output from the phase detection component 120, while the signal processing assembly 110 adjusts the phase of the reference clock signal according to the phase adjustment signal, so that the value of the first phase difference signal can be reduced. That is, by mutual cooperation between the phase detection component 120, the phase comparison assembly 130, and the signal processing assembly 110, the phase of the reference clock signal is adjusted to gradually decrease the first phase difference signal output from the phase detection component 120, and the phase of the reference clock signal can be gradually brought closer to the phase of the measured clock signal, so that the accuracy of the first phase difference signal obtained by the phase detection component 120 based on the reference clock signal and the measured clock signal can be improved. In addition, since the phase adjustment is performed on the reference clock signal within the numerical range of the first phase difference signal and for the purpose of decreasing the first phase difference signal, the phase detection of the measured clock signal can be realized by only performing a limited number of processes within the numerical range of the first phase difference signal. Therefore, in some cases, a better phase detection speed can be obtained according to this embodiment compared to a method of acquiring phase information over one clock period, so that this embodiment can improve the phase detection accuracy and phase detection speed of the clock signal.

[0020] In one embodiment, the signal processing assembly 110 may include a field programmable gate array (FPGA) chip configured to have a phase shifter function, or may include a combination of a digital signal processing (DSP) chip and a digital phase shifter, and the present embodiment is not specifically limited. When the signal processing assembly 110 includes a combination of a DSP chip and a digital phase shifter, the digital phase shifter obtains a reference clock signal, and the DSP chip obtains the reference clock signal and an initial phase value of the reference clock signal, and outputs a constituent signal to the digital phase shifter according to a phase adjustment signal output from the phase comparison assembly 130. Thus, the digital phase shifter performs phase adjustment on the reference clock signal according to the constituent signal, thereby reducing the first phase difference signal obtained by the phase detection component 120 based on the reference clock signal and the clock signal under test. In addition, the DSP chip accumulates the phase values ​​when the phase adjustment is performed on the reference clock signal, and obtains the phase value of the clock signal under test based on the accumulated phase value and the initial phase value of the reference clock signal.

[0021] In one embodiment, the phase detection component 120 may be a digital phase detector or an analog phase detector. When a digital phase detector is used as the phase detection component 120, the phase detection component 120 may be an independent digital phase detector or a digital phase detector built into the signal processing assembly 110, for example, the phase detection component 120 may be a functional component in an FPGA chip. The specific embodiment of the phase detection component 120 is not specifically limited in this embodiment.

[0022] In one embodiment, the phase comparison assembly 130 may include a signal processing chip such as an FPGA chip, or may include a logic processing chip such as a comparator, but is not specifically limited in this embodiment.

[0023] In the case where the phase comparison assembly 130 includes a signal processing chip such as an FPGA chip, when the first phase difference signal output from the phase detection component 120 is received by the phase comparison assembly 130, the phase comparison assembly 130 can first determine whether the first phase difference signal satisfies a predetermined condition, and if the predetermined condition is satisfied, output a corresponding phase adjustment signal. For example, when the phase comparison assembly 130 determines that the first phase difference signal is within a first predetermined interval range, the phase comparison assembly 130 can output a phase adjustment signal set to cause a positive phase shift to the reference clock signal. On the other hand, when the phase comparison assembly 130 determines that the first phase difference signal is within a second predetermined interval range, the phase comparison assembly 130 can output a phase adjustment signal set to cause a negative phase shift to the reference clock signal. Note that the predetermined condition can be appropriately set according to actual usage needs, and this embodiment does not specifically limit this. Note that the first predetermined interval range and the second predetermined interval range can also be appropriately set according to actual usage needs, and this embodiment does not specifically limit this.

[0024] When the phase comparison assembly 130 includes a logic processing chip such as a comparator, when the first phase difference signal output from the phase detection component 120 is received by the phase comparison assembly 130, the phase comparison assembly 130 can logically compare the first phase difference signal with a reference signal and output a corresponding phase adjustment signal according to the comparison result between the first phase difference signal and the reference signal. For example, when the first phase difference signal is larger than the reference signal, the phase comparison assembly 130 can output a phase adjustment signal set to cause a negative phase shift in the reference clock signal. On the other hand, when the first phase difference signal is smaller than the reference signal, the phase comparison assembly 130 can output a phase adjustment signal set to cause a positive phase shift in the reference clock signal. Note that the reference signal may be a signal set based on experience or may be a signal related to the reference clock signal, and may be appropriately set according to the actual use needs, and is not specifically limited in this embodiment.

[0025] 2, in one embodiment, the phase comparison assembly 130 includes, but is not limited to, a first signal generating component 131 and a signal comparing component 132, where the first signal generating component 131 is connected to the phase detection component 120, and the signal comparing component 132 is connected to the first signal generating component 131 and the signal processing assembly 110, respectively. The first signal generating component 131 can be configured to obtain a first voltage signal based on the first phase difference signal, and the signal comparing component 132 can be configured to obtain a reference voltage signal and the first voltage signal, and obtain a phase adjustment signal based on the reference voltage signal and the first voltage signal, the phase adjustment signal being set to perform a phase adjustment with respect to a reference clock signal.

[0026] In one embodiment, the first signal generating component 131 can be a charge pump, which is also called a switched capacitor voltage converter, and can output a voltage value by being charged and storing energy. When the first phase difference signal output from the phase detection component 120 is received by the first signal generating component 131, the first signal generating component 131 charges according to a period indicated by the first phase difference signal to obtain a first voltage signal, thereby providing a basic condition required for obtaining a phase adjustment signal in a subsequent step.

[0027] In one embodiment, the signal comparison component 132 may be a voltage comparator, and the reference voltage signal may be a voltage signal set based on experience, or may be a voltage signal related to the reference clock signal, and may be appropriately set according to the actual use needs, and this embodiment is not specifically limited thereto. When the signal comparison component 132 obtains the reference voltage signal and the first voltage signal, the signal comparison component 132 can obtain a phase adjustment signal set to perform a phase adjustment on the reference clock signal based on the reference voltage signal and the first voltage signal. For example, when the voltage value of the first voltage signal is greater than the voltage value of the reference voltage signal, the signal comparison component 132 can output a phase adjustment signal with a high level value, which can be set to cause the signal processing assembly 110 to perform a phase adjustment on the reference clock signal by a negative phase shift. When the voltage value of the first voltage signal is less than the voltage value of the reference voltage signal, the signal comparison component 132 can output a phase adjustment signal with a low level value, which can be set to cause the signal processing assembly 110 to perform a phase adjustment on the reference clock signal by a positive phase shift. When the voltage value of the first voltage signal is equal to the voltage value of the reference voltage signal, the signal comparing component 132 can output a phase adjustment signal having a level value of a middle level, which can be set to cause the signal processing assembly 110 to stop the phase adjustment operation for the reference clock signal. The middle level is a level between a high level and a low level. Therefore, the cooperation of the first signal generating component 131 and the signal comparing component 132 can provide an accurate adjustment direction for the phase adjustment of the reference clock signal by the signal processing assembly 110, so that the phase of the reference clock signal can be made closer to the phase of the measured clock signal, so that the accuracy of the first phase difference signal output from the phase detecting component 120 can be gradually improved, and the phase detection accuracy for the clock signal can be further improved.

[0028] 3, in one embodiment, the phase comparison assembly 130 may further include a second signal generating component 133 connected to the signal comparing component 132. The second signal generating component 133 may be configured to obtain a phase reference signal derived based on a reference clock signal, and to obtain a reference voltage signal based on the phase reference signal.

[0029] In one embodiment, the second signal generating component 133 can be a charge pump, which is also called a switched capacitor voltage converter, and can output a voltage value by being charged and storing energy. When a phase reference signal is received by the second signal generating component 133, the second signal generating component 133 can charge according to a period indicated by the phase reference signal to obtain a reference voltage signal, thereby providing a basic condition required for obtaining a phase adjustment signal in a subsequent step.

[0030] In one embodiment, the phase reference signal can be obtained based on the period of the reference clock signal. For example, the phase reference signal can be a half period of the reference clock signal, or a quarter period of the reference clock signal, and can be appropriately selected according to the needs of actual use, and this embodiment is not specifically limited thereto.

[0031] In one embodiment, the phase reference signal is a preset fixed value, and the reference voltage signal obtained by charging the second signal generating component 133 according to the period indicated by the phase reference signal is also a fixed value, so that it can be easily compared with the first voltage signal to obtain a phase adjustment signal.

[0032] Also, referring to FIG. 4, in one embodiment, the signal processing assembly 110 includes, but is not limited to, a controller 111 and a phase shift component 112. The phase comparison assembly 130, the controller 111, the phase shift component 112, and the phase detection component 120 are connected in sequence. The controller 111 can be configured to obtain an initial phase value of the reference clock signal, obtain a phase shift signal based on a phase adjustment signal output from the phase comparison assembly 130, and transmit the phase shift signal to the phase shift component 112. Meanwhile, the phase shift component 112 can be configured to obtain a reference clock signal, and perform a phase adjustment on the reference clock signal according to the phase shift signal, so that a first phase difference signal output from the phase detection component 120 is reduced based on the reference clock signal and the measured clock signal. Also, the controller 111 can be further configured to accumulate the phase shift signal to obtain a phase accumulation value, and obtain a phase value of the measured clock signal based on the phase accumulation value and the initial phase value of the reference clock signal.

[0033] In one embodiment, the controller 111 may have different embodiments, for example, the controller 111 may be an FPGA chip, a DSP chip, or a combination of a control chip and a 2-divider, and this embodiment does not specifically limit it. When the controller 111 is a combination of a control chip and a 2-divider, the 2-divider plays a role of generating 2-divide information (for example, a phase shift signal in this embodiment), and the control chip can play a role of configuring the 2-divide information in the phase shift component 112, so that the phase shift component 112 can adjust the shift amount of the phase of the reference clock signal based on the 2-divide information. In addition, the phase shift component 112 may have different embodiments, for example, the phase shift component 112 may be a digital phase shifter, or an analog phase shifter with configuration function, and this embodiment does not specifically limit it.

[0034]

number

[0035] In one embodiment, when the phase comparison assembly 130 includes a signal comparison component 132, which outputs a phase adjustment signal to the controller 111, the phase comparison component 132 being configured to perform a phase adjustment on the reference clock signal, the controller 111 may transmit different types of configuration information to the phase shift component 112 according to different types of phase adjustment signals, so that the phase shift component 112 can perform different phase adjustment processes on the reference clock signal according to the different types of configuration information. For example, when the level value of the phase adjustment signal is high, the controller 111 transmits configuration information to the phase shift component 112 indicating a negative phase shift, so that the phase shift component 112 performs a phase adjustment on the reference clock signal by a negative phase shift according to the configuration information indicating a negative phase shift. When the level value of the phase adjustment signal is low, the controller 111 transmits configuration information to the phase shift component 112 indicating a positive phase shift, so that the phase shift component 112 performs a phase adjustment on the reference clock signal by a positive phase shift according to the configuration information indicating a positive phase shift. When the level value of the phase adjustment signal is the middle level, the controller 111 does not transmit configuration information to the phase shift component 112, i.e., the phase shift component 112 does not perform phase adjustment on the reference clock signal. The middle level is a level between the high level and the low level. In this way, the controller 111 and the phase shift component 112 cooperate to perform phase adjustment on the reference clock signal in a correct adjustment direction, so that the phase of the reference clock signal can be brought closer to the phase of the clock signal to be measured, and therefore the accuracy of the first phase difference signal output from the phase detection component 120 can be gradually increased, and further the phase detection accuracy for the clock signal can be increased.

[0036] In one embodiment, the signal processing assembly 110 further comprises a counter, which may be built into the controller 111 or may be externally connected to the controller 111 .

[0037] In one embodiment, the count value of the counter can be set not only to represent the number of times the signal processing assembly 110 adjusts the phase of the reference clock signal, but also to obtain a phase shift signal for adjusting the phase of the reference clock signal.

[0038] In one embodiment, a maximum count value may be set in the counter, and the controller 111 may reset the counter to 0 when the current count value of the counter reaches the maximum count value, i.e., when the number of phase adjustments of the reference clock signal by the signal processing assembly 110 reaches a preset maximum number of adjustments, or when the controller 111 receives a phase adjustment signal whose level value is a middle level. The resetting of the counter by the controller 111 indicates that the phase measurement has been completed so that the next phase detection can be performed. The middle level is a level between the high level and the low level.

[0039] Moreover, in one embodiment, the controller 111 is specifically configured to obtain the phase value of the clock signal under test based on the phase accumulation value and the initial phase value according to the following formula:

[0040]

number

[0041]

number

[0042]

number

[0043] For example, if it is necessary to perform phase detection on a time stamp-providing clock signal having a frequency of 125 MHz and the period of the time stamp-providing clock signal is 8 ns, when a reference clock signal having the same frequency as the time stamp-providing clock signal is used to perform phase detection on the time stamp-providing clock signal by the phase detection device 100 of this embodiment, if the maximum count value of the counter is 10, that is, the number of phase adjustments of the reference clock signal by the signal processing assembly 110 is 9 times (the reference clock signal is not phase adjusted the first time), as can be seen from the above formula, the measurement accuracy finally obtained is about 8 ps. On the other hand, when the measurement is performed in some cases by a method of acquiring phase information over one clock period, if it is necessary to achieve the same measurement accuracy, that is, if phase information is acquired over one clock period with a step size of 8 ps, 1000 phase shift operations are required, so this embodiment has a better phase detection speed than some cases. Also, as can be seen from the above example, when the same number of phase shifts are performed, this embodiment has a better phase detection accuracy than some cases.

[0044] Further, referring to Fig. 5, another embodiment of the present invention further provides a phase detection device, the phase detection device 200 includes a controller 211, a digital phase shifter 212, a digital phase detector 220, a first charge pump 231, a voltage comparator 232, a second charge pump 233, and a counter 213, the controller 211, the digital phase shifter 212, the digital phase detector 220, the first charge pump 231, and the voltage comparator 232 are serially connected in a loop, the controller 211 is further connected to the counter 213, and the voltage comparator 232 is further connected to the second charge pump 233.

[0045] Referring to FIG. 5, when phase detection is performed on a clock signal under test using phase detection apparatus 200, the devices in phase detection apparatus 200 cooperate with each other to realize the following detection principle.

[0046]

number

[0047] The controller 211 sets the maximum count value of the counter 213 to n, and causes the counter 213 to start counting from zero.

[0048] Before starting the phase detection operation, the current count value of the counter 213 is 0, so no phase adjustment of the reference clock signal is performed. In this case, the digital phase shifter 212 outputs an initial reference clock signal to the digital phase detector 220. The digital phase detector 220 obtains a first phase difference signal based on the initial reference clock signal and the clock signal under test, and outputs the first phase difference signal to the first charge pump 231. The first charge pump 231 charges according to the period indicated by the first phase difference signal, and outputs a first voltage signal to the voltage comparator 232. The voltage comparator 232 obtains a phase adjustment signal based on the first voltage signal and the reference voltage signal, and outputs the phase adjustment signal to the controller 211.

[0049]

number

[0050] After the controller 211 and the digital phase shifter 212 work together to adjust the phase of the reference clock signal, the phase-adjusted reference clock signal is input to the digital phase detector 220. At this time, the digital phase detector 220 obtains and outputs a new first phase difference signal based on the phase-adjusted reference clock signal and the measured clock signal, while the first charge pump 231 and the voltage comparator 232 work together to output a new phase adjustment signal to the controller 211 based on the new first phase difference signal. In this way, detection is repeated until the count value of the counter 213 reaches the predetermined maximum count value, and the phase detection operation of the measured clock signal is completed. In this case, the following results are obtained:

[0051]

number

[0052]

number

[0053] If the level value of the phase adjustment signal is at a middle level (i.e., a level between high and low levels), the phase of the reference clock signal and the phase of the measured clock signal are out of phase by half a period, in which case the phase adjustment operation for the reference clock signal is stopped and the phase detection operation is terminated. In this case, the phase value of the measured clock signal can be obtained in the same way according to the above formula, and the explanation will be omitted here.

[0054] The above described device embodiment is merely illustrative, and the units described as separate parts may or may not be physically separated, i.e., located in one place or distributed among several network units. Some or all of these modules can be selected according to actual needs to achieve the objectives of the aspects of this embodiment.

[0055] Further, referring to Fig. 6, an embodiment of the present invention further provides a phase detection method which can be applied to the phase detection device in the above-mentioned device embodiment, the phase detection method includes, but is not limited to, the following steps:

[0056] In step S100, a reference clock signal and an initial phase value of the reference clock signal are obtained by a signal processing assembly, and the reference clock signal is output to a phase detection component.

[0057] In step S200, a phase detection component obtains a clock signal under test, obtains a first phase difference signal according to a reference clock signal and the clock signal under test, and outputs the first phase difference signal to a phase comparison assembly.

[0058] In step S300, a phase-adjusted signal is obtained by a phase comparison assembly based on the first phase difference signal, and the phase-adjusted signal is output to a signal processing assembly.

[0059] In step S400, the signal processing assembly performs a phase adjustment on the reference clock signal according to the phase adjustment signal so that the first phase difference signal becomes small, accumulates the adjusted phase values ​​to obtain a phase accumulation value, and obtains a phase value of the measured clock signal based on the phase accumulation value and the initial phase value.

[0060] In one embodiment, the test clock signal is a clock signal for which phase detection is desired and the reference clock signal is a known clock signal configured to detect the phase of the test clock signal. When the signal processing assembly first acquires the reference clock signal, the signal processing assembly can acquire an initial phase value of the reference clock signal, thereby providing the necessary baseline for obtaining the phase value of the test clock signal in subsequent operations.

[0061] In one embodiment, the first phase difference signal is a signal obtained by the phase detection component based on the reference clock signal and the measured clock signal, and is not accurate due to limitations in the manufacturing technology or calculation accuracy of the phase detection component. Therefore, the first phase difference signal output from the phase detection component is transmitted to the phase comparison assembly, which enables the phase comparison assembly to obtain a phase adjustment signal based on the first phase difference signal and transmit the phase adjustment signal to the signal processing assembly. Meanwhile, the signal processing assembly performs phase adjustment on the reference clock signal according to the phase adjustment signal so that the numerical value of the first phase difference signal becomes smaller. That is, through the mutual cooperation between the phase detection component, the phase comparison assembly and the signal processing assembly, the phase of the reference clock signal can be adjusted to gradually decrease the first phase difference signal output from the phase detection component, and the phase of the reference clock signal can be gradually approached to the phase of the measured clock signal, thereby improving the accuracy of the first phase difference signal obtained by the phase detection component based on the reference clock signal and the measured clock signal. Furthermore, since phase adjustment is performed on the reference clock signal within the numerical range of the first phase difference signal and for the purpose of reducing the first phase difference signal, phase detection of the measured clock signal can be achieved by performing processing only a limited number of times within the numerical range of the first phase difference signal. Therefore, compared to a method of acquiring phase information over one clock period, this embodiment can obtain a superior phase detection speed, and therefore this embodiment can improve the phase detection accuracy and phase detection speed for the clock signal.

[0062] In addition, since the phase detection method of this embodiment can be applied to the phase detection device in the above-mentioned device embodiment, for specific implementation forms of the signal processing assembly, phase detection components, and phase comparison assembly in this embodiment, reference may be made to the related explanations in the above-mentioned device embodiment, and the explanation will be omitted here.

[0063] Also, in one embodiment, when the phase comparison assembly includes a first signal generating component and a signal comparing component, and the signal processing assembly, the phase detection component, the first signal generating component, and the signal comparing component are serially connected in a loop in sequence, refer to FIG. 7, step S300 may include, but is not limited to, the following steps:

[0064] In step S310, the first signal generating component obtains a first voltage signal based on the first phase difference signal, and outputs the first voltage signal to the signal comparing component.

[0065] In step S320, the signal comparing component obtains the reference voltage signal and the first voltage signal, obtains a phase-adjusted signal according to the reference voltage signal and the first voltage signal, and outputs the phase-adjusted signal by the signal comparing component to the signal processing assembly.

[0066] In one embodiment, the first signal generating component can be a charge pump, also called a switched capacitor voltage converter, which can be charged to store energy and output a voltage value. When the first signal generating component receives the first phase difference signal output from the phase detection component, the first signal generating component can charge according to a period indicated by the first phase difference signal to obtain a first voltage signal, thereby providing a basic condition required for obtaining a phase adjustment signal in a subsequent step.

[0067] In one embodiment, the reference voltage signal may be a voltage signal set based on experience, or may be a voltage signal related to a reference clock signal, and may be appropriately set according to actual usage needs, and this embodiment does not specifically limit this.

[0068] In one embodiment, when the signal comparison component obtains the reference voltage signal and the first voltage signal, the signal comparison component can obtain a phase adjustment signal based on the reference voltage signal and the first voltage signal, the phase adjustment signal being set to perform a phase adjustment on the reference clock signal. For example, if the voltage value of the first voltage signal is greater than the voltage value of the reference voltage signal, the signal comparison component can output a phase adjustment signal having a high level value that can be set to cause the signal processing assembly to perform a phase adjustment on the reference clock signal by a negative phase shift. If the voltage value of the first voltage signal is less than the voltage value of the reference voltage signal, the signal comparison component can output a phase adjustment signal having a low level value that can be set to cause the signal processing assembly to perform a phase adjustment on the reference clock signal by a positive phase shift. If the voltage value of the first voltage signal is equal to the voltage value of the reference voltage signal, the signal comparison component can output a phase adjustment signal having a middle level (i.e., a level between a high level and a low level) that can be set to cause the signal processing assembly to stop the phase adjustment operation on the reference clock signal. In addition, the specific examples in which the above-mentioned signal comparison component obtains a phase adjustment signal based on the reference voltage signal and the first voltage signal can be formed into different combination examples according to actual situations, but in order to avoid duplication of content, the description will be omitted here.

[0069] In one embodiment, the cooperation of the first signal generating component and the signal comparing component can provide a precise adjustment direction for the phase adjustment of the reference clock signal by the signal processing assembly, so that the phase of the reference clock signal can be made closer to the phase of the measured clock signal, thereby gradually improving the accuracy of the first phase difference signal output by the phase detection component, and further improving the phase detection accuracy for the clock signal.

[0070] In addition, in one embodiment, when the phase comparison assembly further includes a second signal generating component, and the second signal generating component and the signal comparison component are connected, refer to FIG. 8, and the phase detection method can further include the following steps:

[0071] In step S500, the second signal generating component obtains a phase reference signal obtained based on a reference clock signal, and obtains a reference voltage signal based on the phase reference signal.

[0072] In step S600, the second signal generating component outputs a reference voltage signal to the signal comparing component.

[0073] In one embodiment, the second signal generating component can be a charge pump, which is also called a switched capacitor voltage converter, and can output a voltage value by being charged and storing energy. When a phase reference signal is received by the second signal generating component, the second signal generating component can be charged according to a period indicated by the phase reference signal to obtain a reference voltage signal, thereby providing a basic condition required for obtaining a phase adjustment signal in a subsequent step.

[0074] In one embodiment, the phase reference signal can be obtained based on the period of the reference clock signal. For example, the phase reference signal can be a half period of the reference clock signal, or a quarter period of the reference clock signal, and can be appropriately selected according to the needs of actual use, and this embodiment is not specifically limited thereto.

[0075] Also, in one embodiment, the signal processing assembly in step S400 performs a phase adjustment on the reference clock signal in response to the phase adjustment signal, but different embodiments may include different specific steps.

[0076] In step S401, if the level value of the phase adjustment signal is at a high level, the signal processing assembly performs phase adjustment with a negative phase shift on the reference clock signal.

[0077] In step S402, if the level value of the phase adjustment signal is at a low level, the signal processing assembly performs a phase adjustment with a positive phase shift on the reference clock signal.

[0078] In step S403, if the level value of the phase adjustment signal is a middle level between the high level and the low level, the signal processing assembly does not perform phase adjustment on the reference clock signal.

[0079] In addition, the above-mentioned steps S401, S402, and S403 may be parallel technical solutions, or may be combined with each other to form different technical solutions. They can be appropriately selected according to the actual situation, and this embodiment does not specifically limit this.

[0080] In one embodiment, according to different level values ​​of the phase adjustment signal, the signal processing assembly can perform phase adjustment in different directions on the reference clock signal, so that the phase of the reference clock signal can be made closer to the phase of the measured clock signal, thereby gradually increasing the accuracy of the first phase difference signal output from the phase detection component, and further increasing the phase detection accuracy for the clock signal.

[0081] Also, in one embodiment, when the signal processing assembly includes a controller and a phase shift component, and the phase comparison assembly, the controller, the phase shift component, and the phase detection component are serially connected in a loop in sequence, refer to FIG. 9, step S400 may include, but is not limited to, the following steps:

[0082] In step S410, the controller obtains a phase shift signal based on the phase adjust signal, and outputs the phase shift signal to the phase shift component.

[0083] In step S420, the phase shift component performs a phase adjustment on the reference clock signal according to the phase shift signal, such that the first phase difference signal becomes smaller.

[0084] In step S430, the controller accumulates the phase shift signals to obtain a phase accumulation value, and obtains a phase value of the measured clock signal based on the phase accumulation value and the initial phase value.

[0085]

number

[0086] In one embodiment, after the controller receives the phase adjustment signal, the controller may send different types of configuration information to the phase shift component according to different types of the phase adjustment signal, so that the phase shift component can perform different phase adjustment processes on the reference clock signal according to the different types of configuration information. For example, when the level value of the phase adjustment signal is a high level, the controller sends configuration information indicating a negative phase shift to the phase shift component, so that the phase shift component performs phase adjustment on the reference clock signal by a negative phase shift according to the configuration information indicating a negative phase shift. When the level value of the phase adjustment signal is a low level, the controller sends configuration information indicating a positive phase shift to the phase shift component, so that the phase shift component performs phase adjustment on the reference clock signal by a positive phase shift according to the configuration information indicating a positive phase shift. When the level value of the phase adjustment signal is a middle level, the controller does not send configuration information to the phase shift component, i.e., the phase shift component does not perform phase adjustment on the reference clock signal. Note that the middle level is a level between a high level and a low level. In this way, by performing phase adjustment in an accurate adjustment direction for the reference clock signal through cooperation between the controller and the phase shift component, the phase of the reference clock signal can be brought closer to the phase of the clock signal to be measured, thereby gradually increasing the accuracy of the first phase difference signal output from the phase detection component and further increasing the phase detection accuracy for the clock signal.

[0087] In addition, in one embodiment, if the signal processing assembly further includes a counter, and the counter is built into the controller or the counter is external to the controller and connected to the controller, referring to FIG. 10, the step of the controller obtaining a phase shift signal based on the phase adjustment signal in step S410 may include the following specific steps:

[0088] In step S411, the controller obtains the count value of the counter. In step S412, the controller derives a phase shift signal based on the count value.

[0089] In one embodiment, the count value of the counter is not only set to represent the number of times the signal processing assembly adjusts the phase of the reference clock signal, but also set to obtain a phase shift signal for adjusting the phase of the reference clock signal. Therefore, by obtaining the count value of the counter, not only can the phase shift signal set to adjust the phase of the reference clock signal be easily obtained, but also the phase shift signal accumulated based on the count value can be calculated to easily obtain the phase value of the measured clock signal.

[0090] In one embodiment, the counter can be set to a maximum count value. When the current count value of the counter is the maximum count value, i.e., when the number of phase adjustments of the reference clock signal by the signal processing assembly reaches a predetermined maximum number of adjustments, the controller can reset the counter to 0. The resetting of the counter by the controller indicates that the phase measurement has been completed so that the next phase detection can be performed.

[0091] In addition, in one embodiment, the step of obtaining the phase value of the clock signal under test based on the phase accumulation value and the initial phase value in step S430 may specifically include the following specific steps:

[0092] In step S431, the controller obtains the phase value of the clock signal under test based on the phase accumulation value and the initial phase value by the following formula:

[0093]

number

[0094]

number

[0095]

number

[0096] Further, referring to FIG. 11, an embodiment of the present invention further provides an apparatus, which may include the phase detection device in any one of the device embodiments described above.

[0097] The device in this embodiment includes the phase detection device in any one of the above embodiments, so that the device in this embodiment has the hardware structure of the phase detection device in the above embodiments, and the components in the phase detection device can cooperate with each other to enable the device in this embodiment to perform the phase detection method in any one of the above method embodiments. Therefore, the specific embodiment of the device in this embodiment can refer to the above embodiments, but the description is omitted here to avoid redundancy.

[0098] Since the device in this embodiment includes the phase detection device in any one of the above embodiments, the device in this embodiment has the technical effect provided by the phase detection device in the above embodiments, that is, compared with some cases, the device in this embodiment can improve the phase detection accuracy and phase detection speed for a clock signal.

[0099] SUMMARY OF THE PREFERRED EMBODIMENTS An embodiment of the present invention provides a phase detection method and an apparatus therefor that can improve the phase detection accuracy and speed of a clock signal.

[0100] In the embodiment of the present invention, the phase of the reference clock signal can be made to approach the phase of the clock signal under test with a limited number of processes, so that the measurement of the clock phase can be completed with high accuracy and high speed.

[0101] Those skilled in the art will understand that all or some steps of the methods, systems disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical assemblies can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on computer readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). Those skilled in the art will appreciate that the term computer storage media includes volatile and non-volatile, removable and non-removable media, implemented in any method or technology for storing information (computer readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cartridges, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and that can be accessed by a computer. Additionally, communication media typically includes computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media, as known to those skilled in the art.

[0102] Although several embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions within the scope of the claims of the present invention without violating the scope of the present invention.

Claims

1. a signal processing assembly, a phase detection component, and a phase comparison assembly, which are connected in series as a loop in turn; the signal processing assembly is configured to acquire a first reference clock signal, acquire an initial phase value of the first reference clock signal when the first reference clock signal is initially acquired, and output the first reference clock signal as a second reference clock signal to the phase detection component; the phase detection component is configured to acquire a clock signal under test, derive a first phase difference signal based on the second reference clock signal and the clock signal under test, and output the first phase difference signal to the phase comparison assembly; the phase comparison assembly is configured to derive a phase adjustment signal based on the first phase difference signal, and output the phase adjustment signal to the signal processing assembly; the signal processing assembly is further configured to: upon receiving the phase adjustment signal from the phase comparison assembly, perform a phase adjustment on the first reference clock signal in response to the phase adjustment signal so as to reduce the first phase difference signal, thereby obtaining the second reference clock signal; output the second reference clock signal to the phase detection component; accumulate adjusted phase values ​​to obtain a phase accumulation value; and obtain a phase value of the measured clock signal based on the phase accumulation value and the initial phase value; the phase comparison assembly comprises a first signal generating component, a second signal generating component, and a signal comparing component; the first signal generating component is connected to the phase detection component and configured to obtain and output a first voltage signal based on the first phase difference signal; The second signal generating component is connected to the signal comparing component, and is configured to obtain a phase reference signal based on the first reference clock signal, and obtain and output a reference voltage signal based on the phase reference signal; the signal comparison component is connected to the first signal generation component, the second signal generation component and the signal processing assembly, respectively, and configured to obtain the reference voltage signal and the first voltage signal, and obtain and output the phase adjustment signal based on the reference voltage signal and the first voltage signal; Phase detector.

2. The signal processing assembly includes: a controller coupled to the phase comparison assembly and configured to obtain an initial phase value of the first reference clock signal and to obtain and output a phase shift signal based on the phase adjustment signal; a phase shift component connected to the controller and the phase detection component, respectively, to acquire the first reference clock signal, and to perform a phase adjustment on the first reference clock signal in response to the phase shift signal so that the first phase difference signal is reduced; The controller is further configured to accumulate the phase shift signals to obtain a phase accumulation value, and to obtain a phase value of the measured clock signal based on the phase accumulation value and the initial phase value.

2. The phase detection device according to claim 1.

3. The signal processing assembly further comprises: A counter is provided which is built into the controller or is externally attached to the controller and connected to the controller.

3. The phase detection device according to claim 2.

4. the controller is configured to derive a phase value of the clock signal under test based on the phase accumulation value and the initial phase value by: [0010] where T1 is the phase value of the clock signal under test, T2 is the initial phase value, [0025] is the phase accumulation value, T is the period of the first reference clock signal, n is the number of phase adjustments for the first reference clock signal, and n≧1.

3. The phase detection device according to claim 2.

5. A phase detection method applied to a phase detection device, the phase detection device comprising: a signal processing assembly, a phase detection component, and a phase comparison assembly, the phase comparison assembly comprising a first signal generating component, a second signal generating component, and a signal comparison component, the signal processing assembly, the phase detection component, the first signal generating component, and the signal comparison component being serially connected in a loop in sequence, the second signal generating component being connected to the signal comparison component, The phase detection method includes: acquiring, by the signal processing assembly, a first reference clock signal, acquiring an initial phase value of the first reference clock signal when the first reference clock signal is acquired for the first time, and outputting the first reference clock signal as a second reference clock signal to the phase detection component; acquiring, by the phase detection component, a clock signal under test, deriving a first phase difference signal based on the second reference clock signal and the clock signal under test, and outputting the first phase difference signal to the phase comparison assembly; obtaining a phase adjustment signal based on the first phase difference signal by the phase comparison assembly, and outputting the phase adjustment signal to the signal processing assembly; receiving the phase adjustment signal from the phase comparison assembly, the signal processing assembly performs a phase adjustment on the first reference clock signal according to the phase adjustment signal so that the first phase difference signal is reduced, thereby obtaining the second reference clock signal, outputting the second reference clock signal to the phase detection component, accumulating the adjusted phase value to obtain a phase accumulation value, and obtaining a phase value of the measured clock signal based on the phase accumulation value and the initial phase value; Including, obtaining a phase adjustment signal based on the first phase difference signal by the phase comparison assembly, and outputting the phase adjustment signal to the signal processing assembly, the first signal generating component derives a first voltage signal based on the first phase difference signal, and outputs the first voltage signal to the signal comparing component; the second signal generating component obtains a phase reference signal based on the first reference clock signal, obtains a reference voltage signal based on the phase reference signal, and outputs the reference voltage signal to the signal comparing component; the signal comparing component obtains the reference voltage signal and the first voltage signal, obtains the phase adjustment signal based on the reference voltage signal and the first voltage signal, and outputs the phase adjustment signal to the signal processing assembly; A method comprising:

6. The step of the signal comparing component obtaining a phase adjustment signal based on the reference voltage signal and the first voltage signal includes: When the first voltage signal is greater than the reference voltage signal, the signal comparing component outputs a phase adjusting signal whose level value is a high level; When the first voltage signal is equal to the reference voltage signal, the signal comparing component outputs a phase adjusting signal whose level value is a middle level between a high level and a low level; When the first voltage signal is smaller than the reference voltage signal, the signal comparing component outputs a phase adjusting signal whose level value is a low level; The method of claim 5 , comprising at least one of:

7. the signal processing assembly performing a phase adjustment on the first reference clock signal in response to the phase adjustment signal, When the level value of the phase adjustment signal is a high level, the signal processing assembly performs a phase adjustment with a negative phase shift on the first reference clock signal; When the level value of the phase adjustment signal is a low level, the signal processing assembly performs a phase adjustment with a positive phase shift on the first reference clock signal; when a level value of the phase adjustment signal is an intermediate level between a high level and a low level, the signal processing assembly does not perform a phase adjustment on the first reference clock signal; The method of claim 5 , comprising at least one of:

8. the signal processing assembly includes a controller and a phase shift component, the phase comparison assembly, the controller, the phase shift component, and the phase detection component being serially connected in a loop in sequence; receiving the phase adjustment signal from the phase comparison assembly, the signal processing assembly performs a phase adjustment on the first reference clock signal in response to the phase adjustment signal so that the first phase difference signal is reduced, thereby obtaining the second reference clock signal, outputting the second reference clock signal to the phase detection component, accumulating the adjusted phase values ​​to obtain a phase accumulation value, and obtaining a phase value of the measured clock signal based on the phase accumulation value and the initial phase value; the controller deriving a phase shift signal based on the phase adjustment signal, and outputting the phase shift signal to the phase shift component; the phase shift component performing a phase adjustment on the first reference clock signal in response to the phase shift signal such that the first phase difference signal is reduced; the controller accumulating the phase shift signal to obtain a phase accumulation value, and obtaining a phase value of the clock signal under test based on the phase accumulation value and the initial phase value.

8. The method according to any one of claims 5 to 7.

9. the signal processing assembly further comprises a counter, the counter being integrated into the controller or external to the controller and connected to the controller; The step of the controller obtaining a phase shift signal based on the phase adjustment signal includes: The controller acquires a count value of the counter; the controller deriving a phase shift signal based on the count value; 9. The method of claim 8, comprising:

10. The step of the controller obtaining a phase value of the clock signal under test based on the phase accumulation value and the initial phase value includes: The controller obtains a phase value of the clock signal under test based on the phase accumulation value and the initial phase value by the following formula: [0030] where T1 is the phase value of the clock signal under test, T2 is the initial phase value, [0045] is the phase accumulation value, T is the period of the first reference clock signal, n is the number of phase adjustments for the first reference clock signal, and n≧1. The method according to claim 8.

11. A phase detection device according to any one of claims 1 to 4. device.

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