CLOCK DATA RECOVERY CIRCUIT AND CLOCK DATA RECOVERY METHOD

Abstract

A clock data recovery circuit and a clock data recovery method, the clock data recovery circuit comprising: a time delay loop (100) configured to delay input data based on a phase of a clock signal to align the phases; a frequency locked loop (200) connected to the time delay loop (100) and configured to adjust the frequency of the clock signal based on the delayed input data to match the frequency of the clock signal with the frequency of the input data; and a deserializer (300) connected to each of the time delay loop (100) and the frequency locked loop (200) and configured to deserialize the input data based on the clock signal.

Description

[Technical field]

[0001] This application is based on and claims priority to a Chinese patent application bearing application number 202110224295.0 and filing date March 1, 2021, the entire contents of which are incorporated by reference.

[0002] The present application relates to the field of communications, and in particular to a clock data recovery circuit and a clock data recovery method. [Background technology]

[0003] In the phase-locked loop in the clock data recovery circuit of some technical solutions, the frequency phase is locked by negative feedback between the phase comparator, the charge pump, the loop filter and the voltage-controlled oscillator. In the small signal model analysis, the small signal equation K of the voltage-controlled oscillator is VCO / s is the integral part, and the phase is always added in the process of locking the phase, and the capacitance of the filter is 1 / sC, and the charge is added in the process of charging and discharging, so it can be seen that there are two poles in the closed-loop simulation. In a system with two poles, the circuit must be designed taking into account factors related to stability such as the phase margin and gain margin of the system, so the phase-locked loop in some technical solutions must be compensated with a high-order stable filter to ensure the stability of the system. In addition, the clock data recovery circuit in some technical solutions further includes a frequency-locked loop to lock the frequency, but the frequency-locked loop must work in cooperation with the phase-locked loop, which makes the circuit structure of the clock data recovery circuit complicated. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE DISCLOSURE The embodiments of the present application provide a clock data recovery circuit and a clock data recovery method. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application provides a clock data recovery circuit including a time delay loop configured to delay and align input data based on a phase of a clock signal, a frequency locked loop connected to the time delay loop and configured to adjust a frequency of the clock signal based on the delayed input data to match a frequency of the clock signal with a frequency of the input data, and a deserializer connected to the time delay loop and the frequency locked loop, respectively, and configured to deserialize the input data based on the clock signal.

[0006] In a second aspect, an embodiment of the present application provides a clock data recovery method applied to a clock data recovery circuit including a time delay loop, a frequency locked loop connected to the time delay loop, and a deserializer connected to the time delay loop and the frequency locked loop, the clock data recovery method including a step of delaying input data based on a phase of a clock signal by the time delay loop to align the phases, a step of adjusting a frequency of the clock signal by the frequency locked loop based on the delayed input data to match the frequency of the clock signal and the frequency of the input data, and a step of deserializing the input data based on the clock signal by the deserializer. Effect of the Invention

[0007] Additional features and advantages of the present application will be set forth in the specification, and in part will be obvious from the specification, or may be learned by the practice of the present application. The objectives and other advantages of the present application may be realized by the structure particularly pointed out in the written description, claims and drawings. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram of a clock data recovery circuit provided by an embodiment of the present application. [Diagram 2]FIG. 2 is a circuit diagram of a numerically controlled delay unit of a clock data recovery circuit provided by an embodiment of the present application. [Diagram 3] FIG. 2 is a circuit diagram of a 1 / 4 frequency multiplier provided by an embodiment of the present application. [Figure 4] 4 is a timing chart of the circuit operation of a 1 / 4 frequency multiplier provided in an embodiment of the present application. [Diagram 5] 4 is a timing chart of zero phase and frequency determination provided by an embodiment of the present application. [Figure 6] 2 is a flowchart of a clock data recovery method provided by an embodiment of the present application; [Figure 7] 4 is a flowchart of a clock data recovery method provided by another embodiment of the present application; [Figure 8] 4 is a flowchart of a clock data recovery method provided by yet another embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The drawings are intended to provide a further understanding of the technical solutions of the present application, form a part of the specification, and are used to explain the technical solutions of the present application together with the examples of the present application, but are not intended to limit the technical solutions of the present application.

[0010] The present application will now be further described with reference to the drawings and examples.

[0011] This section describes in detail specific embodiments of the present application and illustrates some embodiments of the present application. The role of the drawings is to supplement the written description in the specification with figures, so as to enable intuitive understanding of the technical features and overall technical solutions of the present application, but should not be construed as limiting the scope of protection of the present application.

[0012] In the description of this application, the references "first" and "second" are intended only to distinguish technical features and should not be construed as indicating or implying a relative importance, or implicitly indicating the quantity of the technical feature it refers to, or implicitly indicating the context of the technical feature it refers to.

[0013] In the description of the present application, unless otherwise specified, terms such as install, attach, connect, etc. shall be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the above terms in the present application in combination with the specific content of the technical solutions.

[0014] The embodiments of the present application provide a clock data recovery circuit and a clock data recovery method that can simplify the circuit structure.

[0015] The embodiments of the present application will be further described below with reference to the drawings.

[0016] Please refer to FIG. 1, which is a block diagram of a clock data recovery circuit provided in an embodiment of the present application.

[0017] As shown in FIG. 1, an embodiment of a first aspect of the present application provides a clock data recovery circuit including a time delay loop 100 configured to delay and align input data based on a phase of a clock signal, a frequency locked loop 200 connected to the time delay loop 100 and configured to adjust the frequency of the clock signal based on the delayed input data to match the frequency of the clock signal with the frequency of the input data, and a deserializer 300 connected to the time delay loop 100 and the frequency locked loop 200, respectively, and configured to deserialize the input data based on the clock signal.

[0018] In the clock data recovery circuit of this embodiment, the phase of the clock signal is first compared with the phase of the input data, and the input data is delayed to align the phase of the input data with the clock signal, thereby avoiding the introduction of a phase integral element. After the phase is aligned, the phase of the clock signal is consistent with the phase of the delayed input data. If the frequency of the delayed input data does not match the frequency of the clock signal, a certain phase difference will occur after a certain time has passed. The frequency of the clock signal is adjusted by the frequency-locked loop 200 based on the phase difference caused by the frequency mismatch between the delayed input data and the clock signal, thereby achieving the purpose of locking the frequency. After the frequency and phase of the input data and the frequency and phase of the clock signal are locked, the clock signal passes through the deserializer 300 to deserialize the input data. The technical solution provided by this embodiment can avoid the introduction of a phase integral element into the entire circuit system, and an absolutely stable system with only one pole is obtained, and the circuit structure is simplified.

[0019] Referring to FIG. 1, in one embodiment, the time delay loop 100 includes a numerically controlled delay unit 110, a phase comparator 120, a first frequency multiplier 130 and a first accumulator 140 connected in sequence, the output end of the first accumulator 140 is connected to the numerically controlled delay unit 110, the phase comparator 120 is configured to compare the phase of a clock signal and input data, the numerically controlled delay unit 110 is configured to delay the input data according to the phase comparison result, and the output end of the numerically controlled delay unit 110 is also connected to the deserializer 300 to output the delayed input data.

[0020] In this embodiment, input data is transmitted from the input end of the numerically controlled delay unit 110 to the time delay loop 100, and the time delay loop 100 compares the phase of the clock signal and the delayed input data by the phase comparator 120 to cancel out the time delay of the numerically controlled delay unit 110 and the delay of the injection locking control logic.

[0021] Referring to FIG. 1, in one embodiment, the frequency locked loop 200 includes a frequency discriminator 210, a second frequency multiplier 220, a second accumulator 230 and a numerically controlled oscillator 240 connected in sequence, the numerically controlled oscillator 240 outputs clock signals to the phase comparator 120, the frequency discriminator 210 and the deserializer 300, respectively, and the output end of the numerically controlled delay unit 110 is also connected to the frequency discriminator 210 to output delayed input data.

[0022] In this embodiment, the frequency locked loop 200 starts to operate normally after the time delay loop 100 is locked. When the phase is locked, the phase of the injection locked clock signal and the delayed input data match. After a certain time has passed, the frequency of the clock signal and the frequency of the input data do not match, resulting in a certain phase difference. This phase difference can be determined by the frequency discriminator 210, and is input to the second accumulator 230 after passing through the second frequency multiplier 220, and then the output frequency of the numerically controlled oscillator 240 is controlled to achieve the purpose of locking the frequency. After both the phase and frequency are locked, the clock signal passes through the deserializer to deserialize the data, and the half-rate data is output.

[0023] Referring to FIG. 1, in one embodiment, the clock data recovery circuit further includes a pulse generator 400 whose output end is connected to the numerically controlled oscillator 240 to output a zero phase pulse, and the numerically controlled oscillator 240 sets the phase of the output clock signal to zero based on the received zero phase pulse.

[0024] In this embodiment, the phase is locked by making the phase zero, and a pulse signal is generated by a certain control logic to make the phase of the clock signal output from the numerically controlled oscillator 240 zero. This control method makes it possible to avoid introducing a phase integral element into the numerically controlled oscillator 240, and an absolutely stable system with only one pole is obtained, thereby providing an absolutely stable system with a simplified circuit structure.

[0025] Referring to FIG. 1, in one embodiment, a pulse generator 400 is provided with an input configured to receive input data and generates a zero phase pulse based on a rising edge of the input data.

[0026] In this embodiment, after receiving input data, the pulse generator 400 generates a zero-phase pulse based on the rising edge of the input data to set the phase of the clock signal output from the numerically controlled oscillator 240 to zero. It can be understood that the zero-phase pulse is generated once by the pulse generator 400 at regular intervals, for example, every several tens of periods.

[0027] Referring to FIG. 1, in one embodiment, a pulse generator 400 is coupled to the phase comparator 120 to trigger the phase comparator 120 to compare the phase of the clock signal with the incoming data.

[0028] In this embodiment, the pulse generator 400 is connected to the phase comparator 120 in addition to the numerically controlled oscillator 240. After outputting a zero-phase pulse to the numerically controlled oscillator 240, the pulse generator 400 further outputs a trigger signal to the phase comparator 120 to trigger the phase comparator 120 to compare the phase of the clock signal with the input data. After the input data passes through the first frequency multiplier 130 and the first accumulator 140, it is delayed by the numerically controlled delay unit 110 based on the phase difference between the clock signal and the input data, so that the phases of the input data and the clock signal are aligned.

[0029] Referring to FIG. 1, in one embodiment, a pulse generator 400 is coupled to the frequency discriminator 210 to trigger the frequency discriminator 210 to make a frequency decision on the clock signal and delayed input data.

[0030] In this embodiment, the frequency locked loop 200 starts to operate after the time delay loop 100 is locked, so the pulse generator 400 is connected to the frequency discriminator 210 to output a trigger signal to the frequency discriminator 210, and the frequency discriminator 210 performs frequency determination between the clock signal and the delayed input data after the phase is locked. The frequency discriminator 210 may perform frequency determination between the clock signal and the input data before the phase is locked, that is, may perform frequency determination between the clock signal and the non-delayed input data, but it is understood that the frequency determination result will be inaccurate because the clock signal is not injection locked.

[0031] In the above-mentioned clock data recovery circuit, the phase is set to zero to align the phases, a pulse signal is generated by a certain control logic to set the phase of the clock output from the numerically controlled oscillator to zero, and frequency determination is performed within a certain time after the phase is set to zero, thereby reducing one phase integral element, obtaining an absolutely stable system with only one pole, and providing an absolutely stable system with a simplified circuit structure.

[0032] Below, various embodiments of the clock data recovery method will be described based on the clock data recovery circuit of the above embodiment.

[0033] Referring to FIG. 6, an embodiment of the present application further provides a clock data recovery method applied to the clock data recovery circuit shown in FIG. 1, which includes a time delay loop 100, a frequency locked loop 200 connected to the time delay loop 100, and a deserializer 300 connected to the time delay loop 100 and the frequency locked loop 200, respectively, and is characterized in that the clock data recovery method includes the following steps:

[0034] Step S610: The time delay loop 100 delays the input data based on the phase of the clock signal to align the phases.

[0035] Step S620: The frequency locked loop 200 adjusts the frequency of the clock signal based on the delayed input data so that the frequency of the clock signal coincides with the frequency of the input data.

[0036] Step S630: The deserializer 300 deserializes the input data based on the clock signal.

[0037] In the clock data recovery method provided in this embodiment, the time delay loop 100 first compares the phase of the clock signal with the phase of the input data, and delays the input data to align the phase of the input data with the clock signal, thereby avoiding the introduction of a phase integral element. After the phase is aligned, the phase of the clock signal is consistent with the phase of the delayed input data. If the frequency of the delayed input data does not match the frequency of the clock signal, a certain phase difference will occur after a certain time has passed, and the frequency locked loop 200 adjusts the frequency of the clock signal based on the phase difference caused by the frequency mismatch between the delayed input data and the clock signal, thereby achieving the purpose of locking the frequency. After the frequency and phase of the input data and the frequency and phase of the clock signal are locked, the clock signal passes through the deserializer 300 to deserialize the input data. The technical solution provided in this embodiment can avoid the introduction of a phase integral element into the entire circuit system, and an absolutely stable system with only one pole is obtained, and the circuit structure is simplified.

[0038] Referring to FIG. 1, in one embodiment, a time delay loop 100 includes a numerically controlled delay unit 110, a phase comparator 120, a first frequency multiplier 130 and a first accumulator 140 connected in sequence, the output end of the first accumulator 140 is connected to the numerically controlled delay unit 110, and the output end of the numerically controlled delay unit 110 is connected to a deserializer 300.

[0039] Referring to FIG. 7, step S610 of delaying and aligning the input data based on the phase of the clock signal by the time delay loop 100 includes the following steps.

[0040] Step S710: The phase comparator 120 compares the phase of the clock signal with that of the input data.

[0041] Step S720: The numerically controlled delay unit 110 delays the input data based on the phase comparison result to align the phases.

[0042] In this embodiment, input data is transmitted from the input end of the numerically controlled delay unit 110 to the time delay loop 100, and the time delay loop 100 uses the phase comparator 120 to compare the phase of the clock signal and the delayed input data, and the numerically controlled delay unit 110 delays the input data based on the phase comparison result to align the phase, thereby offsetting the time delay of the numerically controlled delay unit 110 and the delay of the injection locking control logic.

[0043] Referring to FIG. 1, in one embodiment, the frequency locked loop 200 includes a frequency discriminator 210, a second frequency multiplier 220, a second accumulator 230 and a numerically controlled oscillator 240 connected in sequence, the numerically controlled oscillator 240 is respectively connected to the phase comparator 120, the frequency discriminator 210 and the deserializer 300, and the output end of the numerically controlled delay unit 110 is also connected to the frequency discriminator 210.

[0044] Referring to FIG. 8, step S620 of adjusting the frequency of the clock signal based on the delayed input data by the frequency locked loop 200 to make the frequency of the clock signal match the frequency of the input data includes the following steps:

[0045] Step S810: The input data delayed by the numerically controlled delay unit 110 is output to the frequency discriminator 210.

[0046] Step S820: The frequency discriminator 210 discriminates the frequencies of the clock signal and the delayed input data.

[0047] Step S830: The numerically controlled oscillator 240 adjusts the frequency of the clock signal according to the phase difference of the frequency determination.

[0048] In this embodiment, the frequency locked loop 200 starts to operate normally after the time delay loop 100 is locked, so the delayed input data from the numerically controlled delay unit 110 is output to the frequency discriminator 210, and when the phase is locked, the phase of the injection-locked clock signal and the delayed input data match, and after a certain time has passed, the frequency of the clock signal and the frequency of the input data do not match, resulting in a certain phase difference, which can be determined by the frequency discriminator 210, and then input to the second accumulator 230 after passing through the second frequency multiplier 220, and then the output frequency of the numerically controlled oscillator 240 is controlled to achieve the purpose of locking the frequency. After both the phase and frequency are locked, the clock signal passes through the deserializer to deserialize the data, and half-rate data is output.

[0049] Next, the embodiment of the present application will be further described with reference to FIGS.

[0050] A clock data recovery circuit provided by a specific embodiment of the present application is shown in Figure 1. The clock data recovery circuit includes a time delay loop 100, a frequency locked loop 200, a deserializer 300 and a pulse generator 400. The time delay loop 100 includes a numerically controlled delay unit 110, a phase comparator 120, a first frequency multiplier 130 and a first accumulator 140, which are connected in sequence. The output of the first accumulator 140 is connected to the numerically controlled delay unit 110. The frequency locked loop 200 is connected in sequence. The numerically controlled delay unit 110 includes a first frequency discriminator 210, a second frequency multiplier 220, a second accumulator 230 and a numerically controlled oscillator 240, and the numerically controlled oscillator 240 outputs clock signals to the phase comparator 120, the frequency discriminator 210 and the deserializer 300, respectively. The output end of the numerically controlled delay unit 110 is also connected to the frequency discriminator 210 and the deserializer 300, and the output end of the pulse generator 400 is connected to the numerically controlled oscillator 240 to output a zero-phase pulse.

[0051] After the system is locked, the data that has passed through the numerically controlled delay unit 110 is deserialized and output. The time delay loop 100 is connected to the clock signal P0 and the delayed input data D by the phase comparator 120. DLY The frequency-locked loop 200 starts to operate normally after the phase of the time delay loop 100 is locked, and when the phase is locked, the injection-locked clock signal P0 and the input data D DLY After a certain period of time has passed, the frequency of the clock signal P0 and the input data D DLYSince the frequency of the clock signal does not match the frequency of the clock signal, a certain phase difference occurs. This phase difference can be determined by the frequency discriminator 210, and is input to the digital accumulator 230 after passing through the 1 / 16 frequency multiplier, and then the output frequency of the numerically controlled oscillator 240 is controlled to achieve the purpose of locking the frequency. After both the frequency and phase are locked, the clock signal passes through the deserializer to deserialize the data, and the half-rate data is output. The phase is locked by making the phase zero, and a pulse signal is generated by a certain control logic to make the phase of the clock signal output from the numerically controlled oscillator 240 zero. This control method avoids the introduction of a phase integral element into the numerically controlled oscillator, and an absolutely stable system with only one pole is obtained, providing an absolutely stable system with a simplified circuit structure.

[0052] 2 is a circuit diagram of the numerically controlled delay unit 110. The numerically controlled delay unit 110 uses a 2-bit binary code to select different signals for coarse adjustment, and a 31-bit thermometer code for fine adjustment. The control bits of the thermometer code are evenly distributed to the four loads, which minimizes the difference in the magnitude of the load capacitance when the thermometer code changes, and ensures that the signal influence on the duty cycle is avoided.

[0053] 3 is a circuit diagram of the 1 / 4 frequency multiplier 130. The frequency of the clock data recovery circuit is usually high, so the data frequency obtained by the frequency discriminator or phase comparator is also high, and it cannot be directly input to the accumulator for processing, so it needs to be processed by the frequency multiplier before being input to the accumulator. The operating principle of the frequency multiplier is to split the single data and clock information into two data, and to reduce the clock frequency to half of what it was before.

[0054] FIG. 4 is a timing chart of the circuit operation of the 1 / 4 frequency multiplier. FIG. 5 is a timing chart of the zero phase and frequency determination of the embodiment of the present application. After the zero phase pulse is generated, the delayed input data D DLYThe phases of the data rate and the clock signal P0 match, and the rising edges are aligned. After the phases match and a certain period of time has elapsed, the data rate and the clock frequency do not match, so a phase difference occurs, and frequency judgment may be performed based on the information of this phase difference. The frequency judgment result shown in FIG. 5 indicates that the frequency of the clock signal is too high, so the output judgment result is used to lower the output frequency of the numerically controlled oscillator 240.

[0055] The embodiment of the present application includes a clock data recovery circuit and a clock data recovery method, the clock data recovery circuit including: a time delay loop configured to delay input data according to the phase of a clock signal to align the phase; a frequency locked loop connected to the time delay loop and configured to adjust the frequency of the clock signal according to the delayed input data to match the frequency of the clock signal and the frequency of the input data; and a deserializer connected to the time delay loop and the frequency locked loop, respectively, configured to deserialize the input data according to the clock signal. The technical solution provided by the embodiment is to first compare the phase of the clock signal with the phase of the input data, and delay the input data to align the phase of the input data and the clock signal, thereby avoiding the introduction of a phase integral element. After the phase is aligned, the phase of the clock signal and the phase of the delayed input data are consistent, and if the frequency of the delayed input data and the clock signal do not match, a certain phase difference will occur after a certain time has passed, and the frequency locked loop adjusts the frequency of the clock signal based on the phase difference caused by the frequency mismatch between the delayed input data and the clock signal to achieve the purpose of locking the frequency. After the frequency and phase of the input data and the frequency and phase of the clock signal are locked, the clock signal passes through the deserializer to deserialize the input data.The technical solution provided by this embodiment can avoid introducing a phase integral element into the whole circuit system, and obtain an absolutely stable system with only one pole, and simplify the circuit structure.

[0056] Although the embodiments of the present application have been described in detail above with reference to the drawings, the present application is not limited to the above-described embodiments, and various modifications may be made within the scope of knowledge held by a person skilled in the art without departing from the scope of the present application.

Claims

1. a time delay loop configured to delay and phase align input data based on a phase of a clock signal; a frequency locked loop coupled to the time delay loop and configured to adjust a frequency of a clock signal based on the delayed input data to match a frequency of the adjusted clock signal to a frequency of the input data; a deserializer coupled to the time delay loop and the frequency locked loop, respectively, and configured to deserialize input data delayed based on a regulated clock signal; the time delay loop comprises a numerically controlled delay unit, a phase comparator, a first frequency multiplier and a first accumulator connected in series; an output terminal of the first accumulator is connected to an input terminal of the numerically controlled delay unit; the phase comparator is configured to compare a phase of a clock signal with the delayed input data; the numerically controlled delay unit is configured to delay the input data based on a phase comparison result; The output of the numerically controlled delay unit is also connected to the deserializer to output the delayed input data. Clock data recovery circuit.

2. the frequency locked loop comprises a frequency discriminator, a second frequency multiplier, a second accumulator and a numerically controlled oscillator connected in series; The numerically controlled oscillator outputs adjusted clock signals to the input terminals of the phase comparator, the frequency discriminator, and the deserializer, respectively; The output of the numerically controlled delay unit is also connected to another input of the frequency discriminator to output delayed input data.

2. The clock data recovery circuit of claim 1.

3. a pulse generator having an output connected to the numerically controlled oscillator for outputting a zero phase pulse; The numerically controlled oscillator sets the phase of the output clock signal to zero based on the received zero phase pulse.

3. The clock data recovery circuit according to claim 2.

4. The pulse generator has an input configured to receive input data, and generates a zero phase pulse based on a rising edge of the input data.

4. The clock data recovery circuit according to claim 3.

5. The pulse generator is coupled to the phase comparator to trigger a comparison of the phase of the clock signal with the phase of the input data by the phase comparator.

4. The clock data recovery circuit according to claim 3.

6. The pulse generator is coupled to the frequency discriminator to trigger a frequency determination by the frequency discriminator for the clock signal and the delayed input data.

4. The clock data recovery circuit according to claim 3.

7. A clock data recovery method applied to a clock data recovery circuit including a time delay loop, a frequency locked loop connected to the time delay loop, and a deserializer connected to the time delay loop and the frequency locked loop, the method comprising: delaying input data based on a phase of a clock signal by the time delay loop to align the phase; adjusting a frequency of a clock signal based on the delayed input data by the frequency locked loop so that the frequency of the adjusted clock signal coincides with the frequency of the input data; and deserializing, by the deserializer, the input data delayed based on the adjusted clock signal; the time delay loop comprises a numerically controlled delay unit, a phase comparator, a first frequency multiplier and a first accumulator connected in sequence, an output end of the first accumulator is connected to an input end of the numerically controlled delay unit, and an output end of the numerically controlled delay unit is connected to the deserializer; The step of delaying input data based on a phase of a clock signal by the time delay loop to align the phases includes: comparing the phase of the clock signal with the delayed input data by the phase comparator; and delaying the input data based on the phase comparison result by the numerically controlled delay unit to align the phase. Clock data recovery method.

8. the frequency locked loop comprises a frequency discriminator, a second frequency multiplier, a second accumulator and a numerically controlled oscillator connected in sequence, the numerically controlled oscillator being connected to the phase comparator, the frequency discriminator and the deserializer respectively, and an output end of the numerically controlled delay unit is also connected to the frequency discriminator; The step of adjusting the frequency of the clock signal based on the delayed input data by the frequency locked loop to match the frequency of the clock signal with the frequency of the input data includes: outputting delayed input data to the frequency discriminator by the numerically controlled delay unit; performing a frequency discrimination between a clock signal and the delayed input data by the frequency discriminator; and adjusting, by the numerically controlled oscillator, the frequency of the clock signal based on the phase difference of the frequency determination.

8. The clock data recovery method according to claim 7.

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