Apparatus for supporting digital circuit design, method for supporting digital circuit design, and program for supporting digital circuit design

Abstract

Provided is a device (100) for assisting with digital circuit design. The device (100) comprises: a memory map generation unit that generates a memory map; and a hardware description generation unit that generates a hardware description. The hardware description generation unit generates a description of a port to be used by an external circuit (130) to communicate with a memory map circuit (120). The port description describes a circuit which is separate from a writing circuit and a reading circuit which go through a bus of a register included in the memory map.

Description

[Technical field]

[0001] The present disclosure relates to a technology for supporting digital circuit design, and more particularly to a technology for automatically generating various hardware descriptions. [Background technology]

[0002] In the field of hardware design such as digital circuits, there is a concept called a memory map or register map, which is a pair of addresses and memory areas (registers). Each register included in the memory map may have various functions other than attributes such as W (write only), R (read only), and RW (read and write).

[0003] In the hardware design process, a memory map is generally created first, and then a hardware description is created based on the attributes and function definitions of each register defined in the memory map. The hardware is then manufactured based on the hardware description. Depending on the hardware description language, there is a technology that automatically generates a hardware description based on the attribute information of each register defined in the memory map.

[0004] Conventional automatic generation technology for hardware descriptions only supports the generation of descriptions of the main attributes of registers: W (writeable), R (readable), and RW (read and write). Therefore, it was not possible to automatically generate hardware descriptions for circuits with special functions, such as circuits in which the target register for writing and the target register for reading are different, or circuits in which registers are rewritten by accessing from circuits other than the normal read or write circuits. As a result, to realize these special functions, users had to add and revise the descriptions of the special functions to the automatically generated hardware description.

[0005] Manually adding and modifying hardware descriptions makes it possible to realize special functions, but on the other hand, when hardware modifications occur, the description of the special functions may not be reflected in the documents or circuits (hardware descriptions), and the work of reflecting the description of the special functions may increase the amount of work required. Therefore, technology that supports hardware design more efficiently is needed.

[0006] Regarding technology for supporting digital circuit design, for example, Japanese Patent Laid-Open Publication No. 2005-309584 (Patent Document 1) discloses a digital circuit design support device comprising: "a database in which templates are registered in advance, the templates being defined in advance by a hardware description language and containing undefined words indicating both or either of the internal wiring of a digital circuit consisting of a combination of registers and combinational circuits and the wiring between the digital circuit and the outside; storage means in which design specifications for a digital circuit in which the internal wiring and the wiring between the digital circuit and the outside are defined in advance as information transfer to a register; and specification reflection means for generating a sequence of statements that represent the digital circuit in a hardware description language by substituting, for the undefined words, words indicating the transfer of information to a register defined as the design specifications" (see [Abstract]). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2005-309584 A Summary of the Invention [Problem to be solved by the invention]

[0008] According to the technology disclosed in Patent Document 1, it is not possible to automatically generate a hardware description for a circuit with a special function other than a read circuit or a write circuit. Therefore, there is a need for a technology for automatically generating a hardware description for a circuit with a special function other than a read circuit or a write circuit.

[0009] The present disclosure has been made in consideration of the above-described background, and an object of one aspect is to provide a technique for automatically generating a hardware description for a circuit with a special function other than a read circuit or a write circuit. [Means for solving the problem]

[0010] According to an embodiment, there is provided an apparatus for supporting digital circuit design. The apparatus includes a memory map generator for generating a memory map, and a hardware description generator for generating a hardware description based on the memory map. The hardware description generator generates a description of ports for an external circuit to communicate with the circuit of the memory map. The description of the ports is a description of a circuit other than a write circuit and a read circuit via a bus of a register included in the memory map. Effect of the Invention

[0011] According to one embodiment, it is possible to automatically generate hardware descriptions for circuits of special functions other than read or write circuits.

[0012] The above and other objects, features, aspects and advantages of the present disclosure will become apparent from the following detailed description of the disclosure taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of an overview of functions of an apparatus 100 for supporting hardware design according to an embodiment. [Diagram 2] 1 illustrates an example of a hardware configuration of an apparatus 100. FIG. [Diagram 3] FIG. 2 is a diagram illustrating an example of functional blocks of software 300. [Figure 4] FIG. 3 is a diagram showing a first example of a UI (User Interface) 304. [Diagram 5] FIG. 13 is a diagram showing a second example of UI 304. [Figure 6] 13 is a diagram showing an example of setting values ​​that can be input to a register setting item 530. FIG. [Figure 7] FIG. 2 is a diagram illustrating an example of a description of the highest hierarchy in a hardware description. [Figure 8] FIG. 13 is a diagram illustrating an example of a description of bus protocol control in a hardware description. [Figure 9] 13 is a diagram showing an example of a hardware description of a register 121 with an RW attribute. FIG. [Figure 10] 9 is a schematic diagram showing an example of a circuit corresponding to the hardware description 900. FIG. [Figure 11] 13 is a diagram showing an example of a hardware description of a register 121 with a W attribute. FIG. [Figure 12] 11 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1100. FIG. [Figure 13] FIG. 13 is a schematic diagram showing an example of an R-attribute circuit. [Figure 14] FIG. 13 is a diagram showing a first example of a hardware description of a register 121 when the value of an option setting item 533 is “sp”. [Figure 15] 14 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1400. FIG. [Figure 16] FIG. 13 is a diagram showing a second example of the hardware description of the register 121 when the value of the option setting item 533 is “sp”. [Figure 17] 16 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1600. FIG. [Figure 18] 13 is a diagram showing an example of a hardware description of the register 121 when the value of the option setting item 533 is “sn”. FIG. [Figure 19] 18 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1800. FIG. [Figure 20] FIG. 2 is a diagram showing an example of a procedure for generating a hardware description by the device 100. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the technical idea according to the present disclosure will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated.

[0015] <A. Outline of the functions of the apparatus for assisting digital circuit design> FIG. 1 is a diagram showing an example of an outline of the functions of an apparatus 100 for hardware design support according to the present embodiment. The apparatus 100 generates a hardware description including a description of a circuit having a special function other than a read circuit or a write circuit by executing software 300 for hardware design support.

[0016] In this specification, the term "apparatus" includes a configuration consisting of one or more apparatuses, a server, a virtual machine or a container constructed in a cloud environment, or a system composed of at least a part of these. Further, the apparatus may include an information processing apparatus such as a personal computer, a workstation, a server apparatus, a tablet, a smartphone, etc., or a combination thereof. In one aspect, the apparatus 100 may be connected to input / output devices such as a display and a keyboard and used by a user. In another aspect, the apparatus 100 may provide various functions to a user as a cloud service or a web application via a network. In this case, the user can use the functions of the apparatus 100 via a browser or client software installed on his / her terminal.

[0017] Also, in this specification, the term "hardware description" or "description" means a description of an entire circuit, a description of a part or a function of a circuit, or a file (hardware description file) including these descriptions, described by a hardware description language (HDL).

[0018] The device 100 (software 300) mainly provides three functions. The first function is a function for defining a special function circuit other than a read circuit or a write circuit for each register included in a memory map, and defining the presence or absence of a register. The second function is a function for defining a special function circuit other than a read circuit or a write circuit, and generating a file representing a memory map including information on the presence or absence of a register. The third function is a function for automatically generating a hardware description including a special function circuit other than a read circuit or a write circuit, and / or a circuit that does not include a register, from a file representing a memory map. The "special function circuit" here refers to a port (each port shown in FIG. 9 to FIG. 19) that communicates with a register without going through a bus protocol control circuit and a bus, unlike a read circuit or a write circuit.

[0019] First, the first function (a function for defining a special function circuit other than a read circuit or a write circuit for each register included in the memory map, and for defining the presence or absence of a register) will be described.

[0020] The circuit 110 is a circuit to be designed by a user, and mainly includes a circuit 120 and a user circuit 130. The circuit 120 is a circuit designed based on a memory map generated by the device 100. The user circuit 130 is a user-defined circuit, and can communicate with the circuit 120 as necessary.

[0021] The circuit 120 includes one or more registers 121 and a bus protocol control circuit 122. In one aspect, the register 121 may be a register including one or more flip-flop circuits. In this case, one register 121 may be treated as a "unit of registers" indicating a certain set of functions. In another aspect, the register 121 may be a flip-flop circuit. In this case, a set of multiple registers 121 may be treated as a "unit of registers" indicating a certain set of functions. The bus protocol control circuit 122 is a circuit that provides a communication function to the register 121. When the register 121 has any of the attributes R attribute (readable), W attribute (writeable), and RW attribute (readable), other circuits may read data from the register 121 and write data to the register 121 via the bus protocol control circuit 122 and the bus.

[0022] All processing of the R attribute and the W attribute for the register 121 is performed via the bus protocol control circuit 122. However, depending on the function to be provided by the circuit 110, the user circuit 130 needs to communicate with the register 121 without using the bus protocol (without going through the bus protocol control circuit 122 and the bus). Therefore, the device 100 provides a means for the user to set a special function in addition to the R attribute, the W attribute, and the RW attribute for each of the registers 121 included in the memory map. The user can set a special function for each of the registers 121 in addition to the R attribute, the W attribute, and the RW attribute via the UI 304 (see FIG. 3). This allows the device 100 to generate the circuit 145, which could not be automatically generated by the conventional automatic generation technology of hardware description, in addition to the circuit (circuit 140) with the R attribute, the W attribute, and the RW attribute. For example, the device 100 may determine whether or not to generate a circuit with a special function by accepting an option for each bit included in the register 121 or the register 121.

[0023] Furthermore, device 100 can generate a circuit that does not include registers 121 by accepting options for each register 121. A circuit that does not include registers 121 is a circuit that does not have a memory area (flip-flop circuit). However, a circuit that does not include registers 121 may include a bus protocol control circuit, a read circuit, a write circuit, and other special function circuits other than the memory area.

[0024] Next, the second function (a function for defining a circuit with a special function other than a read circuit or a write circuit, and for generating a file representing a memory map including information on the presence or absence of a register) will be described.

[0025] The device 100 generates a file representing a memory map defined by the first function. The "file representing the memory map" here is, for example, an IP-XACT file (an xml (Extensible Markup Language) file). The IP-XACT file is a file that conforms to the standard defined by the IEEE-1685 standard (IP-XACT). The device 100 generates an IP-XACT file representing a memory map that includes special functions other than the R attribute, the W attribute, and the RW attribute and / or does not include some or all of the registers 121. In this way, the device 100 can increase the reusability of the description of the special functions included in the memory map without depending on the hardware configuration.

[0026] Finally, we will explain the third function (a function for automatically generating a hardware description including special function circuits other than read circuits or write circuits, and / or circuits that do not include registers, from a file representing a memory map).

[0027] The device 100 interprets a file representing a memory map including a description of special functions, and generates a hardware description. The hardware description includes special functions other than the R attribute, the W attribute, and the RW attribute, and / or descriptions of whether or not a register 121 is included, which could not be generated automatically in the past.

[0028] By having the above three functions, even when the user changes the description of the memory map, the device 100 can automatically generate descriptions representing special functions and / or the presence or absence of the content of the register 121. Thereby, when a hardware modification or the like occurs, the device 100 can suppress the omission of reflecting the description of the special function in the document or the circuit (hardware description) and the increase in man-hours due to the reflection work.

[0029] <B. Configuration of Hardware and Software of the Device> FIG. 2 is a diagram showing an example of the hardware configuration of the device 100. With reference to FIG. 2, the hardware configuration of the device 100 will be described. The device 100 mainly includes a processor 201, a memory 202, a storage 203, an output IF (Interface) 204, an input IF 205, a communication IF 206, an external device IF 207, and an internal bus 208. In a certain aspect, the device 100 may be realized as a server, a cluster, or a cloud environment by the combination of hardware shown in FIG. 2.

[0030] The processor 201 can execute software 300 for realizing various functions of the device 100. The processor 201 is composed of, for example, at least one integrated circuit. The integrated circuit may be composed of, for example, at least one CPU (Central Processing Unit), at least one GPU (Graphics Processing Unit), at least one FPGA (Field Programmable Gate Array), at least one ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0031] The memory 202 stores software 300 executed by the processor 201 and data referenced by the processor 201. In one aspect, the memory 202 may be realized by a dynamic random access memory (DRAM) or a static random access memory (SRAM), etc.

[0032] Storage 203 is a non-volatile memory, and may store software 300 executed by processor 201 and data referenced by processor 201. In this case, processor 201 executes software 300 read from storage 203 to memory 202, and references data read from storage 203 to memory 202. In one aspect, storage 203 may be realized by a hard disk drive (HDD), a solid state drive (SSD), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a flash memory, or the like.

[0033] The output IF 204 can be connected to any output device such as a cathode ray tube display, a liquid crystal display, an organic EL (Electro-Luminescence) display, etc. In one aspect, the output IF 204 may be realized by a USB (Universal Serial Bus) terminal, a D-sub terminal, a DVI (Digital Visual Interface) terminal, an HDMI (High-Definition Multimedia Interface) terminal, etc.

[0034] The input IF 205 may be connected to any input device such as a keyboard, a mouse, a touch pad, a game pad, etc. In one aspect, the input IF 205 may be realized by a USB terminal, a PS / 2 terminal, a Bluetooth (registered trademark) module, etc.

[0035] The communication IF 206 is connected to a wired or wireless network device. In one aspect, the communication IF 206 may be realized by a wired LAN (Local Area Network) port, a Wi-Fi (Wireless Fidelity) (registered trademark) module, or the like. In another aspect, the communication IF 206 may transmit and receive data using a communication protocol such as TCP / IP (Transmission Control Protocol / Internet Protocol) or UDP (User Datagram Protocol).

[0036] The external device IF 207 can be connected to any external device such as a printer, a scanner, an external HDD, etc. In one aspect, the external device IF 207 may be realized by a USB terminal or the like.

[0037] The internal bus 208 connects the processor 201, the memory 202, the storage 203, the output IF 204, the input IF 205, and some or all of the communication IF 206 and the external device IF 207 directly or indirectly so that they can communicate with each other.

[0038] Fig. 3 is a diagram showing an example of functional blocks of the software 300. The functional blocks of the software 300 will be described with reference to Fig. 3. In a certain aspect, some or all of the functional blocks shown in Fig. 3 may be realized as program modules, libraries, or services that can independently communicate with each other.

[0039] The software 300 mainly comprises a memory map generation unit 301, an IP-XACT generation unit 302, a hardware description generation unit 303, and a UI 304.

[0040] The memory map generating unit 301 generates a memory map from various settings input via the UI 304. The generated memory map may include one or more registers 121. In addition, an initial value, an attribute (R attribute, W attribute, RW attribute), and an option (presence or absence of a special function, presence or absence of a register 121 (storage area)) are set in each register 121. The memory map generating unit 301 outputs the generated memory map to the IP-XACT generating unit 302.

[0041] The IP-XACT generator 302 (which may also be called an intermediate file generator) converts the memory map output by the memory map generator 301 into an IP-XACT file (xml file). The IP-XACT generator 302 outputs the generated IP-XACT file to the hardware description generator 303. The generated IP-XACT file includes information on the initial values, attributes, and options of the registers 121. In one aspect, the IP-XACT generator 302 may generate a file in any format other than the IP-XACT (xml) file from the memory map. In this case, the device 100 generates a hardware description from a file in a format other than the generated IP-XACT (xml) file.

[0042] The hardware description generator 303 generates a hardware description from an IP-XACT file (xml file). The generated hardware description includes a description for realizing a function specified by an option in addition to the attributes (R attribute, W attribute, RW attribute) of each register 121. In one aspect, the hardware description generator 303 may generate the hardware description directly from a memory map.

[0043] UI304 is configured to be able to receive various settings of the memory map. When the software 300 is a web application, the device 100 distributes the UI304 to the user's terminal. The terminal can display the UI304 on a display using a browser or client software. Also, the UI304 outputs both or either of the generated IP-XACT file and the hardware description. The UI304 may determine whether to output both the generated IP-XACT file and the hardware description or either one based on an operation from the user. Further, the UI304 may output the hardware description as one or a plurality of files (hardware description files).

[0044] <C. An example of UI304> Next, with reference to FIGS. 4 to 6, an example of the UI304 provided by the device 100 (software 300) will be described. The user can input options (presence or absence of special functions, presence or absence of the register 121) via the UI304 in addition to initial values and attributes (R attribute, W attribute, RW attribute).

[0045] FIG. 4 is a diagram showing a first example of the UI304. The screen 400 is a part of the UI304. The screen 400 is a setting screen such as the top layer of the register map and bus protocol information. The screen 400 includes an interface setting item 401, a module name setting item 402, a data width setting item 403, a register map setting item 404, and a port setting item 405. Each setting item may be a selection type setting item or an input type setting item.

[0046] The interface setting item 401 is an item for setting bus protocol information for accessing the register 121. The bus protocol information may include, for example, AXI4-Lite and Avalon. The hardware description generation unit 303 generates a description of a signal group required for the bus protocol based on the bus protocol information set in the interface setting item 401.

[0047] The module name setting item 402 is an item for setting the topmost module name of the register map.

[0048] The data width setting item 403 is an item for setting the data width of the register 121 . Register map setting item 404 is an item for setting an initial value, an attribute, and an option of register 121. Register map setting item 404 may be capable of accepting settings of multiple registers 121 for each memory map, or may be capable of accepting settings of one register 121 for each memory map. In one aspect, based on selection of register map setting item 404, software 300 may display screen 500 as a dialog or a window on the display of device 100. In another aspect, based on selection of register map setting item 404, software 300 may transition screen 400 to screen 500.

[0049] The port setting item 405 is the type of port connected to the user circuit 130. The port set in the port setting item 405 can be used as a special function circuit other than the standard read circuit and write circuit.

[0050] 5 is a diagram showing a second example of UI 304. Screen 500 is a part of UI 304. Screen 500 is a setting screen for each register 121. Device 100 may simultaneously display screens 400 and 500 on the display. Device 100 may also switch between screens 400 and 500 and display them on the display based on a user operation.

[0051] The screen 500 includes an address setting item 510, a register name setting item 520, and a register setting item 530. The address setting item 510 includes an absolute address setting item 511 and an offset address setting item 512. The register setting item 530 includes an attribute setting item 531, an initial value setting item 532, and an option setting item 533.

[0052] Address setting item 510 is an item for setting the starting address of register 121. The user may input an absolute address into absolute address setting item 511 as the starting address of register 121. The user may also input an offset address from a reference address into offset address setting item 512 as the starting address of register 121. The user may input the address of register 121 into only one of absolute address setting item 511 and offset address setting item 512, or may input the address of register 121 into both.

[0053] The register name setting item 520 is an item for setting the name of the register 121. The register name set in the register name setting item 520 is used for generating an IP-XACT file and a hardware description. In one aspect, the software 300 may directly generate a hardware description from a memory map.

[0054] The register setting item 530 is an item for setting various information of the register 121. The attribute setting item 531 is an item for setting any one of the R attribute, W attribute, and RW attribute in the register 121. The initial value setting item 532 is an item for setting an initial value of the register 121 (a value input to the register 121 when the register 121 is reset). The initial value setting item 532 is configured so that an initial value can be set in each bit of the register 121. The option setting item 533 is an item for setting whether or not to generate a special function circuit in the register 121, whether or not the memory map includes the register 121, etc.

[0055] FIG. 6 is a diagram showing an example of settable values inputtable to the register setting item 530. The attribute setting item 531 is configured to be able to set any one of "RW (readable / writable)", "R (readable)", and "W (writable)". The initial value setting item 532 is configured to be able to set "0" or "1" for each bit. The option setting item 533 is configured to be able to set, as an example, "no option", "rc", "rs", "sp", "sn". Note that the selection items of the option setting item 533 shown in FIG. 6 are just an example, and the selection items of the option setting item 533 are not limited to this. In a certain aspect, the option setting item 533 may be configured to be able to set any option other than the options illustrated in FIG. 6 based on the combination of the presence or absence of a circuit with a special function and the register 121. Also, the type of option may be expressed by a combination of alphanumeric characters other than "no option", "rc", "rs", "sp", "sn".

[0056] "sp" is an option for generating a circuit having the port described in FIG. 15 or FIG. 17. "sn" is an option for generating a circuit having an internal structure obtained by excluding the register 121 from the structure of "sp". A circuit having an internal structure excluding the register 121 is a circuit having no storage area by a flip-flop circuit, and may have a write circuit and a read circuit. "rs" is an option for generating the same circuit as "sp" and further automatically generating an auxiliary code for clearing the register value to 0 at the upper layer during reading. "rs" is an option for generating the same circuit as "sp" and further automatically generating an auxiliary code for setting the register value to 1 at the upper layer during reading.

[0057] <D. An Example of Generated Hardware Description and Circuit> Next, the hardware description generated by the device 100 (software 300) and the circuit corresponding to the hardware description will be described with reference to Figures 7 to 19. The hardware descriptions 700 and 800 shown in Figures 7 and 8 are generated mainly based on the settings of the screen 400 (the attribute information, etc. may include the settings of the screen 500). The hardware descriptions and circuits shown in Figures 9 to 19 are generated mainly based on the settings of the screen 500.

[0058] 7 is a diagram showing an example of a description of the highest hierarchy in the hardware description. The hardware description generator 303 generates a hardware description 700 of the highest hierarchy of the memory map based on the settings of the screens 400 and 500 as shown in FIG.

[0059] Fig. 8 is a diagram showing an example of a description of bus protocol control in a hardware description. The hardware description generator 303 generates a hardware description 800 of bus protocol control as shown in Fig. 8 based on the setting contents of the interface setting item 401. The description of the bus protocol control is generated as a hardware description of a sub-hierarchy of a memory map.

[0060] The device 100 (software 300) further generates a hardware description of the register 121 as one of the hardware descriptions of the sub-hierarchy of the memory map. The hardware description of the register 121 includes the setting contents of the attributes, initial values, and options of the register 121. Below, the hardware description of the register 121 and the circuit corresponding to the hardware description of the register 121 will be described for each setting content of the register setting item 530.

[0061] (a. Example of a circuit with RW attributes) 9 and 10, a description will be given of an example of a hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the attribute setting item 531 is "RW (read / write)". It is assumed that the value of the option setting item 533 is "no option".

[0062] 9 is a diagram showing an example of a hardware description of the register 121 with the RW attribute. The hardware description 900 is an example of a hardware description that is automatically generated when the value of the attribute setting item 531 is "RW (read / write)" and the value of the option setting item 533 is "no option." In addition to a normal hardware description (a description of the register 121 with the RW attribute), the hardware description 900 includes a description 910 of a port 1006 (see FIG. 10) for the user circuit 130 to read the current value of the register 121 without using the bus protocol control circuit 122.

[0063] The device 100 generates a description 910 related to a circuit of a special function other than the normal RW attribute (a port that outputs the current value of the register 121 to the user circuit 130) based on the memory map. The description 910 enables the user circuit 130 to use the current value of the register 121 without going through the bus protocol control circuit 122. Even if a change occurs in the design of the hardware, the device 100 automatically generates the description 910 based on the settings input via the screens 400 and 500. Therefore, when a modification or the like occurs to the hardware, the device 100 can prevent the description of the special function from being omitted from the document or the circuit (hardware description), etc.

[0064] 10 is a schematic diagram showing an example of a circuit corresponding to the hardware description 900. The circuit 1000 is a circuit of the register 121 with the RW attribute. More specifically, the circuit 1000 is composed of a flip-flop circuit 1005 that stores data in the register 121 and its peripheral circuits. The circuit 1000 is also a part (a circuit corresponding to one register 121) of the circuit 120 (a memory-mapped circuit).

[0065] The circuit 1000 mainly comprises a bus circuit 1001, a read circuit 1002, a write circuit 1003, a selector 1004, a flip-flop circuit 1005, and a port 1006. In the example of Fig. 9, only one flip-flop circuit 1005 is shown for the sake of simplicity, but the register 121 has a storage area (flip-flop circuit 1005) corresponding to the data width set in the data width setting item 403.

[0066] The bus circuit 1001 is a circuit for communicating in accordance with a protocol set in the interface setting item 401. The bus circuit 1001 is a part of the bus protocol control circuit 122, or a bus protocol control circuit 122 generated for each register 121. An external circuit normally executes read and write processes on the register 121 via the bus circuit 1001.

[0067] The read circuit 1002 is a circuit for processing (read access) to read out data (values ​​saved in the flip-flop circuit 1005) stored in the register 121. The read circuit 1002 outputs the data stored in the register 121 (flip-flop circuit 1005) to an external circuit via the bus circuit 1001 (bus protocol control circuit 122).

[0068] The write circuit 1003 is a circuit for processing (write access) to write data to the register 121 (flip-flop circuit 1005). The write circuit 1003 writes data acquired from an external circuit to the register 121 (flip-flop circuit 1005) via the bus circuit 1001 (bus protocol control circuit 122).

[0069] The selector 1004 controls the timing of writing data to the flip-flop circuit 1005. For example, the selector 1004 may execute writing of data to the flip-flop circuit 1005 at the timing when a write access notification is input from the write circuit 1003.

[0070] The flip-flop circuit 1005 stores one bit of information. The register 121 includes one or more flip-flop circuits 1005 as a storage area.

[0071] The port 1006 is a port (communication circuit) for the user circuit 130 to obtain the current value of the register 121 (flip-flop circuit 1005). Unlike the read circuit 1002 and the write circuit 1003, the port 1006 is connected to the user circuit 130 without passing through the bus circuit 1001. The port 1006 corresponds to the description 910. In one aspect, the port 1006 may be a circuit that reads data in units of the register 121. In this case, when the data width of the register 121 is 16 bits, the port 1006 reads data in units of 16 bits. In another aspect, the port 1006 may be a circuit that reads data in units of each bit of the register 121.

[0072] (Example of a circuit with bW attributes) 11 and 12, an example of the hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the attribute setting item 531 is "W (writable)" will be described. It is assumed that the value of the option setting item 533 is "no option".

[0073] 11 is a diagram showing an example of a hardware description of the register 121 with the W attribute. The hardware description 1100 is an example of a hardware description that is automatically generated when the value of the attribute setting item 531 is "W (writeable)" and the value of the option setting item 533 is "no option." The hardware description 1100 includes, in addition to a normal hardware description (a description of the register 121 with the W attribute (write only)), a description 1110 of a port 1006 for the user circuit 130 to read the current value of the register 121 without using the bus protocol control circuit 122.

[0074] The device 100 generates a description 1110 for a circuit of a special function other than the normal W attribute (a port that outputs the current value of the register 121 to the user circuit 130) based on the memory map. The description 1110 enables the user circuit 130 to use the current value of the register 121 without going through the bus protocol control circuit 122. Even if a change in the design of the hardware occurs, the device 100 automatically generates the description 1110 based on the settings input via the screens 400 and 500. Therefore, when a modification or the like of the hardware occurs, the device 100 can prevent the description of the special function from being omitted from the document or the circuit (hardware description), etc.

[0075] 12 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1100. The circuit 1200 is a circuit of the W attribute register 121. The circuit 1200 differs from the circuit 1000 in the connection of the read circuit 1002. The read circuit 1002 is not connected to the flip-flop circuit 1005, and is configured to always read out an initial value (or a value indicating that reading is not possible).

[0076] 9 to 12, even when the value of option setting item 533 is "no option", device 100 (software 300) generates a description of a port (communication circuit) for acquiring the current value of register 121 (flip-flop circuit 1005). However, when the value of option setting item 533 is "no option", device 100 does not necessarily have to generate a description of a port (communication circuit) for acquiring the current value of register 121. In one aspect, option setting item 533 may be configured to be selectable as to whether or not to generate a description of a port (communication circuit) for acquiring the current value of register 121 (flip-flop circuit 1005).

[0077] (Example of a circuit with cR attributes) 13 is a schematic diagram showing an example of a circuit with an R attribute. A circuit 1300 is a circuit corresponding to a hardware description that is automatically generated when the value of the attribute setting item 531 is "R (readable)" and the value of the option setting item 533 is "no option." Unlike the circuits 1000 and 1200, the circuit 1300 includes a bus circuit 1001, a read circuit 1002, and a port 1310, but does not include a write circuit 1003, a flip-flop circuit 1005, etc.

[0078] When the value of the attribute setting item 531 is "R (readable)", the device 100 generates a description of a special function circuit (a port 1310 for outputting a value input from a user circuit to the reading circuit 1002) in addition to the description of the R attribute. Many vendors provide a port for connecting to other circuits in a circuit with the R attribute (read only). At that time, the hardware description of the port for connecting to other circuits is added manually. In contrast, the device 100 can automatically generate a description of the port 1310 for connecting to other circuits without depending on hardware by generating a hardware description including the description of the port 1310 via an IP-XACT file. In one aspect, the port 1310 may be a circuit that inputs data to the register 121 in units of the register 121. In this case, when the data width of the register 121 is 16 bits, the port 1310 inputs data to the register 121 in units of 16 bits. In another aspect, the port 1310 may be a circuit that inputs data to the register 121 on a bit-by-bit basis.

[0079] The hardware description of the port 1310 enables the user circuit 130 to output a value input from the user circuit 130 to the reading circuit 1002 when a read access occurs. Furthermore, when a hardware modification or the like occurs, the device 100 can prevent the description of a special function from being omitted from being reflected in the document or the circuit (hardware description) or the like.

[0080] (d. First circuit example for "sp" option) 14 and 15, a first example of the hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the option setting item 533 is "sp" will be described.

[0081] 14 is a diagram showing a first example of a hardware description of register 121 when the value of option setting item 533 is “sp.” Hardware description 1400 is an example of a hardware description that is automatically generated when the value of option setting item 533 is “sp.”

[0082] The hardware description 1400 includes, in addition to a normal hardware description (such as RW attribute), a hardware description of ports 1501, 1502, 1503, 1504, and 1505 (see FIG. 15) which are circuits of special functions. The function of each port will be described later with reference to FIG. 15. In one aspect, when the value of the option setting item 533 is "sp", the device 100 may generate all of the descriptions of the ports 1501, 1502, 1503, 1504, and 1505 which are circuits of special functions. In another aspect, the option setting item 533 may be configured so that the presence or absence of the ports 1501, 1502, 1503, 1504, and 1505 can be individually set. In this case, the device 100 generates only the description of the port enabled by the option setting item 533 among the ports 1501, 1502, 1503, 1504, and 1505. In another aspect, each port may be a circuit that inputs or outputs data to or from register 121 in units of register 121. In this case, when the data width of register 121 is 16 bits, each port inputs or outputs data in units of 16 bits to register 121. In another aspect, each port may be a circuit that inputs or outputs data to or from register 121 in units of bits.

[0083] Based on the memory map, the device 100 generates a description of the circuits of special functions (at least a part of the ports 1501, 1502, 1503, 1504, 1505) other than the normal R, W, RW attributes. Even if a change occurs in the design of the hardware, the device 100 automatically generates a description of the circuits of the special functions based on the settings input via the screens 400 and 500. Therefore, when a hardware correction or the like occurs, the device 100 can prevent the description of the special functions from being omitted from the document or the circuit (hardware description), etc.

[0084] 15 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1400. The circuit 1500 is the circuit of the register 121 when the value of the option setting item 533 is "sp." The circuit 1500 includes a bus circuit 1001, a read circuit 1002, a write circuit 1003, a flip-flop circuit 1005, and ports 1501, 1502, 1503, 1504, and 1505.

[0085] The port 1501 is a port for outputting a value from the user circuit 130 to the read circuit 1002. When a read access occurs from an external circuit via the bus circuit 1001, the circuit 1500 outputs the value input from the port 1501 to the external circuit via the read circuit 1002 and the bus circuit 1001.

[0086] The port 1502 is a port for the user circuit 130 to obtain the current value of the register 121 (flip-flop circuit 1005). The port 1502 is connected to the user circuit 130 without passing through the bus circuit 1001. By using the port 1502, the user circuit 130 can obtain the current value of the register 121 without passing through the bus protocol control circuit 122.

[0087] The port 1503 is a port through which the user circuit 130 inputs an updated value to the register 121 (flip-flop circuit 1005). The value of the flip-flop circuit 1005 is rewritten by a signal input from the port 1503, not by a signal input from the write circuit 1003. The user circuit 130 can update the value of the register 121 by using the port 1502, without going through the bus protocol control circuit 122.

[0088] The port 1504 is a port for notifying the user circuit 130 that a write access has occurred by the write circuit 1003. The user circuit 130 can execute any process (such as a process of updating the value of the flip-flop circuit 1005) when a write access occurs, based on a signal indicating the occurrence of a write access obtained from the port 1504.

[0089] The port 1505 is a port for outputting a value input by the write circuit 1003 to the user circuit 130. The user circuit 130 can execute any process (such as a process of changing a value to be output to the port 1503) based on the value acquired from the port 1505.

[0090] (e. Second circuit example for "sp" option) 16 and 17, a second example of the hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the option setting item 533 is "sp" will be described.

[0091] 16 is a diagram showing a second example of the hardware description of register 121 when the value of option setting item 533 is "sp." The second example of the hardware description is a description in which hardware description 1600 is further added to hardware description 1400. Hardware description 1600 is a description related to port 1706 (see FIG. 17). The function of port 1706 will be described later with reference to FIG. 17.

[0092] In one aspect, when the value of option setting item 533 is "sp", device 100 may generate all of the hardware descriptions of ports 1501, 1502, 1503, 1504, 1505, and 1706, which are circuits for special functions. In another aspect, option setting item 533 may be configured to be able to set the presence or absence of ports 1501, 1502, 1503, 1504, 1505, and 1706 individually. In this case, device 100 generates only the hardware description of the port enabled by option setting item 533 among ports 1501, 1502, 1503, 1504, 1505, and 1706. In another aspect, each port may be a circuit that inputs or outputs data to register 121 in units of register 121. In this case, when the data width of register 121 is 16 bits, each port inputs or outputs data to register 121 in units of 16 bits. In another aspect, each port may be a circuit that inputs or outputs data to or from the register 121 on a bit-by-bit basis.

[0093] Based on the memory map, the device 100 generates a description of the circuits with special functions (at least a part of the ports 1501, 1502, 1503, 1504, 1505, 1706) other than the normal R, W, RW attributes. Even if a change occurs in the design of the hardware, the device 100 automatically generates a description of the circuits with special functions based on the settings input via the screens 400 and 500. Therefore, when a hardware correction or the like occurs, the device 100 can prevent the description of the special functions from being omitted from the document or the circuit (hardware description), etc.

[0094] 17 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1600. The circuit 1700 is the circuit of the register 121 when the value of the option setting item 533 is "sp." The circuit 1700 includes a port 1706 in addition to the configuration of the circuit 1500.

[0095] The port 1706 is a port for notifying the user circuit 130 that a read access has occurred by the reading circuit 1002. The user circuit 130 can execute any process (such as clearing the value of the flip-flop circuit 1005 when a read access has occurred) when a read access has occurred, based on a signal indicating the occurrence of a read access obtained from the port 1706.

[0096] (f. Circuit example for "sn" option) 18 and 19, an example of the hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the option setting item 533 is "sn" will be described.

[0097] FIG. 18 is a diagram showing an example of a hardware description of the register 121 when the value of the option setting item 533 is "sn". A hardware description 1800 is an example of a hardware description that is automatically generated when the value of the option setting item 533 is "sn". The "sn" option is an option for not including the register 121 in the memory map circuit (circuit 120). When the "sn" option is enabled, the device 100 does not generate a hardware description of the register 121 (one or more flip-flop circuits 1005), but generates a hardware description of the peripheral circuit of the register 121. Also, when the "sn" option is enabled, the device 100 generates a hardware description of the special function circuit (ports 1501, 1502, 1503, 1504, 1505, 1706, etc.) in the same manner as when the "sp" option is enabled.

[0098] In one aspect, when the value of option setting item 533 is "sn", device 100 may generate all of the hardware descriptions of ports 1501, 1502, 1503, 1504, 1505, and 1706, which are circuits for special functions. In another aspect, option setting item 533 may be configured to be able to set the presence or absence of ports 1501, 1502, 1503, 1504, 1505, and 1706 individually. In this case, device 100 generates only the hardware description of the port enabled by option setting item 533 among ports 1501, 1502, 1503, 1504, 1505, and 1706. In another aspect, each port may be a circuit that inputs or outputs data to register 121 in units of register 121. In this case, when the data width of register 121 is 16 bits, each port inputs or outputs data to register 121 in units of 16 bits. In another aspect, each port may be a circuit that inputs or outputs data to or from the register 121 on a bit-by-bit basis.

[0099] Based on the memory map, the device 100 generates a hardware description for a circuit with a special function other than the normal R, W, and RW attributes. Even if a change occurs in the design of the hardware, the device 100 automatically generates a description for the circuit with the special function based on the settings input via the screens 400 and 500. Therefore, when a hardware modification or the like occurs, the device 100 can prevent the description of the special function from being omitted from the document or the circuit (hardware description), etc.

[0100] 19 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1800. The circuit 1700 is the circuit of the register 121 when the value of the option setting item 533 is "sn". The circuit 1900 includes ports 1501, 1502, 1503, 1504, 1505, and 1706, similar to the circuit 1700. However, the circuit 1900 does not include the flip-flop circuit 1005. Also, the port 1503 is connected to the port 1502 instead of the flip-flop circuit 1005.

[0101] When the circuit 120 (memory-mapped circuit) includes the register 121, some processing must be performed on the input signal of the port 1503 when the register 121 is not used. This is because, when the input voltage of the port 1503 becomes an intermediate potential due to indefiniteness or high impedance, etc., a through current may occur due to the characteristics of the CMOS circuit. Therefore, in order to solve problems that may occur when the circuit 120 (memory-mapped circuit) includes the register 121, the device 100 provides an "sn" option that does not include the register 121 in the circuit 120 (memory-mapped circuit). In a certain aspect, when the "sn" option is enabled, the device 100 does not need to generate the hardware description of the port 1503 itself.

[0102] <E.フローチャート> Fig. 20 is a diagram showing an example of a procedure for generating a hardware description by the device 100. In one aspect, the processor 201 may load a program for performing the processing of Fig. 20 from the storage 203 into the memory 202 and execute the program. In another aspect, a part or all of the processing may be realized as a combination of circuit elements configured to perform the processing.

[0103] In step S2010, the device 100 accepts input for setting a memory map. More specifically, the device 100 accepts input for setting a memory map and a register 121 included in the memory map via the screens 400 and 500. The setting for the register 121 includes options for generating attributes, initial values, and circuits for special functions of the register 121.

[0104] In step S2020, the device 100 generates a memory map including the options. The device 100 generates the memory map in any format based on the settings received via the screens 400 and 500.

[0105] In step S2030, device 100 acquires the attribute of register 121. More specifically, device 100 acquires the content input in attribute setting item 531 on screen 500 (either the R attribute, the W attribute, or the RW attribute).

[0106] In step S2040, device 100 acquires the initial value of register 121. More specifically, device 100 acquires the content input to initial value setting item 532 on screen 500 (either "0" or "1" is set for each bit of register 121).

[0107] In step S2050, device 100 acquires the option of register 121. More specifically, device 100 acquires the content entered in option setting item 533 on screen 500 ("no option", "rc", "rs", "sp", "sn", or any other optional option).

[0108] In step S2060, the device 100 generates an IP-XACT (xml) file from the memory map. The IP-XACT file includes options (special functions) of the registers 121 expressed in the IP-XACT format. In one aspect, the device 100 may generate a file in any format other than the IP-XACT (xml) file from the memory map. In this case, the device 100 generates a hardware description from a file in a format other than the generated IP-XACT (xml) file.

[0109] In step S2070, the device 100 generates a hardware description from the IP-XACT file. The hardware description includes a description of options (special functions) of the register 121. In one aspect, the device 100 may generate the hardware description directly from the memory map. In this case, the device 100 may not generate an IP-XACT file.

[0110] In step S2080, apparatus 100 outputs the generated hardware description. In one aspect, apparatus 100 may output only the hardware description, may output only the IP-XACT file, or may output both the hardware description and the IP-XACT file. In another aspect, apparatus 100 may output the generated hardware description to a display connected to apparatus 100, or may transmit information about the hardware description to another device.

[0111] As described above, the device 100 (software 300) according to the present embodiment automatically generates a hardware description including a description of a circuit of a special function other than the description related to the R attribute, W attribute, and RW attribute of the register 121. By using the device 100, a user can easily design a circuit including the register 121 having a special function that does not use the bus protocol control circuit 122. Furthermore, since the device 100 automatically generates a hardware description including a description of a special function that does not use the bus protocol control circuit 122 based on the option of the memory map, it is possible to prevent the description of the special function from being omitted from a document or a circuit (hardware description) when a hardware correction or the like occurs.

[0112] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is indicated by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. In addition, the disclosure contents described in the embodiments and each modified example are intended to be implemented, as far as possible, either alone or in combination. [Explanation of symbols]

[0113] 100 device, 110,120,140,145,1000,1200,1300,1500,1700,1900 circuit, 121 register, 122 bus protocol control circuit, 130 user circuit, 201 processor, 202 memory, 203 storage, 204 output IF, 205 input IF, 206 communication IF, 207 external device IF, 208 internal bus, 300 software, 301 memory map generator, 302 IP-XACT generator, 303 hardware description generator, 400,500 screen, 401 interface setting item, 402 module name setting item, 403 data width setting item, 404 register map setting item, 405 port setting item, 510 address setting item, 511 absolute address setting item, 512 offset address setting item, 520 Register name setting item, 530 Register setting item, 531 Attribute setting item, 532 Initial value setting item, 533 Option setting item, 700,800,900,1100,1400,1600,1800 Hardware description, 910,1110 Description, 1001 Bus circuit, 1002 Read circuit, 1003 Write circuit, 1004 Selector, 1005 Flip-flop circuit, 1006,1310,1501,1502,1503,1504,1505,1706 Port.

Claims

1. An apparatus for supporting digital circuit design, comprising: a memory map generator for generating a memory map; a hardware description generator that generates a hardware description based on the memory map; the hardware description generator generates a description of ports for an external circuit to communicate with the memory-mapped circuit; The port description is a description of circuitry separate from write and read circuitry via a bus of registers included in the memory map.

2. The apparatus of claim 1 , wherein the port description includes a port description for reading the current value of the register on a per-register basis.

3. 3. The device according to claim 1, wherein the description of the ports includes a description of a port for inputting a value to be output to the read circuit when a read process via the read circuit occurs for the register.

4. The apparatus of any one of claims 1 to 3, wherein the description of the ports includes a description of a port for inputting an update value to the register.

5. The device according to any one of claims 1 to 4, wherein the description of the port includes a description of a port for outputting a signal indicating the occurrence of a write process to the external circuit when a write process occurs to the register via the write circuit.

6. 6. The device according to claim 1, wherein the description of the ports includes a description of a port for outputting a value input from the write circuit to the external circuit.

7. The device according to any one of claims 1 to 6, wherein the description of the port includes a description of a port for outputting a signal indicating the occurrence of a read process to the external circuit when a read process occurs on the register via the read circuit.

8. An interface for receiving an option input of the register, the memory map includes the options; The apparatus of claim 1 , wherein the hardware description generator is configured to generate a description of the port based on the options.

9. The apparatus of claim 8 , wherein the options include an option to not generate the register in the memory map.

10. 1. A computer-implemented method for assisting digital circuit design, comprising: generating a memory map; generating a hardware description based on the memory map; generating the hardware description includes generating a description of ports for an external circuit to communicate with the memory-mapped circuit; The method, wherein the port description is a description of circuitry separate from write and read circuitry via a bus of registers included in the memory map.

11. A program for supporting digital circuit design, generating a memory map; generating a hardware description based on the memory map; generating the hardware description includes generating a description of ports for an external circuit to communicate with the memory-mapped circuit; The program, wherein the port description is a description of a circuit other than a write circuit and a read circuit that are routed via a bus of a register included in the memory map.

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