Semiconductor Device

Abstract

To reduce on-resistance while suppressing an increase in characteristic dispersion of a vertical MOSFET having an SJ configuration.SOLUTION: A vertical MOSFET has: a semiconductor substrate having an n-type drift region; a p-type base region formed on the surface of the n-type drift region; a plurality of p-type column regions which are arranged in a lower part of the p-type base region and arranged in the n-type drift region at prescribed intervals; a plurality of grooves which are arranged between adjacent p-type column regions and whose bottom surfaces reach positions deeper than the p-type base region; a plurality of gate electrodes formed in the plurality of grooves; and an n-type source region formed in the p-type base region and formed in side parts of the gate electrodes.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including a vertical type Metal Oxide Field Effect Transistor (MOSFET) having a trench gate, and in particular, is a technology that is effective when applied to a semiconductor device having a so-called super junction structure (hereinafter referred to as SJ structure) having a p-type column region formed so as to protrude from the bottom of a p-type base region toward an n-type drift region. [Background technology]

[0002] A semiconductor device having an SJ structure includes, for example, a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions connected to the p-type base region and arranged at predetermined intervals in the n-type drift region, a gate electrode arranged between adjacent p-type column regions and formed in a trench reaching the bottom surface of the p-type base region, and an n-type source region formed in the p-type base region and on the side of the gate electrode.

[0003] An example of a semiconductor device having such an SJ structure is described in Patent Document 1 (JP 2017-168501 A). This document discloses a vertical MOSFET having a plurality of p-type column regions formed in a stripe shape in a plan view, and a stripe-shaped gate electrode disposed between adjacent p-type column regions and formed along the p-type column regions. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-168501 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors have found that there are the following concerns when attempting to further reduce the on-resistance of a vertical MOSFET having an SJ structure.

[0006] In order to further reduce the on-resistance of a vertical MOSFET having a so-called SJ structure as described in Patent Document 1, it is effective to periodically narrow the pitch of the p-type column regions and to increase the concentration of the n-type drift region or the p-type column region. However, there is a problem in that the sensitivity of the breakdown voltage and normalized on-resistance of the vertical MOSFET due to the dimensional changes of the p-type column region and the n-type drift region increases, which leads to an increase in the characteristic variation of the vertical MOSFET.

[0007] Other objects and novel features will become apparent from the description of this specification and the drawings. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment includes a semiconductor substrate having an n-type drift region, a p-type base region formed on a surface of the n-type drift region, a plurality of p-type column regions disposed below the p-type base region and arranged at predetermined intervals in the n-type drift region, a plurality of trenches disposed between adjacent p-type column regions and having bottom surfaces reaching a position deeper than the p-type base region, a plurality of gate electrodes formed in the plurality of trenches via gate insulating films, and an n-type source region formed in the p-type base region and on a side of the gate electrode. Effect of the Invention

[0009] According to a semiconductor device according to an embodiment, the on-resistance can be reduced while suppressing an increase in the variation in characteristics of a vertical MOSFET having an SJ structure. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Diagram 2] FIG. 2 is an enlarged plan view of the cell region indicated by the dotted line in FIG. [Diagram 3] FIG. 3 is a cross-sectional view of a main part of the unit cell UC in FIG. [Figure 4] FIG. 4 is an enlarged plan view of a cell region showing a comparative example of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Diagram 5] FIG. 5 is a cross-sectional view of a main part of the unit cell UC in FIG. [Figure 6] FIG. 6 is a graph showing the relationship between the breakdown voltage BVdss and the normalized on-resistance Rsp of the vertical MOSFET according to the embodiment and the vertical MOSFET according to the comparative example. [Figure 7] FIG. 7 is an enlarged plan view of a cell region showing Modification 1 of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a main part of the unit cell UC in FIG. [Figure 9] FIG. 9 is an enlarged plan view of a cell region showing Modification 2 of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a main part of the unit cell UC in FIG. [Figure 11] FIG. 11 is an enlarged plan view of a cell region showing Modification 3 of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a main part of the unit cell UC in FIG. [Figure 13] 13A to 13C are cross-sectional views of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure according to one embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, following FIG. [Figure 15] FIG. 15 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 16] FIG. 16 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 18] FIG. 18 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 19] FIG. 19 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 20] FIG. 20 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, following FIG. [Figure 21] FIG. 21 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device having a vertical MOSFET structure, subsequent to FIG. [Figure 23] FIG. 23 is an enlarged plan view of a cell region showing Modification 4 of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Figure 24] FIG. 24 is an enlarged plan view of a cell region showing Modification 5 of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Diagram 25] FIG. 25 is an enlarged plan view of a cell region showing a sixth modification of a semiconductor device having a vertical MOSFET structure according to an embodiment. [Figure 26] FIG. 26 is an enlarged plan view of a cell region showing Modification 7 of the semiconductor device having a vertical MOSFET structure according to one embodiment. [Figure 27] FIG. 27 is an enlarged plan view of a cell region showing Modification 8 of the semiconductor device having a vertical MOSFET structure according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] A semiconductor device according to an embodiment will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and duplicated descriptions will be omitted. At least a part of the embodiment and each modification may be arbitrarily combined with each other. In each cross-sectional view, diagonal lines indicating non-cavities may be omitted to make the drawings easier to see. When a cavity is shown, it will be clearly stated in the specification that it is a cavity.

[0012] The code “ - " and " + " indicates the relative concentration of impurities of n-type or p-type conductivity. For example, for n-type impurities, "n -- ", "n - ", "n", "n + ", "n ++ The impurity concentration increases in the order of

[0013] (Embodiment 1) The semiconductor device of this embodiment will be described with reference to Figures 1 to 3. As shown in Figure 1, the semiconductor device including a vertical MOSFET has a gate pad 101 and a source pad 102 on a main surface of a semiconductor substrate 100. Reference numeral 103 typically indicates a cell region of the vertical MOSFET located on the lower surface of the source pad 102.

[0014] 2 is an enlarged plan view of the cell region 103 indicated by the dotted line in FIG. 1, in which a plurality of p-type column regions 104 and a plurality of trench gates (gate electrodes) 105 are arranged in parallel along the Y direction. The interval Pcol between the p-type column regions 104 and the interval Ptr between the trench gates 105 are each set to a constant interval, and in this embodiment, the interval Pcol is preferably set to twice the interval Ptr. Furthermore, when the width of the trench gate 105 in the X direction is Wtr, the unit cell UC is designed so that when a line virtually connecting adjacent p-type column regions 104 is traced, there is always an overlap with the trench gate 105 that is at least twice the width Wtr.

[0015] As shown in FIG. 3, a p-type base region 106 and a p-type + The type base contact regions 107 are repeatedly formed in parallel at intervals Ptr in the X direction.

[0016] 3 is a cross-sectional view taken along the line AA in FIG. 2. Each unit cell UC of the vertical MOSFET is formed in a semiconductor substrate 100. - n-type epitaxial layer - A type drift region 108 and an n - A high impurity concentration n-type drift region 108 is formed in the lower part of the + n-type semiconductor layer + A drain region 109 and an n + A drain electrode 110 is electrically connected to the lower surface of the drain region 109 .

[0017] In the p-type base region 106, a high impurity concentration n + n-type semiconductor layer + The n-type source region 111 is formed. + The p-type source region 111 is shallower than the p-type base region 106 in the Z direction, which is the thickness direction of the semiconductor substrate 100, and the p-type column region 104 is formed deeper than the p-type base region 106. - The trench gate 105 is formed so as to fill two trenches formed by etching the surface of the drift region 108. - A gate insulating film (gate oxide film) 112 is formed at the interface between the type drift region 108 and the trench gate 105. - On the upper surface of the drift region 108, a trench gate 105 and an n + An insulating film 113 is formed so as to cover the type source region 111, and a source electrode 114 is formed on the upper surface of the insulating film 113.

[0018] The source electrode 114 is connected to the n-type MOS transistor 101 via a stripe-shaped contact hole CH1 formed in the insulating film 113 between the adjacent trench gates 105. +The p-type source region 111 is formed so as to reach a position shallower than the p-type base region 106. + The source electrode 114 is connected to the p-type base contact region 107 through a stripe-shaped contact hole CH2 formed in the insulating film 113. + The contact region 107 is connected to the base.

[0019] For comparison with the configuration of the vertical MOSFET according to the first embodiment described above, Figs. 4 and 5 show a comparative example of the vertical MOSFET described in Figs. 2 and 3. Fig. 5 is a cross-sectional view taken along the line B-B in Fig. 4. The vertical MOSFET shown in Figs. 4 and 5 is configured such that a p-type column region 104 is always disposed between adjacent trench gates 105. In other words, only one stripe-shaped trench gate 105 is disposed between adjacent p-type column regions 104 in a plan view.

[0020] 4 and 5, the vertical MOSFET according to the first embodiment can ensure a wider current path by reducing the occupancy rate of the p-type column regions 104 per unit cell UC in plan view. Furthermore, even if the repetition interval Ptr of the trench gates 105 is reduced to improve the gate density, the repetition interval Pcol between the p-type column regions and the drift region (also referred to as n-column) can be ensured to be twice the interval Ptr, so that the on-resistance can be reduced without the need to excessively increase the impurity concentrations of the p-type column regions and the drift region.

[0021] FIG. 6 shows the relationship between the charge imbalance rate (balance of the charge amount between the p-type and n-type column regions) and the breakdown voltage BVdss and normalized on-resistance Rsp when the charge amounts in the p-type column region and n-type column region are equal when the maximum breakdown voltage of a vertical MOSFET is obtained.

[0022] 4 and 5, in order to reduce the normalized on-resistance Rsp while maintaining a charge imbalance margin that satisfies a certain withstand voltage or more, it is necessary to reduce Pcol / Ptr and increase the concentration of the p-type and n-type column regions. Therefore, there is a problem that the sensitivity of the withstand voltage and normalized on-resistance Rsp to the charge imbalance rate becomes high.

[0023] On the other hand, in the vertical MOSFET structure of the first embodiment, the normalized on-resistance Rsp can be significantly reduced without increasing the sensitivity of the breakdown voltage BVdss and the normalized on-resistance Rsp to the charge imbalance rate. Therefore, not only is the basic performance improved, but the device is also tolerant of manufacturing variations and the product yield can be improved.

[0024] (Variation 1) Modification 1 of the first embodiment is shown in Figures 7 and 8. A change in modification 1 compared to the first embodiment is that the repetition interval of the trench gates 105 is set to two types, interval Ptr1 and interval Ptr2, and when the repetition interval of the p-type column regions 104 and the trench gates 105 is interval Pcol, the interval Pcol has a relationship of adding up the interval Ptr1 and the interval Ptr2. Note that Figure 8 is a cross-sectional view taken along CC in Figure 7.

[0025] Since the semiconductor device of the first modification has such a relationship, the degree of freedom in designing the unit cells is higher than that of the first embodiment, and the distance between the p-type column region 104 and the trench gate 105 can be made larger, so that the effect of the p-type column region 104 on the channel resistance can be suppressed. - Since the distance between the PN junction of the type drift region 108) and the trench gate 105 can be made large, the coupling of the electric field strength that increases at the PN junction and the lower part of the trench gate 105 can be alleviated, thereby improving the breakdown voltage.

[0026] (Variation 2) Modification 2 of the first embodiment is shown in Figures 9 and 10. The change in modification 2 compared to the first embodiment is that the trench gate 105 having the minimum trench width Wtr is formed in a honeycomb structure in plan view in order to improve the gate density, and further, the p-type column regions 104 are arranged in a staggered pattern in plan view. Even in this configuration, the unit cell UC is designed so that when tracing a line virtually connecting adjacent p-type column regions 104, there is always an overlap with the trench gate 105 that is at least twice the width Wtr. Note that Figure 10 is a cross-sectional view taken along the line DD in Figure 9.

[0027] In FIG. 10, a trench gate 105 having a width W in the X direction and a width Wtr in the Y direction is formed between adjacent p-type column regions, and the trench gate 105 is designed so that the width W is two or more times the width Wtr.

[0028] In the structure of the second modification, the density of the trench gates 105 in the unit cells UC is higher than that of the first embodiment. This improves the channel density, thereby reducing the on-resistance of the vertical MOSFET. Even if the trench gate density is designed to be high, the occupancy rate of the p-type column region per unit cell in plan view can be reduced, ensuring a wide current path. This allows the on-resistance to be reduced without the need to excessively increase the impurity concentrations of the p-type column region and the n-type drift region.

[0029] (Variation 3) Modification 3 of the first embodiment is shown in Figures 11 and 12. The modification 3 is different from the first embodiment in that the trench gate 105 having a minimum trench width Wtr is formed in a lattice structure in plan view in order to improve the gate density, and further, the p-type column regions 104 are arranged in a staggered pattern in plan view. Even in this configuration, the unit cell UC is designed so that when tracing a line virtually connecting adjacent p-type column regions 104, there is always an overlap with the trench gate 105 that is at least twice the width Wtr. Note that Figure 12 is an E-E cross-sectional view of Figure 11.

[0030] In FIG. 12, a trench gate 105 having a width W in the X direction and a width Wtr in the Y direction is formed between adjacent p-type column regions, and the trench gate 105 is designed so that the width W is two or more times the width Wtr.

[0031] In the structure of the third modification, the density of the trench gates 105 in the unit cells UC is higher than that of the first embodiment. This improves the channel density, thereby reducing the on-resistance of the vertical MOSFET. Even if the trench gate density is designed to be high, the occupancy rate of the p-type column region in the unit cell unit in plan view can be reduced, thereby ensuring a wide current path. This allows the on-resistance to be reduced without the need to excessively increase the impurity concentrations of the p-type column region and the n-type drift region.

[0032] A method for manufacturing a semiconductor device including a vertical MOSFET according to an embodiment of the present invention will now be described.

[0033] As shown in FIG. 13, a semiconductor substrate 100 is prepared in which an epitaxial layer EP is formed on a silicon substrate SB having, for example, a (100) crystal face and made of an n-type high concentration semiconductor layer.

[0034] Next, as shown in FIG. 14, a hard mask HM1 made of an insulating film 10 and a photoresist film 11 is formed on the upper surface of the epitaxial layer EP.

[0035] Next, as shown in FIG. 15, the upper surface of the epitaxial layer EP exposed from the hard mask HM1 is etched to form grooves 12 for trench gates.

[0036] Next, after removing the hard mask HM1, the trench 12 is filled with an insulating film 13, and then an insulating film 14, an insulating film 15, and an insulating film 16 are sequentially formed on the upper surface of the epitaxial layer EP, as shown in Fig. 16. The insulating film 14 and the insulating film 16 are made of, for example, a silicon oxide film formed by a CVD method. The insulating film 15 is made of, for example, a silicon nitride film formed by a CVD method.

[0037] 17, a hard mask HM2 composed of a photoresist film 17 and an insulating film 16 is formed by normal photolithography and etching techniques. Next, using the hard mask HM2 as a mask for doping impurities, p-type impurities such as boron are ion-implanted into the epitaxial layer EP to form p-type column regions 104.

[0038] Next, after removing the hard mask HM2, the insulating film 15, and the insulating film 14, as shown in FIG. 18, a gate insulating film 112 is formed on the surface of the epitaxial layer EP including the surfaces of the trenches 12 by, for example, thermal oxidation treatment.

[0039] 19, a trench gate 105 is formed so as to fill the trench 12. The trench gate 105 is formed, for example, of a polycrystalline silicon film doped with an n-type impurity, and is selectively formed in the trench 12 by depositing the polycrystalline silicon film on the entire surface of the semiconductor substrate 100 and then etching back the polycrystalline silicon film by CMP.

[0040] 20, p-type impurities such as boron are selectively ion-implanted into the epitaxial layer EP to form a p-type base region 106. The p-type base region 106 is formed between adjacent trench gates 105 so as to be connected to the p-type column region 104, and is formed at a position shallower than the bottom surface of the trench gate 105.

[0041] Next, as shown in FIG. 21, n-type impurities such as arsenic are selectively ion-implanted into the epitaxial layer EP to form n + The n-type source region 111 is formed. + The p-type source region 111 is formed on the surface of the p-type base region 106 so as to be located at an end of the trench gate 105 .

[0042] Next, an insulating film 113 is formed on the entire surface of the semiconductor substrate 100, and then the insulating film 113 is patterned by normal photolithography and etching techniques using a photoresist film 18 to form contact holes CH1 and CH2 in the insulating film 113. The contact holes CH1 and CH2 are formed so as to be located between adjacent trench gates 105 and on the p-type column region 104, respectively. In addition, the bottom surfaces of the contact holes CH1 and CH2 are formed by partially etching the surface of the epitaxial layer EP so as to reach the p-type base region 106.

[0043] Next, p-type impurity ions are implanted into the p-type base region 106 exposed from the contact holes CH1 and CH2 using the photoresist film 18 and the insulating film 113 as a mask. + 22, a source electrode 114 mainly made of aluminum is formed, and then a drain electrode 110 having a layered structure made of Au / Cu / Ni is formed on the lower surface of the semiconductor substrate 100, thereby completing a vertical MOSFET.

[0044] The invention made by the inventor has been specifically described above based on an embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0045] For example, although the present invention has been described with respect to an n-channel vertical MOSFET, it can also be applied to a p-channel vertical MOSFET by reversing the conductivity types of the semiconductor layers constituting the source region, drain region, base region (also called a channel formation region), and drift region.

[0046] 2 and 7 may be arranged in a staggered or mesh-like manner in a plan view and scattered in the n-type drift region, as shown in Figures 23 to 26. Figures 23 to 26 are plan views showing semiconductor devices in Modifications 4 to 8.

[0047] 23 to 26, the occupancy rate of the p-type column regions 104 in plan view is the lowest in the staggered arrangement shown in Fig. 23 and Fig. 25, and the width of the current path is wide, so the effect of reducing the on-resistance is high. Also, in the case of the square mesh arrangement shown in Fig. 24 and Fig. 26, the width of the current path is wider than that in the stripe arrangement shown in Fig. 2 and Fig. 7, so the effect of reducing the on-resistance is high.

[0048] On the other hand, the ease of depletion required to obtain a high withstand voltage is better when the distance between the p-type column regions is short and the relationship of the PN junction formed between the p-type column regions and the n-type column regions (n-type drift regions) is uniform, so this is the opposite of the ease of reducing the on-resistance, and the arrangement that is most suitable for achieving high withstand voltage is, in that order, the stripe arrangement, the square mesh arrangement, and the staggered arrangement.

[0049] 27, the p-type column region 104 does not have to be directly connected to the bottom surface of the p-type base region 106. In this case, the p-type column region 104 is -The n-type region between the p-type base region 106 and the p-type column region 104 is surrounded by the p-type drift region 108 and the potential is in a floating state, but the thickness T1 of the n-type region between the p-type base region 106 and the p-type column region 104 should be set to a thickness that suppresses the barrier that allows holes to be supplied from the p-type base region 106 to the p-type column region 104 during actual operation of the vertical MOSFET. A suitable value for the thickness T1 of the n-type region between the p-type column regions 104 can be, for example, about 0.5 μm.

[0050] With this configuration, the distribution of the depletion layer can be optimized more than with the structure shown in FIG. 3, which can contribute to improving the breakdown voltage of the vertical MOSFET. [Explanation of symbols]

[0051] 10. Insulating film 11 Photoresist film 12 grooves 13. Insulating film 14 Insulating film 15 Insulating film 16 Insulating film 17 Photoresist film 18 Photoresist film 100 Semiconductor substrate 101 Gate Pad 102 Sauce Pad 103 Cell Area 104 p-type column region 105 Trench Gate 106 p-type base region 107 p + Mold base contact area 108n - Type Drift Region 109 n + Type drain region 110 Drain electrode 111n + Type Source Area 112 Gate insulating film 113 Insulating film 114 Source Electrode Pcol Spacing of p-type column regions Ptr Trench Gate Spacing Wtr Trench gate width UC unit cell HM1 Hard Mask HM2 Hard Mask CH1 Contact hole CH2 Contact Hole T1 Thickness of n-type region

Claims

1. A semiconductor device having a plurality of unit cells, The plurality of unit cells are arranged in a first direction in a plan view, The unit cell comprises: a drift region formed in a semiconductor substrate and made of a semiconductor layer of a first conductivity type; a base region formed on a surface of the drift region and made of a semiconductor layer of a second conductivity type opposite to the first conductivity type; two column regions each made of the semiconductor layer of the second conductivity type, each of which is disposed below the base region and spaced apart from the other in the drift region, and which are formed in a stripe shape along a second direction perpendicular to the first direction in a plan view; two grooves, each of which is disposed in the drift region between the two column regions and has a bottom surface reaching a position deeper than the base region, and is disposed apart from the two column regions, respectively, and is formed in a stripe shape along the second direction in a plan view; two gate electrodes formed in the two trenches, respectively, via gate insulating films formed on the surfaces of the two trenches so as to fill the two trenches, respectively; a plurality of source regions formed in the base region and on both sides of each of the two gate electrodes, the source regions being made of the semiconductor layer of the first conductivity type; adjacent unit cells among the plurality of unit cells share the column region.

2. 2. The semiconductor device according to claim 1, a bottom surface of the two column regions is located in the drift region at a position deeper than the bottom surfaces of the two trenches.

3. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the distance between the two column regions is set to be at least twice the distance between the two gate electrodes.

4. 2. The semiconductor device according to claim 1, The two column regions are arranged to be connected to a bottom surface of the base region.

5. 2. The semiconductor device according to claim 1, the two column regions are disposed at a predetermined distance from a bottom surface of the base region in a thickness direction of the semiconductor substrate.

6. A semiconductor device having a plurality of unit cells, The plurality of unit cells are arranged in a first direction in a plan view, The unit cell comprises: a drift region formed in a semiconductor substrate and made of a semiconductor layer of a first conductivity type; a base region formed on a surface of the drift region and made of a semiconductor layer of a second conductivity type opposite to the first conductivity type; a plurality of column regions each made of the semiconductor layer of the second conductivity type, the column regions being disposed below the base region, connected to the base region, and disposed in two rows in a staggered manner in the drift region along a second direction perpendicular to the first direction in a plan view; two grooves, the two grooves being disposed in the drift region between the two rows of column regions, the grooves being formed so that their bottom surfaces reach a position deeper than the base region, the grooves being disposed apart from the two rows of column regions, and the two grooves being formed in a stripe shape along the second direction in a plan view; two gate electrodes formed in the two trenches, respectively, via gate insulating films formed on the surfaces of the two trenches so as to fill the two trenches, respectively; a plurality of source regions formed in the base region and on both sides of each of the two gate electrodes, the source regions being made of the semiconductor layer of the first conductivity type; adjacent unit cells among the plurality of unit cells share the column region.

7. 7. The semiconductor device according to claim 6, a bottom surface of the plurality of column regions is located in the drift region at a position deeper than the bottom surfaces of the two trenches.

8. A semiconductor device having a plurality of unit cells, comprising: The plurality of unit cells are arranged in a first direction in a plan view, The unit cell comprises: a drift region formed in a semiconductor substrate and made of a semiconductor layer of a first conductivity type; a base region formed on a surface of the drift region and made of a semiconductor layer of a second conductivity type opposite to the first conductivity type; a plurality of column regions each made of the semiconductor layer of the second conductivity type, the column regions being disposed below the base region, connected to the base region, and arranged in two rows in a mesh shape in the drift region along a second direction perpendicular to the first direction in a plan view; two grooves, the two grooves being disposed in the drift region between the two rows of column regions, the grooves being formed so that their bottom surfaces reach a position deeper than the base region, the grooves being disposed apart from the two rows of column regions, and the two grooves being formed in a stripe shape along the second direction in a plan view; two gate electrodes formed in the two trenches, respectively, via gate insulating films formed on the surfaces of the two trenches so as to fill the two trenches, respectively; a plurality of source regions formed in the base region and on both sides of each of the two gate electrodes, the source regions being made of the semiconductor layer of the first conductivity type; adjacent unit cells among the plurality of unit cells share the column region.

9. 9. The semiconductor device according to claim 8, a bottom surface of the plurality of column regions is located in the drift region at a position deeper than the bottom surfaces of the two trenches.

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