Circuit board manufacturing method

Abstract

A method and planar sheet for fabricating electrical circuits on a laminate from low profile copper layers in which one or more circuits have known and repeatable signal loss is provided. A method for manufacturing a printed circuit board (40) includes providing a planar sheet including a planar dielectric material layer (16) having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane. The plane of the first copper foil is in contact with the plane of the first dielectric material layer, and the first and second surfaces of the first copper foil sheet include adhesion-enhancing layers (12, 12', 14, 14'), respectively. The method further includes forming a circuit pattern on the first planar copper sheet by removing unnecessary portions of the first planar copper sheet while leaving the copper of the circuit pattern in predetermined locations to form an innerlayer sheet including the circuit pattern, and forming another circuit pattern that is not formed in the circuit pattern after forming the circuit pattern.

Description

[Technical field]

[0001] The present invention relates to a method for fabricating electrical circuits on a laminate from low profile copper layers, where one or more circuits have a known and repeatable transmission line total signal loss. [Background technology]

[0002] Printed circuit board (PCB) designers continue to push the limits of materials used in PCBs for high speed digital applications. New PCBs with transmission lines capable of achieving data rates of 25 Gb / channel and above require laminators to develop new designs that improve dielectric properties using novel resin systems, laminates with expanded flat glass cloth and extremely low profile copper foil, and prepregs. Each of these design features impacts the electrical performance of the finished printed circuit board.

[0003] Copper foil technology continues to develop with new and improved surface topographies to improve copper / dielectric adhesion strength and reduce skin effect. The surface topography of copper foil is responsible for signal loss associated with the materials used in the manufacture of PCBs. Up to 30% signal loss difference has been seen between foils with a roughness of 5-7 μm and foils with a roughness of 2-3 μm. This improvement can be leveraged to improve the performance of the entire laminate material. However, the signal loss improvement is limited to the copper foil surface that is bonded to and in direct contact with the laminate (dielectric material layer).

[0004] In innerlayer processing of copper clad laminates to produce circuit patterns, three sides of the copper transmission lines are exposed and treated to enhance adhesion to the prepreg or bonding sheet between the innerlayers. Treatment processes, commonly referred to as oxide or adhesion enhancing processes, are accomplished through a variety of means to modify the copper surface to enhance the mechanical and / or chemical bonding of the treated copper surface with adjacent layers of dielectric material. As with any copper surface modification process, the resulting copper topography will vary depending on the type of chemistry used, the process controls and capabilities of the manufacturer, and the equipment used to process the innerlayers. Each of these major contributing factors is magnified when comparing the resulting copper surface topography variations between printed circuit manufacturers.

[0005] There are four surfaces on a transmission line. Of these surfaces, the laminate manufacturer controls the bottom of the trace - the surface that is bonded to the laminate (approximately 40-45% of the perimeter of the cross-sectional area depending on the copper weight) and only partially controls the top of the transmission line, or the process side of the copper foil. The laminator may select the foil with the lowest surface profile that provides acceptable peel strength, and then bond the lowest profile surface, typically the drum side, to the laminate. The laminator may control the "as-shipped" top copper foil topography, and select copper with an extremely low profile, but the PCB manufacturer typically applies an adhesion enhancing process to the top surface of the copper, or the top surface of the transmission line, and it is the process selected and the performance of the selected process that determines the final transmission line top and sidewall profile, and the subsequent effect on signal loss.

[0006] PCB manufacturers use different adhesion strengthening processes and process parameters to change the profile of the top and side walls of the transmission lines. As the allowable circuit loss specifications continue to decrease, the surface topography differences from adhesion strengthening processes among printed circuit board manufacturers are becoming an issue. Surface topography variations in adhesion strengthening among manufacturers are considered a growing challenge, and the process capabilities of various printed circuit board manufacturers need to be coordinated to ensure that each processes the inner layers through adhesion strengthening and meets the stringent surface topography specifications. Summary of the Invention

[0007] One aspect of the invention is a method for manufacturing a printed circuit board, comprising the steps of: preparing a planar sheet including a planar dielectric material layer having a first plane and a second plane; and a first copper foil sheet having a first plane and a second plane, the first copper foil plane being in contact with a plane of the first dielectric material layer, and each of the first and second surfaces of the first copper foil sheet including an adhesion strengthening layer; and forming a circuit pattern in the first planar copper sheet by removing unnecessary portions of the first planar copper sheet while leaving the copper of the circuit pattern in predetermined places to form an innerlayer sheet including a circuit pattern, the adhesion strengthening layer not being formed in the circuit pattern.

[0008] Another aspect of the invention is a method for manufacturing a plurality of printed circuit boards at a first manufacturing location, comprising the steps of: (a) providing a planar sheet including a dielectric material layer having a first plane and a second plane; and a first copper foil sheet having a first plane and a second plane, the first plane of the first copper foil being in contact with the first plane of the dielectric material layer, each of the first plane and the second plane of the first copper foil sheet including an adhesion strengthening layer; and (b) adhering the first copper foil to a first innerlayer sheet including a circuit pattern in a predetermined location to form a first manufactured innerlayer sheet including the circuit pattern. (b) subsequently manufacturing a plurality of printed circuit boards at a first manufacturing location, the plurality of printed circuit boards including: (a) forming a circuit pattern on the first copper foil sheet by removing unnecessary portions of the first planar copper sheet while leaving the copper of the pattern, wherein an adhesion strengthening layer is not formed on the circuit pattern, and the circuit pattern includes a transmission line having a total circuit loss; and (b) incorporating the first manufactured innerlayer sheet into a first manufactured printed circuit board; and (c) subsequently manufacturing a plurality of printed circuit boards at a second manufacturing location, the plurality of printed circuit boards including the first planar and second copper foil sheets. providing a planar sheet including a dielectric material layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the first plane of the first copper foil sheet being in contact with the first plane of the dielectric material layer, and each of the first surface and the second surface of the first copper foil sheet including an adhesion enhancing layer; and applying a circuit pattern to the first planar copper sheet by removing unwanted portions of the first planar copper sheet while leaving the copper of the circuit pattern in place to form a second manufactured innerlayer sheet including a circuit pattern. manufacturing a plurality of printed circuit boards at a second manufacturing location, the plurality of printed circuit boards including: forming a circuit pattern, wherein an adhesion strengthening layer is not formed on the circuit pattern, and the circuit pattern includes a transmission line having a total circuit loss; and incorporating the second manufactured innerlayer sheet into a second manufactured printed circuit board, wherein the transmission line of the first manufactured innerlayer essentially matches the transmission line of the second manufactured innerlayer;(c) repeating steps (a) and (b) a plurality of times to form a plurality of first fabricated innerlayers and a plurality of second fabricated innerlayers, wherein a measured total loss of at least 90 percent of the transmission lines of the plurality of first fabricated innerlayers and a measured total loss of at least 90 percent of the transmission lines of the plurality of second fabricated innerlayers differ from each other by no more than 10%.

[0009] Yet another aspect of the invention is a planar sheet comprising a planar dielectric material layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the first copper foil plane being in contact with the first dielectric material layer plane, and each of the first and second surfaces of the first copper foil sheet including an adhesion enhancement layer.

[0010] In certain embodiments, the adhesion promotion layer has an Rz roughness of about 0.25 to about 5.0 microns. In other embodiments, the surface roughness of the first planar copper foil sheet on the first plane is less than about 1.5 microns. In yet other embodiments, the surface roughness of the second plane of the first copper foil sheet is less than about 2.5 microns. [Brief description of the drawings]

[0011] [Figure 1A] FIG. 1A is a photograph of the copper foil surface after pre-cleaning and before surface oxidation. [Figure 1B] FIG. 1B is a photograph of the copper foil surface after pre-cleaning and before surface oxidation. [Figure 2A] FIG. 2A is a photograph of a copper foil surface that has been subjected to an oxide treatment step after pre-cleaning. [Figure 2B] FIG. 2B is a photograph of the copper foil surface that was subjected to an oxide treatment step after pre-cleaning. [Figure 3A] FIG. 3A is a process diagram of a method of the present invention for forming a circuit. [Figure 3B]FIG. 3B is a process diagram of a method of the present invention for forming a circuit. [Figure 3C] FIG. 3C is a process diagram of a method of the present invention for forming a circuit. [Figure 4] FIG. 4 is a cross-sectional view of an exemplary printed circuit board including an innerlayer sheet such as that shown in FIG. 3C. [Diagram 5] FIG. 5 is a schematic diagram of a process for manufacturing printed circuit boards at different manufacturing locations where the printed circuit boards contain identical or essentially identical circuitry. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The present invention relates to a method of manufacturing printed circuit boards using planar material sheets such as resin coated copper sheets, copper clad prepregs or copper clad c-staged laminates, the planar sheets including a dielectric material sheet or layer and at least one planar copper foil or sheet surface, the copper foil or sheet including an adhesion enhancing layer on both planar copper surfaces, the adhesion enhancing layer being applied to the copper foil or sheet before a circuit is formed on the copper foil or sheet. The present invention further relates to resin coated copper sheets, copper clad prepregs and copper clad laminates having one or two exposed copper foil or sheet surfaces, both planar surfaces of each copper foil or sheet being provided with an adhesion enhancing layer.

[0013] The methods, prepregs and laminates of the present invention include copper foils or sheets pretreated with an adhesion enhancing layer. For purposes of this specification, the term "foil" refers to thin, planar copper sheet material made by any known method, such as rolled copper foil and electrodeposited copper foil, which is useful when resin coated, used as a prepreg cladding, or otherwise used in the manufacture of printed circuit boards.

[0014] The copper foil sheet may be selected from copper foils having various thicknesses, preferably selected from 2 oz. copper foil, 1 oz. copper foil, ½ oz. copper foil and ¼ oz. copper foil. Also, the copper foil is preferably a low profile copper foil or an extremely low profile copper foil. The term extremely low profile copper foil is defined as a copper foil having an Rz surface roughness of 1.3 micrometers or less, preferably an Rz surface roughness of 0.9 micrometers or less. Typically, low profile copper foil sheets have a thickness of 10 to 400 microns, and extremely low profile copper sheets have a thickness of about 5 to about 200 microns, more narrowly about 5 to about 35 microns.

[0015] The double-treated copper foil of the present invention is planar, including a first plane and a second plane, and both planes of the copper foil are pretreated with a method to form a thin adhesion-enhancing layer on each plane of the copper foil sheet. The pretreatment may be accomplished by any method known in the art, such as nodulation treatment, HET foil treatment, MLS foil treatment, surface oxide treatment, and other similar treatment steps. In one embodiment, the same pretreatment method is used to provide an adhesion-enhancing layer to the first and second planes of the copper foil in a single step. Alternatively, a first treatment method provides an adhesion-enhancing layer to the first plane of the copper foil, and a second treatment method provides an adhesion-enhancing layer to the second plane.

[0016] 1A and 1B are photographs of two surfaces of a copper foil sheet before the adhesion-enhancing layer treatment. Generally, the copper foil before treatment has a surface roughness (Rz) of about 0.4 to about 6.0 μm, preferably about 2.5 μm or less. The term "low-profile copper foil" is defined as a copper foil having one flat surface bonded to a dielectric layer, with an Rz surface roughness of about 2.5 μm or less. For copper foils produced by copper electrodeposition or moving drum, the drum side of the copper foil has a smoother surface roughness than the non-drum or "matte" side, as shown in FIG. 1A and FIG. 1B. In such foils, the matte side may have a surface roughness Rz of 1 to 3 μm greater than the drum side.

[0017] 2A and 2B are photographs of the surface of a copper foil sheet after pretreatment with one or more adhesion enhancement methods to form an adhesion enhancement layer on both copper foil planes. The adhesion enhancement methods typically remove a thin copper layer from the copper foil surface, 1-2 μm. In addition, the adhesion enhancement methods typically reduce the roughness of the adhesion enhanced copper foil surface compared to the surface roughness before adhesion enhancement. In one embodiment, the copper foil sheet with an adhesion enhanced surface has an Rz surface roughness of about 0.25 to about 5.0 μm, preferably less than about 2.5 μm, and most preferably less than about 1.5 μm.

[0018] As used herein, the term "adhesion promotion layer" refers to a surface of a copper foil sheet that has been modified in some way to improve the ability of the copper foil sheet to adhere to an adjacent layer of dielectric material, as evidenced by improved peel strength, and / or to improve the adhesion of a photoresist material to the copper foil surface.

[0019] The adhesion-enhancing layer may be formed by any method known in the art for treating or modifying the surface of a copper foil sheet to improve its adhesion to a dielectric material layer. Methods include chemical methods such as applying silanes or other materials to the copper foil surface, oxide treatments of the copper foil surface, chemical cleaning, etc. Methods also include mechanical methods such as micro-etch treatments, pumice treatments, etc.

[0020] The adhesion promotion layer may further be treated or coated with a material that facilitates adhesion of the copper foil to an adjacent dielectric material layer. For example, the adhesion promotion layer may be a silane material layer or may be coated with a silane material layer, for example, as disclosed in U.S. Patent or Application Nos. 5,525,433, 5,622,782, 6,248,401, and 2013 / 0113523, each of which is incorporated herein by reference.

[0021] The dielectric material layer or sheet in contact with the copper foil layer may be made of any dielectric material that is or can be used in printed circuit board technology. Examples of dielectric materials include thermosetting resins such as epoxy resin and polyimide resin systems. Thermoplastic materials such as polytetrafluoroethane may also be employed as the dielectric material layer.

[0022] The methods and articles of the present invention include a planar sheet comprising a layer of dielectric material having a first planar surface and an opposing second planar surface in contact with or adhered to a planar surface of a copper foil having two planar surfaces, each planar surface of the copper foil comprising an adhesion enhancing layer.

[0023] In one example, the planar sheet is a prepreg. Prepregs are produced by impregnating glass cloth with a specially formulated resin. The resin gives the prepreg specific electrical, thermal and physical properties. The prepreg is incorporated into a copper clad laminate consisting of an inner layer of prepreg laminated on one or both sides with a thin layer of copper foil with an adhesion enhancing layer on both planes. Lamination is accomplished by pressing one or more layers of copper and prepreg together under intense heat, pressure and vacuum conditions. The adhesion enhancing layer is important to facilitate adhesion of the copper foil to the prepreg material and to ensure that the copper foil does not easily peel off from the prepreg material. The prepreg dielectric material is typically b-staged, meaning that the resin has been partially cured.

[0024] In another example, the planar sheet may be a fully cured resin or polymer that includes a copper foil layer adhered to one or both of its planar surfaces.

[0025] In yet another example, the planar sheet may be a resin coated copper foil sheet. Resin coated copper is useful as a thin dielectric for multi-layer high density interconnects. Resin coated copper consists of one or more layers of resin supported on electrodeposited copper foil. The resin is unsupported. Resin coated copper may act as an electrical insulating layer while encapsulating electrical circuits and also acting as an outer layer conductor. The resin in contact with the resin coated copper may be B-stage or C-stage, or may include a combination of B-stage and C-stage resin layers. Resin coated copper may be used as a cap layer or continuous build up with rigid laminates, and may be used in flex coverlay applications. The elimination of glass reinforcement from resin coated copper allows for the mass formation of blind microvias by means other than mechanical drilling.

[0026] Figures 3A, 3B and 3C are representative of certain methods and products of the present invention. A double-treated (adhesion-enhancing layers on both planes) copper foil sheet (10) is shown in Figure 3A. The double-treated copper foil sheet (10) further includes a first surface-treated plane (12) which is a first adhesion-enhancing layer and a second surface-treated plane (14) which is a second adhesion-enhancing layer. In Figure 3B, two double-treated copper foil sheets (10, 10') are bonded to a planar dielectric material layer (16) such that the first surface-treated plane (14) of the first copper sheet is adjacent and bonded to a first plane (18) of the planar dielectric material layer (16). Also in Figure 3B, a second optional copper foil sheet (10') having a first surface-treated plane (14') and a second surface-treated plane (12') is bonded to a second plane (20) of the dielectric material layer (16).

[0027] In FIG. 3B, the second planar surface (12, 12') remains exposed for further processing. Circuits are then formed in the dual-treated foil sheet (10), typically by applying a mask to the first surface-treated planar surface and removing the unmasked copper portions by etching. FIG. 3C shows the result of the etching process in which the inner layer sheet (40) includes a plurality of transmission lines (32, 34 and 36), each transmission line including a second adhesion strengthening layer (12 or 12'), a first adhesion strengthening layer (14 or 14') and a sidewall (20), with the sidewall (42) of the transmission line not including the adhesion strengthening layer. In some embodiments, the transmission lines may have one or more end walls that do not include an adhesion strengthening layer.

[0028] The surface topography of approximately 80-90% of the top and bottom of the copper foil, or the perimeter of the cross-sectional area of ​​the transmission line, will be the result of a well-controlled copper foil manufacturing process. In other words, when a portion of the copper foil is removed to form the circuit, 80-90% of the surfaces that make up the circuit (the top and bottom surfaces, not the sides of the circuit) have been surface treated. As a result, PCB manufacturers do not need to form adhesion-enhancing layers on the circuit structure after it is formed, essentially eliminating the variation of printed circuit boards across two or more manufacturing facilities.

[0029] Printed circuit board manufacturers use copper-clad laminates to produce multi-layer PCBs in a complex process involving multiple, often repeated steps. Typically, the copper surface of the laminate is etched to form the electronic circuits. These etched laminates are assembled into multi-layer configurations by inserting one or more layers of insulating prepreg between each etched laminate. Holes (vias) are then drilled and plated into the PCB to establish electrical connections between the layers. The resulting multi-layer PCB is a complex interconnected device on which semiconductors and other components are populated, which are then assembled into the final product.

[0030] FIG. 4 is a cross-sectional view of a printed circuit board (50) including one or more innerlayer sheets (40, 40', 40'') of the present invention. A typical printed circuit board includes at least one, and more typically multiple, innerlayer sheets (40), optionally separated by prepregs (42) and including optional vias (44) connecting circuitry formed on different innerlayer sheets. The printed circuit board (50) may optionally include upper circuitry (46) and lower circuitry (48).

[0031] 5 is a schematic diagram of a process for manufacturing a printed circuit board in two different manufacturing facilities, namely a first manufacturing facility (100) and a second manufacturing facility (200). According to the method in step (110), the same planar sheet is prepared as a PCB component in both manufacturing facilities. The prepared planar sheet (110) includes a planar dielectric material layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the plane of the first copper foil being in contact with the plane of the first dielectric material layer, and the first surface and the second surface of the first copper foil sheet each include an adhesion enhancing layer.

[0032] Next, in steps (120) and (220), essentially the same transmission line structure is formed in the first planar copper sheet at each of the first and second manufacturing facilities by removing unnecessary portions of the first planar copper sheet while leaving the circuit copper in place to form a first manufactured innerlayer sheet including a transmission line structure. During this step, no adhesion enhancement layer is formed on the transmission line structure. The resulting transmission line structure includes a first transmission line having circuit losses.

[0033] The method (120) used to form the transmission-line structure at the first manufacturing facility may be the same as or different from the method (220) used to form the transmission-line structure at the second manufacturing facility. For example, one step may use a positive photoresist and the other step may use a negative photoresist. This is just one example of how the method for forming the transmission-line structure may vary between the first and second manufacturing facilities, and other method variations would be within the knowledge of one of ordinary skill in the art.

[0034] Next, in steps (130) and (230), the innerlayer sheets containing the transmission line structures are assembled into a printed circuit board. The printed circuit board (shown in FIG. 4) may have a single innerlayer sheet (40) or multiple innerlayer sheets (40', 40'') separated by one or more prepreg layers (42). Layers are stacked on top of each other to form a layup that is then subjected to heat and pressure to bond the sheets together. Further processing such as via formation, outer surface plating, and circuit formation may all be completed in each of the first and second manufacturing facilities to form the final printed circuit board. Examples of PCB processing steps that may be performed include lamination, via drilling, direct metallization, outer layer imaging, plating, strip / etch outer layer, solder mask application, final finishing, routing to form individual PCBs, and electrical testing and inspection. Also, in one embodiment, a plurality of essentially identical PCBs are manufactured at a first manufacturing facility and a plurality of essentially identical PCBs are manufactured at a second manufacturing facility. Moreover, the PCBs manufactured at the first manufacturing facility are essentially identical to the PCBs manufactured at the second manufacturing facility. The term "essentially identical" in this context means that the manufactured PCBs are intended for the same use, for example as a PCB motherboard or as a primary circuit board for a particular mobile phone model.

[0035] Similar to the formation of the transmission line structure, the processes performed to form the printed circuit boards at the first and second manufacturing facilities may be the same or different. However, in one embodiment, the plurality of PCBs manufactured at the first manufacturing facility and the plurality of PCBs manufactured at the second manufacturing facility each have inner layers with the same circuit structure and at least one essentially identical transmission line. In step (140), the total loss of each essentially identical transmission line of the plurality of PCBs is inspected. Since the initially prepared inner layers (110) include copper foil with first and second adhesion strengthening layers manufactured by the same method, the circuit loss should vary within about 10% between the plurality of PCBs.

[0036] Generally, the term "loss" as used herein means "total loss", i.e. It refers to all signal power that is not transmitted to the receiver of a communication system due to undesirable effects in the channel medium. There are many possible causes of signal power loss in a typical channel, including imperfections in the printed circuit board material and manufacturing process that affect the integrity of the electrical signal. At the PCB transmission line level, there are various loss sources, including propagation loss. In one aspect, "loss" is measured using one of the four test methods described in IPC TM-650 2.5.5.12. The four loss test methods are Root Impulse Energy (RIE), Equivalent Bandwidth (EBW), Sparameters, and Short Pulse Propagation (SPP). In another aspect, loss is the insertion loss of a transmission line, either alone or in combination with dielectric loss. The total insertion loss (αT) is measured by taking into account conductor (αC), dielectric (αD), radiation (αR), and leakage losses (αL).

[0037] While the products and methods of using the products have been described in detail, it will be apparent that modifications and variations are possible without departing from the scope of the disclosure as defined in the appended claims. More specifically, although several aspects of the disclosure have been identified herein as particularly advantageous, it is believed that the invention is not necessarily limited to those particular aspects of the disclosure. The disclosure of this specification may include the following aspects. (Aspect 1) (i) providing a planar sheet including a planar dielectric layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the first copper foil plane being in contact with a plane of the first dielectric layer, and each of the first surface and the second surface of the first copper foil sheet including an adhesion enhancing layer; (ii) forming a circuit pattern in the first planar copper sheet by removing unnecessary portions of the first planar copper sheet while leaving the copper of the circuit pattern in predetermined locations to form an innerlayer sheet containing a circuit pattern, wherein an adhesion enhancing layer is not formed in the circuit pattern; A method for manufacturing a printed circuit board, comprising: (Aspect 2) 2. The method of claim 1, wherein a dielectric material layer is laminated to the innerlayer sheet such that the dielectric material layer adheres to the second planar surface of the circuit pattern. (Aspect 3) 2. The method of embodiment 1, wherein an adhesion promotion method is used to form an adhesion promotion layer on a first and second surface of the planar copper foil sheet. (Aspect 4) The method of claim 3, wherein a first adhesion enhancement method is used to form the adhesion strengthening layer on a first surface of the planar copper foil sheet, and a second adhesion enhancement method is used to form the adhesion strengthening layer on a second surface of the planar copper foil sheet, the first adhesion enhancement method and the second adhesion enhancement method being different adhesion enhancement methods. (Aspect 5) 2. The method of embodiment 1, wherein the adhesion promotion layer has an Rz roughness of about 0.25 to about 5.0 microns. (Aspect 6) 2. The method of claim 1, wherein the first planar copper foil sheet has a surface roughness of less than about 1.5 microns. (Aspect 7) 2. The method of claim 1, wherein the second planar surface of the first copper foil sheet has a surface roughness of less than about 2.5 microns. (Aspect 8) The circuit pattern includes a bottom wall corresponding to a first plane of the first copper sheet, a top wall corresponding to a second plane of the first copper foil sheet, and a side wall; 2. The method of embodiment 1, wherein the sidewall does not include an adhesion promotion layer. (Aspect 9) 2. The method of claim 1, wherein the inner layer sheet includes a circuit pattern having a plurality of transmission lines. (Aspect 10) 2. The method of claim 1, wherein the planar sheet includes a second copper foil sheet having a first plane and a second plane, the first plane of the second copper foil contacting the second plane of the dielectric material layer, and each of the first and second surfaces of the second planar copper foil sheet including an adhesion promotion layer. (Aspect 11) 11. The method of embodiment 10, wherein a circuit pattern is formed on the second copper sheet, and an adhesion promotion layer is not formed on the circuit pattern. (Aspect 12) The method of embodiment 1, wherein the layup is formed by stacking at least one innerlayer sheet onto the prepreg. (Aspect 13) 2. The method of claim 1, wherein the roughness of the first and second planar copper surfaces of the first copper foil sheet is essentially the same. (Aspect 14) 2. The method of claim 1, wherein the roughness of the first and second planar copper surfaces of the first copper foil sheet ranges from about 0.1 to about 6.0 microns. (Aspect 15) 2. The method of claim 1, wherein the copper foil is selected from 1 ounce copper foil, ½ ounce copper foil, and ¼ ounce copper foil. (Aspect 16) The method of claim 1, wherein the first copper foil sheet is a low profile copper foil sheet having a thickness of 10 to 400 microns, more preferably an extremely low profile copper sheet having a thickness of about 5 microns to about 200 microns, or more narrowly, about 5 to about 35 microns. (Aspect 17) The method of embodiment 1, wherein the adhesion promotion layer of the at least one first copper sheet comprises a coating. (Aspect 18) 10. The method of claim 9, wherein the circuit pattern includes a plurality of transmission lines having a width of about 25 to about 250 microns. (Aspect 19) 2. The method of embodiment 1, wherein the adhesion promotion layer is applied simultaneously to the first and second planar copper surfaces of the first copper foil sheet. (Aspect 20) 2. The method of claim 1, wherein the planar sheet is selected from resin coated copper, copper coated prepreg, or C-stage laminate. (Aspect 21) (a) manufacturing a plurality of printed circuit boards at a first manufacturing location, providing a planar sheet including a dielectric material layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the first plane of the first copper foil being in contact with the first plane of the dielectric material layer, and each of the first plane and the second plane of the first copper foil sheet including an adhesion strengthening layer; forming a circuit pattern in the first copper foil sheet by removing unnecessary portions of the first planar copper sheet while leaving the copper of the circuit pattern in predetermined places to form a first manufactured innerlayer sheet including a circuit pattern, wherein an adhesion enhancement layer is not formed in the circuit pattern, and the circuit pattern includes a transmission line having a total loss; incorporating the first manufactured innerlayer sheet into a first manufactured printed circuit board; manufacturing a plurality of printed circuit boards at a first manufacturing location; (b) manufacturing a plurality of printed circuit boards at a second manufacturing location, providing a planar sheet including a dielectric material layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the first plane of the first copper foil sheet being in contact with the first plane of the dielectric material layer, and each of the first surface and the second surface of the first copper foil sheet including an adhesion strengthening layer; forming a circuit pattern on the first planar copper sheet by removing unwanted portions of the first planar copper sheet while leaving the copper of the circuit pattern in predetermined places to form a second manufactured innerlayer sheet including a circuit pattern, wherein an adhesion enhancement layer is not formed on the circuit pattern, and the circuit pattern includes a transmission line having a total loss; incorporating the second manufactured innerlayer sheet into a second manufactured printed circuit board, the transmission lines of the first manufactured innerlayer essentially matching the transmission lines of the second manufactured innerlayer; manufacturing a plurality of printed circuit boards at a second manufacturing location, (c) repeating steps (a) and (b) a plurality of times to form a plurality of first manufactured inner layers and a plurality of second manufactured inner layers; repeating steps (a) and (b) a plurality of times, wherein the measured total losses of the transmission lines of at least 90 percent of the plurality of first manufactured inner layers and the measured total losses of the transmission lines of at least 90% of the plurality of second manufactured inner layers differ from each other by no more than 10%; A method for manufacturing a plurality of printed circuit boards, comprising: (Aspect 22) 22. The method of claim 21, wherein a measured total loss of the transmission line for at least 95 percent of the plurality of first manufactured inner layers and a measured total loss of the transmission line for at least 95% of the plurality of second manufactured inner layers differ from each other by no more than 10%. (Aspect 23) 22. The method of claim 21, wherein an adhesion promotion method is used to form an adhesion promotion layer on first and second surfaces of the planar copper foil sheet before the copper foil sheet is contacted with a dielectric material layer. (Aspect 24) 24. The method of claim 23, wherein the adhesion promotion layer is formed on a first surface of the flat copper foil sheet using a first adhesion promotion method and the adhesion promotion layer is formed on a second surface of the flat copper foil sheet using a different second adhesion promotion method. (Aspect 25) 22. The method of claim 21, wherein the adhesion promotion layer has an Rz roughness of about 0.25 to about 5.0 μm. (Aspect 26) 22. The method of claim 21, wherein the surface roughness of the first planar copper foil sheet is less than about 1.5 microns. (Aspect 27) 22. The method of claim 21, wherein the second plane of the first copper foil sheet has a surface roughness of less than about 2.5 microns. (Aspect 28) The circuit pattern formed in steps (a) and (b) includes a bottom wall corresponding to a first plane of the first copper sheet, a top wall corresponding to a second plane of the first copper foil sheet, and a side wall; 22. The method of claim 21, wherein the sidewall does not include an adhesion promotion layer. (Aspect 29) 22. The method of claim 21, wherein the inner layer sheet produced in steps (a) and (b) includes a circuit pattern having a plurality of transmission lines, and the first manufacturing facility and the second manufacturing facility use different methods for forming the first and second manufactured printed circuit boards. (Aspect 30) 22. The method of claim 21, wherein the planar sheet of each of steps (a) and (b) comprises a second copper foil sheet having a first plane and a second plane, the first plane of the second copper foil contacting the second plane of the dielectric material layer, and each of the first surface and second surface of the second planar copper foil sheet comprising an adhesion promotion layer. (Aspect 31) 31. The method of embodiment 30, wherein a circuit pattern is formed on the second copper sheet in steps (a) and (b), and no adhesion promotion layer is formed on the circuit pattern. (Aspect 32) 22. The method of claim 21, wherein the roughness of the first and second planar copper surfaces of the first copper foil sheet is essentially the same. (Aspect 33) 22. The method of claim 21, wherein the roughness of the first and second planar copper surfaces of the first copper foil sheet ranges from about 0.4 to about 6.0 μm. (Aspect 34) 22. The method of embodiment 21, wherein the first copper foil sheet used in steps (a) and (b) is selected from 1 ounce copper foil, ½ ounce copper foil, and ¼ ounce copper foil. (Aspect 35) 22. The method of claim 21, wherein the first copper foil sheet used in steps (a) and (b) is an extremely low profile copper sheet having a thickness of about 5 microns to about 35 microns. (Aspect 36) 22. The method of embodiment 21, wherein the adhesion promotion layer of the at least one first copper sheet comprises a coating. (Aspect 37) 22. The method of embodiment 21, wherein the at least one transmission line has a width of about 25 to about 250 microns. (Aspect 38) 22. The method of embodiment 21, wherein the adhesion promotion layer is applied simultaneously to the first and second planar copper surfaces of the first copper foil sheet used in steps (a) and (b). (Aspect 39) 22. The method of claim 21, wherein the planar sheet of steps (a) and (b) is selected from resin-coated copper, copper-coated prepreg, or C-stage laminate. (Aspect 40) a planar dielectric material layer having a first plane and a second plane; and a first copper foil sheet having a first plane and a second plane; A planar sheet, the planar surface of the first copper foil being in contact with the planar surface of the first dielectric material layer, and each of the first and second surfaces of the first copper foil sheet including an adhesion enhancing layer. (Aspect 41) A planar sheet as described in embodiment 40, wherein a circuit pattern is formed on the first planar copper sheet such that unnecessary portions of the first planar copper sheet are removed leaving the copper of the circuit pattern in place, and an adhesion enhancement layer is not formed on the circuit pattern after it is formed. (Aspect 42) 41. The planar sheet of embodiment 40, comprising a second dielectric material layer laminated to the planar sheet such that the second dielectric material layer is adhered to the second planar surface of the circuit pattern. (Aspect 43) The planar sheet of embodiment 40, wherein the adhesion promotion layers on the first and second surfaces of the first copper foil sheet are formed by different adhesion promotion methods. (Aspect 44) 41. The planar sheet of claim 40, wherein the adhesion promotion layer has an Rz roughness of about 0.25 to about 5.0 microns. (Aspect 45) 41. The planar sheet of embodiment 40, wherein the surface roughness of the first plane of the first copper foil sheet is less than about 1.5 microns. (Aspect 46) 41. The planar sheet of claim 40, wherein the surface roughness of the second planar surface of the first copper foil sheet is less than about 2.5 microns. (Aspect 47) The circuit pattern includes a bottom wall corresponding to a first plane of the first copper sheet, a top wall corresponding to a second plane of the first copper foil sheet, and a side wall; 42. The planar sheet of claim 41, wherein the sidewalls do not include an adhesive promotion layer. (Aspect 48) 48. The planar sheet of claim 47, wherein the circuit pattern includes a plurality of transmission lines. (Aspect 49) a second copper foil sheet having a first planar surface and a second planar surface; A planar sheet as described in embodiment 40, wherein a first plane of the second copper foil contacts a second plane of the dielectric material layer, and each of the first and second surfaces of the second planar copper foil sheet includes an adhesion reinforcement layer. (Aspect 50) 50. The planar sheet of embodiment 49, wherein a circuit pattern is formed on the second copper sheet, and an adhesion promotion layer is not formed on the circuit pattern. (Aspect 51) 41. The planar sheet of embodiment 40, wherein the roughness of the first and second planar copper surfaces of the first copper foil sheet is essentially the same. (Aspect 52) 41. The planar sheet of claim 40, wherein the roughness of the first and second planar copper surfaces of the first copper foil sheet ranges from about 0.1 to about 6.0 microns. (Aspect 53) 41. The planar sheet of embodiment 40, wherein the copper foil is selected from 1 ounce copper foil, ½ ounce copper foil, and ¼ ounce copper foil. (Aspect 54) 41. The planar sheet of embodiment 40, wherein the first copper foil sheet is an extremely low profile copper sheet having a thickness of about 5 microns to about 35 microns. (Aspect 55) 41. The planar sheet of embodiment 40, wherein the adhesion promotion layer of the at least one first copper sheet comprises a coating. (Aspect 56) 41. The planar sheet of embodiment 40, wherein the planar sheet is selected from resin-coated copper, copper-coated prepreg, or copper-coated C-stage laminate.

Claims

1. (i) providing a planar sheet including a planar dielectric layer having a first plane and a second plane, and a first copper foil sheet having a first plane and a second plane, the first plane of the first copper foil sheet being in contact with the first plane of the planar dielectric layer, and each of the first plane and the second plane of the first copper foil sheet including an adhesion strengthening layer, the adhesion strengthening layer being formed by an adhesion strengthening method that reduces surface roughness; (ii) forming a circuit pattern on the first copper foil sheet by removing unnecessary portions of the first copper foil sheet while leaving the copper of the circuit pattern in place to form an inner layer sheet containing a circuit pattern, wherein an adhesion strengthening layer is not formed on the circuit pattern after the circuit pattern is formed; A method for manufacturing a printed circuit board, comprising:

2. The method of claim 1 , wherein a layer of dielectric material is laminated to the innerlayer sheet such that the layer of dielectric material adheres to the second planar surface of the circuit pattern.

3. The method of claim 1 , further comprising forming an adhesion enhancement layer on the first planar surface and the second planar surface of the first copper foil sheet using an adhesion enhancement method.

4. 4. The method of claim 3, wherein a first adhesion enhancement method is used to form the adhesion strengthening layer on the first plane of the first copper foil sheet, and a second adhesion enhancement method is used to form the adhesion strengthening layer on the second plane of the first copper foil sheet, the first adhesion enhancement method and the second adhesion enhancement method being different adhesion enhancement methods.

5. The method of claim 1 , wherein the adhesion promotion layer has an Rz roughness of about 0.25 to about 5.0 microns.

6. 10. The method of claim 1, wherein the first planar surface of the first copper foil sheet has a surface roughness of less than about 1.5 microns.

7. 10. The method of claim 1, wherein the second planar surface of the first copper foil sheet has a surface roughness of less than about 2.5 microns.

8. the circuit pattern includes a bottom wall corresponding to the first plane of the first copper foil sheet, a top wall corresponding to the second plane of the first copper foil sheet, and a side wall; The method of claim 1 , wherein the sidewall does not include an adhesion promotion layer.

9. The method of claim 1 , wherein the inner layer sheet includes a circuit pattern having a plurality of transmission lines.

10. 2. The method of claim 1, wherein the planar sheet includes a second copper foil sheet having a first plane and a second plane, the first plane of the second copper foil sheet contacting a second plane of the planar dielectric material layer, and each of the first plane and the second plane of the second copper foil sheet including an adhesion enhancement layer.

11. 11. The method of claim 10, wherein a circuit pattern is formed on the second copper foil sheet, and an adhesion strengthening layer is not formed on the circuit pattern of the second copper foil sheet after the circuit pattern of the second copper foil sheet is formed.

12. The method of claim 1 , wherein the layup is formed by stacking at least one inner layer sheet onto the prepreg.

13. The method of claim 1 , wherein the roughness of the first planar surface and the second planar surface of the first copper foil sheet are the same.

14. 2. The method of claim 1, wherein the roughness of the first and second planar surfaces of the first copper foil sheet ranges from about 0.1 to about 6.0 microns.

15. 11. The method of claim 10, wherein the first and second copper foil sheets are selected from 1 ounce copper foil, 1 / 2 ounce copper foil, and 1 / 4 ounce copper foil, respectively.

16. The method of claim 1, wherein the first copper foil sheet is a copper foil sheet having a thickness of 10 to 400 microns.

17. The method of claim 1 , wherein the at least one adhesion promotion layer of the first copper foil sheet comprises a coating.

18. The method of claim 9, wherein the circuit pattern comprises a plurality of transmission lines having a width of about 25 to about 250 microns.

19. The method of claim 1 , wherein the adhesion promotion layer is applied simultaneously to the first planar and second planar surfaces of the first copper foil sheet.

20. 10. The method of claim 1, wherein the planar sheet is selected from resin coated copper, copper clad prepreg, or C-stage laminate.

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