POWER CONVERSION DEVICE, CONTROL METHOD FOR POWER CONVERSION DEVICE, AND PROGRAM

Abstract

To provide a power conversion device having high reliability, a method for controlling the power conversion device, and a program.SOLUTION: A power conversion device of an embodiment has a power converter and a converter control part. The power converter includes at least one arm unit in which is connected in series a plurality of unit converters having an energy storage element and a plurality of switching elements. The converter control part switches at least between a first control state in which the unit converters are made output a voltage of the energy storage element and a second control state in which the unit converters are shorted, thereby controlling conversion operation of the power converter. The converter control part has a state count computation part for calculating the number of unit converters to which the control state is allocated, a list computation part for generating list information of voltage magnitude relations of the energy storage element, and a unit converter selection part for selecting a unit converter the control state of which is to be changed. The unit converter selection part excludes a unit converter whose control state has not been continued for a minimum time from the unit converters whose control states are to be changed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a power conversion device, a control method for the power conversion device, and a program. [Background technology]

[0002] In recent years, the modular multilevel converter (MMC) has been put to practical use as a power converter. The MMC is a power converter equipped with an arm unit including multiple unit converters (hereinafter referred to as "cells") connected in series, and is capable of handling high voltage and large capacity by adding the voltages output by each cell. Power converters are used, for example, in direct current transmission systems and reactive power compensators. For example, a power converter for a direct current transmission system is connected between an alternating current system and a direct current system, and performs mutual conversion of the respective powers. For example, a power converter for a reactive power compensator is connected to an alternating current system, and adjusts the reactive power at the interconnection point.

[0003] In a power converter, when performing mutual conversion of power or adjusting reactive power, a switching element included in the power converter is controlled. For example, a phase shift PWM (Pulse Width Modulation) method is known as a switching control method in a power converter, in which a multi-step stepped sine wave is synthesized in the entire arm unit by uniformly shifting the phase of a triangular wave carrier assigned to each cell. However, in the phase shift PWM method, the frequency of the triangular wave carrier needs to be higher than the frequency of the AC system, which results in large losses in switching control (switching losses).

[0004] In this regard, for example, Patent Document 1 and Patent Document 2 disclose a technique for one-pulse control in which each cell is switched once in one cycle of the voltage of an AC system. However, in conventional switching control, there is a problem that the variation in the voltage of the capacitors of each cell increases when the switching frequency decreases. For this reason, in a power converter, a method for equalizing the voltage of the capacitors of each cell during switching control has been proposed, which includes a method for adjusting the phases of the rising and falling of the output voltage of each cell, and a method for changing the order of the rising and falling of the output voltage according to the magnitude relationship of the voltage of the capacitors of each cell.

[0005] The method of changing the order of rising and falling of the output voltage according to the magnitude relationship of the voltages of the capacitors of each cell can be realized by acquiring the voltages of the capacitors of each cell in the arm unit at regular intervals and selecting the target cell for switching control by comparing the magnitude relationship. However, unlike the conventional phase shift PWM method, this method does not manage the switching time for each individual cell, so there are cases where switching control is concentrated on a specific cell. If switching control is concentrated on a specific cell and multiple switching controls are performed in a short period of time, for example, it may cause the switching element to break down due to reasons such as inability to achieve stable state transitions and concentration of heat generation. In this case, the reliability of the power converter is significantly reduced. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-233126 A [Patent Document 2] JP 2015-159687 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a highly reliable power conversion device, a control method for a power conversion device, and a program therefor, by controlling a unit converter included in a power converter. [Means for solving the problem]

[0008] A power conversion device according to an embodiment includes a power converter and a converter control unit. The power converter includes at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element for storing power and a plurality of switching elements capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element. The converter control unit controls the power conversion operation in the power converter by switching the control state to at least one of a first control state in which the terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited. The converter control unit includes a state number calculation unit, a list calculation unit, and a unit converter selection unit. The state number calculation unit calculates a state number representing the number of unit converters belonging to the arm unit to be assigned to any of the control states according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit. The list calculation unit generates list information representing the magnitude relationship between the terminal voltages of the detected energy storage elements. The unit converter selection unit measures the duration for which the same control state continues for each unit converter, and selects the unit converter for which the current control state is to be changed based on the measured duration, the polarity of the arm current flowing through the arm unit, the number of states, and the list information. The unit converter selection unit excludes the unit converter for which the duration has not exceeded a predetermined minimum time as an excluded unit converter, from the unit converters for which the control state is to be changed. [Brief description of the drawings]

[0009] [Figure 1]1 is a diagram showing an example of the configuration of a power conversion device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a configuration of cells in a leg included in a power converter. [Diagram 3] FIG. 2 is a diagram showing an example of the configuration of a converter control unit included in the power conversion device. [Figure 4] 5 is a timing chart illustrating an example of operation timing of a first operation in the power conversion device. [Diagram 5] 6 is a timing chart illustrating an example of operation timing of a second operation in the power conversion device. [Figure 6] 10 is a timing chart illustrating an example of operation timing of a third operation in the power conversion device. [Figure 7] 10 is a timing chart illustrating an example of operation timing of a fourth operation in the power conversion device. [Figure 8] 13 is a timing chart illustrating an example of operation timing of a fifth operation in the power conversion device. [Figure 9] 13 is a timing chart illustrating an example of operation timing of a sixth operation in the power conversion device. [Figure 10] 13 is a timing chart illustrating an example of operation timing of a seventh operation in the power conversion device. [Figure 11] FIG. 13 is a diagram showing an example of the configuration of a power conversion device according to a second embodiment. [Figure 12] FIG. 2 is a diagram showing an example of a configuration of cells in a leg included in a power converter. [Figure 13] 13 is a timing chart illustrating an example of operation timing of an eighth operation in the power conversion device. [Figure 14] 13 is a timing chart illustrating an example of operation timing of a ninth operation in the power conversion device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a power conversion device, a control method for the power conversion device, and a program according to an embodiment will be described with reference to the drawings.

[0011] (First embodiment) [Power conversion device configuration] Fig. 1 is a diagram showing an example of a configuration of a power conversion device according to a first embodiment. Fig. 1 shows an example of a power conversion device 1 that is provided at an interconnection point between an AC system and a DC system, and converts AC power supplied by the AC system into DC power supplied by the DC system, and vice versa. The AC system may be, for example, an AC power source or an AC load. The DC system may be, for example, a DC power source or a DC load. The power conversion device 1 includes a power converter 10 and a converter control unit 50.

[0012] The power converter 10 is a dual star-connected modular multilevel converter (MMC) that converts AC power and DC power mutually in response to control from a converter control unit 50. The power converter 10 includes a plurality of legs 12 between a positive terminal P of a DC system and a negative terminal N of the DC system. The number of legs 12 included in the power converter 10 corresponds to the number of phases of AC power supplied by the AC system. FIG. 1 shows a case where the AC system supplies three-phase AC power, namely, a first phase (R phase), a second phase (S phase), and a third phase (T phase). For this reason, FIG. 1 shows a configuration of the power converter 10 including three legs 12, namely, a leg 12-R, a leg 12-S, and a leg 12-T. Each of the legs 12-R, the leg 12-S, and the leg 12-T has the same configuration.

[0013] In each leg 12, the AC terminal CA is connected to a terminal of a corresponding phase of the AC system. More specifically, in the leg 12-R corresponding to the R phase, the AC terminal CA-R is connected to an AC terminal R of the R phase of the AC system, in the leg 12-S corresponding to the S phase, the AC terminal CA-S is connected to an AC terminal S of the S phase of the AC system, and in the leg 12-T corresponding to the T phase, the AC terminal CA-T is connected to an AC terminal T of the T phase of the AC system. Fig. 1 shows a case where the AC terminal CA of each leg 12 is connected to a terminal of a corresponding phase of the AC system via a transformer TR.

[0014] In each leg 12, a terminal opposite to the AC terminal CA is connected to a respective DC terminal of the DC system. More specifically, in each leg 12, a terminal having the same potential as the positive pole of the DC voltage output by the power converter 10 is connected to a positive terminal P, and a terminal having the same potential as the negative pole of the DC voltage output by the power converter 10 is connected to a negative terminal N. In the following description, the terminal of leg 12 connected to the positive terminal P is also referred to as a DC terminal CP of leg 12, and the terminal of leg 12 connected to the negative terminal N is also referred to as a DC terminal CN of leg 12.

[0015] Each leg 12 includes, for example, two reactors 14 and two arm units 16. Each arm unit 16 includes, for example, n cells 162 (cells 162-1 to 162-n) connected in series (n is a natural number). In FIG. 1, in order to distinguish whether each component included in the leg 12 corresponds to the positive or negative side of the DC system or to which phase of the AC system, a "- (hyphen)" and the letter "P" representing the positive side or the letter "N" representing the negative side are added after each reference symbol, followed by a hyphen and the letter "R" representing the R phase, the letter "S" representing the S phase, or the letter "T" representing the T phase. In the following description, when it is not necessary to distinguish whether each component corresponds to the positive or negative side of the DC system or to which phase of the AC system, the hyphen and the identifying letter following the hyphen added to the reference symbol of each component are omitted.

[0016] In each leg 12, the positive reactor 14-P and the positive arm unit 16-P are connected in series, and the negative reactor 14-N and the negative arm unit 16-N are connected in series. In each leg 12, the connection point between the reactor 14-P and the reactor 14-N is the DC terminal CP. In each leg 12, the terminal of the arm unit 16-P opposite to the reactor 14-P is the DC terminal CP of the leg 12, and the terminal of the arm unit 16-N opposite to the reactor 14-N is the DC terminal CN of the leg 12. In other words, in each leg 12, the cells 162-1 to 162-n and the reactor 14-P are connected in series in this order from the DC terminal CP side to the AC terminal CA side, and are connected to the AC terminal CA. Furthermore, in each leg 12, the cell 162-n to the cell 162-1 and the reactor 14-N are connected in series in this order from the DC terminal CN side toward the AC terminal CA side, and are connected to the AC terminal CA.

[0017] The leg 12 is an example of a "phase unit" in the claims. The arm unit 16-P (which may include the reactor 14-P) is an example of a "first arm unit" in the claims, and the arm unit 16-N (which may include the reactor 14-N) is an example of a "second arm unit" in the claims. The cell 162 is an example of a "unit converter" in the claims. The reactor 14 is an example of an "inductance element" in the claims.

[0018] 1 shows a case where the reactor 14 is arranged on the AC terminal CA side of the arm unit 16 in each leg 12, but the reactor 14 may be arranged on the opposite side of the AC terminal CA side of the arm unit 16 (i.e., on the DC terminal CP side or the DC terminal CN side) or at any position in the arm unit 16 (i.e., between any two cells 162 connected in series in the arm unit 16). The reactor 14 may be replaced with a transformer with a special winding structure having a leakage reactance sufficient to replace the function of the reactor. In this case, the reactor 14 may be integrated with the transformer TR.

[0019] Each arm unit 16 generates an AC voltage with a multi-level waveform, which is a stepped sine wave representing the AC waveform to be supplied to the corresponding phase of the AC system, in response to control from the converter control unit 50 for each of the series-connected cells 162.

[0020] Here, an example of the configuration of the cell 162 included in the arm unit 16 will be described. The cell 162 is, for example, a half-bridge circuit. FIG. 2 is a diagram showing an example of the configuration of the cell 162 in the leg 12 included in the power converter 10. The cell 162 includes two switching elements Q (switching element Q1 and switching element Q2), two diodes D (diode D1 and diode D2), and a capacitor C. The switching element Q is, for example, an insulated gate bipolar transistor (IGBT). The switching element Q is not limited to an IGBT. The switching element Q may be any element as long as it is a self-extinguishing semiconductor switching element capable of realizing a converter or an inverter.

[0021] In the cell 162, the switching element Q1 and the switching element Q2 are connected in series to each other. In the cell 162, the series circuit of the switching element Q1 and the switching element Q2 and the capacitor C are connected in parallel to each other. In the cell 162, each switching element Q and its corresponding diode D are connected in parallel to each other. In the cell 162, the connection point between the emitter of the switching element Q1 and the collector of the switching element Q2 is the positive terminal TP(+) connected to the positive terminal P of the leg 12, and the connection point between the emitter of the switching element Q2 and the capacitor C is the negative terminal TN(-) connected to the negative terminal N of the leg 12.

[0022] A control signal from the converter control unit 50 is input to the gates of the switching element Q1 and the switching element Q2 included in the cell 162 (a control voltage is applied or a control current is supplied). A gate signal gtp is input to the gate of the switching element Q1 as a control signal from the converter control unit 50, and a gate signal gtn is input to the gate of the switching element Q2 as a control signal from the converter control unit 50. As a result, each of the switching elements Q1 and Q2 is switched to either an on state or an off state by the converter control unit 50. In the following description, when a control signal (gate signal gtp, gate signal gtn) of "1 ("High" level)" is input, each of the switching elements Q is turned on, and when a control signal (gate signal gtp, gate signal gtn) of "0 ("Low" level)" is input, each of the switching elements Q is turned off.

[0023] The capacitor C is charged or discharged according to the state of each switching element Q. In the cell 162, the terminal voltage of the capacitor C (hereinafter referred to as "capacitor voltage Vc") is generated as the terminal voltage between the positive terminal TP and the negative terminal TN of the cell 162 (hereinafter referred to as "cell voltage Vo"). More specifically, when the converter control unit 50 sets the control signal (gtp, gtn) = (1, 0), for example, a current flows in the order of the positive terminal TP, the switching element Q1, the capacitor C, and the negative terminal TN, and the cell voltage Vo of the cell 162 coincides with the capacitor voltage Vc. In other words, when the converter control unit 50 sets the control signal (gtp, gtn) = (1, 0), the capacitor C is inserted between the positive terminal TP and the negative terminal TN of the cell 162, and the capacitor voltage Vc is output as the cell voltage Vo. In the following description, the converter control unit 50 setting the control signals (gtp, gtn)=(1, 0) is referred to as "insertion", and the state of the cell 162 in this case is referred to as "insertion state". On the other hand, when the converter control unit 50 sets the control signals (gtp, gtn)=(0, 1), for example, a current flows through the positive terminal TP, the switching element Q2, and the negative terminal TN in that order, and the cell voltage Vo of the cell 162 becomes 0 [V]. In other words, when the converter control unit 50 sets the control signals (gtp, gtn)=(0, 1), the positive terminal TP and the negative terminal TN of the cell 162 are short-circuited, and a current flows without passing through the capacitor C, and the cell voltage Vo of the cell 162 becomes 0 [V]. In the following description, the converter control unit 50 setting the control signals (gtp, gtn)=(0, 1) is referred to as "bypass", and the state of the cell 162 in this case is referred to as "bypass state".

[0024] The cell 162 is not limited to the configuration shown in FIG. 2, and may have any configuration as long as it achieves the same function as the cell 162.

[0025] The switching element Q1 and the diode D1 are an example of a "switching element" and a "first switching element" in the claims, and the switching element Q2 and the diode D2 are an example of a "switching element" and a "second switching element" in the claims. The on state is an example of a "conducting state" in the claims, and the off state is an example of a "non-conducting state" in the claims. The capacitor C is an example of an "energy storage element" in the claims. The positive terminal TP is an example of a "first end" in the claims, and the negative terminal TN is an example of a "second end" in the claims. The insert state is an example of a "first control state" in the claims, and the bypass state is an example of a "second control state" in the claims.

[0026] By connecting a plurality of cells 162 having such a configuration in series, the arm unit 16 outputs a voltage obtained by adding up the cell voltages Vo of the respective cells 162 controlled to the inserted state. Therefore, the arm unit 16 outputs a voltage according to the number of cells 162 controlled to the inserted state by the converter control unit 50. In this way, the arm unit 16 generates a multi-level waveform according to the control from the converter control unit 50.

[0027] Incidentally, in the cell 162, it should be prohibited to set the control signal (gtp, gtn)=(1, 1). This is because when the control signal (gtp, gtn)=(1, 1) is set, both the switching element Q1 and the switching element Q2 are turned on, and both ends of the capacitor C are short-circuited. For this reason, when changing the control signal from (gtp, gtn)=(1, 0) to (gtp, gtn)=(0, 1) or vice versa, the converter control unit 50 controls so as to provide a period during which the control signal is transiently in the state of (gtp, gtn)=(0, 0) for a very short time, that is, a so-called dead time. When the converter control unit 50 stops the operation of the cell 162, it may fix the control signal (gtp, gtn)=(0, 0). In the following explanation, the converter control unit 50 fixing all control signals (gtp, gtn) to (0, 0) and stopping the operation of all cells 162 in the arm unit 16 of the power converter 10 is referred to as "gate block", and the state of the cells 162 in this case is referred to as "gate block state".

[0028] Returning to FIG. 1 , the converter control unit 50 calculates an AC voltage command value including the frequency of the AC system and a DC voltage command value based on the operating state of the power conversion device 1 and detection values ​​(current value, current flow direction (polarity), and voltage value) at each position in the power conversion device 1. Then, the converter control unit 50 obtains a voltage command value for each arm unit 16 including a voltage component represented by the calculated AC voltage command value or DC voltage command value. Based on the obtained voltage command value, the converter control unit 50 generates a control signal for controlling (switching control) the switching element Q in the cell 162 included in each arm unit 16. Then, the converter control unit 50 outputs the generated control signal to the corresponding cell 162. For example, when controlling the arm unit 16-PR, which corresponds to the R phase of the AC system and is connected to the positive pole side of the DC system, the converter control unit 50 calculates an arm voltage command value Varm* to be output from the arm unit 16-PR based on mainly the AC voltage component to be output to the AC terminal CA-R and mainly the DC voltage component to be output between the DC terminal CP-R and the DC terminal CN-R. In the following description, the positive polarity of the arm voltage Varm and the arm voltage command value Varm* is defined as a direction in which the potential of the cell 162-1 side becomes higher as viewed from the cell 162-n side. Then, the converter control unit 50 generates gate signals gtp (gate signals gtp-1-PR to gtp-nPR) and gate signals gtn (gate signals gtn-1-PR to gtn-nPR) for controlling the respective switching elements Q in the respective cells 162 (cells 162-1-PR to 162-nPR) included in the arm unit 16-PR based on the calculated arm voltage command value Varm*. The converter control unit 50 outputs the generated gate signal gtp and gate signal gtn to the corresponding cell 162. The converter control unit 50 controls the other arm units 16 in a similar manner. The converter control unit 50 includes, for example, an insert number calculation unit 52, a sort list calculation unit 54, a cell selection control unit 56, and a gate signal generation unit 58.

[0029] The converter control unit 50 controls the operation of the power converter 10 by, for example, a hardware processor such as a CPU (Central Processing Unit) executing a program (software). The converter control unit 50 may be realized by hardware (including circuitry) such as an LSI (Large Scale Integration), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a GPU (Graphics Processing Unit), or may be realized by cooperation between software and hardware. The converter control unit 50 may be realized by a dedicated LSI. The program may be stored in advance in a storage device (storage device having a non-transient storage medium) such as an HDD (Hard Disk Drive) or a flash memory provided in the converter control unit 50 or the power conversion device 1, or may be stored in a removable storage medium (non-transient storage medium) such as a DVD or a CD-ROM, and the storage medium may be attached to a drive device provided in the converter control unit 50 or the power conversion device 1 to install the program in the HDD or flash memory provided in the converter control unit 50 or the power conversion device 1.

[0030] In the power conversion device 1, a current detector and a voltage detector are provided at desired positions to detect a current value, a polarity of a current, and a voltage value. In the example of FIG. 1, a current detector for detecting a positive arm current Ip flowing from the positive terminal P side to the AC terminal CA side and a current detector for detecting a negative arm current In flowing from the AC terminal CA side to the negative terminal N side are provided in each leg 12. More specifically, in the leg 12-R, a current detector for detecting a positive arm current Ipr flowing from the positive terminal P side to the AC terminal CA-R side is provided between the arm unit 16-PR and the reactor 14-PR, and a current detector for detecting a negative arm current Inr flowing from the AC terminal CA-R side to the negative terminal N side is provided between the arm unit 16-NR and the reactor 14-NR. The other legs 12 are similar. Although not shown in FIG. 2, each cell 162 is also provided with a voltage detector for detecting a capacitor voltage Vc. The R-phase AC current Isr, the S-phase AC current Iss, and the T-phase AC current Ist may be directly detected by providing current detectors at the AC terminals R, S, and T, respectively, or may be indirectly detected by calculating the positive arm current Ip and the negative arm current In detected in each leg 12. For example, the R-phase AC current Isr may be indirectly detected by calculating the difference between the positive arm current Ipr and the negative arm current Inr (i.e., Inr-Ipr). Furthermore, although voltage detectors are not shown in FIG. 1, a case is shown in which the R-phase AC voltage Vsr, the S-phase AC voltage Vss, and the T-phase AC voltage Vst are detected.

[0031] FIG. 3 is a diagram showing an example of the configuration of the converter control unit 50 included in the power conversion device 1. As shown in FIG.

[0032] The insert number calculation unit 52 receives at least the arm voltage command value Varm* to be output by the arm unit 16. The arm voltage command value Varm* is a value (real value) obtained by distributing, for each arm unit 16, a voltage component to be output to the AC system or the DC system, which is obtained as a calculation result of the operating state of the power conversion device 1 and voltage / current control based on each detection value in the power conversion device 1. The insert number calculation unit 52 calculates (calculates), for each arm unit 16, an insert number Ncells representing the number (integer value) of cells 162 to be assigned to an insert state (to be put into an insert state) among the cells 162 included in each arm unit 16, according to the arm voltage command value Varm*. The insert number calculation unit 52 outputs the calculated insert number Ncells to the cell selection control unit 56.

[0033] There are various methods for the insert number calculation unit 52 to calculate (calculate) the insert number Ncells. For example, the insert number calculation unit 52 calculates the insert number Ncells, which represents the number of cells 162 to be put into the insert state, by approximating a value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 162 belonging to the arm unit 16 to an integer. In this case, the converter control unit 50 performs one-pulse control, which controls (puts) the cells 162 belonging to the arm unit 16 into the insert state and the bypass state once each within one period of the AC voltage in the AC system. For example, the insert number calculation unit 52 compares the modulated wave based on the arm voltage command value Varm* with each of the triangular wave carriers, the number of which is the same as the number of cells 162 belonging to the arm unit 16 ("n" in FIG. 1) and has phases shifted from each other, and calculates the number of triangular wave carrier waves for which the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier (becomes larger than the value of the triangular wave carrier) as the insert number Ncells, which represents the number of cells 162 to be put into the insert state. In this case, the converter control unit 50 performs multi-pulse control, controlling the cells 162 belonging to the arm unit 16 multiple times (putting them into the insert state and bypass state) within one period of the AC voltage in the AC system. For example, the insert number calculation unit 52 compares the modulated wave based on the arm voltage command value Varm* with each triangular wave carrier whose level is shifted from each other by the same number as the number of cells 162 belonging to the arm unit 16 ("n" in FIG. 1), and calculates the number of triangular wave carrier waves whose value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier (becomes larger than the value of the triangular wave carrier) as the insert number Ncells representing the number of cells 162 to be inserted. In this case, the converter control unit 50 also performs multi-pulse control. The method by which the insert number calculation unit 52 calculates the insert number Ncells is not limited to the above-mentioned method, and any method may be used as long as it can express the value (real value) distributed to each arm unit 16 as the number (integer value) of the cells 162 to be inserted.

[0034] The insert number calculation unit 52 is an example of a "state number calculation unit" in the claims. The insert number Ncells is an example of a "state number" in the claims.

[0035] The sort list calculation unit 54 calculates (generates) a sort list representing the magnitude relationship of the capacitor voltage Vc of each cell 162 included in the power converter 10 for each arm unit 16. The sort list calculation unit 54 generates the sort list, for example, at a predetermined (constant) calculation period. The sort list is rearranged in descending or ascending order based on the magnitude relationship of the voltage values ​​of the capacitor voltages Vc (capacitor voltages Vc-1 to Vc-n of cells 162-1 to 162-n in FIG. 3) of at least two or more cells 162 belonging to the same arm unit 16. In the following description, it is assumed that the sort list calculation unit 54 generates a sort list in which the voltage values ​​of the capacitor voltages Vc are rearranged in descending order. The sort list calculation unit 54 outputs the generated sort list to the cell selection control unit 56.

[0036] The sort list calculation unit 54 is an example of a "list calculation unit" in the claims. The sort list is an example of "list information" in the claims.

[0037] The cell selection control unit 56 selects a cell 162 whose current control state is to be changed at least every time the insert number Ncells output by the insert number calculation unit 52 changes, that is, every control timing for controlling the cell 162 (putting it into the insert state or the bypass state). More specifically, the cell selection control unit 56 starts selecting a cell 162 when the insert number Ncells changes. Then, the cell selection control unit 56 refers to the polarity of the arm current Iarm (i.e., the positive arm current Ip and the negative arm current In) flowing through the arm unit 16 to be controlled and the sort list of the arm unit 16 to be controlled output by the sort list calculation unit 54, and selects the cell 162 to be changed to the insert state or the cell 162 to be changed to the bypass state.

[0038] At this time, the cell selection control unit 56 measures the duration during which the same control state continues for each cell 162. That is, the cell selection control unit 56 measures the elapsed time from when the control state of the cell 162 was changed last time to when the control state is changed this time. Then, the cell selection control unit 56 excludes the cells 162 whose measured elapsed time has not passed a predetermined minimum pulse time Tmin from the cells 162 whose control state is to be changed this time. In other words, when selecting the cells 162 whose current control state is to be changed, the cell selection control unit 56 selects the cell 162 whose control state is to be changed this time from the cells 162 whose elapsed time is equal to or greater than the minimum pulse time Tmin, or postpones the change of the control state (selection as the cell 162 whose control state is to be changed this time) until the elapsed time becomes equal to or greater than the minimum pulse time Tmin. This is because a time interval equal to or greater than a predetermined threshold time (minimum time) defined by the characteristics of the switching element Q is required to transition the switching element Q of each cell 162 to a stable on state or off state. If the control state of the switching element Q is changed before the minimum pulse time Tmin has elapsed, for example, the state of the carriers in the semiconductor inside the switching element Q may become unstable, or repeated switching may increase switching loss and cause heat generation to concentrate, which may result in failure of the switching element Q. For this reason, the minimum pulse time Tmin is determined based on the characteristics of the switching element Q so as to prevent such a cause from causing a failure. At this time, the minimum pulse time Tmin is set to a time with a margin for the characteristics of the switching element Q. The measurement of the duration in the cell selection control unit 56 may be realized by providing the cell selection control unit 56 with a counter unit (a so-called hardware counter) corresponding to each cell 162, or may be realized by providing a time measurement function (a so-called software counter) corresponding to each cell 162. The counter unit or time measurement function provided in the cell selection control unit 56 may be an up counter or a down counter.For example, if the counter unit or the timekeeping function is a down counter, the cell selection control unit 56 can set the count value of the down counter to a value corresponding to the minimum pulse time Tmin when the control state is changed, and determine that the elapsed time is equal to or longer than the minimum pulse time Tmin when the count value becomes "0". Here, the predetermined threshold time defined by the characteristics of the switching element Q may be different when controlling from the on state to the off state and when controlling from the off state to the on state. In this case, the minimum pulse time Tmin may be the longer of either time, or may be different times corresponding to each control. In the following description, the cell 162 excluded from the target of changing the control state is referred to as the "excluded cell 162e". In the following description, it is assumed that the minimum pulse time Tmin is the same when controlling from the on state to the off state and when controlling from the off state to the on state.

[0039] When the number of inserts Ncells increases, during a period (charging period) in which the polarity of the arm current Iarm is a charging polarity for storing power in the capacitor C of the cell 162 in the inserted state and increasing the charge amount of the entire arm unit 16, the cell selection control unit 56 preferentially selects the cell 162 having the capacitor C with the least amount of stored power from among the cells 162 currently in the bypass state as the cell 162 to be changed to the inserted state. In this case, the cell selection control unit 56 refers to the sort list and selects the cell 162 having the capacitor C with the relatively low voltage value of the capacitor voltage Vc. Here, the cell 162 may be selected from among the cells 162 for which the minimum pulse time Tmin or more has elapsed, or the cell 162 may be selected first regardless of the elapsed time, and the change of the control state (selection as the cell 162 whose control state is to be changed this time) may be suspended until the minimum pulse time Tmin or more has elapsed for that cell 162. The charging polarity is a polarity in which the arm current Iarm flows in the same direction as the positive arm current Ip and the negative arm current In shown in FIG. 1. On the other hand, when the number of inserts Ncells increases, during a period (discharge period) in which the polarity of the arm current Iarm is a discharge polarity for discharging the power stored in the capacitor C of the cell 162 in the insert state to increase the discharge amount of the entire arm unit 16, the cell selection control unit 56 preferentially selects the cell 162 having the capacitor C with the larger amount of stored power from among the cells 162 currently in the bypass state as the cell 162 to be changed to the insert state. In this case, the cell selection control unit 56 refers to the sort list and selects the cell 162 having the capacitor C with a relatively high voltage value of the capacitor voltage Vc. Here, the cell 162 may be selected from among the cells 162 for which the minimum pulse time Tmin or more has elapsed, or the cell 162 may be selected first regardless of the elapsed time, and the change of the control state (selection as the cell 162 whose control state is to be changed this time) may be suspended until the minimum pulse time Tmin or more has elapsed for that cell 162. The discharge polarity is a polarity in which the arm current Iarm flows in a direction opposite to the positive arm current Ip and the negative arm current In shown in FIG. 1.

[0040] When the number of inserts Ncells is decreased, during a period (charging period) in which the polarity of the arm current Iarm is a charging polarity that accumulates power in the capacitor C of the cell 162 in the inserted state to increase the charge amount of the entire arm unit 16, the cell selection control unit 56 preferentially selects the cell 162 having the capacitor C with the most accumulated power from among the cells 162 currently in the inserted state as the cell 162 to be changed to the bypass state. In this case, the cell selection control unit 56 refers to the sort list and selects the cells 162 in order starting from the cell 162 having the capacitor C with a relatively high voltage value of the capacitor voltage Vc. Here, the cell may be selected from the cells 162 for which the minimum pulse time Tmin or more has elapsed, or the cell may be selected first regardless of the elapsed time, and the change of the control state (selection as the cell 162 whose control state is to be changed this time) may be withheld until the minimum pulse time Tmin or more has elapsed for that cell 162. On the other hand, when the number of inserts Ncells is decreased, in a period (discharge period) in which the polarity of the arm current Iarm is a discharge polarity that discharges the power stored in the capacitor C of the cell 162 in the insert state to increase the discharge amount of the entire arm unit 16, the cell selection control unit 56 preferentially selects the cell 162 having the capacitor C with less stored power from among the cells 162 currently in the insert state as the cell 162 to be changed to the bypass state. In this case, the cell selection control unit 56 refers to the sort list and selects the cells 162 in order starting from the cell 162 having the capacitor C with a relatively low voltage value of the capacitor voltage Vc. Here, the cell may be selected from the cells 162 for which the minimum pulse time Tmin or more has elapsed, or the cell may be selected first regardless of the elapsed time, and the change of the control state (selection as the cell 162 whose control state is to be changed this time) may be reserved until the minimum pulse time Tmin or more has elapsed for that cell 162.

[0041] As a result, the cell 162 including the capacitor C whose capacitor voltage Vc has a relatively high voltage value is preferentially charged for a short time and discharged for a long time, so that the capacitor voltage Vc is equalized in each cell 162 included in the arm unit 16. On the other hand, the cell 162 including the capacitor C whose capacitor voltage Vc has a relatively low voltage value is preferentially charged for a long time and discharged for a short time, so that the capacitor voltage Vc is equalized in each cell 162 included in the arm unit 16.

[0042] The cell selection control unit 56 may control the cells 162 in the arm unit 16 to reduce the difference in the charge amount of the capacitor C (to balance the charge amount so that it is relatively uniform). In this case, when the capacitor voltage Vc of the inserted cell 162 exceeds the upper threshold Vc-max during the charging period, the cell selection control unit 56 may control the inserted cell 162 to the bypass state so that the cell 162 is not charged any more (i.e., to prevent overcharging), and instead, may preferentially select other cells 162 of the same number having capacitors C with lower capacitor voltage Vc values ​​from among the bypassed cells 162 and change them to the inserted state. On the other hand, during the discharging period, when the capacitor voltage Vc of the inserted cell 162 exceeds the lower threshold Vc-min, the cell selection control unit 56 may control the inserted cell 162 to the bypass state so that the cell 162 is not discharged any more (i.e., to prevent overdischarging), and instead, may preferentially select other cells 162 of the same number having capacitors C with higher capacitor voltage Vc values ​​from among the bypassed cells 162 and change them to the inserted state. The threshold value Vc-max and the threshold value Vc-min are set, for example, with a value that takes into consideration the allowable fluctuation width of the capacitor C with respect to the rated capacitor voltage command value Vc*. More specifically, the threshold value Vc-max is set, for example, as an upper limit value of the fluctuation width of the capacitor voltage Vc in the normal operation of the power converter 10, and is set to about Vc-max=Vc*×1.1, which is higher than the rated capacitor voltage command value Vc*. The threshold value Vc-min is set, for example, as a lower limit value of the fluctuation width of the capacitor voltage Vc in the normal operation of the power converter 10, and is set to about Vc-min=Vc*×0.9, which is lower than the rated capacitor voltage command value Vc*. The threshold value Vc-max and the threshold value Vc-min may be set based on an average voltage Vc-ave (fluctuation value) of the capacitor voltage Vc in the capacitor C provided in the arm unit 16. The threshold value Vc-max is set to, for example, about Vc-max=Vc-ave×1.1, which is higher than the average voltage Vc-ave, so that the capacitor voltage Vc of the capacitor C does not vary from the average voltage Vc-ave by more than a certain amount.The threshold value Vc-min is set to, for example, about Vc-min=Vc-ave×0.9, which is lower than the average voltage Vc-ave, so that the capacitor voltage Vc of the capacitor C does not vary from the average voltage Vc-ave by more than a certain amount.

[0043] The following methods can be considered as a method in which the cell selection control unit 56 excludes the cells 162 for which the minimum pulse time Tmin or more has not elapsed as excluded cells 162e from the cells 162 for which the control state is to be changed this time. For example, when the cell selection control unit 56 selects the cells 162 to be put into the insert state or bypass state, and determines whether to select the cells 162 in the order of the voltage value of the capacitor voltage Vc included in the sort list from the high one or the low one, the cell selection control unit 56 does not perform a determination on the cells 162 for which the minimum pulse time Tmin or more has not elapsed, that is, skips the determination. In this case, the cell selection control unit 56 repeats the determination of the voltage value of the capacitor voltage Vc included in the sort list until a cell 162 for which the minimum pulse time Tmin or more has elapsed appears. At this time, it is also possible that the number of cells 162 for which the control state should be changed is greater than the number of cells 162 for which the control state is not currently the change target and for which the minimum pulse time Tmin or more has elapsed, that is, the number of cells 162 for which the control state can be changed is insufficient. In this case, even if the cell is an excluded cell 162e, after the elapsed time is equal to or longer than the minimum pulse time Tmin, the excluded cell 162e can be included in the cells 162 whose control state can be changed, so that the cell selection control unit 56 suspends the end of the selection process of the missing cells 162 until the elapsed time is equal to or longer than the minimum pulse time Tmin. In other words, the cell selection control unit 56 suspends the end of the selection process of the missing cells 162 until the shortage of the cells 162 whose control state can be changed is resolved. At this time, the cell selection control unit 56 may store the number of missing cells 162, for example, in a storage unit (not shown), and when the cell selection control unit 56 selects the excluded cell 162e whose minimum pulse time Tmin has elapsed, update the stored number of missing cells, and when the number of missing cells becomes "0", terminate the selection process of the cells 162. The method for preventing the cell selection control unit 56 from selecting the excluded cell 162e is not limited to the above-mentioned method, and may be any method as long as it can determine the cell 162 and the excluded cell 162e.

[0044] The cell selection control unit 56 generates the cell control state CL* for each cell 162. At this time, the cell selection control unit 56 may generate the cell control state CL* at any timing that matches the timing of calculation (generation) of the sort list in the sort list calculation unit 54, the timing of control to balance the charge amount of the capacitor C included in each cell 162 so that it is relatively uniform, and the timing of the operation cycle (so-called operation clock or calculation clock) of the converter control unit 50 and the components included in the converter control unit 50. The cell control state CL* includes information indicating whether the corresponding cell 162 is controlled to at least the insert state or the bypass state. The cell selection control unit 56 outputs the cell control state CL* corresponding to each cell 162 to the gate signal generation unit 58. FIG. 3 shows cell control states CL*-1 to CL*-n corresponding to the cells 162-1 to 162-n, respectively.

[0045] The cell selection control unit 56 is an example of a "unit converter selection unit" in the claims. The excluded cell 162e is an example of an "excluded unit converter" in the claims. The minimum pulse time Tmin is an example of a "minimum time" in the claims. The threshold value Vc-max is an example of a "first threshold value" in the claims, and the threshold value Vc-min is an example of a "second threshold value" in the claims.

[0046] The gate signal generating unit 58 generates control signals (gate signals) to be output to all the cells 162 included in each arm unit 16 according to the respective cell control states CL* output by the cell selection control unit 56. More specifically, the gate signal generating unit 58 generates a gate signal gtp corresponding to the switching element Q1 included in each cell 162 and a gate signal gtn corresponding to the switching element Q2. FIG. 3 shows gate signals gtp-1 to gtp-n and gate signals gtn-1 to gtn-n corresponding to the cells 162-1 to 162-n, respectively. At this time, the gate signal generating unit 58 may generate the gate signal gtn by, for example, logically inverting the gate signal gtp. However, even in this case, as described above, a short dead time is provided to prevent both ends of the capacitor C included in the cell 162 from being short-circuited. The gate signal generating unit 58 outputs each of the generated gate signals to the corresponding cell 162 (more specifically, the switching element Q included in the cell 162).

[0047] 3 shows a configuration in which the gate signal generating unit 58 generates a gate signal corresponding to each cell 162 and outputs it to the corresponding cell 162, but for example, the cell selection control unit 56 may output a cell control state CL* to each cell 162 and generate a gate signal according to the cell control state CL* in each cell 162. In this case, each cell 162 is configured to include a component having a function equivalent to that of the gate signal generating unit 58.

[0048] With this configuration, the converter control unit 50 controls the cells 162 in each arm unit 16 of the power converter 10 to cause the power converter 10 to convert between AC power of the AC system and DC power of the DC system.

[0049] In the conventionally widely known phase shift PWM method, an individual triangular wave carrier and a voltage command value (modulation wave) are assigned to each cell, and a control signal (gate signal) is calculated for each cell. In contrast, in the converter control unit 50, the insert number calculation unit 52 calculates (calculates) the insert number Ncells representing the number of cells 162 to be put into the insert state, based on, for example, a triangular wave carrier not assigned to each cell 162 and a modulation wave based on the arm voltage command value Varm* for each arm unit 16. Then, in the converter control unit 50, the cell selection control unit 56 selects the cell 162 to be changed to the insert state or the bypass state by referring to the polarity of the arm current Iarm and the sort list output by the sort list calculation unit 54, at least when the insert number Ncells is changed. As a result, the gate signal generation unit 58 generates a gate signal for turning the switching element Q of each cell 162 into the on state or the off state. In other words, in the converter control unit 50, there is no triangular wave carrier and a voltage command value (modulation wave) assigned individually to each cell.

[0050] Furthermore, in the conventional phase shift PWM method, when the voltage command value (modulation wave) for each cell passes near the peak or bottom of the triangular wave carrier, the pulse time of the gate signal becomes short, that is, multiple switching control is performed in a short time. For this reason, in the conventional phase shift PWM method, it was necessary to restrict the voltage command value by a limiter or the like so that it does not pass near the peak or bottom of the triangular wave carrier. On the other hand, the switching frequency for each cell is completely consistent with the triangular wave carrier frequency, and it was easy to manage the switching frequency for each cell. In contrast, in the converter control unit 50 of the embodiment, the cell selection control unit 56 excludes the cell 162 (excluded cell 162e) for which the minimum pulse time Tmin has not passed from the cells 162 whose control state is to be changed this time. As a result, in the converter control unit 50, the gate signal generation unit 58 does not generate a gate signal with a pulse width equal to or shorter than the minimum pulse time Tmin, and the switching element Q of each cell 162 can transition to a stable on state or off state. In addition, compared to the phase-shift PWM method, it was difficult to manage the switching frequency for each cell, but by appropriately designing the minimum pulse time Tmin, it is possible to prevent an increase in the switching frequency of a specific cell 162. As a result, the power converter 10 can prevent failure of the switching element Q due to heat concentration or other reasons, and switching instability in the switching element Q that occurs when a gate signal with a pulse width equal to or less than the minimum pulse time Tmin is input. If a gate signal with a pulse width equal to or less than the minimum pulse time Tmin is input to the switching element Q, short-term charge / discharge adjustment is performed on the capacitor C, but this hardly contributes to the equalization of the capacitor voltage Vc, and even if an error occurs due to not outputting a short-term pulse, the effect of voltage distortion is small, so it is considered that it is more advantageous not to input a gate signal with a pulse width equal to or less than the minimum pulse time Tmin. Furthermore, the converter control unit 50 can also control the cell selection control unit 56 to balance the charge amounts of the capacitors C provided in each cell 162 so that they are relatively uniform.

[0051] From these, the power conversion device 1 can simultaneously obtain high capacitor voltage balancing performance in the power converter 10, low loss performance due to a low switching frequency, and high reliability with reduced risk of failure. Furthermore, in the power conversion device 1, by optimizing the minimum pulse time Tmin used when the converter control unit 50 (more specifically, the cell selection control unit 56) selects the cell 162 whose control state is to be changed, it becomes possible to suppress an increase in the switching control frequency of each cell 162 included in the power converter 10 and reduce power loss.

[0052] [First Operation of Power Conversion Device] Next, an example of the operation of the power conversion device 1, that is, the control of the cell 162 in the converter control unit 50 will be described. In the following description, the control of the arm unit 16-PR included in the leg 12-R will be described as a representative of each of the legs 12-R, 12-S, and 12-T included in the power converter 10. In the following description, for ease of explanation, the operation of each of the components included in the converter control unit 50 will be described as being performed by the converter control unit 50 itself.

[0053] FIG. 4 is a timing chart for explaining an example of the operation timing of the first operation in the power conversion device 1. The example of the operation of the power conversion device 1 shown in FIG. 4 is an example of the operation when the arm unit 16-PR (hereinafter simply referred to as "arm unit 16") has six cells 162 (n=6). FIG. 4 shows, on the same time axis, the arm voltage command value Varm*, the arm current Iarm, the arm voltage Varm generated by the arm unit 16 based on the arm voltage command value Varm*, and the gate signals gtp-1 to gtp-6 output by the converter control unit 50 to the switching elements Q1 included in the cells 162-1 to 162-6. Furthermore, FIG. 4 shows an example of a sort list calculated (generated) by the converter control unit 50 (more specifically, the sort list calculation unit 54). In the first operation shown in FIG. 4, it is assumed that the sort list is generated (updated) for each period of the arm voltage command value Varm*.

[0054] The arm voltage command value Varm* includes the frequency of the AC system and a DC component. As described above, the converter control unit 50 (more specifically, the insert number calculation unit 52) ​​calculates (calculates) the insert number Ncells expressed by a stepped pseudo-sine wave based on the arm voltage command value Varm*. In FIG. 4, the insert number Ncells is an integer value with a minimum value of "0" and a maximum value of "n (here, "6")". The insert number Ncells is calculated by approximating a value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 162 belonging to the arm unit 16 to an integer. That is, the operation timing of the power conversion device 1 shown in FIG. 4 is the operation timing when the converter control unit 50 performs one-pulse control. The insert number Ncells represents something equivalent to the arm voltage Varm shown in FIG. 4.

[0055] The converter control unit 50 (more specifically, the cell selection control unit 56 and the gate signal generation unit 58) controls the gate signal gtp output to each cell 162 so that the number of cells 162 in the insert state belonging to the arm unit 16 coincides with the number (integer value) of cells 162 to be put into the insert state represented by the insert number Ncells at each timing when the insert number Ncells changes. Each gate signal gtp turns the switching element Q1 on when it is "1 ("High" level)" and turns the switching element Q1 off when it is "0 ("Low" level). Here, the gate signal gtn output to the switching element Q2 included in the cell 162 can be generated by logically inverting the gate signal gtp as described above. For this reason, the gate signal gtn is omitted from FIG. 4. Therefore, in FIG. 4, the cell 162 is in the insert state when the gate signal gtp is "1" and in the bypass state when the gate signal gtp is "0". Furthermore, for ease of explanation, dead time is omitted in Fig. 4. When the capacitor voltages Vc of the cells 162 are uniformly controlled, the arm voltage Varm is approximately equal to the number (integer value) of the cells 162 to be inserted, which is represented by the number of inserts Ncells, multiplied by the capacitor voltage Vc.

[0056] The arm current Iarm contains the frequency of the AC system and a DC component. In the arm unit 16, when the arm current Iarm is positive (Iarm>0), the capacitor C of the cell 162 in the inserted state is charged, and the capacitor voltage Vc rises during this charging period. In the arm unit 16, when the arm current Iarm is negative (Iarm<0), the capacitor C of the cell 162 in the inserted state is discharged, and the capacitor voltage Vc drops during this discharging period. In the arm unit 16, regardless of the polarity of the arm current Iarm, the capacitor C of the cell 162 in the bypass state is neither charged nor discharged, and the current capacitor voltage Vc is maintained.

[0057] At time t0 shown in FIG. 4, the number of inserts Ncells is "3". Since the polarity of the arm current Iarm at this time is negative, the converter control unit 50 determines that the polarity is discharging. For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C with the large amount of stored power as the cell 162 to be inserted. More specifically, the converter control unit 50 selects the cell 162-1, the cell 162-2, and the cell 162-3, which have the three highest capacitor voltages Vc (Vc-1, Vc-2, and Vc-3) in the sort list. For this reason, at time t0 shown in FIG. 4, the converter control unit 50 sets each of the gate signals gtp-1, gtp-2, and gtp-3 to "1" in order to insert the selected three cells 162.

[0058] After that, when the number of inserts Ncells changes (increases) to "4" at time t1, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has the capacitor C with the second largest amount of stored power as the cell 162 to be inserted. Here, since the converter control unit 50 has already selected three cells 162 with the third highest capacitor voltages Vc in the sort list, it selects the cell 162-4 with the next highest capacitor voltage Vc (i.e., the fourth highest Vc-4). Then, at time t1, the converter control unit 50 sets the gate signal gtp-4 to "1" in order to further insert the selected cell 162-4.

[0059] After that, when the number of inserts Ncells changes (increases) to "5" at time t2, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive polarity (charging polarity). For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with less stored power as the cell 162 to be inserted. Here, the converter control unit 50 selects the cell 162-6 that is the first cell in the sort list with the lowest capacitor voltage Vc (i.e., Vc-6). Then, at time t2, the converter control unit 50 sets the gate signal gtp-6 to "1" to further insert the selected cell 162-6.

[0060] After that, when the number of inserts Ncells changes (increases) to "6" at time t3, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive polarity (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has the capacitor C with the second lowest stored power as the cell 162 to be inserted. Here, since the converter control unit 50 has already selected one cell 162 with the first lowest capacitor voltage Vc in the sort list, it selects the cell 162-5 with the next lowest capacitor voltage Vc (i.e., the second lowest Vc-5). Then, at time t3, the converter control unit 50 sets the gate signal gtp-5 to "1" in order to further insert the selected cell 162-5.

[0061] After that, when the number of inserts Ncells changes (decreases) to "5" at time t4, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive polarity (charging polarity). For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a large amount of stored power as the cell 162 to be placed in the bypass state. Here, the converter control unit 50 selects the cell 162-1, which is the cell with the highest capacitor voltage Vc (i.e., Vc-1) in the sort list. Then, at time t4, the converter control unit 50 sets the gate signal gtp-1 to "0" to place the selected cell 162-1 in the bypass state.

[0062] Then, at time t5, when the number of inserts Ncells changes (decreases) to "4", the converter control unit 50 selects the cell 162-2, which has the second highest capacitor voltage Vc (i.e., Vc-2) in the sort list, as at time t4, and sets the gate signal gtp-2 to "0" to put the selected cell 162-2 into a bypass state.

[0063] Thereafter, at time t6, when the number of inserts Ncells changes (decreases) to "3", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharging polarity). For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with less stored power as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects the cell 162-6 that is the first cell in the sort list with the lowest capacitor voltage Vc (i.e., Vc-6). Then, at time t6, the converter control unit 50 sets the gate signal gtp-6 to "0" to put the selected cell 162-6 into the bypass state.

[0064] Thereafter, from time t7 to time t9, each time the number of inserts Ncells changes (decreases) sequentially from "2", "1", to "0", the converter control unit 50 sequentially selects the cells 162 having the second, third, and fourth lowest capacitor voltages Vc in the sort list (i.e., Vc-5, Vc-4, and Vc-3) in order from the lowest capacitor voltage Vc in the sort list, and sets the gate signal gtp to "0" to put the selected cells 162 into a bypass state, as in the case of time t4. More specifically, the converter control unit 50 selects the cell 162-5 at time t7 and sets the gate signal gtp-5 to "0", selects the cell 162-4 at time t8 and sets the gate signal gtp-4 to "0", and selects the cell 162-3 at time t9 and sets the gate signal gtp-3 to "0".

[0065] Then, at time t10, the sort list is updated.

[0066] After that, when the number of inserts Ncells changes (increases) to "1" at time t11, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 162 to be put into the insert state. Here, the converter control unit 50 selects the cell 162-3, which is the first cell in the sort list with a high capacitor voltage Vc (i.e., Vc-3). However, the cell 162-3 has just been put into the bypass state at time t9, and a time period equal to or greater than the minimum pulse time Tmin has not yet elapsed. Therefore, the converter control unit 50 does not immediately put the cell 162-3 into the insert state at time t11 as the excluded cell 162e, that is, does not immediately set the gate signal gtp-3 to "1", and postpones the change of the control state until a time period equal to or greater than the minimum pulse time Tmin has elapsed in the cell 162-3. Then, after a time equal to or greater than the minimum pulse time Tmin has elapsed in cell 162-3, the converter control unit 50 removes cell 162-3 from the excluded cell 162e, i.e., includes it in the cells 162 whose control state can be changed, and sets the gate signal gtp-3 to "1" to place the selected cell 162-3 in the insert state.

[0067] Thereafter, from time t12 to time t13, each time the number of inserts Ncells changes (increases) sequentially to "2" and "3", the converter control unit 50 sequentially selects the cells 162 having the second and third highest capacitor voltages Vc (i.e., Vc-2 and Vc-1) in the sort list, similar to time t11, and sets the gate signal gtp to "1" to put the selected cells 162 into an insert state. More specifically, the converter control unit 50 selects the cell 162-2 at time t12 and sets the gate signal gtp-2 to "1", and selects the cell 162-1 at time t13 and sets the gate signal gtp-1 to "1".

[0068] In this way, the converter control unit 50 judges whether the polarity is a discharge polarity or a charge polarity based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (increases or decreases), selects the cell 162 whose control state is to be changed to the insert state or the bypass state by referring to the sort list, and controls the gate signal gtp of the selected cell 162. At this time, the converter control unit 50 does not change the control state of the cell 162 whose control state has not been changed previously as an excluded cell 162e, and changes the control state of the cell 162 when the elapsed time becomes equal to or greater than the minimum pulse time Tmin. As a result, in the first operation, the cell 162 whose control state is to be changed is always the cell 162 whose control state has been changed as long as the minimum pulse time Tmin. In the first operation of the power conversion device 1 shown in FIG. 4, a case is shown in which the cell 162-3 becomes the excluded cell 162e whose control state has not been changed yet as long as the minimum pulse time Tmin at time t11, but the operation of changing the control state in the converter control unit 50 is similar for the other cells 162. In this way, the converter control unit 50 does not change the control state of the excluded cell 162e whose elapsed time is less than the minimum pulse time Tmin, so that the power converter 10 can reduce the risk of failure caused by changing the control state of the cell 162 less than the minimum pulse time Tmin. Moreover, in order to not change (suspend) the control state of the excluded cell 162e in the first operation, it is sufficient to execute, for example, counter processing and change time limit logic for each gate signal gtp, and this can be realized with an algorithm that is easy to implement. In other words, it is possible to realize a converter control unit 50 configured to suspend the change of the control state at low cost without adopting a complex or large-scale configuration.

[0069] [Second Operation of Power Conversion Device] Next, another operation of the power converter 1 (another example of the control of the cells 162 in the converter control unit 50) will be described. In the first operation described above, if the converter control unit 50 does not change the control state until the elapsed time of the excluded cell 162e becomes equal to or longer than the minimum pulse time Tmin, the number of cells 162 in the inserted state in the power converter 10 will not match the number of inserts Ncells, and the arm voltage Varm will deviate (including an error) from an ideal stepped waveform according to the arm voltage command value Varm*. In this case, in the power converter 10, the voltage distortion due to the error in the arm voltage Varm may increase harmonics, which may cause a deterioration in the power quality of the AC system to which the power converter 10 is connected. In contrast, in the second operation, as described below, the number of cells 162 in the inserted state can be made to match the number of inserts Ncells, and the arm voltage Varm can be made to match the ideal stepped waveform according to the arm voltage command value Varm*.

[0070] FIG. 5 is a timing chart for explaining an example of the operation timing of the second operation in the power conversion device 1. The second operation shown in FIG. 5 is also an operation in the case where the arm unit 16 includes six cells 162 (n=6) like the first operation shown in FIG. 4. The second operation shown in FIG. 5 is also an operation timing in the case where a sort list is generated (updated) for each period of the arm voltage command value Varm* and the converter control unit 50 performs one-pulse control. The second operation shown in FIG. 5 is an operation in which the control state of an alternative cell 162 is selected and changed instead of changing the control state of an excluded cell 162e whose elapsed time has not passed the minimum pulse time Tmin or more. The operation from time t0 to time t10 shown in FIG. 5 is the same as the first operation shown in FIG. 4, and therefore will not be described again.

[0071] In the second operation shown in FIG. 5, when the number of inserts Ncells changes (increases) to "1" at time t11, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity) as in the first operation shown in FIG. 4, and selects the cell 162-3 having the capacitor C that is currently in the bypass state and has a large amount of stored power (i.e., the capacitor voltage Vc is Vc-3, which is the first one from the highest). However, the cell 162-3 is the excluded cell 162e because it was just put into the bypass state at time t9 as in the first operation shown in FIG. 4. Therefore, in the second operation shown in FIG. 5, the converter control unit 50 does not immediately put the cell 162-3, which is the excluded cell 162e, into the insert state (i.e., the gate signal gtp-3 is "1") at time t11. In other words, the converter control unit 50 skips the selection of the cell 162-3, which is the excluded cell 162e, at time t11. Then, the converter control unit 50 selects the cell 162 having the capacitor C with the next highest stored power as the cell 162 to be inserted as a replacement cell 162 for the skipped cell 162-3. Here, the converter control unit 50 selects the cell 162-2 having the second highest capacitor voltage Vc (i.e., the second highest Vc-2) in the sort list. Then, at time t11, the converter control unit 50 sets the gate signal gtp-2 to "1" to insert the selected cell 162-2.

[0072] After that, when the number of inserts Ncells changes (increases) to "2" at time t12, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharging polarity). For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 162 to be put into the insert state. Here, the converter control unit 50 refers to the sort list and selects the cell 162-3, which is the first cell (i.e., Vc-3) with the highest capacitor voltage Vc, whose selection was skipped at time t11, that is, whose insertion state was not entered, and for which a time equal to or longer than the minimum pulse time Tmin has elapsed since then, that is, whose control state can be changed and which can be included in the cells 162. Then, the converter control unit 50 sets the gate signal gtp-3 to "1" at time t12 in order to further put the selected cell 162-3 into the insert state.

[0073] Then, at time t13, when the number of inserts Ncells changes (increases) to "3", the converter control unit 50 selects the cell 162-1 having the third highest capacitor voltage Vc in the sort list (i.e., Vc-1), as in the first operation shown in FIG. 4, and sets the gate signal gtp-1 to "1" to place the selected cell 162-1 in the insert state.

[0074] In this manner, in the second operation, the converter control unit 50 determines whether the polarity is a discharge polarity or a charge polarity based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (increases or decreases), as in the first operation shown in FIG. 4, selects a cell 162 whose control state is to be changed to an insert state or a bypass state by referring to the sort list, and controls the gate signal gtp of the selected cell 162. At this time, in the second operation, the converter control unit 50 does not change the control state of each cell 162 whose control state has not been changed the minimum pulse time Tmin or more since the last time the control state was changed, as an excluded cell 162e, and selects another cell 162 whose elapsed time is the minimum pulse time Tmin or more as a substitute cell 162, and changes the control state of that cell 162. In the second operation of the power conversion device 1 shown in FIG. 5, a case is shown in which the cell 162-3 becomes the excluded cell 162e whose minimum pulse time Tmin has not passed at time t11, but the converter control unit 50 performs the same operation of changing the control state for the other cells 162. In this way, in the second operation, the converter control unit 50 does not select the excluded cell 162e as the cell 162 whose control state is to be changed (skips the selection), and selects an alternative cell 162 to change the control state. As a result, in the second operation, the cell 162 whose control state is to be changed is always the cell 162 whose minimum pulse time Tmin or more has elapsed. As a result, in the power converter 10, it is possible to reduce a risk of failure caused by changing the control state of the cell 162 before the minimum pulse time Tmin. Moreover, in the second operation, the control state of any of the cells 162 is changed at each timing when the number of inserts Ncells changes (increases or decreases), so that the number of cells 162 that are put into the insert state matches the number of inserts Ncells, and the arm voltage Varm matches an ideal stepped waveform according to the arm voltage command value Varm*. In other words, the arm voltage Varm does not include an error with respect to an ideal stepped waveform according to the arm voltage command value Varm*.As a result, the power converter 10 can reduce harmonics that increase due to voltage distortion caused by an error in the arm voltage Varm, and can improve the power quality of the AC system connected thereto.

[0075] [Third Operation of Power Conversion Device] The converter control unit 50 can also perform multi-pulse control. Next, as yet another operation of the power conversion device 1 (another example of the control of the cells 162 in the converter control unit 50), an operation in the case where the converter control unit 50 performs multi-pulse control will be described. FIG. 6 is a timing chart for explaining an example of the operation timing of a third operation in the power conversion device 1. The third operation shown in FIG. 6 is an operation in the case where the arm unit 16 has six cells 162 (n=6), similar to the first operation shown in FIG. 4 and the second operation shown in FIG. 5. The number of inserts Ncells is calculated as the number of triangular wave carrier waves in which the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier, for example, by comparing a modulated wave based on the arm voltage command value Varm* with each triangular wave carrier that is the same in number as the number of cells 162 belonging to the arm unit 16 (here, "6"). In the third operation, the converter control unit 50 performs multi-pulse control to control the cell 162 belonging to the arm unit 16 multiple times within one period of the arm voltage command value Varm*, so the operation timing of the power conversion device 1 shown in FIG. 6 is shown by enlarging a portion of the range within one period of the arm voltage command value Varm*.

[0076] The third operation shown in Fig. 6 is an example of a case where, for example, in a discharge polarity (discharge period) where the polarity of the arm current Iarm is negative (Iarm<0), the number of cells 162 in the inserted state represented by the number of inserts Ncells alternates between "1" and "2". In other words, the third operation shown in Fig. 6 is an example of a case where, in the past, even if the minimum pulse time Tmin has not elapsed, the control state of the same cell 162 is changed multiple times in a very short period of time. Even in this case, the converter control unit 50 controls so as not to change the control state of the excluded cell 162e for which the minimum pulse time Tmin has not elapsed.

[0077] At time t0 shown in FIG. 6, the number of inserts Ncells is "2". Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C with the most stored power as the cell 162 to be inserted. More specifically, the converter control unit 50 selects the cell 162-1 and the cell 162-2, which have the two highest capacitor voltages Vc (Vc-1 and Vc-2) in the sort list. Therefore, at time t0 shown in FIG. 6, the converter control unit 50 sets each of the gate signals gtp-1 and gtp-2 to "1" in order to insert the two selected cells 162.

[0078] Thereafter, at time t1, when the number of inserts Ncells changes (decreases) to "1", the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with less stored power as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects the cell 162-2, which has the lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from the cell 162-1 and cell 162-2 that are in the insert state. Then, at time t1, the converter control unit 50 sets the gate signal gtp-2 to "0" to put the selected cell 162-2 into the bypass state.

[0079] After that, at time t2, when the number of inserts Ncells changes (increases) to "2" again, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has the capacitor C with the second largest stored power as the cell 162 to be inserted. Here, since the converter control unit 50 has already selected the cell 162-1 with the highest capacitor voltage Vc (Vc-1) in the sort list, the converter control unit 50 selects the cell 162-2 with the next highest capacitor voltage Vc (i.e., the second highest Vc-2). However, the cell 162-2 is an excluded cell 162e that was just put into the bypass state at time t1 and has not yet passed a time equal to or greater than the minimum pulse time Tmin. For this reason, the converter control unit 50 treats cell 162-2 as an excluded cell 162e and does not immediately place cell 162-2 in the inserted state at time t2, that is, does not immediately set gate signal gtp-2 to "1" at time t2, but postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has elapsed in cell 162-2 and cell 162-2 can be included in the cells 162 whose control state can be changed.

[0080] After that, when the number of inserts Ncells changes (decreases) to "1" again at time t3, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with less stored power as the cell 162 to be put into the bypass state. However, since the cell 162-2 is not put into the insert state at time t2, the only cell 162 in the insert state is the cell 162-1. Therefore, the converter control unit 50 maintains the current control state. As a result, the converter control unit 50 does not change the control state of the cell 162 corresponding to the change in the number of inserts Ncells at time t2 and time t3. In other words, the converter control unit 50 ignores the change in the number of inserts Ncells at time t2 and time t3.

[0081] After that, at time t4, when the number of inserts Ncells changes (increases) to "2" again, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has the capacitor C with the second largest stored power as the cell 162 to be put into the insert state. Here, the converter control unit 50 selects the cell 162-2 with the second highest capacitor voltage Vc (i.e., the second highest Vc-2) in the sort list. Then, since a time equal to or greater than the minimum pulse time Tmin has elapsed for the selected cell 162-2, the converter control unit 50 includes the selected cell 162-2 in the cells 162 whose control state can be changed, and sets the gate signal gtp-2 to "1" at time t4 to put the selected cell 162-2 into the insert state.

[0082] After that, at time t5, when the number of inserts Ncells changes (decreases) to "1" again, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with less stored power as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects the cell 162-2, which has the lowest capacitor voltage Vc (i.e., Vc-2) in the sort list, from among the two cells 162 currently in the insert state. However, the cell 162-2 is an excluded cell 162e that was just put into the insert state at time t4 and has not yet passed a time equal to or greater than the minimum pulse time Tmin. For this reason, the converter control unit 50 again sets the cell 162-2 as the excluded cell 162e, and does not immediately put the cell 162-2 into the bypass state at time t5, that is, does not immediately set the gate signal gtp-2 to "0", and postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has passed in the cell 162-2. Then, after a time equal to or greater than the minimum pulse time Tmin has elapsed in the selected cell 162-2, the converter control unit 50 removes the cell 162-2 from the excluded cell 162e, sets the gate signal gtp-2 to “0” so that the cell 162-2 is in the bypass state at time t6 as a cell 162 whose control state can be changed.

[0083] In this way, in the third operation (multiple pulse control), as in the first operation (one pulse control) shown in FIG. 4, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm at each timing when the insert number Ncells changes (increases or decreases), selects the cell 162 whose control state is to be changed to the insert state or bypass state by referring to the sort list, and controls the gate signal gtp of the selected cell 162. At this time, in the third operation, the converter control unit 50 does not change the control state of the cell 162 whose control state has not been changed previously for each cell 162 for which the minimum pulse time Tmin or more has not elapsed, as an excluded cell 162e, and changes the control state of the cell 162 when the elapsed time becomes the minimum pulse time Tmin or more. In the third operation, if the insert number Ncells changes while the change of the control state of the excluded cell 162e is reserved until the minimum pulse time Tmin has elapsed, the converter control unit 50 may not change the control state of the cell 162 corresponding to the change of the insert number Ncells (ignore the change of the insert number Ncells). In the third operation of the power converter 1 shown in FIG. 6, the cell 162-2 is set as the excluded cell 162e at time t2 and time t3, and the change in the number of inserts Ncells is ignored, and the control state of the cell 162-2, which is the excluded cell 162e, is not changed at time t4. However, the control state change operation in the converter control unit 50 is similar for the other cells 162. In this way, in the third operation, the converter control unit 50 does not change or ignores the control state of the excluded cell 162e whose elapsed time is less than the minimum pulse time Tmin, so that in the power converter 10, all gate signals gtp are control signals with a pulse width equal to or greater than the minimum pulse time Tmin. This makes it possible to reduce the risk of failure caused by changing the control state of the cell 162 before the minimum pulse time Tmin in the power converter 10.Moreover, in the third operation, as in the first operation, the converter control unit 50 configured to suspend or ignore changes to the control state of the excluded cell 162e can be realized with an algorithm that is easy to implement, and can be realized at low cost without adopting a complex or large-scale configuration.

[0084] [Fourth operation of the power conversion device] Next, another operation of the power converter 1 (another example of the multi-pulse control of the cell 162 in the converter control unit 50) will be described. In the third operation described above, if the converter control unit 50 does not change the control state or ignores it until the elapsed time of the excluded cell 162e becomes equal to or longer than the minimum pulse time Tmin, the number of cells 162 in the inserted state in the power converter 10 does not match the number of inserts Ncells, so that the arm voltage Varm deviates (contains an error) from the ideal stepped waveform according to the arm voltage command value Varm* in the power converter 10, as in the first operation. For example, if the converter control unit 50 ignores the change in the control state corresponding to the change in the number of inserts Ncells, the arm voltage Varm corresponding to the gate signal gtp for a very short period of time such as between time t2 and time t3 shown in FIG. 6 is not output. In this case, in the power converter 10, as in the first operation shown in FIG. 4, the voltage distortion due to the error in the arm voltage Varm increases harmonics, which may cause a decrease in the power quality of the AC system to which the power converter 10 is connected. On the other hand, in the fourth operation, as described below, the number of cells 162 in the inserted state can be made to match the number of inserts Ncells, so that the arm voltage Varm matches an ideal stepped waveform in accordance with the arm voltage command value Varm*.

[0085] FIG. 7 is a timing chart for explaining an example of the operation timing of the fourth operation in the power conversion device 1. The fourth operation shown in FIG. 7 is also an operation when the arm unit 16 has six cells 162 (n=6) like the third operation shown in FIG. 6. The fourth operation shown in FIG. 7 is also an operation timing when the converter control unit 50 performs multi-pulse control. The fourth operation shown in FIG. 7 is also an example of the case where the number of cells 162 in the insert state represented by the insert number Ncells repeats "1" and "2" in the discharge polarity (discharge period) where the polarity of the arm current Iarm is negative (Iarm<0). The fourth operation shown in FIG. 7 is an operation of selecting an alternative cell 162 and changing the control state instead of changing the control state of the excluded cell 162e whose elapsed time has not passed the minimum pulse time Tmin or more. The operation from time t0 to time t1 shown in FIG. 7 is the same as the third operation shown in FIG. 6, so a repeated description will be omitted.

[0086] In the fourth operation shown in FIG. 7, when the number of inserts Ncells changes (increases) to "2" again at time t2, the converter control unit 50, similar to the third operation shown in FIG. 6, refers to the sort list and selects the cell 162-2 having the capacitor C that is currently in the bypass state and has the second largest stored power (i.e., Vc-2). However, the cell 162-2 is the excluded cell 162e because it was just put into the bypass state at time t1, similar to the third operation shown in FIG. 6. Therefore, in the fourth operation shown in FIG. 7, the converter control unit 50 does not immediately put the cell 162-2, which is the excluded cell 162e, into the insert state (i.e., the gate signal gtp-2 is "1") at time t2. In other words, the converter control unit 50 skips the selection of the cell 162-2, which is the excluded cell 162e, at time t2. Then, the converter control unit 50 selects the cell 162 having the capacitor C with the next highest stored power as the cell 162 to be inserted as a replacement cell 162 for the skipped cell 162-2. Here, the converter control unit 50 selects the cell 162-3 having the third highest capacitor voltage Vc (i.e., the third highest Vc-3) in the sort list. Then, at time t2, the converter control unit 50 sets the gate signal gtp-3 to "1" to insert the selected cell 162-3.

[0087] After that, at time t3, when the number of inserts Ncells changes (decreases) to "1" again, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a small amount of stored power as the cell 162 to be put into the bypass state. Here, since the cell 162-3 is put into the insert state at time t2, the cells 162 in the insert state are the cell 162-1 and the cell 162-3. However, since the cell 162-3 was just put into the insert state at time t2, the converter control unit 50 skips the selection of the cell 162-3 as the excluded cell 162e, and selects the cell 162-1, which is the first cell (i.e., Vc-1) in the order of the minimum pulse time Tmin or more having passed and the capacitor voltage Vc being the highest. Then, the converter control unit 50 sets the gate signal gtp-1 to "0" at time t3 to put the selected cell 162-1 into the bypass state.

[0088] After that, when the number of inserts Ncells changes (increases) to "2" again at time t4, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 162 to be inserted. Here, since the cell 162-1 is in the bypass state at time t3, the cells 162 in the bypass state are the cell 162-1 and the cell 162-2. However, since the cell 162-1 has just been in the bypass state at time t3, the converter control unit 50 skips the selection of the cell 162-1 as an excluded cell 162e, and selects the cell 162-2, which has the second highest capacitor voltage Vc (i.e., Vc-2) and can be included in the cells 162 whose control state can be changed because a time equal to or longer than the minimum pulse time Tmin has elapsed. Then, the converter control unit 50 sets the gate signal gtp-2 to "1" at time t4 to insert the selected cell 162-2.

[0089] After that, at time t5, when the number of inserts Ncells changes (decreases) to "1" again, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a small amount of stored power as the cell 162 to be put into the bypass state. Here, since the cell 162-2 is put into the insert state at time t4, the cells 162 in the insert state are the cell 162-2 and the cell 162-3. Since the minimum pulse time Tmin or more has elapsed, the cell 162 can be included in the cells 162 whose control state can be changed, and the cell 162-3, which is the first cell in the insert state with the lowest capacitor voltage Vc (i.e., Vc-3), is selected. Then, at time t5, the converter control unit 50 sets the gate signal gtp-3 to "0" in order to put the selected cell 162-3 into the bypass state.

[0090] 6, in the fourth operation, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm each time the number of inserts Ncells changes (increases or decreases), refers to the sort list, selects a cell 162 whose control state is to be changed to the insert state or bypass state, and controls the gate signal gtp of the selected cell 162. At this time, in the fourth operation, the converter control unit 50 does not change the control state of each cell 162 for which the elapsed time since the previous control state change has not been equal to or greater than the minimum pulse time Tmin as an excluded cell 162e, and selects another cell 162 for which the elapsed time is equal to or greater than the minimum pulse time Tmin as an alternative cell 162, and changes the control state of that cell 162. In the fourth operation of the power converter 1 shown in FIG. 7, the cell 162-2 at time t2, the cell 162-3 at time t3, the cell 162-1 at time t4, and the cell 162-2 at time t5 are each excluded cells 162e that have not passed the minimum pulse time Tmin, but the operation of changing the control state in the converter control unit 50 is similar for the other cells 162. In this way, in the fourth operation, the converter control unit 50 does not select the excluded cell 162e as the cell 162 whose control state is to be changed (skips the selection), and selects an alternative cell 162 to change the control state, so that in the power converter 10, all gate signals gtp always become control signals with a pulse width equal to or greater than the minimum pulse time Tmin. This makes it possible to reduce the risk of failure caused by changing the control state of the cell 162 before the minimum pulse time Tmin in the power converter 10. Moreover, in the fourth operation, the control state of any of the cells 162 is changed at each timing when the number of inserts Ncells changes (increases or decreases), so that the number of cells 162 in the insert state matches the number of inserts Ncells, and the arm voltage Varm matches an ideal stepped waveform according to the arm voltage command value Varm*. In other words, the arm voltage Varm does not include an error with respect to the ideal stepped waveform according to the arm voltage command value Varm*.As a result, the power converter 10 can reduce harmonics that increase due to voltage distortion caused by an error in the arm voltage Varm, and can improve the power quality of the AC system connected thereto.

[0091] [Fifth operation of the power conversion device] In the second and fourth operations described above, if the converter control unit 50 does not select (skips selection of) the excluded cell 162e whose elapsed time is less than the minimum pulse time Tmin as the cell 162 whose control state is to be changed, there may be a shortage of cells 162 whose elapsed time is equal to or greater than the minimum pulse time Tmin. Here, as yet another operation of the power conversion device 1, an operation for dealing with a shortage of selectable cells 162 due to the converter control unit 50 skipping the selection of a cell 162 in the multi-pulse control (for example, the fourth operation) will be described.

[0092] FIG. 8 is a timing chart for explaining an example of the operation timing of the fifth operation in the power conversion device 1. The fifth operation shown in FIG. 8 is an operation when the arm unit 16 has six cells 162 (n=6), like the third operation shown in FIG. 6 and the fourth operation shown in FIG. 7. The fifth operation shown in FIG. 8 is also an operation timing when the converter control unit 50 performs multi-pulse control. The fifth operation shown in FIG. 8 is an example of a case where the number of cells 162 in the inserted state represented by the number of inserts Ncells repeats "0" and "1" in a discharge polarity (discharge period) where the polarity of the arm current Iarm is negative (Iarm<0). The fifth operation shown in FIG. 8 is an operation when the number of cells 162 whose control state can be changed is insufficient due to the selection of an alternative cell 162 instead of an excluded cell 162e whose elapsed time has not passed the minimum pulse time Tmin or more.

[0093] At time t0 shown in FIG. 8, the number of inserts Ncells is "1". Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 having a capacitor C with a large amount of stored power as the cell 162 to be inserted. More specifically, the converter control unit 50 selects the cell 162-1 having the highest capacitor voltage Vc (Vc-1) in the sort list. Therefore, at time t0 shown in FIG. 8, the converter control unit 50 sets the gate signal gtp-1 to "1" to place the selected cell 162-1 in the inserted state.

[0094] Thereafter, at time t1, when the number of inserts Ncells changes (decreases) to "0", the converter control unit 50 refers to the sort list and selects a cell 162 that is currently in the insert state and has a capacitor C with less stored power as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects cell 162-1 because cell 162-1 is the only cell 162 that is in the insert state. Then, at time t1, the converter control unit 50 sets the gate signal gtp-1 to "0" to put the selected cell 162-1 into the bypass state.

[0095] After that, at time t2, when the number of inserts Ncells changes (increases) to "1" again, the converter control unit 50 refers to the sort list and selects the cell 162-1, which is currently in the bypass state and has the highest capacitor voltage Vc (Vc-1) stored power. However, the cell 162-1 is an excluded cell 162e that has just been put into the bypass state at time t1 and has not yet had a minimum pulse time Tmin or more elapsed. For this reason, in the fifth operation shown in FIG. 8, as in the fourth operation shown in FIG. 7, the converter control unit 50 does not immediately put the cell 162-1 into the insert state at time t2 by setting the cell 162-1 as the excluded cell 162e, that is, does not immediately set the gate signal gtp-1 to "1", and skips the selection of the cell 162-1, which is the excluded cell 162e, at time t2. Then, the converter control unit 50 selects the cell 162-2, which has the second highest capacitor voltage Vc (i.e., the second highest VC-2) in the sort list, as a replacement cell 162 for the skipped cell 162-1. Then, at time t2, the converter control unit 50 sets the gate signal gtp-2 to "1" to put the selected cell 162-2 into the insert state.

[0096] After that, when the number of inserts Ncells changes to "0" (decreases) again at time t3, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a small amount of stored power as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects the cell 162-2 because the only cell 162 that is in the insert state is the cell 162-2. However, the cell 162-2 is an excluded cell 162e that has just been put into the insert state at time t2 and has not yet passed a time equal to or greater than the minimum pulse time Tmin. Therefore, in the fifth operation, the number of cells 162 whose control state can be changed at time t3 is insufficient. In this case, the converter control unit 50 does not immediately put the cell 162-2, which is the excluded cell 162e, into the bypass state (i.e., the gate signal gtp-2 is "0") at time t3, but postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has passed in the cell 162-2. Therefore, the converter control unit 50 maintains the current control state. At this time, the converter control unit 50 stores the number of missing cells 162 (here, "1") in, for example, a storage unit not shown. Then, after a time equal to or longer than the minimum pulse time Tmin has elapsed in the cell 162-2, the converter control unit 50 releases the cell 162-2 from the excluded cell 162e, sets the gate signal gtp-2 to "0" so that the cell 162-2 is in a bypass state at time t4 as a cell 162 whose control state is changeable. At this time, since the number of missing cells 162 has decreased by one, the converter control unit 50 stores the number in, for example, a storage unit not shown and updates the number of cells 162 (here, updates from "1" to "0").

[0097] In this manner, in the fifth operation, similarly to the fourth operation shown in FIG. 7, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (increases or decreases), selects a cell 162 whose control state is to be changed to the insert state or bypass state by referring to the sort list, and controls the gate signal gtp of the selected cell 162. At this time, in the fifth operation, the converter control unit 50 skips the selection of a cell 162 whose control state has not been changed previously as an excluded cell 162e. In the fifth operation, if the number of cells 162 whose control state can be changed is insufficient, the converter control unit 50 may suspend the change of the control state until an elapse of a time equal to or greater than the minimum pulse time Tmin has elapsed for the excluded cell 162e and the excluded cell 162 becomes a cell 162 whose control state can be changed. 8 shows a case where the cell 162-1 becomes the excluded cell 162e that has not yet passed the minimum pulse time Tmin at time t2, but the control state changing operation in the converter control unit 50 is similar for the other cells 162. In this way, in the fifth operation, the converter control unit 50 skips selecting the excluded cell 162e as the cell 162 whose control state is to be changed, and selects an alternative cell 162, or postpones the change of the control state until a cell 162 whose control state can be changed appears, so that in the power converter 10, all gate signals gtp always become control signals with a pulse width equal to or greater than the minimum pulse time Tmin. In the fifth operation, when the converter control unit 50 reserves the change of the control state until the excluded cell 162e becomes a cell 162 whose control state can be changed, in the power converter 10, an error is included in the arm voltage Varm due to the number of cells 162 in the inserted state not matching the insertion number Ncells, but since the control state is changed when the minimum pulse time Tmin has elapsed in the excluded cell 162e, the time during which the error is included in the arm voltage Varm can be minimized. As a result, in the power converter 10, harmonics that increase due to voltage distortion caused by an error in the arm voltage Varm can be reduced, and the power quality of the AC system connected to the power converter 10 can be improved.In the power converter 10, the number of missing cells 162 is stored until the shortage is resolved, thereby preventing a situation in which a shortage in the number of cells 162 whose control state can be changed leads to an increase in error in the arm voltage Varm and makes it impossible to perform normal power conversion.

[0098] [Sixth Operation of Power Conversion Device] The converter control unit 50 may further perform switching control to balance the charge amounts of the capacitors C in the respective cells 162 included in the arm unit 16 so that they are relatively uniform (to reduce the difference in the charge amounts). Here, as yet another operation of the power conversion device 1, an operation in which the converter control unit 50 balances the charge amounts of the capacitors C included in the respective cells 162 in multi-pulse control will be described.

[0099] FIG. 9 is a timing chart for explaining an example of the operation timing of the sixth operation in the power conversion device 1. The sixth operation shown in FIG. 9 is an operation when the arm unit 16 has six cells 162 (n=6), like the third operation shown in FIG. 6, the fourth operation shown in FIG. 7, and the fifth operation shown in FIG. 8. The sixth operation shown in FIG. 9 is also an operation timing when the converter control unit 50 performs multi-pulse control. The sixth operation shown in FIG. 9 is an operation for controlling and balancing the charge amount (more specifically, the capacitor voltage Vc) of the capacitor C of the cell 162 in the inserted state so that it is uniform (hereinafter, referred to as "balance control"). The sixth operation shown in FIG. 9 is an example of a case where balance control is performed during a period in which the number of cells 162 in the inserted state represented by the number of inserts Ncells remains unchanged at "2" in a discharge polarity (discharge period) in which the polarity of the arm current Iarm is negative (Iarm<0).

[0100] At time t0 shown in FIG. 9, the number of inserts Ncells is "2". Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C with the most stored power as the cell 162 to be inserted. In FIG. 9, the converter control unit 50 selects the cell 162-1 with the first highest capacitor voltage Vc (Vc-1) and the cell 162-3 with the third highest capacitor voltage Vc (Vc-3) in the sort list. Therefore, at time t0 shown in FIG. 9, the converter control unit 50 sets each of the gate signals gtp-1 and gtp-3 to "1" in order to insert the two selected cells 162.

[0101] After that, at time t1, if the number of inserts Ncells does not change from "2" but the capacitor voltage Vc (i.e., Vc-3) of the cell 162-3 becomes lower than the threshold value Vc-min, the converter control unit 50 puts the cell 162-3 into a bypass state. This causes the cell 162-3 to stop discharging. Then, at time t1, the converter control unit 50 refers to the sort list and selects the cell 162-2, which has the highest capacitor voltage Vc (Vc-2), from among the cells 162-2, 162-4, 162-5, and 162-6 that are currently in the bypass state, as a replacement for the cell 162-3 that has been put into the bypass state. Then, at time t1, the converter control unit 50 sets the gate signal gtp-2 to "1" in order to put the selected cell 162-2 into the insert state.

[0102] After that, when the number of inserts Ncells changes (decreases) to "1" at time t2, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with less stored power as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects the cell 162-2, which has the lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from among the cell 162-1 and cell 162-2 that are in the insert state. However, the cell 162-2 is an excluded cell 162e that was just put into the insert state at time t1 and has not yet passed a time equal to or greater than the minimum pulse time Tmin. For this reason, the converter control unit 50 does not immediately put the cell 162-2 into the bypass state at time t2 by setting the cell 162-2 as the excluded cell 162e, that is, does not immediately set the gate signal gtp-2 to "0", and postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has passed in the cell 162-2. Then, after a time equal to or greater than the minimum pulse time Tmin has elapsed in the selected cell 162-2, the converter control unit 50 removes the cell 162-2 from the excluded cell 162e, sets the gate signal gtp-2 to "0" so that the cell 162-2 is in the bypass state at time t3 as a cell 162 whose control state can be changed.

[0103] In this manner, in the sixth operation, when the capacitor voltage Vc of any of the cells 162 becomes higher than the threshold Vc-max or lower than the threshold Vc-min, the converter control unit 50 puts the cell 162 into the bypass state. As a result, the cell 162 put into the bypass state stops charging or discharging. Then, the converter control unit 50 refers to the sort list, selects a cell 162 to replace the cell 162 put into the bypass state from among the cells 162 currently in the bypass state, and puts the selected cell into the insert state. As a result, in the power converter 10, the capacitor C included in the cell 162 is not overcharged or overdischarged, and the charge amount of the capacitor C becomes relatively uniform. Also in the sixth operation, as in the third operation shown in FIG. 6, the converter control unit 50 does not change the control state of the cell 162 for which the elapsed time since the last change of the control state has not passed the minimum pulse time Tmin or more as an excluded cell 162e, and changes the control state of the cell 162 when the elapsed time becomes the minimum pulse time Tmin or more. In the sixth operation of the power conversion device 1 shown in FIG. 9, a case where the capacitor voltage Vc of the cell 162-3 becomes lower than the threshold value Vc-min at time t1 is shown, but the operation of changing the control state in the balance control of the converter control unit 50 is similar for the other cells 162. In the sixth operation of the power conversion device 1 shown in FIG. 9, a case where the cell 162-2 is selected as a replacement for the cell 162-3 at time t1 is shown, but the selection as a replacement is similar for the other cells 162. Here, in the sixth operation, it is possible that there is no cell 162 that can be selected as a replacement. In this case, the converter control unit 50 may suspend the change of the control state or cancel the selection of the replacement cell 162 until a selectable cell 162 appears. In the sixth operation of the power conversion device 1 shown in FIG. 9, an example of the balance control when the capacitor voltage Vc becomes lower than the threshold value Vc-min, that is, when overdischarge is prevented, is shown, but the balance control when overcharging is prevented may be equivalent to the balance control for preventing overdischarge described above.In the sixth operation, an example of the case where the converter control unit 50 performs balance control in multi-pulse control has been shown, but the converter control unit 50 can also perform balance control in one-pulse control. In this case, the operation and processing of the converter control unit 50 may be equivalent to the operation and processing described above. In the sixth operation, even when the number of inserts Ncells does not change, the converter control unit 50 changes the control state of the cells 162, so that it is considered that a very short-term fluctuation occurs in the arm voltage Varm. However, it is considered that there is a greater advantage in that it is possible to prevent overcharging and over-discharging of the capacitor C and to equalize the amount of charge of the capacitor C.

[0104] [Seventh operation of the power conversion device] The converter control unit 50 may also perform balance control in an operation of selecting an alternative cell 162 and changing the control state of the excluded cell 162e for which the elapsed time has not yet reached the minimum pulse time Tmin, instead of changing the control state of the excluded cell 162e. Here, a further operation of the power conversion device 1 (another example of balance control of the charge amount of the capacitor C included in the cell 162 in the converter control unit 50) will be described.

[0105] FIG. 10 is a timing chart for explaining an example of the operation timing of the seventh operation in the power conversion device 1. The seventh operation shown in FIG. 10 is also an operation in the case where balance control is performed when the arm unit 16 has six cells 162 (n=6), similarly to the sixth operation shown in FIG. 9. The seventh operation shown in FIG. 10 is also an operation in the case where balance control is performed when the converter control unit 50 is performing multi-pulse control. The seventh operation shown in FIG. 10 is an example of a case where balance control is performed during a period in which the number of cells 162 in the insert state represented by the insert number Ncells remains unchanged at "2" in a discharge polarity (discharge period) in which the polarity of the arm current Iarm is negative (Iarm<0). The seventh operation shown in FIG. 10 is an operation in which the control state of an excluded cell 162e for which the elapsed time has not passed the minimum pulse time Tmin is not changed, but instead an alternative cell 162 is selected and the control state is changed. The operation from time t0 to time t1 shown in FIG. 10 is similar to the sixth operation shown in FIG. 9, and therefore will not be described again.

[0106] In the seventh operation shown in FIG. 10, when the number of inserts Ncells changes (decreases) to "1" at time t2, the converter control unit 50, similar to the sixth operation shown in FIG. 9, refers to the sort list and selects the cell 162-2, which is currently in the insert state and has a capacitor C with less stored power, as the cell 162 to be put into the bypass state. However, similar to the sixth operation shown in FIG. 9, the cell 162-2 has just been put into the insert state at time t1, and is the excluded cell 162e. Therefore, in the seventh operation shown in FIG. 10, the converter control unit 50 does not immediately put the cell 162-2, which is the excluded cell 162e, into the bypass state (the gate signal gtp-2 is "0") at time t2. In other words, the converter control unit 50 skips the selection of the cell 162-2, which is the excluded cell 162e, at time t2. Then, the converter control unit 50 selects the cell 162 having the capacitor C with the next least stored power as the cell 162 to be placed in the bypass state as a replacement cell 162 for the skipped cell 162-2. Here, since the cells 162 placed in the insert state are the cells 162-1 and 162-2, the converter control unit 50 selects the cell 162-1 other than the cell 162-2 as the excluded cell 162e, that is, the cell 162-1 with the highest capacitor voltage Vc (i.e., Vc-1) in the sort list. Then, at time t2, the converter control unit 50 sets the gate signal gtp-1 to "0" to place the selected cell 162-1 in the bypass state.

[0107] In this way, in the seventh operation, when the capacitor voltage Vc of any cell 162 becomes higher than the threshold Vc-max or lower than the threshold Vc-min, the converter control unit 50 puts the cell 162 into the bypass state, similar to the sixth operation shown in FIG. 9. As a result, the cell 162 put into the bypass state stops charging or discharging. Then, similar to the sixth operation shown in FIG. 9, the converter control unit 50 refers to the sort list, selects a cell 162 to replace the cell 162 put into the bypass state from among the cells 162 currently in the bypass state, and puts the selected cell into the insert state. As a result, in the power converter 10, the capacitor C included in the cell 162 is not overcharged or overdischarged, and the charge amount of the capacitor C becomes relatively uniform. In the seventh operation, as in the fourth operation shown in FIG. 7, the converter control unit 50 does not change the control state of each cell 162 for which the elapsed time from the last time when the control state was changed is less than the minimum pulse time Tmin as an excluded cell 162e, selects another cell 162 for which the elapsed time is equal to or more than the minimum pulse time Tmin as a substitute cell 162, and changes the control state of the cell 162. In the seventh operation of the power conversion device 1 shown in FIG. 10, a case where the capacitor voltage Vc of the cell 162-3 becomes lower than the threshold value Vc-min at time t1 is shown, but the operation of changing the control state in the balance control of the converter control unit 50 is similar for the other cells 162. In the seventh operation of the power conversion device 1 shown in FIG. 10, a case where the cell 162-2 is selected as a substitute for the cell 162-3 at time t1 is shown, but the selection as a substitute is similar for the other cells 162. Here, in the seventh operation, as in the sixth operation, it is possible that there is no cell 162 selectable as an alternative, but in this case, the converter control unit 50 may suspend the change of the control state until a selectable cell 162 appears, or may cancel the selection of an alternative cell 162. The seventh operation of the power conversion device 1 shown in Fig. 10 also shows an example of balance control when the capacitor voltage Vc becomes lower than the threshold value Vc-min, that is, when over-discharge is prevented, but the balance control when overcharging is prevented may also be equivalent to the balance control for preventing over-discharge described above.In the seventh operation, an example of the converter control unit 50 performing balance control in multi-pulse control has also been shown, but the converter control unit 50 can also perform balance control in one-pulse control. In this case, the operation and processing of the converter control unit 50 may be equivalent to the operation and processing described above. In the seventh operation, as in the sixth operation, the converter control unit 50 changes the control state of the cells 162 even when the number of inserts Ncells does not change, so it is considered that the arm voltage Varm may fluctuate for a very short period of time. However, it is considered that there is a greater advantage in that it is possible to prevent overcharging and over-discharging of the capacitor C and to equalize the amount of charge of the capacitor C.

[0108] With such a configuration and operation, in the power conversion device 1, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm for each arm unit 16 included in the power converter 10 at least at each timing when the number of inserted cells Ncells of the cells 162 changes (increases or decreases). Then, in the power conversion device 1, the converter control unit 50 refers to the sort list calculated (generated) for each arm unit 16, selects the cell 162 whose control state is to be changed to the inserted state or bypass state, and changes the control state of the selected cell 162. At this time, in the power conversion device 1, for each selected cell 162, the converter control unit 50 does not change the control state of the cell 162 for which the elapsed time since the last change of the control state has not passed the minimum pulse time Tmin or more, as an excluded cell 162e, and changes the control state of the cell 162 when the elapsed time becomes the minimum pulse time Tmin or more. Alternatively, in the power conversion device 1, the converter control unit 50 does not change the control state of the excluded cell 162e for which the elapsed time is less than the minimum pulse time Tmin for each selected cell 162, but instead selects an alternative cell 162 and changes the control state. As a result, in the power conversion device 1, all the cells 162 for which the converter control unit 50 changes the control state are the cells 162 for which the minimum pulse time Tmin or more has elapsed. As a result, in the power conversion device 1, it is possible to reduce the risk of a failure that occurs in the power converter 10 due to the control state of the cell 162 being changed before the minimum pulse time Tmin. As a result, in the power conversion device 1, it is possible to realize a highly reliable power conversion device.

[0109] As described above, in the power conversion device 1 of the first embodiment, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm for each arm unit 16 included in the power converter 10 at least at each timing when the number of inserts Ncells of the cells 162 changes (increases or decreases). Then, in the power conversion device 1 of the first embodiment, the converter control unit 50 refers to the sort list calculated (generated) for each arm unit 16, selects the cell 162 whose control state is to be changed to the insert state or bypass state, and changes the control state of the selected cell 162. At this time, in the power conversion device 1 of the first embodiment, the converter control unit 50 does not change the control state of the cell 162 selected by the converter control unit 50 as an excluded cell 162e for which the elapsed time from the last time when the control state was changed has not elapsed by more than the minimum pulse time Tmin, and changes the control state of the cell 162 when the elapsed time becomes more than the minimum pulse time Tmin. Alternatively, in the power conversion device 1 of the first embodiment, the converter control unit 50 does not change the control state of the excluded cell 162e for which the elapsed time is less than the minimum pulse time Tmin for each selected cell 162, but instead selects an alternative cell 162 and changes the control state. As a result, in the power conversion device 1 of the first embodiment, all the cells 162 for which the converter control unit 50 changes the control state are the cells 162 for which the minimum pulse time Tmin or more has elapsed. As a result, in the power conversion device 1 of the first embodiment, it is possible to reduce the risk of a failure caused by changing the control state of the cell 162 in less than the minimum pulse time Tmin in the power converter 10. As a result, in the power conversion device 1 of the first embodiment, it is possible to realize a highly reliable power conversion device.

[0110] In the power conversion device 1 of the first embodiment described above, the power converter 10 is, for example, provided at an interconnection point between an AC system and a DC system, and is a double star-connected MMC that mutually converts AC power supplied by the AC system and DC power supplied by the DC system in response to control from the converter control unit 50. However, the power converter 10 may be a power converter with a different configuration.

[0111] Second Embodiment [Power conversion device configuration] The second embodiment will be described below. FIG. 11 is a diagram showing an example of the configuration of a power conversion device according to the second embodiment. FIG. 11 shows an example of a power conversion device 2 that is connected to an AC system and adjusts the reactive power of the AC system. The power conversion device 2 can adjust the active power of the AC system when the cell 262 described later is configured to include an energy storage element such as a storage battery. The AC system may be, for example, an AC power source or an AC load, as in the first embodiment. The power conversion device 2 includes a power converter 20 and a converter control unit 50a. In FIG. 11, components having the same functions as those of the power conversion device 1 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0112] The power converter 20 is a single delta-connected modular multilevel converter (MMC) that converts AC power in response to control from a converter control unit 50a. The power converter 20 includes a plurality of legs 22 between lines of an AC system. The number of legs 22 included in the power converter 20 corresponds to the number of lines of the AC power supplied by the AC system. FIG. 11 shows a case where the AC system supplies three-phase AC power, namely, a first phase (R phase), a second phase (S phase), and a third phase (T phase). For this reason, FIG. 11 shows a configuration of the power converter 20 including three legs 22, namely, a leg 22-RS, a leg 22-ST, and a leg 22-TR. The legs 22-RS, the leg 22-ST, and the leg 22-TR each have the same configuration.

[0113] In each leg 22, the AC terminal CA is connected to a terminal of any phase of the AC system, and the AC terminal CB is connected to a terminal of any other phase in the AC system that is different from the phase connected to the AC terminal CA. More specifically, in the leg 22-RS corresponding to the R-phase and S-phase interphase, the AC terminal CA-R is connected to the R-phase AC terminal R of the AC system, and the AC terminal CB-S is connected to the S-phase AC terminal S of the AC system. In the leg 22-ST corresponding to the S-phase and T-phase interphase, the AC terminal CA-S is connected to the AC terminal S of the AC system, and the AC terminal CB-T is connected to the T-phase AC terminal T of the AC system. In the leg 22-TR corresponding to the T-phase and R-phase interphase, the AC terminal CA-T is connected to the AC terminal T of the AC system, and the AC terminal CB-R is connected to the AC terminal R of the AC system. FIG. 11 shows a case where the AC terminal CA of each leg 22 is connected to a terminal of a corresponding phase of the AC system via a transformer TR.

[0114] Each leg 22 includes, for example, a reactor 14 and an arm unit 26. Each arm unit 26 includes, for example, n cells 262 (cells 262-1 to 262-n) connected in series (n is a natural number). In FIG. 11, in order to distinguish which phase or interphase of the AC system each component included in the leg 22 corresponds to, a "- (hyphen)" and the letter "R" representing the R phase, the letter "S" representing the S phase, the letter "T" representing the T phase, the letter "RS" representing the interphase between the R phase and the S phase, the letter "ST" representing the interphase between the S phase and the T phase, or the letter "TR" representing the interphase between the T phase and the R phase are added after each reference symbol. In the following description, when it is not necessary to distinguish which phase or interphase of the AC system each component corresponds to, the hyphen and the identifying letter following the hyphen added to the reference symbol of each component are omitted.

[0115] In each leg 22, the reactor 14 is connected in series to the AC terminal CA side of the arm unit 26. In each leg 22, one end of the reactor 14 that is not connected to the arm unit 26 serves as the AC terminal CA. In each leg 22, the terminal of the arm unit 26 opposite the reactor 14 serves as the AC terminal CB of the leg 22. In other words, in each leg 22, the reactor 14 and the cells 262-1 to 262-n are connected in series in this order from the AC terminal CA side toward the AC terminal CB side, and are connected to the AC terminal CA.

[0116] The leg 22 is an example of a "phase unit" in the claims. The arm unit 26 (which may include the reactor 14) is an example of an "arm unit" in the claims. The cell 262 is an example of a "unit converter" in the claims. The reactor 14 is an example of an "inductance element" in the claims.

[0117] 11 shows a case where the reactor 14 is disposed on the AC terminal CA side of the arm unit 26 in each leg 22, but the reactor 14 may be disposed on the side opposite to the AC terminal CA side of the arm unit 26 (i.e., on the AC terminal CB side) or at any position within the arm unit 26 (i.e., a position between any two cells 262 connected in series in the arm unit 26). The reactor 14 may be replaced with a transformer with a special winding structure having a leakage reactance sufficient to replace the function of the reactor. In this case, the reactor 14 may be integrated with the transformer TR.

[0118] Each arm unit 26 generates a stepped sine wave (multi-level waveform) AC voltage representing the AC waveform to be supplied between the corresponding phases of the AC system in response to control from the converter control unit 50a for each of the series-connected cells 262.

[0119] Here, an example of the configuration of the cell 262 included in the arm unit 26 will be described. The cell 262 is, for example, a full bridge circuit. FIG. 12 is a diagram showing an example of the configuration of the cell 262 in the leg 22 included in the power converter 20. The cell 262 includes four switching elements Q (switching elements Q1 to Q4), four diodes D (diodes D1 to D4), and a capacitor C. The switching elements Q are, for example, insulated gate bipolar transistors (IGBTs) like the switching elements Q included in the cell 162 of the first embodiment. Therefore, the switching elements Q are not limited to IGBTs, and may be any elements as long as they are self-extinguishing semiconductor switching elements capable of realizing a converter or an inverter.

[0120] In the cell 262, the switching element Q1 and the switching element Q2 are connected in series, and the switching element Q3 and the switching element Q4 are connected in series. In the cell 262, the series circuit of the switching element Q1 and the switching element Q2, the series circuit of the switching element Q3 and the switching element Q4, and the capacitor C are connected in parallel. In the cell 262, the switching elements Q and the corresponding diodes D are connected in parallel. In the cell 262, the connection point between the emitter of the switching element Q1 and the collector of the switching element Q2 is the positive terminal TP(+) connected to the AC terminal CA side in the leg 22, and the connection point between the emitter of the switching element Q3 and the collector of the switching element Q4 is the negative terminal TN(-) connected to the AC terminal CB side in the leg 22.

[0121] A control signal from the converter control unit 50a is input to each gate of the switching element Q1 to switching element Q4 included in the cell 262 (a control voltage is applied or a control current is supplied). A gate signal gta is input to the gate of the switching element Q1 as a control signal from the converter control unit 50a, a gate signal gtb is input to the gate of the switching element Q2 as a control signal from the converter control unit 50a, a gate signal gtc is input to the gate of the switching element Q3 as a control signal from the converter control unit 50a, and a gate signal gtd is input to the gate of the switching element Q4 as a control signal from the converter control unit 50a. As a result, each of the switching elements Q1 to Q4 is switched to either an on state or an off state by the converter control unit 50a. In the following explanation, when a control signal (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) of “1 (High level)” is input, each switching element Q is turned on, and when a control signal (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) of “0 (Low level)” is input, each switching element Q is turned off.

[0122] The capacitor C is charged or discharged according to the state of each switching element Q. In the cell 262, the terminal voltage (capacitor voltage Vc) of the capacitor C is generated as the terminal voltage (cell voltage Vo) between the positive terminal TP and the negative terminal TN of the cell 262. More specifically, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(1, 0, 0, 1), for example, a current flows in the order of the positive terminal TP, the switching element Q1, the capacitor C, the switching element Q4, and the negative terminal TN, and the cell voltage Vo of the cell 262 coincides with the capacitor voltage Vc. In other words, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(1, 0, 0, 1), the capacitor C is inserted between the positive terminal TP and the negative terminal TN of the cell 262, and the capacitor voltage Vc is output as the cell voltage Vo. In the following description, the converter control unit 50a setting the control signals (gta, gtb, gtc, gtd)=(1, 0, 0, 1) is referred to as "positive voltage insertion", and the state of the cell 262 in this case is referred to as "positive voltage insertion state". On the other hand, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(0, 1, 1, 0), for example, a current flows in the order of the positive terminal TP, the switching element Q2, the capacitor C, the switching element Q3, and the negative terminal TN, and the cell voltage Vo of the cell 262 coincides with the inversion of the capacitor voltage Vc. In other words, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(0, 1, 1, 0), the capacitor C is inserted in the reverse direction between the positive terminal TP and the negative terminal TN of the cell 262, and the negative capacitor voltage Vc is output as the cell voltage Vo. In the following description, the converter control unit 50a setting the control signals (gta, gtb, gtc, gtd)=(0, 1, 1, 0) is referred to as "negative voltage insert", and the state of the cell 262 in this case is referred to as "negative voltage insert state".Furthermore, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(1, 0, 1, 0) or (0, 1, 0, 1), for example, a current flows in the order of the positive terminal TP, diode D1, switching element Q3, and negative terminal TN, or in the order of the positive terminal TP, switching element Q2, diode D4, and negative terminal TN, and the cell voltage Vo of the cell 262 becomes 0 [V]. In other words, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(1, 0, 1, 0) or (0, 1, 0, 1), the positive terminal TP and the negative terminal TN of the cell 262 are short-circuited, and a current flows without passing through the capacitor C, and the cell voltage Vo of the cell 262 becomes 0 [V]. In the following description, the converter control unit 50a setting the control signals (gta, gtb, gtc, gtd)=(1, 0, 1, 0) or (0, 1, 0, 1) is referred to as "bypass", and the state of the cell 262 in this case is referred to as the "bypass state".

[0123] The cell 262 is not limited to the configuration shown in FIG. 12, and may have any configuration as long as it achieves the same function as the cell 262.

[0124] The switching element Q1 and the diode D1 are an example of the "switching element" and the "first switching element" in the claims, the switching element Q2 and the diode D2 are an example of the "switching element" and the "second switching element" in the claims, the switching element Q3 and the diode D3 are an example of the "switching element" and the "third switching element" in the claims, and the switching element Q4 and the diode D4 are an example of the "switching element" and the "fourth switching element" in the claims. The parallel circuit of the switching element Q1 and the diode D1 and the parallel circuit of the switching element Q2 and the diode D2 are an example of the "first series circuit" in the claims, and the parallel circuit of the switching element Q3 and the diode D3 and the parallel circuit of the switching element Q4 and the diode D4 are an example of the "second series circuit" in the claims. The on state is an example of the "conductive state" in the claims, and the off state is an example of the "non-conductive state" in the claims. The capacitor C is an example of an "energy storage element" in the claims. The positive terminal TP is an example of a "first end" in the claims, and the negative terminal TN is an example of a "second end" in the claims. The positive voltage insert state is an example of a "first first control state" in the claims, the negative voltage insert state is an example of a "second first control state" in the claims, and the bypass state is an example of a "second control state" in the claims.

[0125] By connecting a plurality of cells 262 having such a configuration in series, the arm unit 26 outputs a voltage obtained by adding up the cell voltages Vo of the cells 262 controlled to the insert state (positive voltage insert state or negative voltage insert state). Therefore, the arm unit 26 outputs a voltage according to the number of cells 262 controlled to the insert state (positive voltage insert state or negative voltage insert state) by the converter control unit 50a. In this way, the arm unit 26 generates a multilevel waveform according to the control from the converter control unit 50a. The cell 262 may be provided in each arm unit 16 provided in the power converter 10 of the first embodiment, instead of the cell 162 of the first embodiment.

[0126] Incidentally, in the cell 262, it should be prohibited to set the control signals (gta, gtb)=(1, 1) or (gtc, gtd)=(1, 1). This is because, when the control signals (gta, gtb)=(1, 1) are set, both the switching elements Q1 and Q2 are turned on, and when the control signals (gtc, gtd)=(1, 1) are set, both the switching elements Q3 and Q4 are turned on, and in either case, both ends of the capacitor C are short-circuited. For this reason, when switching (changing) the control signals (gta, gtb, gtc, gtd) between (1, 0, 0, 1), (0, 1, 1, 0), (1, 0, 1, 0), and (0, 1, 0, 1), the converter control unit 50a performs control so as to provide a period (so-called dead time) during which the control signals (gta, gtb) = (0, 0) or the control signals (gtc, gtd) = (0, 0) are transiently in a very short time. When the converter control unit 50a stops the operation of the cell 262, the control signals (gta, gtb, gtc, gtd) may be fixed to (0, 0, 0, 0). In the following explanation, the converter control unit 50a fixing all control signals (gta, gtb, gtc, gtd) to (0, 0, 0, 0) to stop the operation of all cells 262 in the arm unit 26 of the power converter 20 is referred to as "gate block", and the state of the cells 262 in this case is referred to as the "gate block state".

[0127] Returning to FIG. 11, the converter control unit 50a calculates an AC voltage command value including the frequency of the AC system based on the operating state of the power conversion device 2 and detection values ​​(current value, current flow direction (polarity), and voltage value) at each position in the power conversion device 2, similar to the converter control unit 50 included in the power conversion device 1 of the first embodiment. Then, the converter control unit 50a calculates a voltage command value for each arm unit 26 including a voltage component represented by the calculated AC voltage command value. The converter control unit 50a generates a control signal for controlling the switching of the switching element Q in the cell 262 included in each arm unit 26 based on the calculated voltage command value. Then, the converter control unit 50a outputs the generated control signal to the corresponding cell 262. For example, when controlling the arm unit 26-RS, which is the arm unit 26 between the R phase and the S phase of the AC system, the converter control unit 50a calculates an arm voltage command value Varm* corresponding to an arm voltage Varm-R to be output between the AC terminal CA-R and the AC terminal CB-S. In the following description, the positive polarity of the arm voltage Varm and the arm voltage command value Varm* is defined as a direction in which the potential of the cell 262-1 side becomes higher as viewed from the cell 262-n side. Then, based on the calculated arm voltage command value Varm*, the converter control unit 50a generates gate signals gta (gate signals gta-1-RS to gta-n-RS), gate signals gtb (gate signals gtb-1-RS to gtb-n-RS), gate signals gtc (gate signals gtc-1-RS to gtc-n-RS), and gate signals gtd (gate signals gtd-1-RS to gtd-n-RS) for controlling the respective switching elements Q in the respective cells 262 (cells 262-1-RS to 262-n-RS) included in the arm unit 26-RS. The converter control unit 50a outputs the generated gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd to the corresponding cell 262. The converter control unit 50a operates in a similar manner when controlling other arm units 16. The converter control unit 50a includes, for example, an insert number calculation unit 52a, a sort list calculation unit 54a, a cell selection control unit 56a, and a gate signal generation unit 58a.

[0128] The converter control unit 50a controls the operation of the power converter 20 by, for example, a hardware processor such as a CPU executing a program (software). The converter control unit 50a may be realized by hardware (including circuitry) such as an LSI, ASIC, FPGA, or GPU, or may be realized by cooperation between software and hardware. The converter control unit 50a may be realized by a dedicated LSI. The program may be stored in advance in a storage device (storage device having a non-transient storage medium) such as an HDD or flash memory provided in the converter control unit 50a or the power conversion device 2, or may be stored in a removable storage medium (non-transient storage medium) such as a DVD or CD-ROM, and the storage medium may be attached to a drive device provided in the converter control unit 50a or the power conversion device 2 to install the program in the HDD or flash memory provided in the converter control unit 50a or the power conversion device 2.

[0129] In the power conversion device 2, similarly to the power conversion device 1 of the first embodiment, a current detector and a voltage detector are provided at desired positions to detect a current value, a polarity of a current, and a voltage value. The example of FIG. 11 shows a case where a current detector for detecting an arm current I flowing from the AC terminal CA side to the AC terminal CB side is provided in each leg 22. More specifically, a current detector for detecting an arm current Irs flowing from the AC terminal CA-R side to the AC terminal CB-S side is provided between the reactor 14-RS and the arm unit 26-RS in the leg 22-RS. The other legs 22 are similar. Although not shown in FIG. 12, each cell 262 is also provided with a voltage detector for detecting a capacitor voltage Vc. The R-phase AC current Ir, the S-phase AC current Is, and the T-phase AC current It may be directly detected by providing a current detector at the AC terminal R, the AC terminal S, and the AC terminal T, or may be indirectly detected by calculating the arm current I detected in each leg 22. For example, the R-phase AC current Ir may be indirectly detected by calculating the difference between the R-phase and S-phase arm current Irs and the T-phase and R-phase arm current Itr (i.e., Irs-Itr). Furthermore, although voltage detectors are not shown in Fig. 11, a case is shown in which the R-phase AC voltage Vsr, the S-phase AC voltage Vss, and the T-phase AC voltage Vst are detected.

[0130] The arm unit 16 included in the power conversion device 1 of the first embodiment is replaced by the arm unit 26 in the power conversion device 2, so that the converter control unit 50a outputs control signals (gate signals) corresponding to the respective cells 262 included in the arm unit 26. However, the configuration of the converter control unit 50a is similar to the configuration of the converter control unit 50 included in the power conversion device 1 of the first embodiment shown in Fig. 3. Therefore, an example of the configuration of the converter control unit 50a included in the power conversion device 2 is not illustrated, and different operations between the respective components included in the converter control unit 50 of the first embodiment and the respective components included in the converter control unit 50a will be described below.

[0131] The insert number calculation unit 52a performs the same process as the insert number calculation unit 52 of the first embodiment. The insert number calculation unit 52a calculates the number of inserts Ncells for each arm unit 26 based on the arm voltage command value Varm*. However, unlike the insert number calculation unit 52, the insert number calculation unit 52a calculates the number of inserts Ncells including information indicating whether the insert state is a positive voltage insert state or a negative voltage insert state for each arm unit 26. More specifically, for example, the insert number calculation unit 52a calculates the number (integer value, absolute value) of cells 162 to be assigned to the insert state (to be put into the insert state) among the cells 262 included in the arm unit 26 and the signed number of inserts Ncells indicating whether the insert state is a positive voltage insert state or a negative voltage insert state (polarity, sign). Like the insert number calculation unit 52, the insert number calculation unit 52a also performs one-pulse control or multiple-pulse control by calculating the number of inserts Ncells. The insert number calculation unit 52a outputs the calculated insert number Ncells to the cell selection control unit 56a. The insert number calculation unit 52a is an example of the "number of states calculation unit" in the claims.

[0132] The sort list calculation unit 54a performs the same processing as the sort list calculation unit 54 of the first embodiment. The sort list calculation unit 54a calculates (generates) a sort list indicating the magnitude relationship of the capacitor voltages Vc of the respective cells 262 included in the power converter 20 for each arm unit 26, and outputs the generated sort list to the cell selection control unit 56a. The sort list calculation unit 54a is an example of a "list calculation unit" in the claims.

[0133] The cell selection control unit 56a performs the same process as the cell selection control unit 56 of the first embodiment. The cell selection control unit 56a refers to the sort list and selects a cell 262 for which the current cell control state CL* is to be changed at least every time the insert number Ncells output by the insert number calculation unit 52a changes, that is, every control timing for controlling the cell 262 (putting it into the positive voltage insert state, the negative voltage insert state, and the bypass state). At this time, the cell selection control unit 56a also determines whether or not a time equal to or greater than the minimum pulse time Tmin has elapsed for each cell 262, and sets a cell 262 for which a time equal to or greater than the minimum pulse time Tmin has not elapsed as an excluded cell 262e that is excluded from the cell control state CL* to be changed.

[0134] When the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a stores power in the capacitor C of the cell 262 in the insert state (positive voltage insert state or negative voltage insert state) based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, and in a period (charging period) in which the charge polarity is such that the charge amount of the entire arm unit 26 is increased, the cell selection control unit 56a selects, from among the cells 262 currently in the bypass state, the cell 262 having the capacitor C with the least amount of stored power as the cell 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cell 262 having the capacitor C with a relatively low voltage value of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cell 262. Here, the cell 262 may be selected from among the cells 262 for which the minimum pulse time Tmin or more has elapsed, or the cell 262 may be selected primarily regardless of the elapsed time, and the change of the control state (selection as the cell 262 whose control state is to be changed this time) may be withheld until the minimum pulse time Tmin or more has elapsed. The charging polarity corresponds to (1) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 11 is higher than that on the cell 262-n side, and the arm current Iarm flows in the same direction as the arm current I shown in FIG. 11, or (2) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 11 is lower than that on the cell 262-n side, and the arm current Iarm flows in the opposite direction to the arm current I shown in FIG. 11. On the other hand, when the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a preferentially selects, from among the cells 262 currently in the bypass state, a cell 262 having a capacitor C with a large amount of accumulated power as the cell 262 to be changed to the insert state during a period (discharge period) in which the combination of the arm voltage command value Varm* and the polarity of the arm current Iarm is such that the power stored in the capacitor C of the cell 262 in the insert state (positive voltage insert state or negative voltage insert state) is discharged to increase the discharge amount of the entire arm unit 26.In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cells 262 having the capacitors C with relatively high voltage values ​​of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cells 262. Here, the cells 262 may be selected from among the cells 262 for which the minimum pulse time Tmin or more has elapsed, or a primary selection may be made regardless of the elapsed time, and the change in the control state (selection as the cell 262 whose control state is to be changed this time) may be suspended until the minimum pulse time Tmin or more has elapsed for the cell 262. The discharge polarity corresponds to (1) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 11 is higher than that on the cell 262-n side, and the arm current Iarm has a polarity flowing in the opposite direction to the arm current I shown in FIG. 11, or (2) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 11 is lower than that on the cell 262-n side, and the arm current Iarm has a polarity flowing in the direction of the arm current I shown in FIG. 11.

[0135] When the absolute value of the number of inserts Ncells has decreased, the cell selection control unit 56a selects, from among the cells 262 currently in the insert state (positive voltage insert state or negative voltage insert state), a cell 262 having a capacitor C with a large amount of stored power as a cell 262 to be changed to a bypass state in a period (charging period) in which the charging polarity is such that power is stored in the capacitor C of the cell 262 in the insert state based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, as the cell 262 to be changed to a bypass state. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cell 262 having a capacitor C with a relatively high voltage value of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cell 262. Here, the cell 262 may be selected from among the cells 262 for which the minimum pulse time Tmin or more has elapsed, or may be selected regardless of the elapsed time, and the change of the control state may be suspended until the minimum pulse time Tmin or more has elapsed. On the other hand, when the absolute value of the number of inserts Ncells has decreased, the cell selection control unit 56a, in a period (discharge period) in which the power stored in the capacitor C of the cell 262 in the insert state is discharged from the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm to increase the discharge amount of the entire arm unit 26, selects the cell 262 having the capacitor C with less stored power from among the cells 262 currently in the insert state (positive voltage insert state or negative voltage insert state) as the cell 262 to be changed to the bypass state with priority. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cell 262 having the capacitor C with a relatively low voltage value of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cell 262. Here, the cell 262 may be selected from among the cells 262 for which the minimum pulse time Tmin or more has elapsed, or may be selected regardless of the elapsed time and the change of the control state may be suspended until the minimum pulse time Tmin or more has elapsed.

[0136] As a result, the cell 262 including the capacitor C whose capacitor voltage Vc is relatively high has a shorter charge time and a longer discharge time, and thus the capacitor voltage Vc is equalized in each cell 262 included in the arm unit 26. On the other hand, the cell 262 including the capacitor C whose capacitor voltage Vc is relatively low has a longer charge time and a shorter discharge time, and thus the capacitor voltage Vc is equalized in each cell 262 included in the arm unit 26.

[0137] Like the cell selection control unit 56 of the first embodiment, the cell selection control unit 56a may also perform switching control to reduce the difference in the charge amount of the capacitor C in each cell 262 of the arm unit 26 (to balance the charge amount so that it is relatively uniform).

[0138] The cell selection control unit 56a outputs the cell control state CL* corresponding to each cell 262 to the gate signal generating unit 58a. The cell selection control unit 56a is an example of a "unit converter selection unit" in the claims. The excluded cell 262e is an example of an "exclusion unit converter" in the claims.

[0139] The gate signal generating unit 58a performs the same process as the gate signal generating unit 58 of the first embodiment. The gate signal generating unit 58a generates control signals (gate signals) to be output to all the cells 262 included in each arm unit 26 according to the respective cell control states CL* output by the cell selection control unit 56a. More specifically, the gate signal generating unit 58a generates a combination of gate signals, including a gate signal gta corresponding to the switching element Q1, a gate signal gtb corresponding to the switching element Q2, a gate signal gtc corresponding to the switching element Q3, and a gate signal gtd corresponding to the switching element Q4, included in each cell 262 in order to realize the cell control state CL*. At this time, the gate signal generating unit 58a also provides a short dead time to prevent both ends of the capacitor C included in the cell 262 from being short-circuited. The gate signal generating unit 58a outputs each generated gate signal to the corresponding cell 262 (more specifically, the switching element Q included in the cell 262).

[0140] The power conversion device 2 may also be configured such that, for example, the cell selection control unit 56a outputs the cell control state CL* to each cell 262, and generates a gate signal according to the cell control state CL* in each cell 262. In this case, each cell 262 is configured to include a component having a function equivalent to that of the gate signal generation unit 58a.

[0141] With this configuration, the converter control unit 50a controls the cells 262 in each arm unit 26 included in the power converter 20, and causes the power converter 20 to adjust the reactive power (or active power) of the AC system.

[0142] [Eighth operation of the power conversion device] Next, an example of the operation of the power converter 2, that is, the control of the cell 262 in the converter control unit 50a will be described. In the following description, the control over the arm unit 26-RS of the leg 22-RS will be described as a representative of each of the legs 22, ie, the leg 22-RS, the leg 22-ST, and the leg 22-TR, that are provided in the power converter 20. In the following description, for ease of explanation, the operation of each of the components provided in the converter control unit 50a will be described as being performed by the converter control unit 50a itself.

[0143] FIG. 13 is a timing chart for explaining an example of the operation timing of the eighth operation in the power conversion device 2. The example of the operation of the power conversion device 2 shown in FIG. 13 is an example of the operation in the case where the arm unit 26-RS (hereinafter simply referred to as the "arm unit 26") has three cells 262 (n=3). In FIG. 13, like each operation in the power conversion device 1 of the first embodiment, the temporal changes of the arm voltage command value Varm*, the arm current Iarm, and the arm voltage Varm generated by the arm unit 26 based on the arm voltage command value Varm* are shown on the same time axis. In FIG. 13, instead of the gate signal gtp shown in each operation in the power conversion device 1, the temporal changes of the cell control states CL*-1 to CL*-3 of the cells 262-1 to 262-3 changed by the converter control unit 50a are shown on the same time axis. In FIG. 13, like each operation in the power conversion device 1, the dead time is omitted for ease of explanation. Further, Fig. 13 shows an example of a sort list calculated (generated) by the converter control unit 50a (more specifically, the sort list calculation unit 54a). In the eighth operation shown in Fig. 13, similarly to the first operation in the power conversion device 1 of the first embodiment shown in Fig. 4, the sort list is generated (updated) for each period of the arm voltage command value Varm*.

[0144] In the power converter 20, the arm voltage command value Varm* includes the frequency of the AC system. The converter control unit 50a (more specifically, the insert number calculation unit 52a) calculates (calculates) the insert number Ncells expressed by a stepped pseudo-sine wave based on the arm voltage command value Varm*. In FIG. 13, the insert number Ncells is an integer value with a minimum value of "-n (here, "-3")" and a maximum value of "n (here, "3")". The insert number Ncells represents the number of cells 262 to be put into a positive voltage insert state when it is positive (i.e., "0" to "3"), and represents the number of cells 262 to be put into a negative voltage insert state when it is negative (i.e., "-1" to "-3"). The insert number Ncells is calculated by, for example, approximating a value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 262 belonging to the arm unit 26 to an integer. That is, the operation timing of the power conversion device 2 shown in Fig. 13 is the operation timing when the converter control unit 50a performs one-pulse control, similar to the first operation of the power conversion device 1 of the first embodiment. Therefore, the number of inserts Ncells represents something equivalent to the arm voltage Varm shown in Fig. 13, similar to the first operation of the power conversion device 1.

[0145] The converter control unit 50a (more specifically, the cell selection control unit 56a) generates a cell control state CL* of each cell 262 so that the number (integer value) of the cells 262 in the insert state (positive voltage insert state or negative voltage insert state) belonging to the arm unit 26 matches the number of cells 262 to be put into the insert state (positive voltage insert state or negative voltage insert state) represented by the insert number Ncells at each timing when the insert number Ncells changes. When the arm voltage command value Varm* is positive (Varm*>0), the insert number Ncells is a value of "0" or more, so the converter control unit 50a generates a cell control state CL* that puts each cell 262 into the positive voltage insert state or the bypass state. On the other hand, when the arm voltage command value Varm* is negative (Varm*<0), the insert number Ncells is a value of "0" or less, so the converter control unit 50a generates a cell control state CL* that puts each cell 262 into the negative voltage insert state or the bypass state. Each cell control state CL* represents a positive voltage insert state when it is "1", a bypass state when it is "0", and a negative voltage insert state when it is "-1".

[0146] The converter control unit 50a (more specifically, the gate signal generating unit 58a) generates control signals (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) to be output to all the cells 262 included in each arm unit 26 according to the cell control state CL* generated by the cell selection control unit 56a. Then, each arm unit 26 outputs an arm voltage Varm by putting each cell 262 into a positive voltage insert state, a bypass state, or a negative voltage insert state by the gate signal output by the gate signal generating unit 58a. When the capacitor voltages Vc of the cells 262 are uniformly controlled, the arm voltage Varm is approximately a voltage value obtained by multiplying the number (integer value) of the cells 262 to be put into the insert state (positive voltage insert state or negative voltage insert state) represented by the insert number Ncells by the capacitor voltage Vc.

[0147] The arm current Iarm includes the frequency of the AC system. In the arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is positive (Iarm>0), the capacitor C included in the cell 262 in the positive voltage insertion state is charged, and the capacitor voltage Vc rises during this charging period. In the arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is negative (Iarm<0), the capacitor C included in the cell 262 in the negative voltage insertion state is charged, and the capacitor voltage Vc rises during this charging period. In the arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), the capacitor C included in the cell 262 in the positive voltage insertion state is discharged, and the capacitor voltage Vc drops during this discharging period. In the arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is positive (Iarm>0), the capacitor C included in the cell 262 in the negative voltage insertion state is discharged, and the capacitor voltage Vc drops during this discharge period. In this manner, in the arm unit 26, the charging period occurs when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are equal, and the discharging period occurs when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are different. In the arm unit 26, regardless of the polarity of the arm voltage command value Varm* or the polarity of the arm current Iarm, the capacitor C included in the cell 262 in the bypass state is neither charged nor discharged, and the current capacitor voltage Vc is maintained.

[0148] At time t0 shown in FIG. 13, the number of inserts Ncells is "0". The polarity of the arm current Iarm at this time is positive. The converter control unit 50a may arbitrarily determine whether to determine the polarity as charge polarity or discharge polarity when the number of inserts Ncells or the arm current Iarm is "0". In any case, the converter control unit 50a generates a cell control state CL* that indicates that all the cells 262 are in the bypass state so as to match the number of inserts Ncells.

[0149] After that, at time t1, when the number of inserts Ncells changes to "1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive polarity and the polarity of the arm current Iarm is positive polarity (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with less accumulated power as the cell 262 to be put into the positive voltage insert state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t1, the converter control unit 50a sets the cell control state CL*-3 to "1" to put the selected cell 262-3 into the positive voltage insert state.

[0150] Thereafter, from time t2 to time t3, each time the number of inserts Ncells changes sequentially to "2" and "3" (the absolute value increases), the converter control unit 50a, like at time t1, sequentially selects the cells 262 with the second and third lowest capacitor voltages Vc (i.e., Vc-2, Vc-1) in the sort list, and sets the cell control state CL* to "1" to put the selected cells 262 into a positive voltage insert state. More specifically, the converter control unit 50a selects the cell 262-2 at time t2 and sets the cell control state CL*-2 to "1", and selects the cell 262-1 at time t3 and sets the cell control state CL*-1 to "1".

[0151] After that, at time t4, when the number of inserts Ncells changes to "2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive polarity and the polarity of the arm current Iarm is negative polarity (discharge polarity). For this reason, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with less stored power as the cell 262 to be placed in the bypass state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t4, the converter control unit 50a sets the cell control state CL*-3 to "0" to place the selected cell 262-3 in the bypass state.

[0152] Thereafter, from time t5 to time t6, each time the number of inserts Ncells changes sequentially from "1" to "0" (the absolute value decreases), the converter control unit 50a sequentially selects the cells 262 having the second and third lowest capacitor voltages Vc (i.e., Vc-2, Vc-1) in the sort list, as in the case of time t4, and sets the cell control state CL* to "0" to put the selected cells 262 into a bypass state. More specifically, the converter control unit 50a selects the cell 262-2 at time t5 and sets the cell control state CL*-2 to "0", and selects the cell 262-1 at time t6 and sets the cell control state CL*-1 to "0".

[0153] After that, at time t7, when the number of inserts Ncells changes to "-1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative polarity and the polarity of the arm current Iarm is negative polarity (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a small amount of stored power as the cell 262 to be put into the negative voltage insert state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t7, the converter control unit 50a sets the cell control state CL*-3 to "-1" in order to put the selected cell 262-3 into the negative voltage insert state.

[0154] Thereafter, from time t8 to time t9, each time the number of inserts Ncells changes sequentially to "-2", "-3" (the absolute value increases), the converter control unit 50a sequentially selects the cells 262 having the second and third lowest capacitor voltages Vc (i.e., Vc-2, Vc-1) in the sort list, as in the case of time t7, and sets the cell control state CL* to "-1" to put the selected cells 262 into a negative voltage insert state. More specifically, the converter control unit 50a selects the cell 262-2 at time t8 and sets the cell control state CL*-2 to "-1", and selects the cell 262-1 at time t9 and sets the cell control state CL*-1 to "-1".

[0155] Then, at time t10, the sort list is updated.

[0156] After that, at time t11, when the number of inserts Ncells changes to "-2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative polarity and the polarity of the arm current Iarm is positive polarity (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the negative voltage insert state and has a capacitor C with a small amount of stored power as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects the cell 262-1 with the lowest capacitor voltage Vc (i.e., Vc-1) in the sort list. However, the cell 262-1 has just been put into the negative voltage insert state at time t9, and a time period equal to or greater than the minimum pulse time Tmin has not yet elapsed. For this reason, the converter control unit 50a does not immediately put the cell 262-1 into the bypass state at time t11 as the excluded cell 262e, that is, does not immediately set the cell control state CL*-1 to "0", but postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has elapsed in the cell 262-1. Then, after a time equal to or greater than the minimum pulse time Tmin has elapsed in the cell 262-1, the converter control unit 50a removes the cell 262-1 from the excluded cell 262e, that is, includes the cell 262 whose control state can be changed, and sets the cell control state CL*-1 to "0" in order to put the selected cell 262-1 into the bypass state.

[0157] Thereafter, from time t12 to time t13, each time the number of inserts Ncells changes sequentially from "-1" to "0" (the absolute value decreases), the converter control unit 50a, like time t11, sequentially selects the cells 262 having the second and third lowest capacitor voltages Vc (i.e., Vc-2 and Vc-3) in the sort list, and sets the cell control state CL* to "0" to put the selected cells 262 into a bypass state. More specifically, the converter control unit 50a selects the cell 262-2 at time t12 and sets the cell control state CL*-2 to "0", and selects the cell 262-3 at time t13 and sets the cell control state CL*-3 to "0".

[0158] In this way, the converter control unit 50a determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (the absolute value increases or decreases), selects a cell 262 whose control state (cell control state CL*) is to be a positive voltage insert state, a bypass state, or a negative voltage insert state by referring to the sort list, and controls the control state of the selected cell 262, that is, the gate signal gta, the gate signal gtb, the gate signal gtc, and the gate signal gtd. At this time, the converter control unit 50a does not change the control state of the cell 262 for which the elapsed time from the last time when the control state was changed has not elapsed more than the minimum pulse time Tmin for each cell 262 as an excluded cell 262e, and changes the control state of the cell 262 when the elapsed time becomes more than the minimum pulse time Tmin. As a result, in the eighth operation, the cell 262 whose control state is changed is always the cell 262 whose control state has been changed before the minimum pulse time Tmin, as in the first, third, fifth, and sixth operations of the power conversion device 1 of the first embodiment. In the eighth operation of the power conversion device 2 shown in FIG. 13, the case where the cell 262-1 is the excluded cell 262e whose control state has not been changed before the minimum pulse time Tmin at time t11 is shown, but the control state change operation in the converter control unit 50a is the same for the other cells 262. In this way, in the power conversion device 2, as in the power conversion device 1, the converter control unit 50a does not change the control state of the excluded cell 262e whose control state has been changed before the minimum pulse time Tmin, so that the power converter 20 can reduce the risk of failure caused by changing the control state of the cell 262 before the minimum pulse time Tmin. Moreover, in the eighth operation of the power conversion device 2, as in the first operation of the power conversion device 1, the converter control unit 50a configured to suspend the change in the control state of the excluded cell 262e can be realized with an algorithm that is easy to implement, and can be realized at low cost without adopting a complex or large-scale configuration.

[0159] [Ninth operation of the power conversion device] Next, another operation of the power conversion device 2 (another example of the control of the cells 262 in the converter control unit 50a) will be described. FIG. 14 is a timing chart for explaining an example of the operation timing of the ninth operation in the power conversion device 2. The ninth operation shown in FIG. 14 is also an operation in the case where the arm unit 26 has three cells 262 (n=3), similar to the eighth operation shown in FIG. 13. In the ninth operation, the number of inserts Ncells is calculated as the number of triangular wave carrier waves in which the value of the arm voltage command value Varm* (modulation wave) exceeds the value of the triangular wave carrier, for example, by comparing a modulated wave based on the arm voltage command value Varm* with each triangular wave carrier in the same number (here, "3") of the cells 262 belonging to the arm unit 26, the phase and the level of which are shifted from each other. That is, the ninth operation shown in FIG. 14 is the operation timing in the case where the converter control unit 50a performs the multi-pulse control. For this reason, the operation timing of the ninth operation shown in FIG. 14 is shown by enlarging a part of the range within one period of the arm voltage command value Varm*.

[0160] The ninth operation shown in Fig. 14 is an example of a case where, for example, in a discharge polarity (discharge period) where the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), the number of cells 262 in a positive voltage insert state represented by the insert number Ncells repeats between "1" and "2." In other words, the ninth operation shown in Fig. 14 is an example of a case where, in the past, even if the minimum pulse time Tmin has not elapsed, the control state of the same cell 262 is changed multiple times in a very short period of time.

[0161] In the ninth operation, the control state of the cell 262-2 is assumed to be a state in which a positive voltage insert state and a bypass state are repeated, and attention is focused on the cell 262-2. The cell control state CL*-2 generated by the converter control unit 50a for the cell 262-2 and the temporal changes of the gate signals gta-2 to gtd-2 output from the converter control unit 50a to the switching elements Q1 to Q4 of the cell 262-2 are shown on the same time axis as the arm voltage command value Varm*, the arm current Iarm, and the arm voltage Varm. As in the eighth operation shown in FIG. 13, the dead time is omitted in FIG. 14 as well.

[0162] At time t0 shown in FIG. 14, the number of inserts Ncells is "2". Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 having the capacitor C with the large amount of stored power as the cell 262 to be put into the positive voltage insert state. More specifically, the converter control unit 50a selects the cell 262-1 and the cell 262-2, which have the two capacitor voltages Vc (Vc-1 and Vc-2) from the highest in the sort list. Therefore, at time t0 shown in FIG. 14, the converter control unit 50a sets each of the cell control state CL*-1 (not shown) and the cell control state CL*-2 to "1" in order to put the two selected cells 262 into the positive voltage insert state. Then, the converter control unit 50a sets the gate signal gta-2 corresponding to the cell 262-2 to "1", the gate signal gtb-2 to "0", the gate signal gtc-2 to "0", and the gate signal gtd-2 to "1".

[0163] After that, at time t1, when the number of inserts Ncells changes to "1" (the absolute value decreases), the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with less stored power as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects the cell 262-2, which has the lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from among the cell 262-1 and the cell 262-2 that are in the positive voltage insert state. Then, at time t1, the converter control unit 50a sets the cell control state CL*-2 to "0" in order to put the selected cell 262-2 into the bypass state. Then, the converter control unit 50a sets the gate signal gta-2 corresponding to the cell 262-2 to "1", the gate signal gtb-2 to "0", the gate signal gtc-2 to "1", and the gate signal gtd-2 to "0".

[0164] After that, at time t2, when the number of inserts Ncells changes to "2" again (the absolute value increases), the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 262 to be put into the positive voltage insert state. Here, since the converter control unit 50a has already selected the cell 262-1 with the highest capacitor voltage Vc (Vc-1) in the sort list, the converter control unit 50a selects the cell 262-2 with the next highest capacitor voltage Vc (i.e., the second highest Vc-2). However, the cell 262-2 is an excluded cell 262e that was just put into the bypass state at time t1 and has not yet passed a time equal to or greater than the minimum pulse time Tmin. For this reason, the converter control unit 50a does not immediately put the cell 262-2 into a positive voltage insert state at time t2 as the excluded cell 262e, that is, does not immediately put the cell control state CL*-2 into "1" at time t2, but postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has elapsed in the cell 262-2 and the cell 262-2 can be included in the cells 262 whose control state can be changed. For this reason, the converter control unit 50a maintains "1" for the gate signal gta-2, "0" for the gate signal gtb-2, "1" for the gate signal gtc-2, and "0" for the gate signal gtd-2 corresponding to the cell 262-2.

[0165] Then, at time t3, when the elapsed time of the selected cell 262-2 is equal to or greater than the minimum pulse time Tmin, the converter control unit 50a includes the cell 262-2 in the cells 262 whose control state can be changed and sets the cell control state CL*-2 to "1" to put the selected cell 262-2 into a positive voltage insert state. Then, the converter control unit 50a sets the gate signal gta-2 corresponding to the cell 262-2 to "1", the gate signal gtb-2 to "0", the gate signal gtc-2 to "0", and the gate signal gtd-2 to "1".

[0166] After that, at time t4, when the number of inserts Ncells changes to "1" again (the absolute value decreases), the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with less stored power as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects the cell 262-2, which has the lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from the cell 262-1 and the cell 262-2 that are in the positive voltage insert state. However, the cell 262-2 is an excluded cell 262e that was just put into the positive voltage insert state at time t3 and has not yet passed the minimum pulse time Tmin or more. For this reason, the converter control unit 50a does not immediately put the cell 262-2 into a bypass state at time t4 as the excluded cell 262e, that is, does not immediately set the cell control state CL*-2 to "0" at time t4, but postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has elapsed in the cell 262-2 and the cell 262-2 can be included in the cells 262 whose control state can be changed. For this reason, the converter control unit 50a maintains "1" for the gate signal gta-2, "0" for the gate signal gtb-2, "0" for the gate signal gtc-2, and "1" for the gate signal gtd-2 corresponding to the cell 262-2.

[0167] Then, at time t5, when the elapsed time of the selected cell 262-2 is equal to or longer than the minimum pulse time Tmin, the converter control unit 50a includes the cell 262-2 in the cells 262 whose control state can be changed, and sets the cell control state CL*-2 to "0" to put the selected cell 262-2 in the bypass state. Then, the converter control unit 50a sets the gate signal gta-2 corresponding to the cell 262-2 to "0", the gate signal gtb-2 to "1", the gate signal gtc-2 to "0", and the gate signal gtd-2 to "1". Here, the converter control unit 50a may put the cell 262-1 in the bypass state by setting the gate signal gta-2 to "1", the gate signal gtb-2 to "0", the gate signal gtc-2 to "1", and the gate signal gtd-2 to "0".

[0168] After that, at time t6, when the number of inserts Ncells changes to "2" again (the absolute value increases), the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 262 to be put into the positive voltage insert state. Here, since the converter control unit 50a has already selected the cell 262-1 with the highest capacitor voltage Vc (Vc-1) in the sort list, the converter control unit 50a selects the cell 262-2 with the next highest capacitor voltage Vc (i.e., the second highest Vc-2). However, the cell 262-2 is an excluded cell 262e that was just put into the bypass state at time t5 and has not yet passed a time equal to or greater than the minimum pulse time Tmin. For this reason, the converter control unit 50a does not immediately put the cell 262-2 into the positive voltage insert state at time t5 by setting the cell 262-2 as the excluded cell 262e, and postpones the change of the control state until a time equal to or greater than the minimum pulse time Tmin has passed in the cell 262-2. Therefore, the converter control unit 50a maintains the gate signal gta-2 at "0", the gate signal gtb-2 at "1", the gate signal gtc-2 at "0", and the gate signal gtd-2 at "1" corresponding to the cell 262-2.

[0169] After that, at time t7, when the number of inserts Ncells changes to "1" again (the absolute value decreases), the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with less stored power as the cell 262 to be put into the bypass state. However, here, since the cell 262-2 is not put into the positive voltage insert state at time t6, the only cell 262 in the positive voltage insert state is the cell 262-1. Therefore, the converter control unit 50a maintains the current cell control state CL*-2. As a result, the converter control unit 50a does not change the cell control state CL*-2 of the cell 262-2 in response to the change in the number of inserts Ncells at time t6 and time t7. In other words, the converter control unit 50a ignores the change in the number of inserts Ncells at time t6 and time t7.

[0170] In this way, in the ninth operation (multiple pulse control), as in the eighth operation (one pulse control) shown in Fig. 13, the converter control unit 50a determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (the absolute value increases or decreases), refers to the sort list, selects a cell 262 whose control state (cell control state CL*) is to be a positive voltage insert state, a bypass state, or a negative voltage insert state, and controls the control state of the selected cell 262, that is, the gate signal gta, the gate signal gtb, the gate signal gtc, and the gate signal gtd. At this time, in the ninth operation, the converter control unit 50a does not change the control state of the cell 262 for which the elapsed time from the last time when the control state was changed has not elapsed more than the minimum pulse time Tmin, as an excluded cell 262e, and changes the control state of the cell 262 when the elapsed time has elapsed more than the minimum pulse time Tmin. In the ninth operation, similarly to the third operation in the power converter 1 of the first embodiment shown in Fig. 6, if the insert number Ncells changes while the change in the control state is suspended until the minimum pulse time Tmin has elapsed in the excluded cell 262e, the converter control unit 50a may not change the control state of the cell 262 corresponding to the change in the insert number Ncells (ignore the change in the insert number Ncells). In the ninth operation of the power converter 2 shown in Fig. 14, the control state of the cell 262-2, which is the excluded cell 262e, is not changed at time t2 and time t4, and the cell 262-2 is the excluded cell 262e at time t6 and time t7, and the change in the insert number Ncells is ignored. However, the converter control unit 50a performs the same operation to change the control state for the other cells 262. Thus, in the ninth operation, the converter control unit 50a does not change or ignores the control state of the excluded cell 262e whose elapsed time is less than the minimum pulse time Tmin, so that in the power converter 20, all gate signals always become control signals with pulse widths equal to or greater than the minimum pulse time Tmin.This makes it possible to reduce the risk of a failure occurring due to changing the control state of the cell 262 in less than the minimum pulse time Tmin in the power converter 20. Moreover, in the ninth operation, as in the first operation and the eighth operation in the power conversion device 1, the converter control unit 50a configured to suspend or ignore the change in the control state of the excluded cell 262e can be realized with an algorithm that is easy to implement, and can be realized at low cost without adopting a complex or large-scale configuration.

[0171] In the above description, the converter control unit 50a does not change the control state of the excluded cell 262e or ignores it until the elapsed time of the excluded cell 262e becomes equal to or longer than the minimum pulse time Tmin. The converter control unit 50a of the power conversion device 2 may be configured to select an alternative cell 262 and change the control state of the excluded cell 262e, similar to the converter control unit 50 of the first embodiment, instead of changing the control state of the excluded cell 262e, whose elapsed time has not yet passed the minimum pulse time Tmin. Furthermore, the converter control unit 50a may be configured to skip the selection of the excluded cell 262e, or to further perform switching control to balance the charge amount of the capacitor C in each cell 262, similar to the converter control unit 50. The operation of the power conversion device 2 in these cases may be equivalent to the second operation, the fourth operation, the fifth operation, the sixth operation, and the seventh operation of the power conversion device 1. Therefore, detailed description of the operation of the power conversion device 2 when the alternative cell 262 of the excluded cell 262e is selected and the control state is changed will be omitted.

[0172] With such a configuration and operation, in the power conversion device 2, the converter control unit 50a determines whether the polarity is a discharge polarity or a charge polarity for each arm unit 26 included in the power converter 20, based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, at least at each timing when the number of inserts Ncells of the cells 262 changes (the absolute value increases or decreases). Then, in the power conversion device 2, the converter control unit 50a refers to the sort list calculated (generated) for each arm unit 26, selects the cell 262 whose control state is to be changed to a positive voltage insert state, a bypass state, or a negative voltage insert state, and changes the control state of the selected cell 262. At this time, in the power conversion device 2, as in the converter control unit 50 included in the power conversion device 1 of the first embodiment, the converter control unit 50a does not change the control state of the cell 262 selected for each selected cell 262, as an excluded cell 262e, for which the elapsed time since the last time the control state was changed has not elapsed more than the minimum pulse time Tmin, and changes the control state of the cell 262 when the elapsed time becomes more than the minimum pulse time Tmin. Alternatively, in the power conversion device 2, the converter control unit 50a, like the converter control unit 50, does not change the control state of the excluded cell 262e for which the elapsed time has not passed the minimum pulse time Tmin or more for each selected cell 262, but instead selects an alternative cell 262 and changes the control state. As a result, in the power conversion device 2, all the cells 262 for which the converter control unit 50a changes the control state are the cells 262 for which the minimum pulse time Tmin or more has passed. As a result, in the power conversion device 2, it is possible to reduce the risk of a failure that occurs in the power converter 20 due to the control state of the cell 262 being changed before the minimum pulse time Tmin. As a result, in the power conversion device 2, it is possible to realize a highly reliable power conversion device.

[0173] As described above, in the power converter 2 of the second embodiment, similarly to the power converter 1 of the first embodiment, the converter control unit 50a determines whether the polarity is a discharge polarity or a charge polarity for each arm unit 26 included in the power converter 20, based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, at least at each timing when the number of inserts Ncells of the cells 262 changes (increases or decreases). Then, in the power converter 2 of the second embodiment, the converter control unit 50a refers to the sort list calculated (generated) for each arm unit 26, selects the cell 262 whose control state is to be changed to a positive voltage insert state, a bypass state, or a negative voltage insert state, and changes the control state of the selected cell 262. At this time, in the power converter 2 of the second embodiment, the converter control unit 50a does not change the control state of the cell 262 selected by the respective cells 262 for which the elapsed time from the last time when the control state was changed has not elapsed more than the minimum pulse time Tmin, as an excluded cell 262e, and changes the control state of the cell 262 when the elapsed time becomes more than the minimum pulse time Tmin. Alternatively, in the power conversion device 2 of the second embodiment, the converter control unit 50a does not change the control state of the excluded cell 262e for which the elapsed time has not passed the minimum pulse time Tmin or more for each selected cell 262, but instead selects an alternative cell 262 and changes the control state. As a result, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, all the cells 262 for which the converter control unit 50a changes the control state are the cells 262 for which the minimum pulse time Tmin or more has elapsed. As a result, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, the risk of failure caused by changing the control state of the cell 262 in the power converter 20 before the minimum pulse time Tmin can be reduced. As a result, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, a highly reliable power conversion device can be realized.

[0174] As described above, in the power conversion device of each embodiment, the converter control unit that changes the control state of the unit converter in the arm unit provided in the power converter measures the elapsed time from the last time the control state was changed to the current time when the control state is changed when controlling each unit converter. Then, in the power conversion device of each embodiment, unit converters for which the elapsed time has not exceeded a predetermined minimum pulse time are excluded from targets for which the control state is changed this time. This makes it possible for the power conversion device of each embodiment to reduce the risk of failure caused by changing the switching element provided in the unit converter in less than the minimum pulse time. This makes it possible for the power conversion device of each embodiment to realize a highly reliable power conversion device.

[0175] In the power conversion device of each of the above-described embodiments, the insert number calculation unit included in the converter control unit calculates (calculates) the insert number Ncells representing the number of cells (integer value) to be put into the insert state, and the cell selection control unit included in the converter control unit selects the cells to be changed to the insert state or the bypass state in response to a change in the insert number Ncells. However, the trigger for the cell selection control unit to select a cell is not limited to a change in the insert number Ncells. For example, the cell selection control unit may select a cell to be changed to the insert state or the bypass state in response to a change in the number of cells (integer value) to be put into the bypass state, instead of the insert number Ncells representing the number of cells to be put into the insert state. In this case, the operation and processing of the power conversion device and the converter control unit may be equivalent to the operation and processing of the power conversion device and the converter control unit of each of the above-described embodiments.

[0176] According to at least one of the embodiments described above, a power converter (10) is provided with at least one arm unit (16) having a plurality of unit converters (162) connected in series, the unit converters (162) having an energy storage element (C) for storing power and a plurality of switching elements (Q, D) capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element, and a converter control unit (50) for controlling a power conversion operation in the power converter by switching at least one of a first control state (insertion state) in which a terminal voltage (Vc) of the energy storage element is output between a first end (TP) and a second end (TN) of the unit converter, and a second control state (bypass state) in which the first end and the second end of the unit converter are short-circuited, and the converter control unit controls a power conversion operation in the power converter by switching at least one of a first control state (insertion state) in which a terminal voltage (Vc) of the energy storage element is output between a first end (TP) and a second end (TN) of the unit converter, and a unit converter selection unit (56) that measures the duration during which the same control state continues for each unit converter, and selects a unit converter for changing the current control state based on the measured duration, the polarity of an arm current (Iarm) flowing through the arm unit, the number of states, and the list information, and the unit converter selection unit excludes, as an excluded unit converter (162e), a unit converter whose duration has not passed a predetermined minimum time (minimum pulse time Tmin), from the unit converters for which the control state is to be changed, thereby reducing the concentration of changes in the control state for a specific unit converter, and realizing a highly reliable power conversion device.

[0177] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0178] 1,2···Power conversion device, 10···Power converter, 12,12-R,12-S,12-T···Leg, 14,14-PR,14-NR,14-PS,14-NS,14-PT,14-NT,14-RS,14-ST,14-TR···Reactor, 16,16-PR,16-NR,16-PS,16-NS,16-PT,16-NT···Arm unit, 162,162-1,162-n,16 2-1-PR, 162-nPR, 162-1-NR, 162-nNR, 162-1-PS, 162-nPS, 162-1-NS, 162-nNS, 162-1-PT, 162-nPT, 162-1-NT, 162-nNT...cell, 20...power converter, 22, 22-RS, 22-ST, 22-TR...leg, 26, 26-RS, 26-ST, 26-TR...arm unit, 262, 262 -1, 262-n, 262-1-RS, 262-n-RS, 262-1-ST, 262-n-ST, 262-1-TR, 262-n-TR...cell, 50, 50a...converter control unit, 52, 52a...insert number calculation unit, 54, 54a...sort list calculation unit, 56, 56a...cell selection control unit, 58, 58a...gate signal generation unit, Q, Q1, Q2, Q3, Q4...switching element D, D1, D2, D3, D4...Diode, C...Capacitor, TR...Transformer, R, S, T...AC terminal, P...Positive side terminal, N...Negative side terminal, CA, CA-R, CA-S, CA -T, CB, CB-R, CB-S, CB-T...AC terminal, CP,CP-R,CP-S,CP-T,CN,CN-R,CN-S,CN-T...DC terminal, TP...Positive terminal, TN...Negative terminal

Claims

1. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element; a converter control unit that controls a power conversion operation of the power converter by switching between at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited; Equipped with The converter control unit includes: a state number calculation unit that calculates a state number representing the number of the unit converters that belong to the arm unit and are assigned to any one of the control states according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit; a list calculation unit that generates list information representing a magnitude relationship between the detected terminal voltages of the energy storage element; a unit converter selection unit that measures, for each of the unit converters, a duration during which the same control state continues, and selects the unit converter for which the current control state is to be changed based on the measured duration, a polarity of an arm current flowing through the arm unit, the number of states, and the list information; Equipped with the unit converter selection unit excludes the unit converter whose duration does not exceed a predetermined minimum time as an excluded unit converter from the unit converters whose control state is to be changed; Power conversion equipment.

2. The unit converter selection unit is When selecting the unit converter to be changed to the first control state from the unit converters whose duration of the second control state has exceeded the minimum time, during a charging period in which the polarity of the arm current becomes a charging polarity for storing power in the energy storage element of the unit converter in the first control state, preferentially selecting the unit converter having the energy storage element included in the list information and having a relatively low inter-terminal voltage of the energy storage element; during a discharge period in which the polarity of the arm current becomes a discharge polarity for discharging power from the energy storage element of the unit converter in the first control state, preferentially selecting the unit converter having the energy storage element included in the list information and having a relatively high inter-terminal voltage of the energy storage element; When selecting the unit converter to be changed to the second control state from the unit converters whose duration of the first control state has exceeded the minimum time, During the charging period, the unit converter having the energy storage element included in the list information and having a relatively high inter-terminal voltage of the energy storage element is selected preferentially; during the discharge period, preferentially selecting the unit converter having the energy storage element whose inter-terminal voltage included in the list information is relatively low; The power conversion device according to claim 1 .

3. The unit converter selection unit is When the number of states is changed, selection of the unit converter for changing the control state is started; When an absolute value of the number of states to be assigned to the first control state is increased, a converter unit to be changed to the first control state is selected from the converter unit in the second control state; When the absolute value of the number of states to be assigned to the first control state is decreased, a converter unit to be changed to the second control state is selected from the converter units in the first control state. The power conversion device according to claim 1 or 2.

4. The unit converter selection unit is In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state, When a terminal-to-terminal voltage of the energy storage element of a first converter unit that is the converter unit in the first control state exceeds a first threshold value that is higher than a rated voltage, the first converter unit is changed to the second control state, and among the converter unit in the second control state, other converter unit in the same number as the first converter unit is selected as the converter unit to be changed to the first control state; In a discharge period in which the polarity of the arm current becomes a discharge polarity for discharging power from the energy storage element of the unit converter in the first control state, when a terminal-to-terminal voltage of the energy storage element of a second converter unit which is the converter unit in the first control state exceeds a second threshold value which is lower than a rated voltage, the second converter unit is changed to the second control state, and among the converter unit in the second control state, other converter unit in the same number as the second converter unit are selected as converter unit to be changed to the first control state; The power conversion device according to any one of claims 1 to 3.

5. the state number calculation unit approximates a value obtained by dividing the arm voltage command value by an average value or a rated value of the inter-terminal voltage of the energy storage element of the unit converter belonging to the arm unit to an integer, and calculates the resultant value approximated to the integer as the state number to be assigned to the first control state; The power conversion device according to any one of claims 1 to 4.

6. The state number calculation unit a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers, the number of which is the same as the number of the unit converters belonging to the arm unit and which are phase-shifted from each other, and the number of the triangular wave carriers, in which the value of the modulation wave is greater than the value of the triangular wave carrier, is calculated as the number of states to be assigned to the first control state; The power conversion device according to any one of claims 1 to 4.

7. The state number calculation unit a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers whose levels are shifted from each other and whose number is the same as the number of the unit converters belonging to the arm unit; and the number of the triangular wave carriers whose value of the modulation wave is greater than the value of the triangular wave carrier is calculated as the number of states to be assigned to the first control state; The power conversion device according to any one of claims 1 to 4.

8. the unit converter selection unit, when the duration of the excluded unit converter exceeds the minimum time, includes the excluded unit converter in the unit converters that are capable of changing the control state; The power conversion device according to any one of claims 1 to 7.

9. When the duration in the excluded unit converter has not elapsed the minimum time, and the excluded unit converter is represented by the list information as the unit converter whose control state is to be changed next, the unit converter selection unit: Skip the selection of the excluded unit converter; repeating the determination for selecting another unit converter until the unit converter that has not been excluded from the unit converters for which the control state is to be changed is selected as the unit converter for which the control state is to be changed next; The power conversion device according to any one of claims 1 to 7.

10. When the number of the unit converters that are not excluded from the unit converters that change the control state is smaller than the number of the unit converters that change the control state, the unit converter selection unit storing the number of unit converters that are insufficient; selecting a unit converter as a target for changing the control state from among the unit converters that are not excluded from the unit converters for which the control state is to be changed until the shortage is resolved; The power conversion device according to any one of claims 1 to 9.

11. the unit converter is a half-bridge circuit in which a series circuit in which two switching elements, a first switching element and a second switching element, are connected in series and the energy storage element are connected in parallel, a connection point between the first switching element and the second switching element is the first end, and a connection point between the second switching element and the energy storage element is the second end, The converter control unit includes: putting the first switching element into a conductive state and the second switching element into a non-conductive state to put the unit converter into the first control state; putting the first switching element into a non-conductive state and the second switching element into a conductive state, thereby putting the unit converter into the second control state; The power conversion device according to any one of claims 1 to 10.

12. the unit converter is a full bridge circuit in which a first series circuit in which two switching elements, a first switching element and a second switching element, are connected in series, a second series circuit in which two switching elements, a third switching element and a fourth switching element, are connected in series, and the energy storage element are connected in parallel, a connection point between the first switching element and the second switching element being the first end, and a connection point between the third switching element and the fourth switching element being the second end; The converter control unit includes: by setting the first switching element in a conductive state, the second switching element in a non-conductive state, the third switching element in a non-conductive state, and the fourth switching element in a conductive state, the unit converter is set in a first control state, which is the first control state in which a positive voltage is output; by setting the first switching element to a non-conductive state, the second switching element to a conductive state, the third switching element to a conductive state, and the fourth switching element to a non-conductive state, the unit converter is set to a second first control state, which is the first control state in which a negative voltage is output; the unit converter is put into the second control state by setting the first switching element in a conductive state, the second switching element in a non-conductive state, the third switching element in a conductive state, and the fourth switching element in a non-conductive state, or by setting the first switching element in a non-conductive state, the second switching element in a conductive state, the third switching element in a non-conductive state, and the fourth switching element in a conductive state; determining the first control state or the second control state according to a polarity of the valve branch voltage represented by the valve branch voltage command value; The power conversion device according to any one of claims 1 to 10.

13. the power converter is a double star-connected modular multilevel converter having a phase unit for each AC phase, in which two arm units, a first arm unit and a second arm unit, are connected in series, a connection point between the first arm unit and the second arm unit belonging to each of the phase units is an AC terminal connected to the corresponding AC phase, an inductance element is connected to one end of each of the first arm unit and the second arm unit or to an arbitrary position between each of the unit converters connected in series, and a terminal on the opposite side to the AC terminal in each of the first arm unit and the second arm unit is a DC terminal; The converter control unit includes: Distributing an AC voltage command value and a DC voltage command value to the first arm unit and the second arm unit belonging to each of the phase units to obtain the arm voltage command values, changing the control state for each of the arm units in accordance with the distributed arm voltage command value; The power conversion device according to any one of claims 1 to 12.

14. the power converter is a single delta-connection modular multilevel converter in which the arm units are connected between AC terminals of the AC phases, and inductance elements are connected to one end of each of the arm units or at any position between the unit converters connected in series, The converter control unit includes: Distributing an AC voltage command value to each of the arm units between the AC terminals to obtain each of the arm voltage command values; changing the control state for each of the arm units in accordance with the distributed arm voltage command value; The power conversion device according to any one of claims 1 to 12.

15. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element; A control method for a power conversion device including: a converter control unit that controls a power conversion operation of the power converter by switching to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited, The computer of the converter control unit calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit; generating list information representing a magnitude relationship between the detected terminal voltages of the energy storage element; Measure the duration during which the same control state continues for each of the unit converters; When selecting the unit converter for which the current control state is to be changed based on the measured duration, the polarity of the arm current flowing through the arm unit, the number of states, and the list information, the unit converter for which the duration does not exceed a predetermined minimum time is excluded as an excluded unit converter from the unit converters for which the control state is to be changed. A method for controlling a power conversion device.

16. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element; A program for controlling a power conversion device including: a converter control unit that controls a power conversion operation in the power converter by switching to either a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, or a second control state in which the first end and the second end of the unit converter are short-circuited, The computer of the converter control unit Calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit; generating list information representing a magnitude relationship between the detected terminal voltages of the energy storage element; Measure the duration during which the same control state continues for each of the unit converters; When selecting the unit converter for which the current control state is to be changed based on the measured duration, the polarity of the arm current flowing through the arm unit, the number of states, and the list information, the unit converter for which the duration has not exceeded a predetermined minimum time is excluded as an excluded unit converter from the unit converters for which the control state is to be changed. program.

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